Nitride semiconductor device

Abstract

To reduce local electric field concentration in a gate layer.SOLUTION: A nitride semiconductor device 10 includes an electron transit layer 26, an electron supply layer 28, a gate layer 30, a gate electrode 40 on the gate layer 30, a source electrode 42, and a drain electrode 44. The gate layer 30 includes a first gate portion 31, a second gate portion 32, and a recess 33 between the first gate portion 31 and the second gate portion 32. The gate electrode 40 is provided across both the first gate portion 31 and the second gate portion 32. The nitride semiconductor device 10 further includes an insulating portion 80 formed in the recess 33.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to nitride semiconductor devices. [Background technology]

[0002] Currently, high electron mobility transistors (HEMTs) using nitride semiconductors such as gallium nitride (GaN) are being commercialized. Patent Document 1 describes an example of a normally-off type HEMT using a nitride semiconductor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-73506 A

[0004] [overview] In a HEMT using a nitride semiconductor, for example, when a positive voltage is applied to the gate electrode, an electric field is locally concentrated in a portion of the gate layer near the end of the gate electrode. Such localized electric field concentration can cause crystal defects in the gate layer and reduce the gate breakdown voltage. Therefore, there is a need to alleviate the localized electric field concentration in the gate layer. [Brief description of the drawings]

[0005] [Figure 1] FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device according to the first embodiment. [Diagram 2] FIG. 2 is a schematic plan view showing a portion of the nitride semiconductor device of FIG. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the nitride semiconductor device taken along line F3-F3 in FIG. [Figure 4] FIG. 4 is a schematic enlarged cross-sectional view showing a portion of the nitride semiconductor device of FIG. [Diagram 5] FIG. 5 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to the second embodiment. [Figure 6]FIG. 6 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to the third embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view of an illustrative nitride semiconductor device according to the fourth embodiment.

[0006] [Detailed Description] Hereinafter, embodiments of a semiconductor device according to the present disclosure will be described with reference to the accompanying drawings.

[0007] In addition, for simplicity and clarity of illustration and description, the components shown in the drawings are not necessarily drawn to scale. For ease of understanding, features may be enlarged, and the dimensional ratio of each component is not necessarily the same in each drawing. The accompanying drawings are merely illustrative of embodiments of the present disclosure, and should not be considered as limiting the present disclosure.

[0008] The terms "first", "second", "third", etc., used in this disclosure are used to clearly distinguish components of the object, and are not used to rank the objects. In addition, the expression "at least one" used in this disclosure means one or more of the desired multiple options. As an example, if the number of options is two, the expression "at least one" means only one option or both of the two options. As another example, if the number of options is three or more, the expression "at least one" means only one option or any combination of two or more options.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] [First embodiment] [1. Schematic structure of nitride semiconductor device] Fig. 1 is a schematic plan view of an exemplary nitride semiconductor device 10 according to a first embodiment. The nitride semiconductor device 10 includes a chip body 12. The Z-axis direction of the mutually orthogonal XYZ axes shown in Fig. 1 and other drawings is a direction orthogonal to the main surface (top surface 13 in Fig. 1) of the chip body 12. The term "plan view" used in this disclosure refers to viewing the nitride semiconductor device 10 from above in the Z-axis direction, unless otherwise explicitly stated.

[0011] The nitride semiconductor device 10 includes at least one gate pad 14, at least one source pad 16, and at least one drain pad 18. For example, in FIG. 1 , the nitride semiconductor device 10 includes one gate pad 14, a plurality of source pads 16, and a plurality of drain pads 18. The gate pad 14, the source pad 16, and the drain pad 18 are formed on the upper surface 13 of the chip body 12, and can be used as external connection terminals of the nitride semiconductor device 10.

[0012] The gate pad 14, the source pad 16, and the drain pad 18 are each formed, for example, in a rectangular shape in a plan view. The gate pad 14 may be disposed at one corner of the upper surface 13. The source pad 16 and the drain pad 18 each extend in one direction in a plan view, that is, in the Y-axis direction in FIG. 1. The source pads 16 and the drain pads 18 are alternately disposed one by one in the X-axis direction perpendicular to the Y-axis direction.

[0013] Fig. 2 is a schematic plan view showing a part of the internal structure of the nitride semiconductor device 10 of Fig. 1. Also, Fig. 3 is a schematic cross-sectional view of the nitride semiconductor device 10 taken along line F3-F3 shown in Fig. 2. The nitride semiconductor device 10 is configured as a high electron mobility transistor (HEMT) using a nitride semiconductor.

[0014] As shown in FIG. 3, the nitride semiconductor device 10 includes a semiconductor substrate 20, a nucleation layer 22 formed on the semiconductor substrate 20, a buffer layer 24 formed on the nucleation layer 22, an electron transit layer 26 formed on the buffer layer 24, and an electron supply layer 28 formed on the electron transit layer 26.

[0015] The semiconductor substrate 20 may be formed of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), sapphire, or other substrate materials. For example, the semiconductor substrate 20 is a Si substrate. The thickness of the semiconductor substrate 20 may be, for example, 200 μm or more and 1500 μm or less. The Z-axis direction corresponds to the thickness direction of the semiconductor substrate 20.

[0016] The nucleation layer 22 is made of a nitride semiconductor. For example, the nucleation layer 22 may be formed as an aluminum nitride (AlN) layer having a thickness of 100 nm or more and 500 nm or less. The nucleation layer 22 may be included as the bottom layer of the buffer layer 24.

[0017] The buffer layer 24 may be made of any material capable of suppressing the occurrence of wafer warpage and cracks due to mismatch in thermal expansion coefficient between the semiconductor substrate 20 and the electron transport layer 26. The buffer layer 24 may include one or more nitride semiconductor layers. The buffer layer 24 may include, for example, at least one of an AlN layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different aluminum (Al) compositions. For example, the buffer layer 24 may be made of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure.

[0018] The electron transport layer 26 is composed of a nitride semiconductor. The electron transport layer 26 may be, for example, a GaN layer. The thickness of the electron transport layer 26 can be, for example, 0.1 μm or more and 2 μm or less. The electron transport layer 26 may include one or more nitride semiconductor layers. Further, in order to suppress the leakage current in the electron transport layer 26, impurities may be introduced into a part of the electron transport layer 26 to make the region other than the surface layer region of the electron transport layer 26 semi-insulating. In that case, the impurity is, for example, C, and the concentration of the impurity can be, for example, 1×10 19 cm -3 or more. GaN is an example of a first nitride semiconductor.

[0019] The electron supply layer 28 is composed of a nitride semiconductor having a larger bandgap than the electron transport layer 26. The electron supply layer 28 may be, for example, an AlGaN layer. Since the larger the Al composition, the larger the bandgap, the electron supply layer 28 which is an AlGaN layer has a larger bandgap than the electron transport layer 26 which is a GaN layer. In one example, the electron supply layer 28 is composed of Al x Ga 1-x N, where x satisfies 0.1 < x < 0.4, and more preferably, 0.1 < x < 0.3. The thickness of the electron supply layer 28 can be, for example, 5 nm or more and 20 nm or less. AlGaN is an example of a second nitride semiconductor.

[0020] The electron transport layer 26 and the electron supply layer 28 have different lattice constants in the bulk region. Therefore, the nitride semiconductor (for example, GaN) constituting the electron transport layer 26 and the nitride semiconductor (for example, AlGaN) constituting the electron supply layer 28 form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the electron transport layer 26 and the electron supply layer 28 and the piezo-polarization caused by the compressive stress received by the hetero-junction portion of the electron transport layer 26, the energy level of the conduction band of the electron transport layer 26 near the hetero-junction interface between the electron transport layer 26 and the electron supply layer 28 becomes lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 27 is formed in the electron transport layer 26 at a position close to the hetero-junction interface between the electron transport layer 26 and the electron supply layer 28 (for example, at a distance of about several nm from the interface).

[0021] The nitride semiconductor device 10 further includes a gate layer 30 formed on a portion of the electron supply layer 28 , and a gate electrode 40 formed on the gate layer 30 . The gate layer 30 is made of a nitride semiconductor. For example, the gate layer 30 is made of a nitride semiconductor having a band gap smaller than that of the electron supply layer 28 and containing acceptor-type impurities. In one example, the gate layer 30 is a GaN layer doped with acceptor-type impurities (p-type GaN layer). Note that pGaN is an example of a third nitride semiconductor. The acceptor-type impurities may be at least one of magnesium (Mg), zinc (Zn), and C. The maximum concentration of the acceptor-type impurities in the gate layer 30 is, for example, 7×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0022] The gate electrode 40 includes one or more metal layers. For example, the gate electrode 40 may be a titanium nitride (TiN) layer. Alternatively, the gate electrode 40 may be formed by a first metal layer made of Ti and a second metal layer made of TiN provided on the first metal layer. For example, the gate electrode 40 may be formed by a material that forms a Schottky junction with the gate layer 30. An example of such a material is TiN. The thickness of the gate electrode 40 may be, for example, 50 nm or more and 200 nm or less.

[0023] The nitride semiconductor device 10 further includes a passivation layer 50. The passivation layer 50 covers the electron supply layer 28, the gate layer 30, and the gate electrode 40. The passivation layer 50 may be made of, for example, one or any combination of silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), alumina (Al2O3), AlN, and aluminum oxynitride (AlON). The thickness of the passivation layer 50 may be, for example, 50 nm or more and 200 nm or less, preferably 80 nm or more and 150 nm or less. The passivation layer 50 includes a source opening 50A and a drain opening 50B that expose a part of the upper surface of the electron supply layer 28, respectively.

[0024] The nitride semiconductor device 10 further includes a source electrode 42 formed in the source opening 50A and a drain electrode 44 formed in the drain opening 50B. The source electrode 42 includes a source contact portion 42A in contact with the electron supply layer 28 through the source opening 50A. The drain electrode 44 includes a drain contact portion 44A in contact with the electron supply layer 28 through the drain opening 50B.

[0025] The source electrode 42 and the drain electrode 44 include one or more metal layers. For example, the source electrode 42 and the drain electrode 44 may be composed of one or any combination of Ti, TiN, Al, aluminum silicon copper (AlSiCu), and aluminum copper (AlCu).

[0026] A portion of the source electrode 42 fills the source opening 50A and is in ohmic contact with the 2DEG 27 directly below the electron supply layer 28 through the source opening 50A. Similarly, a portion of the drain electrode 44 fills the drain opening 50B and is in ohmic contact with the 2DEG 27 directly below the electron supply layer 28 through the drain opening 50B. Although not shown in the figure, the semiconductor substrate 20 is electrically connected to the source electrode 42, and a voltage of the same potential as that of the source electrode 42 is applied to the semiconductor substrate 20.

[0027] In a structure in which the gate layer 30 is formed of a nitride semiconductor containing acceptor-type impurities, the conductive path (channel) is cut off by depleting the 2DEG 27 in the region directly below the gate layer 30 at zero bias when no voltage is applied to the gate electrode 40. This realizes a normally-off HEMT in which the threshold voltage is a positive value.

[0028] The nitride semiconductor device 10 further includes a field plate electrode 60 provided on the passivation layer 50. The field plate electrode 60 is electrically connected to the source electrode 42. In the example of FIG. 3, the field plate electrode 60 is formed integrally with the source electrode 42, and a part of the source electrode 42 is provided as the field plate electrode 60. Therefore, a voltage having the same potential as that of the source electrode 42 is applied to the field plate electrode 60. The field plate electrode 60 is also called a source field plate. The field plate electrode 60 covers the entire gate layer 30 in a plan view.

[0029] The field plate electrode 60 is spaced apart from the drain electrode 44 and includes an end 61 located between the gate layer 30 and the drain electrode 44 in a plan view. The field plate electrode 60 plays a role in reducing electric field concentration near the end of the gate electrode 40 and near the end of the gate layer 30 when a drain voltage is applied to the drain electrode 44 in a zero bias state in which no voltage is applied to the gate electrode 40.

[0030] 2. Example Structure of Gate Layer 3 and 4, an exemplary structure of the gate layer 30 will be described. FIG 4 is a schematic enlarged cross-sectional view showing a portion of the nitride semiconductor device 10 of FIG.

[0031] The gate layer 30 is located between the source contact portion 42A and the drain contact portion 44A in the X-axis direction. The gate layer 30 is spaced apart from each of the source contact portion 42A and the drain contact portion 44A, and is located closer to the source contact portion 42A than the drain contact portion 44A.

[0032] The gate layer 30 includes a first gate portion 31, a second gate portion 32, and a recess 33 between the first gate portion 31 and the second gate portion 32. The gate electrode 40 is provided across both the first gate portion 31 and the second gate portion 32. Therefore, the first gate portion 31 and the second gate portion 32 are connected to each other by the gate electrode 40.

[0033] Each of the first and second gate portions 31, 32 is formed, for example, in a ridge-like cross section (approximately rectangular cross section). However, the cross-sectional shape of the first gate portion 31 is not particularly limited, and may be, for example, a trapezoidal cross section or other cross-sectional shapes. The thickness of each of the first and second gate portions 31, 32 (the distance from the upper surface to the lower surface of each of the gate portions 31, 32) may be determined in consideration of various parameters such as the gate threshold voltage. For example, the thickness of each of the first and second gate portions 31, 32 may be 80 nm or more and 150 nm or less.

[0034] The nitride semiconductor device 10 further includes an insulating portion 80 formed in the recess 33. The insulating portion 80 is made of one of SiO2, SiN, SiON, Al2O3, AlN, and AlON, or any combination thereof. The gate electrode 40 is provided covering the insulating portion 80 and extending across both the first gate portion 31 and the second gate portion 32.

[0035] 4, insulating portion 80 includes a filling portion 81 filled in recess 33, and an upper protrusion 82 formed integrally with filling portion 81 and protruding from recess 33. Upper protrusion 82 includes a first overlap portion 82A covering a portion of the upper surface of first gate portion 31, and a second overlap portion 82B covering a portion of the upper surface of second gate portion 32.

[0036] The first overlap portion 82A extends a first extension length EL1 in the -X direction (leftward along the X-axis in FIG. 4) from a first opening end 33A of the recess 33 corresponding to the upper inner edge of the first gate portion 31, to cover the upper surface of the first gate portion 31. The second overlap portion 82B extends a second extension length EL2 in the +X direction (rightward along the X-axis in FIG. 4) from a second opening end 33B of the recess 33 corresponding to the upper inner edge of the second gate portion 32, to cover the upper surface of the second gate portion 32. In the example of FIG. 4, the -X direction corresponds to the first direction, and the +X direction corresponds to the second direction.

[0037] The first overlapping portion 82A covers a part of the upper surface of the first gate portion 31, but does not cover the entire upper surface of the first gate portion 31. As an example, the length in the X-axis direction of the first gate portion 31 can be 200 nm or more and 400 nm or less. The first extension length EL1 of the first overlapping portion 82A can be, for example, 10 nm or more and 200 nm or less. However, it is sufficient that the first overlapping portion 82A covers a part of the upper surface of the first gate portion 31, and the first extension length EL1 may be less than 10 nm. In addition, from the viewpoint of maintaining a good on state of the normally-off type HEMT, it is preferable that the first extension length EL1 is relatively short. For example, in the case of an embodiment in which the gate electrode 40 forms a Schottky junction with the gate layer 30, the first extension length EL1 may be 100 nm or less. The gate electrode 40 contacts the upper surface of the first gate portion 31 with a contact length CL1 in the X-axis direction. This contact length CL1 is set to a value that maintains the gate current supply capability, taking into consideration the length of the first gate portion 31 in the X-axis direction and the first extension length EL1 of the first overlap portion 82A, etc. The thickness T1 of the first overlap portion 82A is set to a value less than the thickness of the gate electrode 40, and is, for example, 10 nm or more and 200 nm or less, more preferably 50 nm or more and 100 nm or less.

[0038] The sidewall of the first gate portion 31 (the left sidewall in FIG. 4) is connected in a stepped manner to the sidewall of the gate electrode 40 (the left sidewall in FIG. 4). Therefore, the upper surface of the first gate portion 31 includes an upper surface portion exposed to the outside of the gate electrode 40 (the left side in FIG. 4) as a source-side side space.

[0039] Similarly, the second overlap portion 82B covers a part of the upper surface of the second gate portion 32, but does not cover the entire upper surface of the second gate portion 32. As an example, the length in the X-axis direction of the second gate portion 32 can be 200 nm or more and 400 nm or less. The total length in the X-axis direction of the first gate portion 31 and the second gate portion 32 is, for example, 400 nm or more and 800 nm or less, and the lengths of the first and second gate portions 31 and 32 may be the same or different. In addition, the second extension length EL2 of the second overlap portion 82B can be, for example, 10 nm or more and 200 nm or less. However, it is sufficient that the second overlap portion 82B covers a part of the upper surface of the second gate portion 32, and the second extension length EL2 may be less than 10 nm. Moreover, from the viewpoint of maintaining a good on state of the normally-off HEMT, it is preferable that the second extension length EL2 is relatively short. For example, in the case of an embodiment in which the gate electrode 40 forms a Schottky junction with the gate layer 30, the second extension length EL2 may be 100 nm or less. The gate electrode 40 is in contact with the upper surface of the second gate portion 32 at a contact length CL2 in the X-axis direction. This contact length CL2 is set to a value that maintains the gate current supply capability, taking into consideration the length of the second gate portion 32 in the X-axis direction and the second extension length EL2 of the second overlap portion 82B, etc. The second overlap portion 82B can have the same thickness T1 as the first overlap portion 82A.

[0040] The sidewall of the second gate portion 32 (the right sidewall in FIG. 4) is connected in a stepped manner to the sidewall of the gate electrode 40 (the right sidewall in FIG. 4). Therefore, the upper surface of the second gate portion 32 includes an upper surface portion exposed to the outside of the gate electrode 40 (the right sidewall in FIG. 4) as a drain-side side space.

[0041] The recess 33 includes a bottom 33C made of a third nitride semiconductor (pGaN in the first embodiment). Therefore, the insulating portion 80 filled in the recess 33 is provided on the bottom 33C without contacting the electron supply layer 28. The bottom 33C is formed integrally with the first and second gate portions 31, 32. That is, the first gate portion 31 and the second gate portion 32 are connected to each other by the bottom 33C and are not separated from each other. The depth of the recess 33 may be the same as or different from the height of each of the side walls of the first and second gate portions 31, 32.

[0042] The gate layer 30 further includes a source side extension portion 34 extending from the first gate portion 31 toward the source contact portion 42A (see FIG. 3), and a drain side extension portion 35 extending from the second gate portion 32 toward the drain contact portion 44A (see FIG. 3).

[0043] The source side extension 34 and the drain side extension 35 are made of a third nitride semiconductor (pGaN in the first embodiment). The source side extension 34 has a thickness smaller than that of the first gate portion 31 and is formed integrally with the first gate portion 31. The drain side extension 35 has a thickness smaller than that of the second gate portion 32 and is formed integrally with the second gate portion 32. Both the source side extension 34 and the drain side extension 35 are in contact with the electron supply layer 28.

[0044] The drain side extension portion 35 may have a length in the X-axis direction greater than that of the source side extension portion 34. The length in the X-axis direction of the source side extension portion 34 may be, for example, 0.2 μm or more and 0.3 μm or less. The length in the X-axis direction of the drain side extension portion 35 may be, for example, 0.2 μm or more and 0.6 μm or less. Due to the presence of the source side extension portion 34 and the drain side extension portion 35, the gate layer 30 is in contact with the electron supply layer 28 over a larger contact area.

[0045] [3. Example Planar Layout of Nitride Semiconductor Device] Next, an exemplary planar layout of the HEMT structure (nitride semiconductor device 10) will be described with reference to Fig. 2. For clarity, the passivation layer 50 is omitted in Fig. 2. Also, the source opening 50A, the drain opening 50B, and the field plate electrode 60 are depicted by dashed lines.

[0046] 2, the nitride semiconductor device 10 includes a gate wiring 72, a source wiring 74, and a drain wiring 76. The gate wiring 72, the source wiring 74, and the drain wiring 76 are formed on an interlayer insulating layer (not shown) that covers the source electrode 42 and the drain electrode 44. For example, the gate wiring 72 is connected to the gate electrode 40 by a gate connection conductor 73 that penetrates the interlayer insulating layer and extends to the gate electrode 40. The source wiring 74 is connected to the source electrode 42 by a source connection conductor 75 that penetrates the interlayer insulating layer. The drain wiring 76 is connected to the drain electrode 44 by a drain connection conductor 77 that penetrates the interlayer insulating layer.

[0047] The nitride semiconductor device 10 includes a plurality of transistor elements each having a HEMT structure in an element region. Although Fig. 2 shows only a plurality of transistor elements aligned in the X-axis direction, in reality, the transistor elements may be aligned in both the X-axis direction and the Y-axis direction.

[0048] The drain electrode 44 is provided for each transistor element and extends in the Y-axis direction in a planar view. The source electrode 42 is provided, for example, so as to surround each drain electrode 44 in a planar view. As described with reference to FIG. 3, the source electrode 42 includes a field plate electrode 60. That is, the field plate electrode 60 is formed integrally with the source electrode 42 and extends toward the adjacent drain electrode 44 in a planar view. Note that, in the example of FIG. 2, the source electrode 42 is formed continuously in the X-axis direction across multiple transistor elements adjacent in the X-axis direction, but may be separated into multiple parts in the X-axis direction.

[0049] The gate layer 30 and the gate electrode 40 are provided for each transistor element. Each gate layer 30 and each gate electrode 40 is formed in an annular shape so as to surround one of the drain electrodes 44 in a plan view.

[0050] In order to avoid complicating the illustration, the first gate portion 31, the second gate portion 32, the recess 33, and the insulating portion 80 are omitted from Fig. 2. The recess 33 (see Fig. 3) may be formed as an elongated recess extending in, for example, the Y-axis direction in Fig. 2 in the gate layer 30 below the gate electrode 40. The insulating portion 80 (see Fig. 3) formed in the recess 33 may be provided as an elongated insulating member extending in, for example, the Y-axis direction in Fig. 2 in the gate layer 30 below the gate electrode 40.

[0051] [4. Function of nitride semiconductor device] In general, in a HEMT using a nitride semiconductor, for example, when a positive voltage is applied to the gate electrode, an electric field is locally concentrated in a portion of the gate layer near the end of the gate electrode. Such localized electric field concentration can cause crystal defects in the gate layer and reduce the gate breakdown voltage. Therefore, there is a need to alleviate the localized electric field concentration in the gate layer.

[0052] In the first embodiment, the gate layer 30 includes a first gate portion 31, a second gate portion 32, and a recess 33 provided between the first gate portion 31 and the second gate portion 32. The gate electrode 40 is provided across both the first gate portion 31 and the second gate portion 32. In this configuration, since the gate layer 30 is divided into the first and second gate portions 31 and 32, the locations of electric field concentration in the gate layer 30 are dispersed to other locations, and localized electric field concentration is alleviated.

[0053] Furthermore, since the gate electrode 40 is continuous across the first and second gate portions 31, 32, the gate electrode 40 is also present on the insulating portion 80 provided in the recess 33 between the first and second gate portions 31, 32. In this structure, the presence of the insulating portion 80 and the gate electrode 40 above the recess 33 improves the gate breakdown voltage compared to a structure in which the gate electrode 40 is separated between the first and second gate portions 31, 32, for example, a structure in which individual gate electrode portions are independently provided on the first and second gate portions 31, 32.

[0054] For example, in the case of a conventional gate structure in which the gate layer 30 is not divided into the first and second gate portions 31, 32 (for example, in FIG. 4, a structure in which the gate layer 30 does not include the recess 33 and the insulating portion 80), local electric field concentrations typically occur at upper surface points P1, P2 (see FIG. 4) of the gate layer 30 that contact the outer lower end of the gate electrode 40. Furthermore, in this structure, the maximum electric field strength at these upper surface points P1, P2 is also relatively large.

[0055] In contrast, in a structure in which the gate layer 30 is divided into the first and second gate portions 31, 32, the electric field concentration locations are dispersed to upper surface portions P3, P4 (see FIG. 4) of the gate layer 30 in contact with the inner lower end portion of the gate electrode 40. The upper surface portion P3 corresponds to the upper surface portion of the first gate portion 31 in contact with the inner lower end portion of the gate electrode 40, and the upper surface portion P4 corresponds to the upper surface portion of the second gate portion 32 in contact with the inner lower end portion of the gate electrode 40.

[0056] In addition to these upper surface points P3 and P4, electric field concentration locations are also distributed to the bent portions of the first gate portion 31 and the bent portions of the second gate portion 32, for example, near the upper inner edge (i.e., the first opening end 33A) of the first gate portion 31 and near the upper inner edge (i.e., the second opening end 33B) of the second gate portion 32. In this way, the electric field concentration locations are distributed to the upper surface points P3 and P4 and the bent portions of the first and second gate portions 31 and 32, thereby suppressing the electric field from concentrating locally only on the upper surface points P1 and P2 of the gate layer 30. As a result, the maximum electric field intensity at the upper surface points P1 and P2 is alleviated, suppressing crystal defects in the gate layer and, ultimately, crystal destruction. This improves the gate breakdown voltage.

[0057] Moreover, in the first embodiment, the nitride semiconductor device 10 includes an insulating portion 80 formed in the recess 33 of the gate layer 30. The insulating portion 80 includes a filling portion 81 filled in the recess 33, and an upper protruding portion 82 formed integrally with the filling portion 81 and protruding from the recess 33. The upper protruding portion 82 includes a first overlapping portion 82A covering a portion of the upper surface of the first gate portion 31, and a second overlapping portion 82B covering a portion of the upper surface of the second gate portion 32.

[0058] By providing such first and second overlapping portions 82A, 82B between the gate electrode 40 and the first and second gate portions 31, 32, respectively, electric field concentration is alleviated at the bending portion (near the upper inner edge) of the first gate portion 31 and the bending portion (near the upper inner edge) of the second gate portion 32. In this way, a part of the insulating portion 80 can be made to function as a field plate for alleviating electric field concentration.

[0059] In addition, the first and second overlapping portions 82A, 82B have the effect of suppressing leakage current flowing inside the gate layer 30. In a structure in which the gate layer 30 is divided into the first and second gate portions 31, 32, there is a concern about the occurrence of leakage current flowing through two wall surfaces of the recess 33 (the wall surface of the recess 33 at the position of the first opening end 33A and the wall surface of the recess 33 at the position of the second opening end 33B in FIG. 4).

[0060] In this regard, in the first embodiment, the first overlap portion 82A extends onto the upper surface of the first gate portion 31 to cover the first opening end 33A, thereby suppressing current leakage from the first opening end 33A through the wall surface of the recess 33. Similarly, the second overlap portion 82B extends onto the upper surface of the second gate portion 32 to cover the second opening end 33B, thereby suppressing current leakage from the second opening end 33B through the wall surface of the recess 33. This suppresses a decrease in gate breakdown voltage due to division of the gate layer 30 into the first and second gate portions 31, 32.

[0061] Furthermore, for the same gate length, when compared with a conventional gate structure in which the gate layer 30 is not divided into the first and second gate portions 31, 32, in the structure in which the gate layer 30 is divided into the first and second gate portions 31, 32, the length of the gate layer 30 in the X-axis direction is relatively shorter by the length (width) of the recess 33 (insulating portion 80). This makes it possible to substantially shorten the gate length and reduce the on-resistance.

[0062] The nitride semiconductor device 10 of the first embodiment has the following advantages. (1-1) The gate layer 30 includes the first and second gate portions 31 and 32, and the gate electrode 40 is provided across both the first and second gate portions 31 and 32. With this configuration, the electric field concentration locations in the gate layer 30 can be dispersed to a plurality of locations in each of the first and second gate portions 31 and 32. This can alleviate local electric field concentration in the gate layer 30 and improve the gate breakdown voltage. In addition, the gate electrode 40 is continuous across the first and second gate portions 31 and 32 and is also present on the insulating portion 80 provided in the recess 33 between the first and second gate portions 31 and 32, so that the gate breakdown voltage can be improved.

[0063] (1-2) In addition, for the same gate length, in a structure in which the gate layer 30 is divided into the first and second gate portions 31 and 32, the length of the gate layer 30 in the X-axis direction can be relatively shortened by the length (width) of the recess 33 (insulating portion 80) when compared with a conventional gate structure. This makes it possible to reduce the on-resistance.

[0064] (1-3) An insulating portion 80 is formed in the recess 33 of the gate layer 30. The insulating portion 80 includes a filling portion 81 and an upper protrusion 82. The upper protrusion 82 includes a first overlap portion 82A that covers a part of the upper surface of the first gate portion 31, and a second overlap portion 82B that covers a part of the upper surface of the second gate portion 32. With this configuration, electric field concentration in the first and second gate portions 31 and 32 can be alleviated at positions directly below the first and second overlap portions 82A and 82B. In addition, the first and second overlap portions 82A and 82B can suppress current leakage through the two wall surfaces of the recess 33.

[0065] (1-4) The first overlap portion 82A extends with a first extension length EL1, and the second overlap portion 82B extends with a second extension length EL2. In this case, preferably, the first extension length EL1 and the second extension length EL2 are each 10 nm or more and 200 nm or less. In this configuration, by making each extension length EL1, EL2 10 nm or more, it is possible to effectively realize the function of alleviating local electric field concentration in the gate layer 30 and the function of suppressing current leakage. In addition, by making each extension length EL1, EL2 200 nm or less, it is possible to suppress the HEMT from becoming difficult to turn on. For example, if the first extension length EL1 is greater than 200 nm, the area (contact length CL1) of the gate electrode 40 contacting the upper surface of the first gate portion 31 becomes smaller, and the current supply capability of the first gate portion 31 decreases. As a result, it becomes difficult for the HEMT to turn on. Therefore, it is preferable that the first extension length EL1 is 200 nm or less. The same applies to the second extension length EL2.

[0066] (1-5) The first overlap portion 82A and the second overlap portion 82B each have a thickness of 10 nm or more and 200 nm or less. In this configuration, by making each thickness 10 nm or more, the function of alleviating electric field concentration can be effectively realized. Also, by making each thickness 200 nm or less, the current supply capacity of each gate portion 31, 32 can be effectively maintained.

[0067] (1-6) The recess 33 includes a bottom 33C, and the insulating portion 80 is provided on the bottom 33C without contacting the electron supply layer 28. With this configuration, a part of the gate layer 30 exists as the bottom 33C directly below the insulating portion 80 (i.e., the electron supply layer 28 is not exposed in the recess 33), so that the gate withstand voltage can be more appropriately maintained than in a structure in which the insulating portion 80 is in contact with the electron supply layer 28.

[0068] (1-7) The gate layer 30 includes a source-side extension portion 34 extending from the first gate portion 31 toward the source contact portion 42A, and a drain-side extension portion 35 extending from the second gate portion 32 toward the drain contact portion 44A. With this configuration, the electric field concentration locations in the first and second gate portions 31 and 32 can be dispersed to the source-side extension portion 34 and the drain-side extension portion 35, respectively. This can further improve the gate breakdown voltage.

[0069] [Second embodiment] 5 is a schematic cross-sectional view of an exemplary nitride semiconductor device 10 according to the second embodiment, and is shown as a cross-section of the gate structure of the second embodiment corresponding to the cross-sections of the gate structure of the first embodiment in FIGS. 3 and 4 described above. In the second embodiment, the configuration of the insulating portion 80 of the first embodiment is partially changed. Other configurations are similar to those of the first embodiment, and therefore detailed description of similar configurations will be omitted.

[0070] As shown in Fig. 5, in the second embodiment, the insulating portion 80 includes only the filling portion 81, and does not have the upper protrusion 82 (see Figs. 3 and 4). That is, the upper protrusion 82 described in the first embodiment can be omitted from the insulating portion 80. In this configuration, the upper surface of the insulating portion 80 is flush with the upper surfaces of the first and second gate portions 31, 32. Therefore, the lower surface of the gate electrode 40 is formed flat rather than stepped.

[0071] The nitride semiconductor device 10 of the second embodiment has the following advantages in addition to the advantages (1-1) to (1-2) and (1-6) to (1-7) of the first embodiment described above. (2-1) The insulating portion 80 of the second embodiment does not include the first and second overlap portions 82A and 82B as described in the first embodiment. Therefore, the current supply capability of the first and second gate portions 31 and 32 can be improved compared to the first embodiment.

[0072] [Third embodiment] 6 is a schematic cross-sectional view of an exemplary nitride semiconductor device 10 according to the third embodiment, and is shown as a cross-section of the gate structure of the third embodiment corresponding to the cross-sections of the gate structure of the first embodiment in FIGS. 3 and 4 described above. In the third embodiment, the configuration of the insulating section 80 of the first embodiment is partially changed. Other configurations are similar to those of the first embodiment, and therefore detailed description of similar configurations will be omitted.

[0073] 6, in the third embodiment, the insulating portion 80 has a thickness smaller than the thickness of each of the first and second gate portions 31, 32. Therefore, the insulating portion 80 is not formed in the entire recess 33, but is formed in a part of the recess 33. That is, the insulating portion 80 does not completely fill the recess 33. On the other hand, a part of the gate electrode 40 is embedded in the recess 33. Therefore, a part of the gate electrode 40 is embedded in the recess 33 together with the insulating portion 80.

[0074] Such a nitride semiconductor device 10 of the third embodiment has advantages similar to the advantages (1-1) to (1-2) and (1-6) to (1-7) of the first embodiment described above. [Fourth embodiment] 7 is a schematic cross-sectional view of an exemplary nitride semiconductor device 10 according to a fourth embodiment, and is shown as a cross-section of the gate structure of the second embodiment corresponding to the cross-sections of the gate structure of the first embodiment in FIGS. 3 and 4 described above. In the third embodiment, the configuration of the insulating portion 80 of the first embodiment is partially changed. Other configurations are similar to those of the first embodiment, and therefore detailed description of similar configurations will be omitted.

[0075] 7, in the fourth embodiment, the electron supply layer 28 is at least partially exposed in the recess 33, and the insulating portion 80 is in contact with the electron supply layer 28 in the recess 33. Note that, although the first gate portion 31 and the second gate portion 32 are shown in a separated state in FIG. 7, the first gate portion 31 is connected to the second gate portion 32 at a position of the gate layer 30 where the recess 33 is not formed. Therefore, the first gate portion 31 and the second gate portion 32 are not physically separated.

[0076] The nitride semiconductor device 10 of the fourth embodiment has the following advantages in addition to the advantages (1-1) to (1-5) and (1-7) of the first embodiment described above. (4-1) Since the electron supply layer 28 is at least partially exposed in the recess 33, the gate layer 30 (e.g., a pGaN layer) is not present at the position of the recess 33. This results in a structure in which the 2DEG 27 (see FIG. 3) is generated in the region directly below the recess 33. Therefore, this structure is more advantageous than the structure of the first embodiment in terms of reducing the on-resistance.

[0077] [Example of change] The above-described embodiments may be modified as follows: The above-described embodiments and the following modifications may be combined with each other to the extent that no technical contradiction occurs.

[0078] The nitride semiconductor device 10 is not limited to a HEMT using GaN, and may be a semiconductor device using other nitride semiconductors. The nitride semiconductor device 10 of the present disclosure is not limited to being configured with the numerical values ​​or numerical ranges described in the above-described embodiments.

[0079] The gate layer 30 is not limited to a structure including the source side extension portion 34 and the drain side extension portion 35. The source side extension portion 34 and the drain side extension portion 35 may be omitted from the gate layer 30.

[0080] The upper protruding portion 82 of the insulating portion 80 may have a structure that does not include the first and second overlapping portions 82A, 82B. For example, in the configuration of Fig. 4, the upper protruding portion 82 may have a structure that includes only a portion that protrudes above the filling portion 81 (and therefore does not include the first and second overlapping portions 82A, 82B).

[0081] The field plate electrode 60 does not have to be formed integrally with the source electrode 42. For example, a voltage of the same potential as that of the source electrode 42 may be applied to the field plate electrode 60 provided physically separated from the source electrode 42.

[0082] The recess 33 may be formed with a depth equivalent to, for example, half the thickness of the first and second gate portions 31, 32. In other words, the depth of the recess 33 is not particularly limited. The sidewall of the first gate portion 31 (the left sidewall in FIG. 4) is not limited to being stepped with the sidewall of the gate electrode 40 (the left sidewall in FIG. 4), and may be flush with the sidewall of the gate electrode 40. Similarly, the sidewall of the second gate portion 32 (the right sidewall in FIG. 4) is not limited to being stepped with the sidewall of the gate electrode 40 (the right sidewall in FIG. 4), and may be flush with the sidewall of the gate electrode 40.

[0083] The term "on" as used in this disclosure includes the meanings "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the phrase "a first element is mounted on a second element" is intended to mean that in some embodiments, the first element may be directly disposed on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0084] The Z-axis direction used in this disclosure does not necessarily have to be vertical, and does not have to be completely vertical. Therefore, the various structures according to this disclosure are not limited to the "up" and "down" of the Z-axis direction described in this specification being "up" and "down" of the vertical direction. For example, the X-axis direction may be vertical, or the Y-axis direction may be vertical.

[0085] [Note] The technical ideas that can be understood from the above-mentioned embodiments and each modified example are described below. Note that the reference numerals of the components of the embodiments corresponding to the components described in each appendix are shown in parentheses. The reference numerals are shown as examples to aid in understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0086] (Appendix 1) an electron transit layer (26) made of a first nitride semiconductor; an electron supply layer (28) provided on the electron transit layer (26) and made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor; a gate layer (30) made of a third nitride semiconductor and provided on a portion of the electron supply layer (28); a gate electrode (40) provided on the gate layer (30); a source electrode (42) and a drain electrode (44) provided on the electron supply layer (28); The gate layer (30) is A first gate portion (31); A second gate portion (32); a recess (33) between the first gate portion (31) and the second gate portion (32), the gate electrode (40) is provided across both the first gate portion (31) and the second gate portion (32); The nitride semiconductor device (10) further comprises an insulating portion (80) formed in the recess (33).

[0087] (Appendix 2) The insulating portion (80) is a filling portion (81) filled in the recess (33) of the gate layer (30); an upper protruding portion (82) formed integrally with the filling portion (81) and protruding from the recess (33); 2. The nitride semiconductor device (10) of claim 1, comprising:

[0088] (Appendix 3) The upper protrusion (82) of the insulating portion (80) is a first overlap portion (82A) covering a part of an upper surface of the first gate portion (31); a second overlap portion (82B) covering a part of an upper surface of the second gate portion (32); 3. The nitride semiconductor device (10) of claim 2, comprising:

[0089] (Appendix 4) the first overlap portion (82A) extends in a first direction (-X) from a first opening end (33A) of the recess (33) corresponding to an upper inner edge of the first gate portion (31) by a first extension length (EL1) and covers an upper surface of the first gate portion (31); the second overlap portion (82B) extends from a second opening end (33B) of the recess (33) corresponding to an upper inner edge of the second gate portion (32) in a second direction (+X) opposite to the first direction (-X) by a second extension length (EL2) to cover an upper surface of the second gate portion (32); The nitride semiconductor device (10) according to appendix 3, wherein the first extension length (EL1) and the second extension length (EL2) are each not less than 10 nm and not more than 200 nm.

[0090] (Appendix 5) 5. The nitride semiconductor device (10) according to claim 3 or 4, wherein the first overlap portion (82A) and the second overlap portion (82B) each have a thickness of not less than 10 nm and not more than 200 nm.

[0091] (Appendix 6) the recess (33) includes a bottom (33C) made of the third nitride semiconductor, 6. The nitride semiconductor device (10) according to any one of claims 1 to 5, wherein the insulating portion (80) is provided on the bottom portion (33C) without contacting the electron supply layer (28).

[0092] (Appendix 7) the electron supply layer (28) is at least partially exposed in the recess (33); 6. The nitride semiconductor device (10) according to any one of claims 1 to 5, wherein the insulating portion (80) is in contact with the electron supply layer (28) within the recess (33).

[0093] (Appendix 8) the insulating portion (80) has a thickness smaller than a thickness of each of the first gate portion (31) and the second gate portion (32); 2. The nitride semiconductor device (10) according to claim 1, wherein a portion of the gate electrode (40) is embedded in the recess (33).

[0094] (Appendix 9) the source electrode (42) includes a source contact portion (42A) in contact with the electron supply layer (28), the drain electrode (44) includes a drain contact portion (44A) in contact with the electron supply layer (28); The gate layer (30) is a source side extension portion (34) extending from the first gate portion (31) toward the source contact portion (42A); a drain side extension portion (35) extending from the second gate portion (32) toward the drain contact portion (44A); A nitride semiconductor device (10) according to any one of appendices 1 to 8, comprising:

[0095] (Appendix 10) The nitride semiconductor device (10) according to any one of claims 1 to 9, wherein the insulating portion (80) is made of one of SiO2, SiN, SiON, Al2O3, AlN, and AlON, or any combination thereof.

[0096] (Appendix 11) the electron supply layer (28) is an AlGaN layer; The nitride semiconductor device (10) according to any one of appendixes 1 to 10, wherein the gate layer (30) is a GaN layer containing at least one of Mg and Zn as the acceptor-type impurity.

[0097] The above description is merely illustrative. Those skilled in the art may recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of describing the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and alterations that fall within the scope of the present disclosure, including the scope of the claims. [Explanation of symbols]

[0098] 10...Nitride semiconductor device 20...Semiconductor substrate 26...Electron transport layer 28…electron supply layer 30…Gate layer 31…First Gate 32…Second gate section 33…Recess 33A…First opening end 33B…Second opening end 33C…Bottom 34…Source side extension part 35...Drain side extension 40...Gate electrode 42...Source electrode 42A…Source contact section 44...Drain electrode 44A…Drain contact part 50…passivation layer 50A…Source opening 50B…Drain opening 60...Field plate electrode 80…Insulation part 81…Filling section 82...Top protrusion 82A…First overlap section 82B…Second overlap section EL1…First extension length EL2: Second extension length CL1: First contact length CL2: Second contact length T1…Thickness

Claims

1. an electron transit layer made of a first nitride semiconductor; an electron supply layer provided on the electron transit layer and made of a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor; a gate layer formed on a portion of the electron supply layer and made of a third nitride semiconductor; a gate electrode provided on the gate layer; a source electrode and a drain electrode provided on the electron supply layer, The gate layer is A first gate portion; A second gate portion; a recess between the first gate portion and the second gate portion, the gate electrode is provided across both the first gate portion and the second gate portion, The nitride semiconductor device further comprises an insulating portion formed in the recess.

2. The insulating portion is a filling portion filled in the recess of the gate layer; an upper protrusion formed integrally with the filling portion and protruding from the recess; The nitride semiconductor device according to claim 1 ,

3. The upper protrusion of the insulating part is a first overlap portion covering a portion of an upper surface of the first gate portion; a second overlap portion covering a portion of an upper surface of the second gate portion; The nitride semiconductor device according to claim 2 , comprising:

4. the first overlap portion extends in a first direction from a first opening end of the recess corresponding to an upper inner edge of the first gate portion by a first extension length to cover an upper surface of the first gate portion; the second overlap portion extends from a second opening end of the recess corresponding to an upper inner edge of the second gate portion in a second direction opposite to the first direction by a second extension length to cover an upper surface of the second gate portion; The nitride semiconductor device according to claim 3 , wherein said first extension length and said second extension length are each not less than 10 nm and not more than 200 nm.

5. The nitride semiconductor device according to claim 3 , wherein the first overlap portion and the second overlap portion each have a thickness of not less than 10 nm and not more than 200 nm.

6. the recess includes a bottom portion made of the third nitride semiconductor, The nitride semiconductor device according to claim 1 , wherein said insulating portion is provided on said bottom portion without being in contact with said electron supply layer.

7. the electron supply layer is at least partially exposed in the recess; The nitride semiconductor device according to claim 1 , wherein said insulating portion is in contact with said electron supply layer within said recess.

8. the insulating portion has a thickness smaller than a thickness of each of the first gate portion and the second gate portion; The nitride semiconductor device according to claim 1 , wherein a portion of said gate electrode is buried in said recess.

9. the source electrode includes a source contact portion in contact with the electron supply layer, the drain electrode includes a drain contact portion in contact with the electron supply layer, The gate layer is a source side extension portion extending from the first gate portion toward the source contact portion; a drain side extension portion extending from the second gate portion toward the drain contact portion; The nitride semiconductor device according to claim 1 ,

10. The insulating portion is made of SiO ２ , SiN, SiON, Al ２ O ３ 2. The nitride semiconductor device according to claim 1, wherein the nitride semiconductor device is made of one or a combination of two or more of AlN, AlN, and AlON.

11. the electron supply layer is an AlGaN layer; 11. The nitride semiconductor device according to claim 1, wherein the gate layer is a GaN layer containing at least one of Mg and Zn as an acceptor-type impurity.

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