Power supply control device and power supply device

Abstract

To provide a power supply control device and a power supply device for preventing an output voltage from rising when an abnormality occurs in a feedback terminal.SOLUTION: A power supply control device 10 includes: a feedback terminal FB; a feedback control circuit 11 that controls an output stage 12 of a power supply device X according to a feedback voltage Vfb applied to the feedback terminal FB; and a terminal inspection circuit 17 that forcibly stops driving the output stage 12 when it is detected that the feedback voltage Vfb is below a first threshold value and an output current IL flowing to the output stage 12 is above a second threshold value during a first period at startup time or the feedback voltage Vfb is below the first threshold value at the end of the first period.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present disclosure relates to a power supply control device and a power supply device. [Background technology]

[0002] 2. Description of the Related Art Power supply devices that generate a desired output voltage from an input voltage have been used as power supply means for various applications.

[0003] As an example of the related art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-213317 A

[0005] [overview] In conventional power supply devices, there is a risk that the output voltage will rise abnormally if a problem occurs in the output feedback terminal of the semiconductor device that serves as the main controller.

[0006] For example, a power supply control device according to the present disclosure includes a feedback terminal, a feedback control circuit configured to control an output stage of the power supply device according to a feedback voltage applied to the feedback terminal, and a terminal inspection circuit that forcibly stops driving the output stage when it is detected that the feedback voltage is below a first threshold value and an output current flowing through the output stage is above a second threshold value within a first interval at start-up, or when it is detected that the feedback voltage is below the first threshold value at the completion of the first interval.

[0007] Furthermore, for example, a power supply control device according to the present disclosure may include a feedback terminal, a feedback control circuit configured to control an output stage of the power supply device in accordance with a feedback voltage applied to the feedback terminal, an overvoltage protection circuit configured to forcibly stop driving of the output stage when the feedback voltage exceeds an overvoltage protection threshold, and a terminal inspection circuit that flows a source current from a node at a higher potential than the overvoltage protection threshold toward the feedback terminal for a predetermined period during startup. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing a comparative example of a power supply device. [Diagram 2] FIG. 2 is a diagram showing a startup waveform when the feedback terminal of the comparative example is normal. [Diagram 3] FIG. 3 is a diagram showing startup waveforms when the feedback terminal of the comparative example is abnormal (lower resistor open or upper resistor short). [Figure 4] FIG. 4 is a diagram showing startup waveforms when the feedback terminal of the comparative example is abnormal (upper resistor open or lower resistor short). [Diagram 5] FIG. 5 is a diagram showing startup waveforms when the feedback terminal of the comparative example is abnormal (upper and lower resistors are open). [Figure 6] FIG. 6 is a diagram showing a first embodiment of a power supply device. [Figure 7] FIG. 7 is a diagram showing startup waveforms when the feedback terminal in the first embodiment is abnormal (upper resistor open or lower resistor short). [Figure 8] FIG. 8 is a diagram showing a second embodiment of the power supply device. [Figure 9] FIG. 9 is a diagram showing startup waveforms when the feedback terminal of the second embodiment is abnormal (upper and lower resistors are open). [Figure 10] FIG. 10 is a diagram showing a startup waveform when the feedback terminal of the second embodiment is normal. [Figure 11] FIG. 11 is a diagram showing a third embodiment of the power supply device. [Figure 12]FIG. 12 is a diagram showing a startup waveform when the feedback terminal of the third embodiment is normal. [Figure 13] FIG. 13 is a diagram showing a fourth embodiment of the power supply device.

[0009] [Detailed Description] <Power supply device (comparative example)> Fig. 1 is a diagram showing a comparative example of a power supply device (= a configuration to be compared with the embodiments described later). The power supply device X of this comparative example is a step-down switching power supply (so-called DC / DC converter) that steps down an input voltage Vin to generate a desired output voltage Vout. With reference to this diagram, the power supply device X comprises a power supply control device 10 and various discrete components (a capacitor C1, an inductor L1, and resistors R1 and R2) that are externally attached thereto.

[0010] The power supply control device 10 is a semiconductor integrated circuit device (a so-called power supply control IC [integrated circuit]) that comprehensively controls the operation of the power supply device X. The power supply control device 10 has a plurality of external terminals (only a feedback terminal FB is shown in the figure) as a means for establishing an electrical connection with the outside of the device.

[0011] Next, the external connections of the power supply control device 10 will be described. A first terminal of the inductor L1 is connected to an application terminal of the switch voltage Vsw. A second terminal of the inductor L1 and a first terminal of each of the resistor R1 and the capacitor C1 are all connected to an application terminal of the output voltage Vout. A second terminal of the resistor R1 and a first terminal of the resistor R2 are all connected to a feedback terminal FB. A second terminal of each of the capacitor C1 and the resistor R2 are all connected to a ground terminal.

[0012] The inductor L1 and the capacitor C1 function as an LC filter that rectifies and smoothes a square-wave switch voltage Vsw (described in detail later) to generate an output voltage Vout.

[0013] The resistors R1 and R2 function as a resistor voltage divider circuit that generates a divided voltage Vdiv (=Vout×R2 / (R1+R2)) according to the output voltage Vout and outputs it to the feedback terminal FB. Although not shown in the figure, a speed-up capacitor may be connected in parallel across the resistor R1 to ensure smooth startup of the power supply device X.

[0014] <Power supply control device (comparison example)> The internal configuration and operation of the power supply control device 10 will be described in detail with reference to Fig. 1. In the power supply control device 10 of this comparative example, a feedback control circuit 11, an output stage 12 (more precisely, an output transistor M1 and a synchronous rectifier transistor M2 which form the output stage 12), a first overcurrent protection circuit 13, a second overcurrent protection circuit 14, a zero-cross detection circuit 15, and an overvoltage protection circuit 16 are integrated.

[0015] The feedback control circuit 11 controls the output stage 12 in response to a feedback voltage Vfb applied to a feedback terminal FB. Referring to the figure, the feedback control circuit 11 includes a soft-start voltage generation circuit 111, a reference voltage generation circuit 112, an error amplifier 113, a ripple voltage generation circuit 114, an adder circuit 115, a comparator 116, an on-time setting circuit 117, and a control drive circuit 118.

[0016] The soft-start voltage generating circuit 111 generates a soft-start voltage Vss that rises gently at a predetermined gradient when the power supply control device 10 is started up.

[0017] The reference voltage generating circuit 112 generates a predetermined reference voltage Vref (corresponding to a voltage signal for setting a target value of the output voltage Vout).

[0018] The error amplifier 113 generates an error voltage Vc according to the difference between the lower of the soft start voltage Vss and the reference voltage Vref input to the two non-inverting input terminals (+) and the feedback voltage Vfb input to the inverting input terminal (-). The error voltage Vc rises when the feedback voltage Vfb is lower than the lower of the soft start voltage Vss and the reference voltage Vref. The error voltage Vc falls when the feedback voltage Vfb is higher than the lower of the soft start voltage Vss and the reference voltage Vref.

[0019] The ripple voltage generating circuit 114 generates a ripple voltage Vrpl that simulates the ripple component of the output voltage Vout.

[0020] The adder circuit 115 adds the ripple voltage Vrpl to the feedback voltage Vfb to generate the slope voltage Vslp.

[0021] The comparator 116 compares the slope voltage Vslp input to the inverting input terminal (-) with the error voltage Vc input to the non-inverting input terminal (+) to generate a comparison signal S1. The comparison signal S1 goes high when the slope voltage Vslp is lower than the error voltage Vc. The comparison signal S1 goes low when the slope voltage Vslp is higher than the error voltage Vc. The comparator 116 may be provided with a hysteresis characteristic.

[0022] The on-time setting circuit 117 generates the switch control signal S2 so that the output transistor M1 is maintained in the on-state for the on-time Ton after the comparison signal S1 rises to a high level.

[0023] The control drive circuit 118 generates the gate drive signals G1 and G2 as basic output feedback control by a bottom detection type fixed on-time method according to the switch control signal S0 so that the output voltage Vout coincides with a desired target value. For example, the gate drive signals G1 and G2 are at a low level when the switch control signal S2 is at a high level, and are at a high level when the switch control signal S2 is at a low level.

[0024] The control drive circuit 118 has a function of limiting the output current IL (=current flowing through the inductor L1) flowing through the output stage 12 in response to the upper overcurrent protection signal S3 and the lower overcurrent protection signal S4.

[0025] The control drive circuit 118 also has a function of stopping the switching drive of the output stage 12 under a light load in response to the zero-cross detection signal S5. For example, the control drive circuit 118 may turn off the synchronous rectification transistor M2 when the zero-cross detection signal S5 rises to a high level while the output transistor M1 is in an off state and the synchronous rectification transistor M2 is in an on state, that is, when it is detected that the switch voltage Vsw has become higher than a zero-cross detection value (for example, GND).

[0026] The control drive circuit 118 also has a function of forcibly stopping the switching drive of the output stage 12 in response to the overvoltage protection signal S6.

[0027] The output stage 12 generates an output voltage Vout from an input voltage Vin under the control of the power supply control device 10. The output stage 12 may be of a switching type including an output transistor M1 (e.g., a PMOSFET [P-channel type metal oxide semiconductor field effect transistor]) and a synchronous rectifier transistor M2 (e.g., an NMOSFET [N-channel type MOSFET]) in addition to the inductor L1 and capacitor C1 described above.

[0028] The output transistor M1 functions as an upper switch element of the output stage 12. The source of the output transistor M1 is connected to an application terminal of the input voltage Vin. The drain of the output transistor M1 is connected to an application terminal of the switch voltage Vsw. The gate of the output transistor M1 is connected to an application terminal of the gate drive signal G1. The output transistor M1 is in an on state when the gate drive signal G1 is at a low level. On the other hand, the output transistor M1 is in an off state when the gate drive signal G1 is at a high level.

[0029] The synchronous rectifier transistor M2 functions as a lower-side switch element of the output stage 12. The drain of the synchronous rectifier transistor M2 is connected to an application terminal of the switch voltage Vsw. The source of the synchronous rectifier transistor M2 is connected to a reference potential terminal (e.g., a ground terminal to which a ground voltage GND is applied). The gate of the synchronous rectifier transistor M2 is connected to an application terminal of a gate drive signal G2. The synchronous rectifier transistor M2 is in an ON state when the gate drive signal G2 is at a high level. On the other hand, the synchronous rectifier transistor M2 is in an OFF state when the gate drive signal G2 is at a low level.

[0030] In this way, the output transistor M1 and the synchronous rectifier transistor M2 are connected in a half-bridge configuration and are complementarily turned on / off in response to the gate drive signals G1 and G2. By such switching control, the output stage 12 generates a square-wave switch voltage Vsw that is pulse-driven between the input voltage Vin and the ground voltage GND.

[0031] In this specification, the term "complementary" is used to mean not only the case where the on / off states of the output transistor M1 and the synchronous rectifier transistor M2 are completely reversed, but also the case where a delay is provided in the timing of their on / off transitions (i.e., the case where a simultaneous off period is provided).

[0032] As the rectifying element, a rectifying diode (e.g., a Schottky barrier diode) having a cathode connected to the application terminal of the switch voltage Vsw and an anode connected to the ground terminal may be used instead of the synchronous rectifying transistor M2. In other words, the rectifying method of the output stage 12 is not limited to the synchronous rectifying method, and may be a diode rectifying method.

[0033] Furthermore, the output transistor M1 and the synchronous rectifier transistor M2 may be externally attached to the power supply control device 10. Furthermore, if the output stage 12 needs to have a high withstand voltage, high-voltage elements such as an IGBT [insulated gate bipolar transistor], a SiC device, or a GaN device may be used as the output transistor M1 and the synchronous rectifier transistor M2.

[0034] The upper overcurrent protection circuit 13 generates an upper overcurrent protection signal S3 so as to limit the upper output current IL1 flowing through the on-state output transistor M1 to a predetermined overcurrent protection threshold Iocp or less. The upper overcurrent protection circuit 13 may include a comparator that generates the upper overcurrent protection signal S3 by comparing the drain-source voltage of the output transistor M1 with a predetermined input offset voltage.

[0035] The low-side overcurrent protection circuit 14 generates a low-side overcurrent protection signal S4 so as to limit the low-side output current IL2 flowing through the on-state synchronous rectification transistor M2 to a predetermined overcurrent protection threshold Iocp or less. The low-side overcurrent protection circuit 14 may include a comparator that generates the low-side overcurrent protection signal S4 by comparing the drain-source voltage of the synchronous rectification transistor M2 with a predetermined input offset voltage.

[0036] When the output transistor M1 is in an off state and the synchronous rectifier transistor M2 is in an on state, the zero-cross detection circuit 15 detects a zero-cross (reverse flow) of the lower-side output current IL2 flowing through the synchronous rectifier transistor M2 and generates a zero-cross detection signal S5. For example, the zero-cross detection circuit 15 may include a comparator that detects whether the drain-source voltage (corresponding to the switch voltage Vsw) of the synchronous rectifier transistor M2 is positive or negative, thereby generating the zero-cross detection signal S5.

[0037] When the feedback voltage Vfb exceeds a predetermined overvoltage protection threshold Vovp, the overvoltage protection circuit 16 generates an overvoltage protection signal S6 to forcibly stop the switching drive of the output stage 12. Note that the overvoltage protection threshold Vovp is preferably set to a voltage value higher than the reference voltage Vref.

[0038] The feedback control circuit 11 of this configuration example controls the output stage 12 so that the feedback voltage Vfb coincides with the lower of the soft start voltage Vss and the reference voltage Vref. Therefore, when resistors R1 and R2 are properly connected externally to the feedback terminal FB, Vout=Vref×(R1+R2) / R2 is established. That is, the output voltage Vout can be arbitrarily adjusted according to the resistance ratio of the resistors R1 and R2 (corresponding to the voltage division ratio of the resistor voltage divider circuit).

[0039] 2 is a diagram showing the startup waveforms when the feedback terminal FB of the comparative example is normal, that is, when resistors R1 and R2 are properly connected externally to the feedback terminal FB. The upper part of the figure shows the behavior of the output voltage Vout. The lower part of the figure shows the behavior of the soft start voltage Vss and the feedback voltage Vfb.

[0040] As shown in this figure, when the feedback terminal FB is normal, Vdiv = Vfb. Note that while Vss < Vref, the feedback voltage Vfb gradually rises following the soft start voltage Vss. Therefore, the output voltage Vout also gradually rises. Then, when Vss > Vref, feedback control is applied so that the feedback voltage Vfb matches the reference voltage Vref. Therefore, the output voltage Vout is maintained at the desired target value (= Vref × (R1 + R2) / R2).

[0041] Figure 3 is a diagram showing the startup waveforms when the feedback terminal FB of the comparative example is abnormal (lower resistor open or upper resistor short). The lower resistor open can be understood as a state where the first end of resistor R2 is not correctly connected to the feedback terminal FB, the second end of resistor R2 is not correctly connected to the ground terminal, or both occur. The upper resistor short can be understood as a state where both ends of resistor R1 are short-circuited. Note that the behavior of the output voltage Vout is shown in the upper part of this figure. Also, the behaviors of the soft start voltage Vss and the feedback voltage Vfb are depicted in the lower part of this figure.

[0042] As shown in this figure, when an open in the lower resistor or a short in the upper resistor of the feedback terminal FB occurs, Vout = Vfb. Therefore, the output voltage Vout only rises up to the reference voltage Vref. That is, the output voltage Vout fails to reach the desired target value (= Vref × (R1 + R2) / R2). Therefore, there is a possibility of hindering the operation of the load receiving the supply of the output voltage Vout.

[0043] However, conversely, the output voltage Vout does not exceed the target value. In other words, there is no concern that the output voltage Vout exceeds the breakdown voltage of the load. Therefore, without taking any special measures, the safety of the power supply device X and the load (and thus the entire system) is not impaired.

[0044] FIG. 4 is a diagram showing the start-up waveform when the feedback terminal FB of the comparative example is abnormal (upper resistor open or lower resistor short). The upper resistor open can be understood as a state in which the first end of the resistor R1 is not properly connected to the application end of the output voltage Vout, the second end of the resistor R1 is not properly connected to the feedback terminal FB, or both of these occur. The lower resistor short can be understood as a state in which both ends of the resistor R2 are short-circuited. In particular, the lower resistor short may be understood as a grounded state of the feedback terminal FB (= a short-circuited state to the ground end or a low potential end equivalent thereto). The upper part of this figure shows the behavior of the output voltage Vout. The lower part of this figure shows the behavior of the soft-start voltage Vss and the feedback voltage Vfb.

[0045] As shown in this figure, when the upper resistor of the feedback terminal FB is open or the lower resistor is short, the feedback voltage Vfb sticks to a low level (=ground voltage GND). Therefore, feedback control is applied so as to raise the output voltage Vout indefinitely. Also, since the feedback voltage Vfb does not exceed the overvoltage protection threshold Vovp, the switching drive of the output stage 12 continues. As a result, the output voltage Vout exceeds the desired target value (=Vref×(R1+R2) / R2) and rises to the input voltage Vin. In such a situation, there is a risk that the output voltage Vout will exceed the withstand voltage of the load.

[0046] FIG. 5 is a diagram showing the startup waveform when the feedback terminal FB of the comparative example is abnormal (upper and lower resistors open). Upper and lower resistors open can be understood as a state in which both the upper resistor open and the lower resistor open occur. The upper part of this figure shows the behavior of the output voltage Vout. The lower part of this figure shows the behavior of the soft start voltage Vss and the feedback voltage Vfb.

[0047] As shown in this figure, when an open circuit occurs in the upper and lower resistors of the feedback terminal FB, the feedback voltage Vfb becomes indeterminate (refer to the dashed frame of the feedback voltage Vfb). Therefore, the output voltage Vout also becomes indeterminate and can rise up to the input voltage Vin exceeding the desired target value (= Vref × (R1 + R2) / R2) (refer to the dashed frame of the output voltage Vout). When such a situation occurs, there is a risk that the output voltage Vout exceeds the breakdown voltage of the load. In particular, in the situation where Vref < Vfb < Vovp, the output voltage Vout is maintained in a state exceeding the target value without overvoltage protection being applied.

[0048] In the following, in view of the above considerations, a power supply device X that can prevent an increase (overvoltage) in the output voltage Vout during an abnormality in the feedback terminal FB is proposed.

[0049] <Power Supply Device (First Embodiment)> FIG. 6 is a diagram showing a first embodiment of the power supply device. The power supply device X of the present embodiment further includes a terminal inspection circuit 17 while being based on the previous comparative example (FIG. 1). In the first embodiment, as will be described in detail below, the generation of overvoltage associated with an open circuit in the upper resistor or a short circuit in the lower resistor of the feedback terminal FB can be prevented.

[0050] The terminal inspection circuit 17 detects an abnormality in the feedback terminal FB at the start-up of the power supply device X and forcibly stops the switching drive of the output stage 12. Speaking with reference to this figure, the terminal inspection circuit 17 includes a detection interval setting circuit 171 and a lower limit detection circuit 172.

[0051] Also, the terminal inspection circuit 17 can be understood as a functional block including not only the detection interval setting circuit 171 and the lower limit detection circuit 172 but also a control drive circuit 118, an upper overcurrent protection circuit 13, and a lower overcurrent protection circuit 14.

[0052] The detection section setting circuit 171 generates a detection section setting signal S7 for setting the abnormality detection section Tchk of the feedback terminal FB. The control drive circuit 118, which functions as a part of the terminal inspection circuit 17, sets the abnormality detection section Tchk of the feedback terminal FB at the start of the power supply device X in response to the detection section setting signal S7. The detection section setting signal S7 may be, for example, a binary signal whose logic level changes in response to a comparison result between the soft start voltage Vss and the detection section completion threshold Vchk. The detection section completion threshold Vchk may be set to a reference voltage Vref or a voltage value lower than the reference voltage Vref. In this case, the control drive circuit 118 completes the abnormality detection section Tchk at the time when the soft start voltage Vss exceeds the detection section completion threshold Vchk.

[0053] The lower limit detection circuit 172 generates a lower limit detection signal S8 by comparing the feedback voltage Vfb with a predetermined lower limit detection threshold VfbL. The lower limit detection threshold VfbL is preferably set to a voltage value lower than the reference voltage Vref. The lower limit detection threshold VfbL is also preferably set to a voltage value lower than the detection section completion threshold Vchk.

[0054] The control drive circuit 118 detects an abnormality in the feedback terminal FB based on the detection section setting signal S7, the lower limit detection signal S8, the upper overcurrent protection signal S3, and the lower overcurrent protection signal S4. For example, when the control drive circuit 118 detects that the feedback voltage Vfb is below the lower limit detection threshold VfbL within the abnormality detection section Tchk at the time of startup and the output current IL flowing through the output stage 12 is above the upper limit detection threshold (for example, the overcurrent protection threshold Iocp), the control drive circuit 118 forcibly stops the switching drive of the output stage 12.

[0055] 7 is a diagram showing the startup waveform when the feedback terminal FB of the first embodiment is abnormal (upper resistor open or lower resistor short). The upper part of the figure shows the behavior of the output voltage Vout. The middle part of the figure shows the behavior of the soft start voltage Vss and the feedback voltage Vfb. The lower part of the figure shows the behavior of the output current IL.

[0056] As described above in FIG. 4, when the upper resistor of the feedback terminal FB is open or the lower resistor is short, the feedback voltage Vfb sticks to a low level (=ground voltage GND). Therefore, feedback control is applied to keep raising the output voltage Vout. Also, since the feedback voltage Vfb does not exceed the overvoltage protection threshold Vovp, the switching drive of the output stage 12 continues. Therefore, unless some measure is taken, the output voltage Vout may exceed the target value (=Vref×(R1+R2) / R2) and rise to the input voltage Vin.

[0057] On the other hand, in the power supply device X of this embodiment, when an abnormality in the feedback terminal FB is detected at startup, the switching drive of the output stage 12 is forcibly stopped. In accordance with this figure, when it is detected that the feedback voltage Vfb is below the lower limit detection threshold VfbL within the abnormality detection section Tchk at startup and the output current IL flowing through the output stage 12 is above the upper limit detection threshold (= overcurrent protection threshold Iocp), the switching drive of the output stage 12 is forcibly stopped.

[0058] According to such an abnormality protection operation of the feedback terminal FB, the switching drive of the output stage 12 is forcibly stopped before the output voltage Vout exceeds the target value (=Vref×(R1+R2) / R2). Therefore, the safety of the power supply device X and the load (and therefore the entire system) is improved.

[0059] As a modification of the above, the terminal inspection circuit 17 may forcibly stop the switching drive of the output stage 12 when it is detected that the feedback voltage Vfb is below the lower limit detection threshold VfbL at the completion point of the abnormality detection section Tchk. In this case, the upper side overcurrent protection circuit 13 and the lower side overcurrent protection circuit 14 may be excluded from the components of the terminal inspection circuit 17.

[0060] <Power supply device (second embodiment)> Fig. 8 is a diagram showing a second embodiment of the power supply device. The power supply device X of this embodiment is based on the above-mentioned first embodiment (Fig. 6), but has additional components added to the terminal inspection circuit 17. Referring to this figure, the terminal inspection circuit 17 includes a current source 173 and a switch 174 in addition to the above-mentioned detection range setting circuit 171 and lower limit detection circuit 172. Note that in the second embodiment, as will be described in detail below, not only can the occurrence of an upper resistor open or a lower resistor short in the feedback terminal FB be prevented, but also the occurrence of an overvoltage caused by an upper and lower resistor open in the feedback terminal FB.

[0061] A first terminal of the current source 173 is connected to an application terminal of the input voltage Vin. A second terminal of the current source 173 is connected to a first terminal of the switch 174. A second terminal of the switch 174 is connected to a feedback terminal FB. The current source 173 generates a predetermined source current I1. The switch 174 is turned on / off in response to a switching signal S9. For example, the switch 174 may be in an on state throughout a current supply section Tcs that is set when the power supply device X is started up, and in an off state during the remaining section.

[0062] In this way, the terminal inspection circuit 17 causes the source current I1 to flow from a node having a higher potential than the overvoltage protection threshold Vovp (the application terminal of the input voltage Vin in this figure) to the feedback terminal FB throughout the current supply section Tcs at startup. The technical significance of this will be described in detail below.

[0063] 9 is a diagram showing the startup waveform when the feedback terminal FB of the second embodiment is abnormal (upper and lower resistors are open). The upper part of the figure shows the behavior of the output voltage Vout. The lower part of the figure shows the behavior of the feedback voltage Vfb.

[0064] As described above in Figure 5, when the upper and lower resistors of the feedback terminal FB are open, the feedback voltage Vfb becomes unstable. Therefore, the output voltage Vout also becomes unstable. Therefore, unless some countermeasure is taken, the output voltage Vout may exceed the desired target value (=Vref×(R1+R2) / R2) and rise to the input voltage Vin.

[0065] On the other hand, in the power supply device X of this embodiment, the source current I1 is flowed into the feedback terminal FB in an open state throughout the current supply section Tcs at startup. Therefore, immediately after the power supply device X is started up, the feedback voltage Vfb rises to exceed the overvoltage protection threshold Vovp. As a result, the existing overvoltage protection function forcibly stops the switching drive of the output stage 12. In other words, when the feedback terminal FB is in an open state, the output voltage Vout does not rise even when the power supply device X is started up (see the solid and dashed lines in the upper row).

[0066] According to such an abnormality protection operation of the feedback terminal FB, the switching drive of the output stage 12 is forcibly stopped before the output voltage Vout exceeds the target value (=Vref×(R1+R2) / R2). Therefore, the safety of the power supply device X and the load (and therefore the entire system) is improved.

[0067] 10 is a diagram showing the startup waveform when the feedback terminal FB of the second embodiment is normal. The upper part of the figure shows the behavior of the output voltage Vout. The lower part of the figure shows the behavior of the soft start voltage Vss and the feedback voltage Vfb.

[0068] When the feedback terminal FB is normal, in the current supply section Tcs described above, the source current I1 is added to the current flowing through the resistor R2. Therefore, as shown in this figure, a negative offset component -ΔVofs caused by the increase in the voltage across the resistor R2 is added to the output voltage Vout. However, the source current I1 is stopped after the current supply section Tcs is completed. Therefore, the above-mentioned offset component -ΔVofs is not added to the output voltage Vout after startup. For example, if the current supply section Tcs is set to complete before the soft-start voltage Vss exceeds the reference voltage Vref, there is no particular problem with the steady-state operation of the power supply device X.

[0069] Furthermore, when care for an open circuit in the upper resistor or a short circuit in the lower resistor of the feedback terminal FB is not taken into consideration, the detection range setting circuit 171 and the lower limit detection circuit 172 described above may be omitted.

[0070] <Power supply device (third embodiment)> Fig. 11 is a diagram showing a third embodiment of the power supply device. The power supply device X of this embodiment is based on the first embodiment (Fig. 6) above, but the components of the terminal inspection circuit 17 are changed. Referring to this figure, the terminal inspection circuit 17 includes a current source 175 and a switch 176 instead of the current source 173 and switch 174 described above. Note that in the third embodiment, as will be described in detail below, not only can the occurrence of an upper resistor open or a lower resistor short in the feedback terminal FB be prevented, but also the occurrence of an overvoltage caused by an upper and lower resistor open in the feedback terminal FB.

[0071] A first terminal of the current source 175 is connected to the ground terminal. A second terminal of the current source 175 is connected to a first terminal of a switch 176. A second terminal of the switch 176 is connected to a feedback terminal FB. The current source 175 generates a predetermined sink current I2. The switch 176 is turned on / off in response to a switching signal S9. For example, the switch 176 may be in an on state throughout a current supply section Tcs that is set when the power supply device X is started up, and in an off state during the remaining section.

[0072] In this way, the terminal inspection circuit 17 causes the sink current I2 to flow from the feedback terminal FB to a node (ground terminal in this figure) at a potential lower than the lower limit detection threshold VfbL over the current supply section Tcs at startup. The technical significance of this will be described in detail below.

[0073] As described above in Figure 5, when the upper and lower resistors of the feedback terminal FB are open, the feedback voltage Vfb becomes unstable. Therefore, the output voltage Vout also becomes unstable. Therefore, unless some countermeasure is taken, the output voltage Vout may exceed the desired target value (=Vref×(R1+R2) / R2) and rise to the input voltage Vin.

[0074] On the other hand, in the power supply device X of the third embodiment, the sink current I2 is drawn from the feedback terminal FB in an open state throughout the current supply section Tcs at startup. Therefore, the feedback voltage Vfb is stuck at a low level (=ground voltage GND). Therefore, the startup waveform when the feedback terminal FB is abnormal (upper and lower resistors open) is the same as that shown in FIG. 7 above.

[0075] For example, the current supply section Tcs may coincide with the abnormality detection section Tchk or may be included in the abnormality detection section Tchk. With such a setting, it is detected that the feedback voltage Vfb is below the lower limit detection threshold VfbL and the output current IL flowing through the output stage 12 is above the upper limit detection threshold (= overcurrent protection threshold Iocp) within the abnormality detection section Tchk at the time of startup. As a result, the switching drive of the output stage 12 is forcibly stopped.

[0076] According to such an abnormality protection operation of the feedback terminal FB, the switching drive of the output stage 12 is forcibly stopped before the output voltage Vout exceeds the target value (=Vref×(R1+R2) / R2). Therefore, the safety of the power supply device X and the load (and therefore the entire system) is improved.

[0077] 12 is a diagram showing the startup waveform when the feedback terminal FB of the third embodiment is normal. The upper part of the figure shows the behavior of the output voltage Vout. The lower part of the figure shows the behavior of the soft start voltage Vss and the feedback voltage Vfb.

[0078] When the feedback terminal FB is normal, in the current supply section Tcs mentioned above, the sink current I2 is subtracted from the current flowing through resistor R2. Therefore, as shown in this figure, a positive offset component +ΔVofs caused by the voltage drop across resistor R2 is applied to the output voltage Vout. However, the sink current I2 is stopped after the current supply section Tcs is completed. Therefore, the above-mentioned offset component +ΔVofs is not applied to the output voltage Vout after startup. For example, if the current supply section Tcs is set to complete before the soft-start voltage Vss exceeds the reference voltage Vref, there is no particular problem with the steady-state operation of the power supply device X.

[0079] <Power supply device (fourth embodiment)> 13 is a diagram showing a fourth embodiment of the power supply device. The power supply device Y of this embodiment is a step-down linear power supply (e.g., an LDO [low drop out] regulator) that steps down an input voltage Vin to generate a desired output voltage Vout. With reference to this figure, the power supply device Y includes a power supply control device 20 and various discrete components (a capacitor C2, resistors R3 and R4) that are externally attached thereto.

[0080] The power supply control device 20 is a semiconductor integrated circuit device (so-called power supply control IC) that comprehensively controls the operation of the power supply device Y. The power supply control device 20 includes a plurality of external terminals (only a feedback terminal FB is illustrated in this figure) as a means for establishing an electrical connection with the outside of the device.

[0081] Next, the external connections of the power supply control device 20 will be described. The first terminals of the resistor R3 and the capacitor C2 are both connected to the application terminal of the output voltage Vout. The second terminal of the resistor R3 and the first terminal of the resistor R4 are both connected to the feedback terminal FB. The second terminals of the capacitor C2 and the resistor R4 are both connected to the ground terminal.

[0082] The resistors R3 and R4 function as a resistor voltage divider circuit that generates a divided voltage Vdiv (=Vout×R4 / (R3+R4)) according to the output voltage Vout and outputs it to the feedback terminal FB. Although not shown in the figure, a speed-up capacitor may be connected in parallel across the resistor R3 to ensure smooth startup of the power supply Y.

[0083] <Power supply control device (fourth embodiment)> The internal configuration and operation of the power supply control device 20 will be described in detail with reference to Fig. 13. In the power supply control device 20 of this embodiment, a feedback control circuit 21, an overvoltage protection circuit 22, and a terminal inspection circuit 23 are integrated.

[0084] The feedback control circuit 21 controls the linear output stage so that the feedback voltage Vfb applied to the feedback terminal FB coincides with the lower of the soft start voltage Vss and the reference voltage Vref. Therefore, when resistors R3 and R4 are properly connected externally to the feedback terminal FB, Vout=Vref×(R3+R4) / R4 holds. That is, the output voltage Vout can be arbitrarily adjusted according to the resistance ratio of the resistors R3 and R4 (corresponding to the voltage division ratio of the resistor voltage divider circuit).

[0085] The feedback control circuit 21 may incorporate an output transistor as a linear output stage, which is connected between the application terminal of the input voltage Vin and the application terminal of the output voltage Vout.

[0086] The overvoltage protection circuit 22 forcibly stops the linear drive of the feedback control circuit 21 (particularly the output stage) when the feedback voltage Vfb exceeds a predetermined overvoltage protection threshold Vovp.

[0087] The terminal inspection circuit 23 detects an abnormality in the feedback terminal FB when the power supply Y is started up, and forcibly stops the linear drive of the feedback control circuit 21 (particularly the output stage). The configuration and operation of the terminal inspection circuit 23 may be arbitrarily applied to the first to third embodiments (FIGS. 6, 8, and 11). Therefore, a duplicated description will be omitted.

[0088] <Additional Notes> The following is an additional note regarding the above disclosure.

[0089] For example, a power supply control device according to the present disclosure is configured (first configuration) to include a feedback terminal, a feedback control circuit configured to control an output stage of the power supply device according to a feedback voltage applied to the feedback terminal, and a terminal inspection circuit that forcibly stops driving the output stage when it is detected that the feedback voltage is below a first threshold and the output current flowing to the output stage is above a second threshold within a first interval at start-up, or when it is detected that the feedback voltage is below the first threshold at the completion of the first interval.

[0090] In addition, the power supply control device according to the first configuration described above may be configured (second configuration) to further include an overvoltage protection circuit configured to forcibly stop driving the output stage when the feedback voltage exceeds an overvoltage protection threshold.

[0091] In addition, in the power supply control device having the above-mentioned second configuration, the terminal inspection circuit may be configured (third configuration) to flow a source current from a node having a higher potential than the overvoltage protection threshold to the feedback terminal over a second period during startup.

[0092] In addition, in the power supply control device having the above first or second configuration, the terminal inspection circuit may be configured (fourth configuration) to flow a sink current from the feedback terminal to a node having a lower potential than the first threshold value over a second period during startup.

[0093] In addition, in a power supply control device having any of the first to fourth configurations, the feedback control circuit may be configured (fifth configuration) to control the output stage so that the feedback voltage matches the lower of a soft-start voltage that rises at a predetermined gradient at start-up and a predetermined reference voltage.

[0094] In addition, in the power supply control device of the above-mentioned fifth configuration, the terminal inspection circuit may be configured (sixth configuration) to complete the first section when the soft-start voltage exceeds the reference voltage or a third threshold value lower than the reference voltage.

[0095] In addition, the power supply control device according to any one of the first to sixth configurations may further include an overcurrent protection circuit configured to limit the output current to an overcurrent protection threshold or less, and the terminal inspection circuit may be configured to set the overcurrent protection threshold as the second threshold (seventh configuration).

[0096] Furthermore, for example, the power supply control device according to the present disclosure may be configured (eighth configuration) to include a feedback terminal, a feedback control circuit configured to control an output stage of the power supply device in accordance with a feedback voltage applied to the feedback terminal, an overvoltage protection circuit configured to forcibly stop driving of the output stage when the feedback voltage exceeds an overvoltage protection threshold, and a terminal inspection circuit that flows a source current from a node at a higher potential than the overvoltage protection threshold toward the feedback terminal for a predetermined period during startup.

[0097] Furthermore, for example, a power supply device according to the present disclosure is configured (ninth configuration) to include a power supply control device having any one of the first to eighth configurations described above, an output stage configured to be controlled by the power supply control device to generate an output voltage from an input voltage, and a resistive voltage divider circuit configured to generate a divided voltage of the output voltage and output it to the feedback terminal.

[0098] In the power supply device according to the ninth configuration, the output stage may be of a switching type or a linear type (tenth configuration).

[0099] According to the present disclosure, an increase in the output voltage can be prevented when an abnormality occurs in the feedback terminal.

[0100] <Other> In addition, various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation, in addition to the above-mentioned embodiment. In other words, the above-mentioned embodiment should be considered to be illustrative and not restrictive in all respects. In addition, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0101] 10 Power supply control device 11 Feedback control circuit 111 Soft start voltage generation circuit 112 Reference voltage generation circuit 113 Error Amplifier 114 Ripple voltage generation circuit 115 Adding Circuit 116 Comparator 117 ON time setting circuit 118 Control drive circuit 12 Output stage 13 1st overcurrent protection circuit 14 2nd overcurrent protection circuit 15 Zero-cross detection circuit 16 Overvoltage protection circuit 17 Terminal inspection circuit 171 Detection section setting circuit 172 Lower limit detection circuit 173 Current source 174 Switch 175 Current source 176 Switch 20 Power supply control device 21 Feedback control circuit 22 Overvoltage protection circuit 23 Terminal inspection circuit C1, C2 capacitors FB Feedback pin L1 Inductor M1 Output transistor M2 Synchronous rectifier transistor R1, R2, R3, R4 resistance X Power supply (switching power supply) Y Power Supply (Linear Power Supply)

Claims

1. A feedback terminal; a feedback control circuit configured to control an output stage of the power supply device in response to a feedback voltage applied to the feedback terminal; a terminal inspection circuit that forcibly stops driving the output stage when it is detected that the feedback voltage is below a first threshold value and the output current flowing through the output stage is above a second threshold value during a first period during startup, or when it is detected that the feedback voltage is below the first threshold value at the completion of the first period; A power supply control device comprising:

2. The power supply control device of claim 1 , further comprising an overvoltage protection circuit configured to forcibly stop driving the output stage when the feedback voltage is above an overvoltage protection threshold.

3. 3 . The power supply control device according to claim 2 , wherein the terminal inspection circuit causes a source current to flow from a node having a higher potential than the overvoltage protection threshold to the feedback terminal throughout a second interval during startup.

4. 2 . The power supply control device according to claim 1 , wherein the terminal inspection circuit flows a sink current from the feedback terminal to a node having a lower potential than the first threshold value over a second interval during startup.

5. 2. The power supply control device according to claim 1, wherein the feedback control circuit controls the output stage so that the feedback voltage coincides with the lower of a soft start voltage that rises at a predetermined gradient at start-up and a predetermined reference voltage.

6. 6. The power supply control device according to claim 5, wherein the terminal inspection circuit completes the first section when the soft-start voltage exceeds the reference voltage or a third threshold value lower than the reference voltage.

7. an overcurrent protection circuit configured to limit the output current below an overcurrent protection threshold; The power supply control device according to claim 1 , wherein the terminal inspection circuit sets the overcurrent protection threshold as the second threshold.

8. A feedback terminal; a feedback control circuit configured to control an output stage of the power supply device in response to a feedback voltage applied to the feedback terminal; an overvoltage protection circuit configured to forcibly stop driving the output stage when the feedback voltage exceeds an overvoltage protection threshold; a terminal inspection circuit that causes a source current to flow from a node having a potential higher than the overvoltage protection threshold to the feedback terminal over a predetermined period during startup; A power supply control device comprising:

9. A power supply control device according to any one of claims 1 to 8, the output stage configured to be controlled by the power supply controller to generate an output voltage from an input voltage; a resistor voltage divider circuit configured to generate a divided voltage of the output voltage and output the divided voltage to the feedback terminal; A power supply device comprising:

10. 10. The power supply of claim 9, wherein the output stage is of the switching or linear type.

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