Control device for solar electric power generating system
Patent Information
- Application Number
- JP2023139725
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-08-30
- Publication Date
- 2025-03-13
- Estimated Expiration
- 2043-08-30
AI Technical Summary
【0007】 上記の技術思想では、最大効率電圧を探索するにあたって所定範囲全体を走査するのに要する時間を短縮できる。
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Figure 2025033765000001_ABST
Abstract
Description
[Technical field]
[0001] The present invention relates to a control device for a solar power generation system. [Background technology]
[0002] The vehicle disclosed in Patent Document 1 includes a solar panel, a DCDC converter, and a control device. The solar panel generates power by receiving sunlight. The solar panel outputs the generated power to the DCDC converter. The DCDC converter converts the output voltage from the solar panel and outputs the converted voltage. The control device controls the output voltage of the DCDC converter.
[0003] The control device performs a scanning process to determine a reference voltage that is a reference for controlling the DCDC converter. In the scanning process, the control device monitors the output power of the DCDC converter obtained at each output voltage while gradually changing the output voltage of the DCDC converter within a predetermined range. Then, the control device determines the output voltage of the DCDC converter when the output power of the DCDC converter is maximized as the reference voltage. Then, the control device controls the DCDC converter so that the output voltage of the DCDC converter approaches the determined reference voltage. [Prior art documents] [Patent documents]
[0004] [Patent Document 1] JP 2020-141545 A Summary of the Invention [Problem to be solved by the invention]
[0005] In a technique such as that of Patent Document 1, which searches for a reference voltage by a scan process, in order to start normal control as soon as possible, it is necessary to shorten the time required for the scan process as much as possible. However, Patent Document 1 does not consider this point. [Means for solving the problem]
[0006] A control device for a solar power generation system for solving the above problems is applied to a solar power generation system including a solar panel and a DCDC converter that converts the output voltage of the solar panel into a voltage and outputs the converted voltage. The control device is capable of executing the following: searching for a maximum efficiency voltage, which is the output voltage of the DCDC converter at which the output power of the DCDC converter is maximum within the predetermined range, by scanning the output voltage of the DCDC converter within a predetermined range; and controlling the output voltage of the DCDC converter so as to approach the maximum efficiency voltage. In searching for the maximum efficiency voltage, the control device controls the output voltage of the DCDC converter to a first voltage within the predetermined range; The method sequentially performs the following operations: acquiring, as a first power, an output power of the DCDC converter when the output voltage of the DCDC converter is controlled to the first voltage; controlling the output voltage of the DCDC converter to a second voltage within the specified range obtained by changing the output voltage of the DCDC converter from the first voltage by a first change width; acquiring, as a second power, an output power of the DCDC converter when the output voltage of the DCDC converter is controlled to the second voltage; and controlling the output voltage of the DCDC converter to a third voltage within the specified range obtained by changing the output voltage of the DCDC converter from the second voltage by a second change width in the same direction as the first change width. When the second power is smaller than the first power, the second change width is set to a value larger than the first change width. Effect of the Invention
[0007] The above concept reduces the time required to scan the entire range in search of the most efficient voltage. [Brief description of the drawings]
[0008] [Figure 1] FIG. 1 is a schematic diagram of a vehicle. [Diagram 2] FIG. 2 is a time chart for explaining the execution timing of the scan process and the normal process. [Diagram 3]FIG. 3 is a diagram illustrating an example of a PV characteristic line. [Figure 4] FIG. 4 is a flowchart showing the procedure of the scan process. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0009] Hereinafter, an embodiment of a control device for a solar power generation system will be described with reference to the drawings. <Overall composition> As shown in FIG. 1, the vehicle 100 includes a solar panel 70, a converter unit 30, a driving battery 80, an auxiliary battery 90, and a control device 20.
[0010] The solar panel 70 is configured by arranging a plurality of solar cells that generate electricity by irradiation with sunlight in a panel shape. The solar panel 70 is installed, for example, on the roof of the vehicle 100. The solar panel 70 may also be installed on the hood of the vehicle 100.
[0011] The converter unit 30 supplies the power generated by the solar panel 70 to the driving battery 80 and the auxiliary battery 90. The converter unit 30 will be described in detail later. The driving battery 80 is a secondary battery. The driving battery 80 stores the power supplied from the converter unit 30. The driving battery 80 supplies power to a drive system (not shown) mounted on the vehicle 100. The drive system of the vehicle 100 includes one or more motors for driving the vehicle 100.
[0012] The auxiliary battery 90 is a secondary battery. The auxiliary battery 90 stores the power supplied from the converter unit 30. The auxiliary battery 90 supplies power to an auxiliary system (not shown) mounted on the vehicle 100. The auxiliary system of the vehicle 100 is configured to include one or more auxiliary devices. The auxiliary devices are, for example, an electric oil pump, a navigation system, and lamps.
[0013] <Converter unit> The converter unit 30 includes a first DCDC converter 31, a second DCDC converter 32, a third DCDC converter 33, and a measurement circuit 27. The converter unit 30 and a solar panel 70 form a solar power generation system. Each DCDC converter is a voltage conversion circuit that steps down or steps up a DC voltage and outputs it. In the following, when describing each DCDC converter, DCDC will be omitted and the converter will be simply referred to as a converter. For example, the first DCDC converter 31 will be referred to as a first converter 31.
[0014] The first converter 31 is connected to the solar panel 70. The first converter 31 converts the output voltage of the solar panel 70, which is an input voltage, into a voltage based on an instruction from the control device 20 and outputs the voltage.
[0015] The second converter 32 is interposed between the first converter 31 and the driving battery 80. The second converter 32 converts the voltage output by the first converter 31 into a voltage within a predetermined range and outputs it to the driving battery 80.
[0016] The third converter 33 is interposed between the first converter 31 and the auxiliary battery 90. The third converter 33 converts the voltage output by the first converter 31 to a voltage within a predetermined range and outputs the voltage to the auxiliary battery 90. The voltage output by the third converter 33 is lower than the voltage output by the second converter 32.
[0017] The measurement circuit 27 repeatedly detects, at a predetermined control period, the output voltage of the first converter 31 and the output current of the first converter 31. The measurement circuit 27 repeatedly outputs, to the control device 20, signals corresponding to the output voltage and output current detected by the measurement circuit 27.
[0018] <Control device> The control device 20 includes a CPU 21 and a memory 22. The memory 22 prestores various programs in which processes to be executed by the CPU 21 are described. The CPU 21 controls the first converter 31, the second converter 32, and the third converter 33 by executing the programs stored in the memory 22.
[0019] When controlling the first converter 31, the CPU 21 sets a voltage command value Q related to the output voltage of the first converter 31. Then, the CPU 21 controls the first converter 31 so as to realize the output voltage of this voltage command value Q. Note that when controlling the first converter 31, the CPU 21 refers to the output power of the first converter 31. The CPU 21 can calculate the output power of the first converter 31 by multiplying the output current and output voltage of the first converter 31 acquired from the measurement circuit 27.
[0020] <Overview of 1st converter control> The CPU 21 is in an activated state as necessary while the start switch of the vehicle 100 is on, and also while the start switch is off. The start switch is a switch for switching on and off the main system of the vehicle 100. The CPU 21 performs a first converter process for controlling the first converter 31 while the CPU 21 is in an activated state. There are two types of first converter process: a normal process and a scan process. As shown in FIG. 2, the CPU 21 alternates between the normal process and the scan process. The CPU 21 performs the normal process for a certain period of time, for example, one minute. Then, the CPU 21 promptly performs the scan process within an extremely short time, for example, within one second. That is, the CPU 21 basically performs the normal process while performing the scan process by interruption.
[0021] The PV characteristic line, which is the premise of the normal processing and the scan processing, will be described. As shown in FIG. 3, consider an orthogonal coordinate system with the output voltage of the first converter 31 on the X axis and the output power of the first converter 31 on the Y axis. In this orthogonal coordinate system, the PV characteristic line represents the correspondence between the output voltage of the first converter 31 and the output power of the first converter 31 that the first converter 31 can realize according to the power generation state of the solar panel 70 at the current time. The PV characteristic line basically has a mountain-shaped distribution. That is, the PV characteristic line has a maximum power point where the output power of the first converter 31 is maximum. The shape shown by the PV characteristic line differs depending on the situation in which the solar panel 70 is placed, such as the amount of solar radiation. The PV characteristic line may have a distribution in which there are multiple peaks where the output power of the first converter 31 changes from increasing to decreasing. Hereinafter, one and the other regions sandwiching the peak where the output power of the first converter 31 changes from increasing to decreasing are referred to as an upward gradient region and a downward gradient region, respectively. The upwardly sloping region is a region on the PV characteristic line where the output power of the first converter 31 increases as the output voltage of the first converter 31 increases. The downwardly sloping region is a region on the PV characteristic line where the output power of the first converter 31 decreases as the output voltage of the first converter 31 increases.
[0022] In the scan process, the CPU 21 searches for the maximum efficiency voltage Y by scanning the output voltage of the first converter 31 within the scanning range. The maximum efficiency voltage Y is the output voltage of the first converter 31 at which the output power of the first converter 31 is maximum within the scanning range. That is, the maximum efficiency voltage Y is the output voltage of the first converter 31 corresponding to the maximum power point on the PV characteristic line. The scanning range is a range of output voltages with zero as the lower limit and the characteristic voltage as the upper limit. The characteristic voltage has the following value. Now, on the PV characteristic line, it is assumed that the output voltage of the first converter 31 is increased from zero. Note that when the output voltage of the first converter 31 is zero, the output power of the first converter 31 is zero. When the output voltage of the first converter 31 is increased from zero, the output power of the first converter 31 increases and decreases and eventually returns to zero. The output voltage of the first converter 31 when the output power of the first converter 31 returns to zero is the characteristic voltage. The scanning range corresponds to a predetermined range.
[0023] In the normal process, the CPU 21 controls the output voltage of the first converter 31 so that the output voltage of the first converter 31 approaches the maximum efficiency voltage Y. In this normal process, the CPU 21 uses a known hill-climbing method. Specifically, the CPU 21 performs the following process in the normal process. At the start of the normal process, the CPU 21 sets the voltage command value Q for the first converter 31 to the maximum efficiency voltage Y identified in the scan process and controls the first converter 31. After this, the CPU 21 gradually changes the output voltage of the first converter 31 in a direction in which the output power of the first converter 31 increases. Specifically, first, the CPU 21 gradually increases the output voltage of the first converter 31. The CPU 21 continues to gradually increase the output voltage of the first converter 31 while the continuation condition is satisfied. The continuation condition is that the output power of the first converter 31 is greater than the previous value. When the continuation condition is no longer satisfied, the CPU 21 switches the direction in which the output voltage of the first converter 31 is changed. That is, the CPU 21 gradually reduces the output voltage of the first converter 31. After that, the CPU 21 continues to gradually reduce the output voltage of the first converter 31 while the continuation condition is satisfied. Then, when the continuation condition is no longer satisfied, the CPU 21 again switches the direction in which the output voltage of the first converter 31 is changed. In this manner, the CPU 21 switches the direction in which the output voltage of the first converter 31 is changed in normal processing.
[0024] <Specific details of scanning process> As a premise for explaining the details of the scan process, the power acquisition process will be explained. The CPU 21 performs the power acquisition process as a part of the scan process. In the power acquisition process, the CPU 21 controls the first converter 31 so that the output voltage of the first converter 31 coincides with a voltage command value Q set in advance. Then, the CPU 21 calculates the output power of the first converter 31 when the output voltage of the first converter 31 is controlled so that it coincides with the voltage command value Q. As described above, the CPU 21 can calculate the output power of the first converter 31 based on the detection result of the measurement circuit 27. The CPU 21 calculating the output power of the first converter 31 corresponds to the CPU 21 acquiring the output power of the first converter 31. When the CPU 21 acquires the output power of the first converter 31, the CPU 21 stores a set of the output power and the voltage command value Q that is the basis for realizing this output power in the memory 22 as scan result information. The CPU 21 performs such a series of processes in the power acquisition process. Note that the amount of scan result information stored in the memory 22 increases every time the CPU 21 performs the power acquisition process. Hereinafter, a group of a plurality of pieces of scan result information stored in memory 22 will be referred to as a result list. A result list is a list in which a plurality of pieces of scan result information are arranged in chronological order.
[0025] As a premise for explaining the details of the scan process, the initial change width EA will be explained. When the CPU 21 scans the output voltage of the first converter 31 within the scanning range, the change width of the output voltage per scan is called the voltage change width E. The initial change width EA is the initial value of the voltage change width E. The memory 22 stores the initial change width EA in advance. The initial change width EA is determined in advance, for example, by experiments or simulations from the following viewpoints, for PV characteristic lines under various conditions with different amounts of sunlight. Now, assume that a certain upward gradient region in the PV characteristic line is focused on. The minimum value of the output voltage of the first converter 31, which is the starting point of this upward gradient region, is called the minimum voltage. The initial change width EA is a value adjusted so that the output power of the first converter 31 falls within the value of the upward gradient region, that is, so that the output power does not reach the peak of its increase or decrease, when the voltage instruction value Q for the first converter 31 is increased by the initial change width EA from the minimum voltage.
[0026] A specific procedure of the scan process will be described below. When the scan process is started, the CPU 21 executes the process of step S10 after setting an initial voltage instruction value Q. The CPU 21 sets the initial voltage instruction value Q to a value obtained by adding an initial variation width EA to zero.
[0027] 4, in step S10, the CPU 21 performs an initial power acquisition process. In this initial power acquisition process, the CPU 21 controls the first converter 31 based on the initial voltage instruction value Q, and stores the output power of the first converter 31 obtained thereby as scan result information in the memory 22. After completing the execution of the initial power acquisition process, the CPU 21 advances the process to step S20.
[0028] In step S20, the CPU 21 judges whether the latest power Pnew is smaller than the previous power Pold. The latest power Pnew is the output power of the first converter 31 obtained by the most recent power acquisition process. The previous power Pold is the output power obtained by the power acquisition process performed immediately before the most recent power acquisition process. The CPU 21 can grasp the latest power Pnew and the previous power Pold by referring to the result list. When the CPU 21 executes the process of step S20 for the first time after the start of the scanning process, the previous power Pold is treated as zero. When the latest power Pnew is equal to or greater than the previous power Pold (step S20: NO), the CPU 21 advances the process to step S40. The situation in which the judgment result of step S20 is NO is a situation in which the control point of the first converter 31 is located in an upward gradient area on the PV characteristic line. The control point of the first converter 31 is a combination of a voltage command value Q for the first converter 31 and an output power corresponding to the voltage command value Q.
[0029] In step S40, the CPU 21 sets a new voltage change width Enew. Specifically, the CPU 21 sets the new voltage change width Enew to a value obtained by subtracting the second set value C2 from the previous change width Eold, which is the previous value of the voltage change width E. When the CPU 21 executes the process of step S40 for the first time after the start of the scanning process, the previous change width Eold is set to the initial change width EA. The second set value C2 is previously determined as a value smaller than the initial change width EA and larger than zero. For example, the second set value C2 is a value that is 10% of the initial change width EA. The memory 22 previously stores the second set value C2.
[0030] In addition, when the value obtained by subtracting the second set value C2 from the previous change width Eold is set as the calculated value, the CPU 21 sets the lower limit change width as the new voltage change width Enew instead of the calculated value if the calculated value is smaller than the lower limit change width. The lower limit change width is previously determined as a value smaller than the initial change width EA and larger than zero. For example, the lower limit change width is a value of 10% of the initial change width EA. The memory 22 stores the lower limit change width in advance. The lower limit change width is previously determined, for example, by experiments or simulations from the following viewpoints, for PV characteristic lines under various conditions with different amounts of sunlight. Here, if the voltage change width E is made small, the maximum power point of the output power on the PV characteristic line and therefore the maximum efficiency voltage Y can be detected with high accuracy. On the other hand, if the voltage change width E is made small, it takes a lot of time to scan the entire scanning range. The lower limit change width is a value that ensures that the maximum efficiency voltage Y can be detected with high accuracy while not requiring excessive time to scan the entire scanning range. After setting the new voltage change width Enew, the CPU 21 advances the process to step S50.
[0031] On the other hand, in step S20, if the latest power Pnew is smaller than the previous power Pold (step S20: YES), the CPU 21 proceeds to step S30. The determination result in step S20 becomes YES when the control point of the first converter 31 is located in a downward gradient region on the PV characteristic line.
[0032] In step S30, the CPU 21 sets a new voltage change width Enew. Specifically, the CPU 21 sets a value obtained by adding a first set value C1 to the previous change width Eold, which is the previous value of the voltage change width E, as the new voltage change width Enew. The first set value C1 is determined in advance as a value smaller than the initial change width EA and larger than zero. For example, the first set value C1 is a value that is 50% of the initial change width EA. The memory 22 stores the first set value C1 in advance.
[0033] In addition, when the value obtained by adding the first set value C1 to the previous change width Eold is set as the calculated value, the CPU 21 sets the upper limit change width as the new voltage change width Enew instead of the calculated value if the calculated value is greater than the upper limit change width. For example, the upper limit change width is five times the initial change width EA. The memory 22 stores the upper limit change width in advance. The upper limit change width is determined in advance, for example, by experiment or simulation, from the following viewpoint, for PV characteristic lines under various conditions with different amounts of sunlight. As described above, the PV characteristic line may have a distribution in which there are multiple peaks at which the output power of the first converter 31 changes from increasing to decreasing. In the case where the PV characteristic line has such a distribution, if the voltage change width E is made too large, the following concern arises. That is, when the output voltage of the first converter 31 is increased by the voltage change width E, the control point of the first converter 31 located in the downward gradient region may reach the peak of the next upward region. The upper limit change width is determined from the viewpoint of preventing such a situation. After setting the new voltage change width Enew, the CPU 21 advances the process to step S50.
[0034] In step S50, the CPU 21 sets a new voltage command value Qnew. Specifically, the CPU 21 sets the new voltage command value Qnew to a value obtained by adding the voltage change width Enew calculated in step S30 or step S40 to the previous command value Qold, which is the previous value of the voltage command value Q. After setting the new voltage command value Qnew, the CPU 21 advances the process to step S60.
[0035] In step S60, the CPU 21 performs a power acquisition process. That is, the CPU 21 controls the first converter 31 based on the voltage instruction value Qnew set in step S50, and stores the output power of the first converter 31 obtained thereby as scan result information in the memory 22. After that, the CPU 21 advances the process to step S70.
[0036] In step S70, the CPU 21 determines whether the latest power Pnew is zero. The latest power Pnew is the output power obtained in step S60. If the latest power Pnew is greater than zero (step S70: NO), the CPU 21 returns to the process of step S20. On the other hand, if the latest power Pnew is zero (step S70: YES), the CPU 21 advances the process to step S80. The situation in which the determination result in step S70 is YES corresponds to the situation in which the output voltage of the first converter 31 has reached the upper limit of the scanning range.
[0037] In step S80, the maximum efficiency voltage Y is identified. Specifically, the CPU 21 identifies the maximum value among the multiple output power values in the result list stored in the memory 22. Then, the CPU 21 identifies the voltage command value Q associated with this maximum value as the maximum efficiency voltage Y. Thereafter, the CPU 21 erases the result list from the memory 22, and ends the series of steps of the scanning process.
[0038] <Operation of the embodiment> It is assumed that the scan process is currently being performed. The CPU 21 is scanning the uphill region of the PV characteristic line. In this case, the CPU 21 repeats the following cycle of processes in the scan process. That is, since the latest power Pnew is greater than the previous power Pold (step S20: NO), the CPU 21 sets a new voltage change width Enew to a value smaller than the previous change width Eold (step S40). The CPU 21 then sets a value larger than the previous command value Qold by this voltage change width Enew to a new voltage command value Qnew (step S50). The CPU 21 then performs a power acquisition process based on this voltage command value Qnew (step S60). By repeatedly making the new voltage change width Enew smaller than the previous change width Eold in step S40, the CPU 21 gradually reduces the new voltage change width Enew. This point will be specifically described using four consecutive timings as an example. That is, the CPU 21 performs the following processes in order when searching for the maximum efficiency voltage Y. As shown in Fig. 3, first, at a first timing, the CPU 21 controls the output voltage of the first converter 31 to a first voltage V1 and obtains the output power of the first converter 31 at that time as a first power P1. At the next second timing, the CPU 21 controls the output voltage of the first converter 31 to a second voltage V2 that is changed from the first voltage V1 to a side larger by a first change width E1 and obtains the output power of the first converter 31 at that time as a second power P2. At the next third timing, the CPU 21 controls the output voltage of the first converter 31 to a third voltage V3 that is changed from the second voltage V2 to a side larger by a second change width E2 and obtains the output power of the first converter 31 at that time as a third power P3. At this time, the CPU 21 sets the second change width E2 to a value smaller than the first change width E1. Furthermore, at a fourth timing after the third timing, the CPU 21 controls the output voltage of the first converter 31 to a fourth voltage V4, which is changed from the third voltage V3 to a fourth voltage V4 by a third change width E3, and obtains the output power of the first converter 31 at that time as a fourth power P4. At this time, the CPU 21 also sets the third change width E3 to a value smaller than the second change width E2.
[0039] Now, consider a situation where the CPU 21 is scanning the descending region of the PV characteristic line. In this case, the CPU 21 repeats the following cycle of processing in the scan processing. That is, as shown in FIG. 4, since the latest power Pnew is smaller than the previous power Pold (step S20: YES), the CPU 21 sets a new voltage change width Enew to a value larger than the previous change width Eold (step S30). Then, the CPU 21 sets a value larger than the previous command value Qold by this voltage change width Enew to a new voltage command value Qnew (step S50). Then, the CPU 21 performs a power acquisition processing based on this voltage command value Qnew (step S60). By repeatedly increasing the new voltage change width Enew with respect to the previous change width Eold in step S30, the CPU 21 gradually increases the new voltage change width Enew. This point will be specifically described using four consecutive timings as an example. Here, the fifth, sixth, seventh, and eighth timings after the above-mentioned fourth timing are taken as examples. When searching for the maximum efficiency voltage Y, the CPU 21 performs the following processes in order. As shown in FIG. 3, first, at the fifth timing, the CPU 21 controls the output voltage of the first converter 31 to a fifth voltage V5, and obtains the output power of the first converter 31 at that time as a fifth power P5. At the next sixth timing, the CPU 21 controls the output voltage of the first converter 31 to a sixth voltage V6, which is changed from the fifth voltage V5 to the larger side by the fourth change width E4, and obtains the output power of the first converter 31 at that time as the sixth power P6. At the next seventh timing, the CPU 21 controls the output voltage of the first converter 31 to a seventh voltage V7, which is changed from the sixth voltage V6 to the larger side by the fifth change width E5, and obtains the output power of the first converter 31 at that time as the seventh power P7. At this time, the CPU 21 sets the fifth change width E5 to a value larger than the fourth change width E4. Furthermore, at an eighth timing after the seventh timing, the CPU 21 controls the output voltage of the first converter 31 to an eighth voltage V8, which is changed from the seventh voltage V7 to an eighth voltage V8 larger by a sixth change width E6, and obtains the output power of the first converter 31 at that time as an eighth power P8.Similar to the difference between the fourth change width E4 and the fifth change width E5, the CPU 21 sets the sixth change width E6 to a value larger than the fifth change width E5. Note that the voltage, power, and voltage change width at each timing shown in FIG. 3 are examples for explaining the operation of this embodiment, and do not necessarily correspond to the actual ones.
[0040] <Effects of the embodiment> (1) If the latest power Pnew is smaller than the previous power Pold (step S20: YES), the area of the PV characteristic line currently scanned by the CPU 21 is likely to be a downward gradient area. In other words, if the latest power Pnew is smaller than the previous power Pold, the output power of the first converter 31 when the output voltage of the first converter 31 is further increased is likely to be smaller than the latest power Pnew. The output power at this time is unlikely to be the maximum power point on the PV characteristic line. In this case, even if the voltage change width E for setting a new voltage command value Qnew is large, the CPU 21 is unlikely to fail to detect the maximum power point and therefore the maximum efficiency voltage Y. Therefore, when the latest power Pnew is smaller than the previous power Pold, the CPU 21 sets the new voltage change width Enew to be larger than the previous change width Eold (step S30). In this way, by increasing the change width of the output voltage of the first converter 31 at one time, the time required for the CPU 21 to scan the entire scanning range to detect the maximum efficiency voltage Y can be shortened.
[0041] (2) If the latest power Pnew is greater than the previous power Pold (step S20: NO), the region of the PV characteristic line currently scanned by the CPU 21 is likely to be an upwardly sloping region. In other words, if the latest power Pnew is greater than the previous power Pold, the output power of the first converter 31 when the output voltage of the first converter 31 is further increased is likely to be greater than the latest power Pnew. The output power of the first converter 31 at that time may be the maximum power point on the PV characteristic line. When scanning such an upwardly sloping region, if the change width of the output voltage of the first converter 31 at one time is large, there is a risk that the maximum power point on the PV characteristic line, and therefore the maximum efficiency voltage Y, may not be detected. In other words, if the change width of the output voltage of the first converter 31 at one time is large, there is a risk that the output power of the first converter 31 may exceed the maximum power point on the PV characteristic line and enter a downwardly sloping region. Conversely, when scanning an upward gradient region, if the amount of change in the output voltage of the first converter 31 at one time is reduced, the maximum power point and therefore the maximum efficiency voltage Y can be detected with high accuracy. Therefore, when the latest power Pnew is greater than the previous power Pold, the CPU 21 sets the voltage change amount E to be smaller than the previous change amount Eold (step S40). In this manner, by reducing the amount of change in the output voltage of the first converter 31 at one time, the maximum power point on the PV characteristic line and therefore the maximum efficiency voltage Y can be detected with high accuracy.
[0042] <Example of change> The above embodiment can be modified as follows: The above embodiment and the following modifications can be combined with each other to the extent that no technical contradiction occurs.
[0043] When the control point of the first converter 31 switches from an upward gradient region to a downward gradient region on the PV characteristic line, the previous change width Eold may be reset to the initial change width EA. This also applies to when the control point of the first converter 31 switches from a downward gradient region to an upward gradient region on the PV characteristic line.
[0044] The method for setting the new voltage change width Enew in step S30 is not limited to the example of the above embodiment. For example, the first set value C1 may be changed from the example of the above embodiment. The first set value C1 may be the same as the second set value C2. The first set value C1 may be changed every time the process of step S30 is performed. A suitable method may be adopted to set the new voltage change width Enew from the viewpoint of shortening the time required to scan the entire scanning target range.
[0045] The upper limit change width is not limited to the example in the above embodiment, and may be any value that is suitable for the upper limit of the voltage change width E in the downward gradient region. The upper limit of change may be abolished.
[0046] In the above embodiment, while the CPU 21 is scanning the downward gradient area, the new voltage change width Enew is changed every time the CPU 21 performs the process of step S30. This causes the new voltage change width Enew to change gradually. However, it is not essential to change the new voltage change width Enew gradually in this manner. The CPU 21 may increase the new voltage change width Enew with respect to the previous change width Eold at least once while the CPU 21 is scanning the downward gradient area.
[0047] The method of setting the new voltage change width Enew in step S40 is not limited to the example of the embodiment. For example, the second set value C2 may be changed from the example of the embodiment. The second set value C2 may be changed every time the process of step S40 is performed. The new voltage change width Enew may be set by adopting an appropriate preferable method from the viewpoint of accurately detecting the maximum efficiency voltage Y.
[0048] The lower limit change width is not limited to the example in the above embodiment. The lower limit change width may be any value that is suitable for the lower limit of the voltage change width Enew in the upward gradient region. The lower limit change width may be any value that is larger than zero.
[0049] In the above embodiment, while the CPU 21 is scanning an area with an upward gradient, the new voltage change width Enew is changed every time the CPU 21 performs the process of step S40. This causes the new voltage change width Enew to change gradually. However, it is not essential to change the new voltage change width Enew gradually in this manner. The CPU 21 may make the new voltage change width Enew smaller than the previous change width Eold at least once while the CPU 21 is scanning an area with an upward gradient.
[0050] It is not essential for the CPU 21 to change the voltage change width E while scanning an upward gradient area. In other words, the same voltage change width E may always be used in an upward gradient area.
[0051] In the above embodiment, the maximum efficiency voltage Y is searched for while increasing the output voltage of the first converter 31 from zero. Conversely, the maximum efficiency voltage Y may be searched for while decreasing the output voltage of the first converter 31 from the upper limit side of the scanning range.
[0052] The configuration of the solar power generation system is not limited to the example of the above embodiment. For example, the number of solar panels may be changed from the example of the above embodiment. Also, the number of DCDC converters may be changed depending on the amount of required power, the number of power supply destinations, etc. The solar power generation system may include at least one solar panel and a DCDC converter that converts the output voltage of the solar panel and outputs it. [Explanation of symbols]
[0053] 20...Control device 31...First converter 70...Solar panel
Claims
1. The present invention is applied to a solar power generation system including a solar panel and a DC-DC converter that converts the output voltage of the solar panel and outputs the converted voltage, By scanning the output voltage of the DC-DC converter within a predetermined range, a maximum efficiency voltage is searched for, which is an output voltage of the DC-DC converter at which an output power of the DC-DC converter is maximized within the predetermined range; and controlling an output voltage of the DC-DC converter so as to approach the maximum efficiency voltage; In searching for the maximum efficiency voltage, Controlling an output voltage of the DC-DC converter to a first voltage within the predetermined range; acquiring, as a first power, an output power of the DC-DC converter when an output voltage of the DC-DC converter is controlled to the first voltage; Controlling an output voltage of the DC-DC converter to a second voltage within the predetermined range obtained by changing the first voltage by a first change width; acquiring, as a second power, an output power of the DC-DC converter when an output voltage of the DC-DC converter is controlled to the second voltage; controlling an output voltage of the DC-DC converter to a third voltage within the predetermined range obtained by changing the output voltage of the DC-DC converter from the second voltage by a second change amount in the same direction as the first change amount; When the second power is smaller than the first power, the second change amount is set to a value larger than the first change amount. Control device for solar power generation system.
2. When the second power is equal to or greater than the first power, the second change amount is set to a value smaller than the first change amount. The control device for a solar power generation system according to claim 1.
Citation Information
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