Method for manufacturing power element based on wide bandgap semiconductor, and power element

Abstract

To provide a method for manufacturing a power element based on a wide bandgap semiconductor, and a power element.SOLUTION: According to a first aspect, there is proposed a method for manufacturing a power element based on a wide bandgap semiconductor, the method providing a device wafer with a substrate. On the substrate, one or plural function layers forming a power element are formed. Between the function layer and the substrate, at least one design layer is arranged. The present invention aims to remove the substrate from a device wafer completely by selectively removing at least one design layer.SELECTED DRAWING: Figure 2a

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a power component, in particular of the vertical type, based on wide bandgap semiconductors.The present invention further relates to a power component. [Background technology]

[0002] Wide bandgap semiconductors (also called wide bandgap semiconductors or WBG semiconductors or WBGS) are semiconductor materials that have a bandgap larger than conventional semiconductors. While conventional semiconductors such as silicon have bandgaps in the range of 0.6 to 1.5 electron volts (eV), wide bandgap semiconductors have bandgaps in the range of more than 2 eV. In general, wide bandgap semiconductors have electronic properties between conventional semiconductors and insulators.

[0003] Semiconductors with wide bandgaps generally enable devices to operate at higher voltages, frequencies, and temperatures than traditional semiconductor materials such as silicon and gallium arsenide. Exemplary wide bandgap semiconductors are silicon carbide (SiC) and gallium nitride (GaN), although many additional wide bandgap semiconductors are known to those skilled in the art.

[0004] Gallium nitride (GaN) based transistors offer the possibility of realizing components with a lower on-resistance and at the same time a higher breakdown voltage than comparable components based on silicon or silicon carbide. GaN transistors are known among other things by the so-called high electron mobility transistors (HEMTs), in which the current flow is generated laterally above the substrate by a two-dimensional electron gas forming the transistor channel. Such lateral elements can be produced by heteroepitaxy of functional GaN layers on silicon wafers.

[0005] When the breakdown voltage is high and the on-resistance per unit area is small, a so-called vertical element in which current flows from the front side to the back side of the substrate is more advantageous in terms of both mounting size and electric field distribution within the component.

[0006] Such vertical devices cannot be realized directly with heteroepitaxial GaN layers on silicon (Si), because an insulating intermediate layer (a so-called buffer) is needed to accommodate the lattice mismatch between GaN and Si and to reduce the substrate curvature. The buffer itself is mechanically stressed to just compensate the stress of the GaN layer at room temperature. However, since the buffer is an insulator, it prevents the flow of current from the front to the back. Currently, there are also native GaN substrates on which the further required epitaxial GaN layers of the component can be grown without the need for an insulating buffer, but these are small (typically 50 mm in diameter) and relatively expensive.

[0007] To reduce the transistor price per planar element, it is advantageous to use available heteroepitaxial GaN layers on a large silicon substrate. For this purpose, vertical elements have been shown in the literature; see, for example, Khadar et al., "Fully vertical GaN-on-Si power MOSFETs," IEEE Electron Device Letters (2019) or Zhang et al., "720-V / 0.35-mOhmcm^2 Fully Vertical GaN-on-Si Power Diodes by Selective Removal of Si Substrates and Buffer Layers," IEEE Electron Device Letters (2018). In the vertical elements thus produced, the silicon substrate and the non-conductive buffer beneath the components are selectively removed, thereby allowing direct contact to the backside of the drift area of ​​the components.

[0008] Figure 1a shows the principle structure of such a component (here for the example of a trench MOSFET) with an insulating buffer and a back trench. The back trench is also called a back cavity, a back aperture or a recess. It should be understood that the ability to provide such a conductive access to the back side of the drift area is not limited to this type of component, but in principle any vertical power element can be manufactured by this technique.

[0009] For fabrication, the following III-V nitride semiconductor layers (GaN except for the buffer) are epitaxially grown on a silicon substrate 61 or typically a carrier substrate: an insulating buffer 33, a highly doped contact semiconductor layer 34 having n conductivity, a lightly doped n-conducting drift layer 35, a p-conducting body layer 36, and a highly doped n-conducting source contact layer 37. A trench 51 is drilled in the source contact layer 37 and the body layer 36, the sidewalls and bottom of which are separated from the gate electrode 21 by the gate dielectric 22. The source contact layer 37 and the body layer 36 are contacted by a source electrode 41, which is separated from the gate electrode by an insulating layer 31.

[0010] At the back side, the silicon substrate and buffer are removed by a back trench 51, which terminates in a highly conductive semiconductor contact layer 34. The semiconductor contact layer 34 is contacted by a back drain electrode 52. In operation, application of a gate voltage to the gate electrode 21 creates a conductive channel in the body layer 36, through which current can flow from the source electrode 41 to the drain electrode 52. For simplicity, FIG. 1a shows a transistor with three cells, i.e., three repeating structures. In a real transistor, there are typically many such cells, and thus are substantially connected in parallel. This allows the resistance of the component to be reduced and the current capacity to be increased. Typical active areas are in the range of a few square millimeters, and the remaining GaN layer has a thickness of a few micrometers. This aspect ratio is difficult to represent in a diagram. The drain electrode 52 may consist of multiple metal layers and may also include a thick metal. Ultimately, the back trench 51 may be completely filled with metal (not shown).

[0011] In the case of incompletely filled cavities, the above method results in membranes with thicknesses in the micrometer range and lateral dimensions of a few millimeters. To protect these fragile membranes during processing, the wafer can be bonded on the front side to a carrier wafer 63 by means of a connection layer 62 (see FIG. 1b) before creating the trenches 51 in the silicon. This process is referred to below as temporary bonding.

[0012] After the silicon has been removed and the above-mentioned metal layers have been applied, the transistor chips are singulated along so-called sawing or singulation lines by sawing or laser dicing to produce the individual chips.

[0013] The membranes consisting of the above mentioned semiconductor and metal layers have limited stability: processing, wafer handling and especially singulation (where the wafer is singulated into individual chips by sawing or laser dicing) can lead to deformation or rupture of the membrane, which can destroy or damage components or change parameters such as, for example, threshold voltages. [Prior art documents] [Non-patent literature]

[0014] [Non-Patent Document 1] Khadar et al., "Fully vertical GaN-on-Si power MOSFETs," IEEE Electron Device Letters (2019) [Non-Patent Document 2] Zhang et al., "720-V / 0.35-mOhmcm^2 Fully Vertical GaN-on-Si Power Diodes by Selective Removal of Si Substrates and Buffer Layers," IEEE Electron Device Letters (2018) Summary of the Invention

[0015] The object of the present invention can therefore be seen as providing a method for manufacturing a power element based on wide band gap semiconductors, for example GaN or GaO, which can be advantageously processed using established assembly and connection techniques, such as sintering for die attachment, wire bonding for front contacts, or embedding, and which has particularly low thermal and electrical resistance. For this purpose, a layer structure and a manufacturing method are proposed that allow a vertical current flow in the power element, even if the element is grown heteroepitaxially on an insulating substrate or with an insulating epitaxial intermediate layer. In contrast to the prior art, no cavities are created, which are disadvantageous in terms of thermal and electrical connections and in terms of the use of the aforementioned established assembly and connection techniques.

[0016] The membranes consisting of the above mentioned semiconductor and metal layers have limited stability: processing, wafer handling and especially singulation (where the wafer is singulated into individual chips by sawing or laser dicing) can lead to deformation or rupture of the membrane, which can destroy or damage components or change parameters such as, for example, threshold voltages.

[0017] By complete removal of the substrate according to the invention, the semiconductor layer can be subsequently stabilized more effectively and more completely than in the case of a film. According to a first aspect of the present invention, a method is proposed for manufacturing a power device based on a wide bandgap semiconductor, in which a device wafer having a substrate is provided. On the substrate, one or more functional layers forming the power device are formed. Between the functional layers and the substrate, at least one engineered layer is arranged. According to the present invention, it is contemplated that the substrate is completely removed from the device wafer by selectively removing the at least one engineered layer.

[0018] The invention thus enables a procedure in which the active semiconductor layer is separated from the substrate without destroying the substrate, which usually represents a significant proportion of the cost, and which can be reused in this way. Furthermore, the process can be significantly cheaper, since it requires fewer process steps than if the substrate were completely or partially removed from the backside.

[0019] The approach of completely removing the substrate can be realized for example for GaN on so-called engineered substrates (eg QST wafers), and this approach is also conceivable for gallium oxide (GaO) on foreign substrates.

[0020] Complete removal of the substrate reduces parasitic electrical resistance and improves thermal connection to the circuit carrier, especially in vertical power devices, so this approach is also advantageous for lateral devices. Preferably, before removing the substrate, the already applied layers are stabilized by a carrier layer, in particular a carrier wafer. For this purpose, it can be temporarily bonded, for example, to a glass or silicon wafer. This advantageously ensures that the components are efficiently stabilized. By detaching the bonding layer, the carrier wafer can be easily removed and the power components are already singulated and can be immediately subjected to further processing.

[0021] Before removal of the carrier wafer, the device wafer may advantageously be peeled off on a dicing tape, which makes singulation and further processing even easier. A particularly preferred embodiment of the method according to the invention comprises a. providing a device wafer (100) having a substrate (1), on which one or more functional layers (4, 5, 6, 7, 8, 9, 10, 11, 12) forming power devices are formed, and at least one design layer (2, 3) is disposed between the functional layers (4, 5, 6, 7, 8, 9, 10, 11, 12) and the substrate (1); b. forming at least one trench (23) through the functional layers (4, 5, 6, 7, 8, 9, 10, 11, 12), the trench (23) reaching down to the design layers (2, 3); c. applying a passivation (13) to the surface of the device wafer (100) and to the sidewalls of at least one trench (23); d. removing the passivation at the bottom (23') of at least one trench (23) and forming a recess (24) in the trench (23) so as to expose the design layers (2, 3); e. applying a carrier wafer (15) to the surface of the device wafer (100), the carrier wafer (15) having openings (25) at predetermined locations through which an etching medium can be introduced into the trenches (23) and recesses (24); f. introducing an etching medium into the opening (25), thereby removing at least one design layer (2, 3); g. Removing the device wafer (100) from the substrate (1); h. Removing the individual power elements; Includes.

[0022] In one possible embodiment, at least one design layer is formed as a silicon layer, which can be removed by introducing an etching medium comprising xenon difluoride gas.

[0023] In a further possible embodiment, at least one design layer is formed as a silicon oxide layer, which can be removed by the introduction of an etching medium comprising HF gas.

[0024] Preferably, after removal of the device wafer from the substrate, any design layers and / or buffer layers which may still be present are removed, in particular by plasma etching.

[0025] After removal of the device wafer from the substrate, one or more metallization layers may be applied to the exposed functional layers, thus effectively making a drain contact, for example, if the power device is a MOSFET.

[0026] According to a second aspect of the present invention, a power element based on a wide band gap semiconductor is proposed, which is manufactured according to the method according to the first aspect, in particular formed as a power transistor or diode. Examples of such power elements are Schottky diodes, pn diodes, vertical diffused MOSFETs (VDMOS), current aperture vertical electron transistors (CAVET), vGroove vertical high electron mobility transistors or fin field effect transistors (FinFET). Further examples are known to the skilled person.

[0027] In particular, the power elements have GaN or GaO or SiC as functional semiconductor material and can, among other things, achieve low losses in switching regulators, handle high voltages, operate at high (ambient) temperatures, handle higher frequencies, and / or have higher reliability.

[0028] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS With reference to the accompanying drawings, an embodiment of the present invention will be described in detail. [Brief description of the drawings]

[0029] [Figure 1a] FIG. 1 illustrates the fabrication of a GaN trench MOSFET according to the prior art. [Figure 1b]FIG. 1 illustrates the fabrication of a GaN trench MOSFET according to the prior art. [Figure 2a] 1A-1D illustrate the fabrication of a vertical GaN MOSFET according to a possible embodiment of the present invention. [Figure 2b] 1A-1D illustrate the fabrication of a vertical GaN MOSFET according to a possible embodiment of the present invention. [Figure 2c] 1A-1D illustrate the fabrication of a vertical GaN MOSFET according to a possible embodiment of the present invention. [Figure 2d] 1A-1D illustrate the fabrication of a vertical GaN MOSFET according to a possible embodiment of the present invention. [Figure 2e] 1A-1D illustrate the fabrication of a vertical GaN MOSFET according to a possible embodiment of the present invention. [Figure 2f] 1A-1D illustrate the fabrication of a vertical GaN MOSFET according to a possible embodiment of the present invention. [Figure 2g] 1A-1D illustrate the fabrication of a vertical GaN MOSFET according to a possible embodiment of the present invention. [Figure 2h] 1A-1D illustrate the fabrication of a vertical GaN MOSFET according to a possible embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] In the following description of exemplary embodiments of the invention, like elements are provided with like reference numerals and a repeated description of these elements will be omitted.The figures only diagrammatically represent the subject matter of the invention.

[0031] 2a-2f show intermediate steps in a possible process sequence for realizing the invention described herein, as an example of the manufacture of a GaN-MOSFET as a vertical power device. Firstly, a substrate 1 is prepared, on which several layers are formed. In the example shown, two so-called design layers 2 and 3 are formed on the substrate 1. On top of the design layers 2, 3, a drain contact layer 4 of GaN epitaxy and a drift layer 5 are arranged. On top of the drift layer 5, a semiconductor p-doped layer 6 is arranged, on top of which an n-doped source layer 7 and an insulating layer 8 are arranged. Reference numerals 10 indicate the power metallization of the device, 11 the gate dielectric and 12 the gate electrode.

[0032] After the front side processing, a stabilized metal layer 9 can be applied optionally. First, etching is performed along the sawing trench 23 over all functional layers, including the epitaxial layers 5 and 4, the side walls and the surface being protected with a passivation 13. This passivation 13 is then opened at the bottom of the opening in a second etch, and the underlying design layers 2 and 3 are etched away, resulting in a recess 24. Here, the passivation 13 must not be removed anywhere else along the opening side. It should be noted that ideally the passivation at the wafer surface in the region of the contact pads is opened as well. Optionally, this etching procedure can also be performed at another suitable time during the front side processing, and the opening is protected during the subsequent deposition, for example by masking.

[0033] In a next step (FIG. 2b), a carrier wafer 15 is applied to the front side of the device wafer 100, for example by means of a temporary bonding layer 14. The carrier wafer 15 and also the bonding layer 14 have openings 25, 26, through which gas can reach the pre-etched trenches 23, 24 of the device wafer 100. The openings 25, 26 can be formed, for example, as holes at the intersections of sawing lines.

[0034] During the subsequent gas-phase etching, the etching gas 40 is directed through these openings 25, 26 into the trenches 23, 24 towards the design layers 2, 3. The etching gas 40 and the material of the passivation 13 are selected such that there is a very high etching selectivity between them. An example is silicon dioxide as a passivation, which is not etched by xenon difluoride (XeF2). But at the same time, at least one of the exposed design layers 2, 3 should be etched by the etching gas 40. Usually, GaN epitaxy starts on a thin silicon layer, which is well etched by XeF2. Alternatively, the process can be reversed and the SiO2 layer in the design layers 2, 3 can be etched using the etching gas 40, for example hydrofluoric acid gas (HF gas). In this case, the passivation 13 can be selected as, for example, a polysilicon layer, which is not etched by HF gas. These two variants are shown, for example, in FIG. 2c for etching silicon (layer 2) with XeF2 and in FIG. 2d for etching SiO2 (layer 3) with HF gas.

[0035] A gas is then used to remove at least one of the design layers 2, 3 under the epitaxy between the openings of the device wafer 100. After complete removal, the device wafer 100 can be removed from the substrate 1.

[0036] As shown in Figure 2e, the device wafer 100 is then turned over and any layers (in this example design layer 3) and buffer layers (not shown) that may still be present are removed (Figure 2e), for example by plasma etching.

[0037] Once the epitaxy drain layer 4 is exposed (see FIG. 2f), contact metal is applied as metallization layer 16 and optionally a further stabilization metal layer, as shown in FIG. 2g. The power element is now complete, the chips already singulated since the initial etching has reached the substrate 1. The device wafer 100 can be turned over again and peeled off on a dicing tape 17 (see FIG. 2h). After detachment of the carrier wafer 15, the bonding layer 14 is removed. The chips can then be removed individually. [Explanation of symbols]

[0038] 1 Board 2, 3 design layers 4, 5, 6, 7, 8, 9, 10, 11, 12 Functional layers 13 Passivation 14 Bonding layer 15 Carrier wafer 16 Metallization Layer 17 Dicing tape 23 Trench 23' bottom 24 Recess 25 Opening 100 Device Wafer

Claims

1. A method for manufacturing a power element based on a wide bandgap semiconductor, comprising: providing a device wafer (100) having a substrate (1), on which one or more functional layers (4, 5, 6, 7, 8, 9, 10, 11, 12) forming said power element are formed, and at least one design layer (2, 3) is arranged between said functional layers (4, 5, 6, 7, 8, 9, 10, 11, 12) and said substrate (1), characterized in that said substrate (1) is completely removed from said device wafer (100) by selectively removing at least one design layer (2, 3).

2. 2. The method according to claim 1, wherein, before the removal of the substrate (1), the already applied layers (4, 5, 6, 7, 8, 9, 10, 11, 12) are stabilized by a carrier layer, in particular a carrier wafer (15).

3. a. providing a device wafer (100) having a substrate (1), on which one or more functional layers (4, 5, 6, 7, 8, 9, 10, 11, 12) forming the power devices are formed, and at least one design layer (2, 3) is arranged between the functional layers (4, 5, 6, 7, 8, 9, 10, 11, 12) and the substrate (1); b. forming at least one trench (23) through said functional layers (4, 5, 6, 7, 8, 9, 10, 11, 12), said trench (23) reaching down to said design layers (2, 3); c. applying a passivation (13) to the surface of the device wafer (100) and to the sidewalls of the at least one trench (23); d. removing said passivation at the bottom (23') of said at least one trench (23) and forming a recess (24) in said trench (23) so as to expose said design layers (2, 3); e. applying a carrier wafer (15) to the surface of the device wafer (100), the carrier wafer (15) having openings (25) at predetermined locations through which an etching medium can be introduced into the trenches (23) and into the recesses (24); f. introducing an etching medium into said opening (25), thereby removing at least one design layer (2, 3); g. Detaching the device wafer (100) from the substrate (1); h. Removing the individual power elements; The method of claim 1 or 2, comprising:

4. 4. The method according to claim 1, wherein at least one first design layer (2) is formed as a silicon layer, and the first design layer (2) is removed by an etching medium comprising xenon difluoride gas.

5. 5. The method according to claim 1, wherein at least one second design layer (3) is formed as a silicon oxide layer, and said second design layer (3) is removed by an etching medium comprising HF gas.

6. The method according to any one of claims 2 to 5, wherein the carrier wafer (15) is connected to the surface of the device wafer (100) by a bonding layer (14).

7. 7. The method according to claim 1, wherein after the detachment of the device wafer (100) from the substrate (1), all design layers (2, 3) and / or buffer layers still present are removed, in particular by plasma etching.

8. 8. The method according to any one of the preceding claims, wherein after the removal of the device wafer (100) from the substrate (1), one or more metallization layers (16) are applied to the exposed functional layer (4).

9. The method according to any one of claims 2 to 8, wherein after the detachment of the device wafer (100) from the substrate (1), the carrier wafer (15) and optionally the bonding layer (14) are removed.

10. The method according to any one of claims 2 to 9, wherein before the removal of the carrier wafer (15), the device wafer (100) is peeled off on a dicing tape (17).

11. 11. A power component based on a wide bandgap semiconductor, produced according to the method of any one of claims 1 to 10, in particular formed as a power transistor or diode.

12. 12. A power element according to claim 11, comprising GaN, GaO or SiC as the functional semiconductor material.

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