Transistor and semiconductor memory device including the same

Abstract

To provide a transistor with improved durability and reliability.SOLUTION: A transistor according to the present invention includes a substrate including an active region, an element separation film that defines the active region in the substrate, a first impurity region disposed on a lower surface of the element separation film, a second impurity region disposed in the substrate, a gate electrode extending on the substrate in a first direction, a source / drain region disposed on at least one side of the gate electrode, a first source / drain contact group disposed on the source / drain region, and a second source / drain contact group that is apart from the first source / drain contact group in the first direction on the source / drain region. The second impurity region is disposed between the first source / drain contact group and the second source / drain contact group.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a transistor and a semiconductor memory including the same. More particularly, the present invention relates to a three-dimensional semiconductor memory device including a transistor and memory cells including the transistor and arranged three-dimensionally. [Background technology]

[0002] In order to meet the demands of consumers for superior performance and low prices, there is a demand for increased integration density of semiconductor memory devices, especially in the case of semiconductor memory devices, since the integration density is a key factor in determining the price of the product.

[0003] In the case of two-dimensional or planar semiconductor memory devices, the integration level is determined mainly by the area occupied by a unit memory cell, and is therefore greatly affected by the level of fine pattern formation technology. However, since extremely expensive equipment is required for fine patterning, the integration level of two-dimensional semiconductor devices is increasing but is still limited. Therefore, three-dimensional semiconductor devices having memory cells arranged three-dimensionally have been proposed. Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a transistor with improved durability and reliability.

[0005] It is another object of the present invention to provide a semiconductor memory device including a transistor having improved durability and reliability.

[0006] The technical problems of the present invention are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] In order to achieve the above object, one aspect of a transistor of the present invention includes a substrate including an active region, an isolation film defining the active region in the substrate, a first impurity region disposed on a lower surface of the isolation film, a second impurity region disposed in the substrate, a gate electrode extending in a first direction on the substrate, a source / drain region disposed on at least one side of the gate electrode, a first source / drain contact group disposed on the source / drain region, and a second source / drain contact group on the source / drain region spaced apart from the first source / drain contact group in the first direction, and the second impurity region is disposed between the first source / drain contact group and the second source / drain contact group.

[0008] Another aspect of the transistor of the present invention made to achieve the above object includes a substrate including an active region, a gate electrode extending in a first direction on the substrate, an isolation film defining the active region in the substrate, a first impurity region disposed on a lower surface of the isolation film, a second impurity region disposed in the substrate and extending in a second direction intersecting the first direction, a source / drain region disposed on at least one side of the gate electrode, a first source / drain contact group disposed on the source / drain region, and a second source / drain contact group on the source / drain region spaced apart from the first source / drain contact group in the first direction, the source / drain region includes a third impurity region in contact with the first source / drain contact group and a fourth impurity region disposed between the third impurity region and the gate electrode, an N-type impurity concentration of the third impurity region is greater than an N-type impurity concentration of the fourth impurity region, and the second impurity region does not overlap with the first source / drain contact group in a third direction perpendicular to an upper surface of the substrate.

[0009] In order to achieve the above object, one aspect of a semiconductor memory device of the present invention includes a peripheral circuit structure including a transistor and a cell structure arranged on the peripheral circuit structure, the cell structure includes a cell substrate, a mold structure including a plurality of cell gate electrodes stacked in sequence on the cell substrate, and a channel structure penetrating the plurality of cell gate electrodes, and the transistor includes a substrate including an active region, an element isolation film defining the active region within the substrate, a first impurity region arranged on a lower surface of the element isolation film, a second impurity region arranged within the substrate, a gate electrode extending in a first direction on the substrate, a source / drain region arranged on at least one side of the gate electrode, a first source / drain contact group arranged on the source / drain region, and a second source / drain contact group spaced apart in the first direction from the first source / drain contact group, and the second impurity region is arranged between the first source / drain contact group and the second source / drain contact group. Effect of the Invention

[0010] According to the present invention, it is possible to provide a transistor with improved integration density and reliability. [Brief description of the drawings]

[0011] [Figure 1] FIG. 2 is an exemplary layout diagram illustrating transistors according to some embodiments. [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Diagram 3] FIG. 2 is a cross-sectional view taken along line BB in FIG. [Figure 4] FIG. 1 is a layout diagram illustrating transistors according to some embodiments. [Diagram 5] 1 is a cross-sectional view illustrating a transistor according to some embodiments. [Figure 6] 1 is a cross-sectional view illustrating a transistor according to some embodiments. [Figure 7]FIG. 1 is a diagram illustrating a transistor according to some embodiments. [Figure 8] FIG. 1 is a diagram illustrating a transistor according to some embodiments. [Figure 9] FIG. 1 is a layout diagram illustrating transistors according to some embodiments. [Figure 10] 1 is an exemplary block diagram illustrating a semiconductor memory device according to some embodiments. [Figure 11] 1 is an exemplary circuit diagram illustrating a semiconductor memory device according to some embodiments. [Figure 12] 1 is a diagram illustrating a semiconductor memory device according to some embodiments. [Figure 13] FIG. 13 is an enlarged view for explaining the R1 region in FIG. [Figure 14] 1 is a diagram illustrating a semiconductor memory device according to some embodiments. [Figure 15] 1 is a diagram illustrating a semiconductor memory device according to some embodiments. [Figure 16] FIG. 1 is an exemplary block diagram illustrating an electronic system according to some embodiments. [Figure 17] FIG. 1 is an exemplary perspective view illustrating an electronic system according to some embodiments. [Figure 18] FIG. 18 is a schematic cross-sectional view taken along line II in FIG. 17. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] In this specification, the terms "first", "second", etc. are used to describe various elements or components, but these elements or components are not limited by these terms. These terms are used merely to distinguish one element or component from another element or component. Therefore, a first element or component referred to below may be a second element or component within the technical concept of the present invention.

[0013] In the drawings of the transistors according to some embodiments, a transistor including a planar channel region is shown as an example, but is not limited thereto. The transistors according to some embodiments include a FinFET including a channel region in a fin-like pattern, a transistor including a nanowire or nanosheet, and a Multi-Bridge Channel Field Effect Transistor (MBCFET). The semiconductor device according to some embodiments includes a tunneling transistor or a three-dimensional (3D) transistor. Furthermore, the technical concept of the present invention can be applied to 2D material based FETs and heterostructures thereof.

[0014] In the following, transistors according to exemplary embodiments will be described with reference to FIGS.

[0015] Figure 1 is an exemplary layout diagram for illustrating a transistor according to some embodiments. Figure 2 is a cross-sectional view taken along line AA in Figure 1. Figure 3 is a cross-sectional view taken along line BB in Figure 1. Figure 4 is a layout diagram for illustrating a transistor according to some embodiments.

[0016] 1 to 4, a transistor according to some embodiments includes a substrate 200, a first impurity region 210, a second impurity region 215, a gate electrode 220, a gate insulating film 225, a source / drain region 230, and a source / drain contact 250.

[0017] The substrate 200 is made of or includes a semiconductor material. The substrate 200 may be a silicon substrate or a silicon-on-insulator (SOI) substrate. Alternatively, the substrate 200 may include, but is not limited to, silicon germanium, silicon germanium on insulator (SGOI), indium antimony, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimony.

[0018] The active area AR is disposed on the substrate. The active area AR is defined by an isolation layer 235. In one example, the active area AR is a region in which an NMOS is to be formed. In another example, the active area AR is a region in which a PMOS is to be formed.

[0019] The isolation film 235 is disposed in the substrate 200. The isolation film 235 is formed on the substrate 200 to define an active area AR. The isolation film 235 fills an isolation trench. The isolation film 235 is formed in a shallow trench isolation (STI) structure that has excellent isolation characteristics and a small occupying area, which is advantageous for high integration, but is not limited thereto. The isolation film 235 includes, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0020] The first impurity region 210 is disposed in the substrate 200. The first impurity region 210 is formed on a bottom surface 235_BS of the device isolation film 235. The interface between the first impurity region 210 and the device isolation film 235 is the bottom surface of the device isolation trench. The first impurity region 210 surrounds the active region AR.

[0021] The second impurity region 215 is disposed within the substrate 200. The second impurity region 215 extends in a first direction X. The second impurity region 215 is surrounded by the substrate 200. In other words, the second impurity region 215 is disposed within the substrate 200.

[0022] The second impurity region 215 is disposed between a first source / drain contact group 250_G1 and a second source / drain contact group 250_G2, and between the second source / drain contact group 250_G2 and a third source / drain contact group 250_G3, which will be described later. The second impurity region 215 does not overlap with the first to third source / drain contact groups 250_G1, 250_G2, 250_G3 in the third direction Z.

[0023] The first impurity region 210 has a first height H1 to the upper surface 200_US of the substrate 200. Here, the first height H1 is the distance from the top of the first impurity region 210 to the upper surface 200_US of the substrate 200.

[0024] The second impurity region 215 has a second height H2 to the upper surface 200_US of the substrate 200. Here, the second height H2 is the distance from the top of the second impurity region 215 to the upper surface 200_US of the substrate 200. The first height H1 and the second height H2 are the same.

[0025] The first impurity region 210 and the second impurity region 215 include dopants of the same conductivity type. As an example, the dopant includes a P-type impurity. The P-type impurity is, for example, any one of boron (B) and gallium (Ga), but is not limited thereto. As another example, the dopant includes an N-type impurity. The N-type impurity is, for example, at least one of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). In the following description, it is assumed that the dopant includes a P-type impurity.

[0026] The gate electrode 220 is disposed on the substrate 200 and the active region AR. The gate electrode 220 extends in a second direction Y. The gate electrode 220 overlaps with the second impurity region 215 in the substrate 200 in a third direction Z.

[0027] The gate electrode 220 includes at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. The gate electrode 220 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), or aluminium. The conductive metal oxides and conductive metal oxynitrides may include, but are not limited to, at least one of aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof. The conductive metal oxides and conductive metal oxynitrides may include, but are not limited to, oxidized forms of the above-mentioned materials.

[0028] Although the gate electrode 220 is shown to be a single layer, the present invention is not limited thereto, and may be, for example, a multi-layer structure made of a conductive metal material or a combination thereof.

[0029] The gate insulating film 225 is disposed on the upper surface 200_US of the substrate 200. The gate insulating film 225 is disposed between the substrate 200 and the gate electrode 220.

[0030] Although the gate insulating film 225 is illustrated as being a single film, it is not limited thereto, and may include an interfacial insulating film and a high dielectric constant insulating film.

[0031] The gate insulating film 225 includes silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant greater than that of silicon oxide. The high dielectric constant material may include, for example, one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0032] The gate spacer 260 is disposed on the substrate 200. The gate spacer 260 is disposed on the sidewall of the gate insulating film 225 and the sidewall of the gate electrode 220. The gate spacer 260 is shown in a bar shape, but is not limited thereto. For example, the shape of the gate spacer 260 may be different, such as an L-shape.

[0033] The gate spacer 160 may be made of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. Although the gate spacer 160 is shown as being a single film, this is for convenience of explanation and is not intended to be limiting.

[0034] The source / drain region 230 is disposed on the substrate 200. The source / drain region 230 is disposed on at least one side of the gate electrode 220. The source / drain region 230 is disposed on both sides of the gate electrode 220.

[0035] The source / drain region 230 includes a third impurity region 232 and a fourth impurity region 234 .

[0036] The third impurity regions 232 are arranged to be spaced apart in the second direction Y. The third impurity regions 232 are arranged corresponding to source / drain contacts 250, which will be described later. The third impurity regions 232 do not overlap the second impurity regions 215 in the third direction Z.

[0037] The third impurity region 232 contacts a source / drain contact 250, which will be described later. The depth of the third impurity region 232 is greater than the depth of the fourth impurity region 234. The third impurity region 232 and the fourth impurity region 234 are aligned in the first direction X. The fourth impurity region 234 is formed on both sides of the gate electrode 220. Although the fourth impurity region 234 overlaps with the gate spacer 260 in the third direction Z, this is not limiting. For example, the fourth impurity region 234 does not overlap with the gate spacer 260 in the third direction Z.

[0038] The third impurity region 232 and the fourth impurity region 234 contain impurities of the same conductivity type. The impurity concentration of the third impurity region 232 is greater than the impurity concentration of the fourth impurity region 234.

[0039] The source / drain contacts 250 are disposed on the source / drain regions 230. The source / drain contacts 250 contact the third impurity regions 232. The source / drain contacts 250 are disposed on both sides of the gate electrode 220. The source / drain contacts 250 are arranged in the second direction Y.

[0040] The source / drain contacts 250 form a first source / drain contact group 250_G1, a second source / drain contact group 250_G2, and a third source / drain contact group 250_G3.

[0041] Each of the first source / drain contact group 250_G1, the second source / drain contact group 250_G2, and the third source / drain contact group 250_G3 includes the same number of source / drain contacts 250. For example, the number of source / drain contacts 250 in each of the first source / drain contact group 250_G1, the second source / drain contact group 250_G2, and the third source / drain contact group 250_G3 is four.

[0042] The first source / drain contact group 250_G1, the second source / drain contact group 250_G2, and the third source / drain contact group 250_G3 are aligned in the second direction Y. Specifically, the first source / drain contact group 250_G1 and the second source / drain contact group 250_G2 are spaced apart in the second direction Y. The second source / drain contact group 250_G2 and the third source / drain contact group 250_G3 are spaced apart in the second direction Y. The separation distance between the first source / drain contact group 250_G1 and the second source / drain contact group 250_G2 is the same as the separation distance between the second source / drain contact group 250_G2 and the third source / drain contact group 250_G3.

[0043] Although the first to third source / drain contact groups 250_G1, 250_G2, and 250_G3 each include four source / drain contacts, the present invention is not limited to this. For example, the number of source / drain contacts 250 may be two as shown in FIG. 4. As another example, the number of source / drain contacts may be three or five or more.

[0044] The source / drain contacts 250 include a conductive material and may include, for example, at least one of a metal, a metal nitride, a metal carbonitride, a two-dimensional (2D) material, and a conductive semiconductor material.

[0045] A first inter-wiring insulating film 240 is formed on an upper surface 200_US of the substrate 200. The first inter-wiring insulating film 240 includes an insulating material. The first inter-wiring insulating film 240 covers the device isolation film 235, the gate electrode 220, and the source / drain contacts 250.

[0046] Fig. 5 is a cross-sectional view for explaining a transistor according to some embodiments. Fig. 6 is a cross-sectional view for explaining a transistor according to some embodiments. For convenience of explanation, the following description will focus on points that are different from those described in Figs. 1 to 4.

[0047] 5 and 6, the first impurity region 210 has a first height H1 from the upper surface 200_US of the substrate 200. Here, the first height H1 is the distance from the top of the first impurity region 210 to the upper surface 200_US of the substrate 200.

[0048] The second impurity region 215 has a second height H2 from the upper surface 200_US of the substrate 200. Here, the second height H2 is the distance from the top of the second impurity region 215 to the upper surface 200_US of the substrate 200.

[0049] As an example, the first height H1 is greater than the second height H2 as shown in Fig. 5. As another example, the first height H1 is less than the second height H2 as shown in Fig. 6.

[0050] 7 and 8 are diagrams for explaining transistors according to some embodiments. For convenience of explanation, the following will mainly explain the points that are different from the contents explained with reference to FIGS.

[0051] 7 and 8, the third impurity region 232 includes a sub-impurity region 232S.

[0052] The sub-impurity region 232S has a shape in which the third impurity region 232 in FIG. 2 is separated in correspondence with the source / drain contact 250. Except for this difference, the description of the sub-impurity region 232S is substantially the same as the description of the third impurity region 232 in FIG.

[0053] Specifically, the sub-impurity regions 232S are in contact with the source / drain contacts 250. The sub-impurity regions 232S are arranged in the second direction Y corresponding to the source / drain contacts 250. The sub-impurity regions 232S are aligned in the second direction Y to be spaced apart from each other.

[0054] 9 is a layout diagram illustrating transistors according to some embodiments. For convenience of explanation, the following will focus on differences from the contents explained with reference to FIGS.

[0055] 9, the second impurity region 215 is disposed in the substrate 200. The second impurity region 215 is surrounded by the substrate 200. The second impurity region 215 does not overlap with the source / drain contact groups 250_G1, 250_G2, and 250_G3 in the second direction Y.

[0056] Hereinafter, a semiconductor memory device including a transistor according to an exemplary embodiment will be described with reference to FIGS.

[0057] FIG. 10 is an exemplary block diagram illustrating a semiconductor memory device according to some embodiments.

[0058] Referring to FIG. 10, a semiconductor memory device 10 according to some embodiments includes a memory cell array 20 and a peripheral circuit 30.

[0059] The memory cell array 20 includes a plurality of memory cell blocks BLK1 to BLKn. Each of the memory cell blocks BLK1 to BLKn includes a plurality of memory cells. The memory cell array 20 is connected to a peripheral circuit 30 via bit lines BL, word lines WL, at least one string selection line SSL, and at least one ground selection line GSL. Specifically, the memory cell blocks BLK1 to BLKn are connected to a row decoder 33 via the word lines WL, the string selection lines SSL, and the ground selection line GSL. In addition, the memory cell blocks BLK1 to BLKn are connected to a page buffer 35 via the bit lines BL.

[0060] The peripheral circuit 30 receives an address ADDR, a command CMD, and a control signal CTRL from outside the semiconductor memory device 10, and transmits and receives data DATA to and from devices outside the semiconductor memory device 10. The peripheral circuit 30 includes a control logic 37, a row decoder 33, and a page buffer 35. Although not shown in the drawing, the peripheral circuit 30 further includes various sub-circuits such as an input / output circuit, a voltage generating circuit that generates various voltages necessary for the operation of the semiconductor memory device 10, and an error correction circuit that corrects errors in the data DATA read from the memory cell array 20.

[0061] The control logic 37 is coupled to the row decoder 33, the input / output circuitry, and the voltage generating circuitry. The control logic 37 controls the overall operation of the semiconductor memory device 10. The control logic 37 generates various internal control signals used within the semiconductor memory device 10 in response to a control signal CTRL. For example, the control logic 37 adjusts the voltage levels provided to the word lines WL and bit lines BL when a memory operation such as a program operation or an erase operation is performed.

[0062] The row decoder 33 selects at least one of the memory cell blocks BLK1 to BLKn in response to the address ADDR, and selects at least one word line WL, at least one string selection line SSL, and at least one ground selection line GSL of the selected memory cell block BLK1 to BLKn. The row decoder 33 also transmits a voltage for executing a memory operation to the word line WL of the selected memory cell block BLK1 to BLKn.

[0063] The page buffer 35 is connected to the memory cell array 20 via bit lines BL. The page buffer 35 operates as a writer driver or a sense amplifier. More specifically, during a program operation, the page buffer 35 operates as a writer driver to apply a voltage to the bit lines BL corresponding to data DATA to be stored in the memory cell array 20. During a read operation, the page buffer 35 operates as a sense amplifier to sense the data DATA stored in the memory cell array 20.

[0064] FIG. 11 is an example circuit diagram illustrating a semiconductor memory device according to some embodiments.

[0065] 11, a memory cell array (eg, 20 in FIG. 10) of a semiconductor memory device according to some embodiments includes a common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR.

[0066] The common source line CSL extends in a first direction X. In some embodiments, the common source lines CSL are arranged two-dimensionally. For example, the common source lines CSL are spaced apart from each other and extend in the first direction X. The common source lines CSL are electrically controlled separately by applying the same voltage or applying different voltages to each of the common source lines CSL.

[0067] A plurality of bit lines BL are arranged two-dimensionally. For example, the bit lines BL are spaced apart from each other and extend in a second direction Y intersecting with the first direction X. A plurality of cell strings CSTR are connected in parallel to each bit line BL. The cell strings CSTR are commonly connected to a common source line CSL. That is, a plurality of cell strings CSTR are arranged between the bit lines BL and the common source line CSL.

[0068] Each cell string CSTR includes a ground selection transistor GST connected to a common source line CSL, a string selection transistor SST connected to a bit line BL, and a plurality of memory cell transistors MCT arranged between the ground selection transistor GST and the string selection transistor SST. Each memory cell transistor MCT includes a data storage element. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT are connected in series.

[0069] The common source line CSL is commonly connected to the sources of the ground select transistors GST. Between the common source line CSL and the bit line BL, a ground select line GSL, a plurality of word lines WL11 to WL1n, WL21 to WL2n, and a string select line SSL are arranged. The ground select line GSL is used as a cell gate electrode of the ground select transistor GST, the word lines WL11 to WL1n, WL21 to WL2n are used as cell gate electrodes of the memory cell transistors MCT, and the string select line SSL is used as a cell gate electrode of the string select transistor SST.

[0070] In some embodiments, an erase control transistor ECT is disposed between a common source line CSL and a ground select transistor GST. The common source line CSL is commonly connected to the sources of the erase control transistors ECT. An erase control line ECL is disposed between the common source line CSL and the ground select line GSL. The erase control line ECL is used as a cell gate electrode of the erase control transistor ECT. The erase control transistor ECT generates a gate induced drain leakage (GIDL) to perform an erase operation of the memory cell array.

[0071] 12 is a diagram illustrating a semiconductor memory device according to some embodiments, and FIG 13 is an enlarged view illustrating region R1 of FIG 12.

[0072] 12 and 13, a semiconductor memory device according to some embodiments includes a memory cell region CELL and a peripheral circuit region PERI. The memory cell region CELL is stacked on the peripheral circuit region PERI.

[0073] The memory cell region CELL includes a cell substrate 100, an insulating substrate 101, mold structures MS1, MS2, interlayer insulating films 140a, 140b, a channel structure CH, a channel pad 136, a bit line BL, a cell contact 162, a source contact 164, a through via 166, and a first wiring structure 180.

[0074] The cell substrate 100 may include a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the cell substrate 100 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. In some embodiments, the cell substrate 100 includes an impurity. For example, the cell substrate 100 includes an N-type impurity (e.g., phosphorus (P), arsenic (As), etc.).

[0075] The cell substrate 100 includes a cell array region CAR and an extension region EXT.

[0076] In the cell array region CAR, a memory cell array (e.g., 20 in FIG. 10) including a plurality of memory cells is formed. For example, in the cell array region CAR, a channel structure CH, bit lines BL, and cell gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, SSL2, etc., which will be described later, are arranged. In the following description, the surface of the cell substrate 100 on which the memory cell array is arranged is referred to as the front side of the cell substrate 100. Conversely, the surface of the cell substrate 100 opposite to the front side of the cell substrate 100 is referred to as the back side of the cell substrate 100.

[0077] The extension region EXT is arranged around the cell array region CAR. In the extension region EXT, cell gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2, which will be described later, are stacked in a stepped shape.

[0078] In some embodiments, the cell substrate 100 further includes a through region THR. The through region THR is disposed inside the cell array region CAR and the extension region EXT, or outside the cell array region CAR and the extension region EXT. A through via 166, which will be described later, is disposed in the through region THR.

[0079] The insulating substrate 101 is formed in the cell substrate 100 in the extension region EXT. The insulating substrate 101 forms an insulating region in the cell substrate 100 in the extension region EXT. The insulating substrate 101 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. In some embodiments, the insulating substrate 101 is formed in the cell substrate 100 in the through region THR.

[0080] Although the bottom surface of insulating substrate 101 is shown only as being coplanar with the bottom surface of cell substrate 100, this is merely an example. As another example, the bottom surface of insulating substrate 101 may be lower than the bottom surface of cell substrate 100.

[0081] The mold structures MS1 and MS2 are formed on the front surface of the cell substrate 100. The mold structures MS1 and MS2 include a plurality of cell gate electrodes ECL, GSL1, GSL2, WL11-WL1n, WL21-WL2n, SSL1, SSL2, and a plurality of mold insulating films 110 and 115 that are stacked on the cell substrate 100. The cell gate electrodes ECL, GSL1, GSL2, WL11-WL1n, WL21-WL2n, SSL1, SSL2, and the mold insulating films 110 and 115 have layered structures extending parallel to the front surface of the cell substrate 100. The cell gate electrodes ECL, GSL1, GSL2, WL11-WL1n, WL21-WL2n, SSL1, SSL2 are stacked in order on the cell substrate 100, separated from each other by the mold insulating films 110 and 115.

[0082] In some embodiments, the mold structures MS1, MS2 include a first mold structure MS1 and a second mold structure MS2 that are stacked in sequence on the cell substrate 100.

[0083] The first mold structure MS1 includes first cell gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, and a first mold insulating film 110, which are alternately stacked on the cell substrate 100. In some embodiments, the first cell gate electrodes ECL, GSL1, GSL2, WL11 to WL1n include an erase control line ECL, ground selection lines GSL1, GSL2, and a plurality of first word lines WL11 to WL1n, which are stacked in sequence on the cell substrate 100. The ground selection lines GSL1, GSL2 include a first ground selection line GSL1 and a second ground selection line GSL2, which are stacked in sequence. Although the first cell gate electrodes ECL, GSL1, GSL2, WL11 to WL1n are shown only to include two ground selection lines GSL1, GSL2, this is only an example, and the first cell gate electrodes ECL, GSL1, GSL2, WL11 to WL1n may include three or more ground selection lines. In some other embodiments, the erase control line ECL may be omitted.

[0084] The second mold structure MS2 includes second cell gate electrodes WL21-WL2n, SSL1, SSL2, and a second mold insulating film 115, which are alternately stacked on the first mold structure MS1. In some embodiments, the second cell gate electrodes WL21-WL2n, SSL1, SSL2 include a plurality of second word lines WL21-WL2n and string selection lines SSL1, SSL2, which are stacked in sequence on the first mold structure MS1. The string selection lines SSL1, SSL2 include a first string selection line SSL1 and a second string selection line SSL2, which are stacked in sequence. Although the second cell gate electrodes WL21-WL2n, SSL1, SSL2 are shown to include only two string selection lines SSL1, SSL2, this is merely an example, and the second cell gate electrodes WL21-WL2n, SSL1, SSL2 may include three or more string selection lines.

[0085] The cell gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2 each include, but are not limited to, a conductive material, for example, a metal such as tungsten (W), cobalt (Co), or nickel (Ni), or a semiconductor material such as silicon.

[0086] Each of the mold insulating layers 110, 115 includes an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0087] In some embodiments, the mold structure MS1, MS2 of the through region THR includes a plurality of mold sacrificial films 112, 117 and a plurality of mold insulating films 110, 115 alternately stacked on the cell substrate 100 and / or the insulating substrate 101. Each of the mold sacrificial films 112, 117 and each of the mold insulating films 110, 115 has a layered structure extending parallel to the upper surface of the cell substrate 100. The mold sacrificial films 112, 117 are sequentially stacked on the cell substrate 100, spaced apart from each other by the mold insulating films 110, 115.

[0088] In some embodiments, the first mold structure MS1 of the through region THR includes a first mold sacrificial film 112 and a first mold insulating film 110 alternately stacked on the cell substrate 100, and the second mold structure MS2 of the through region THR includes a second mold sacrificial film 117 and a second mold insulating film 115 alternately stacked on the first mold structure MS1.

[0089] The mold sacrificial layers 112, 117 each include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, and silicon oxynitride. In some embodiments, the mold sacrificial layers 112, 117 include a material that has an etch selectivity with respect to the mold insulating layers 110, 115. As an example, the mold insulating layers 110, 115 include silicon oxide and the mold sacrificial layers 112, 117 include silicon nitride.

[0090] The interlayer insulating films 140a and 140b are formed on the cell substrate 100 and cover the mold structures MS1 and MS2. In some embodiments, the interlayer insulating films 140a and 140b include a first interlayer insulating film 140a and a second interlayer insulating film 140b that are sequentially stacked on the cell substrate 100. The first interlayer insulating film 140a covers the first mold structure MS1, and the second interlayer insulating film 140b covers the second mold structure MS2. The interlayer insulating films 140a and 140b include, for example, but are not limited to, at least one of silicon oxide, silicon oxynitride, and a low-k material having a dielectric constant smaller than that of silicon oxide.

[0091] The channel structure CH is formed in the mold structures MS1, MS2 in the cell array region CAR. The channel structure CH extends in a vertical direction (hereinafter, third direction Z) intersecting with the upper surface of the cell substrate 100 and penetrates the mold structures MS1, MS2. For example, the channel structure CH has a pillar shape (e.g., a cylindrical shape) extending in the third direction Z. Therefore, the channel structure CH intersects with each of the cell gate electrodes ECL, GSL1, GSL2, WL11-WL1n, WL21-WL2n, SSL1, SSL2. In some embodiments, the channel structure CH has a bent portion between the first mold structure MS1 and the second mold structure MS2.

[0092] The channel structure CH includes a semiconductor pattern 130 and an information storage film 132 .

[0093] The semiconductor pattern 130 extends in a third direction Z and penetrates the mold structures MS1 and MS2. Although only a cup-shaped semiconductor pattern 130 is shown, this is merely an example. For example, the semiconductor pattern 130 may have various shapes such as a cylinder, a rectangular tube, a solid pillar, etc. For example, the semiconductor pattern 130 may include semiconductor materials such as, but not limited to, single crystal silicon, polycrystalline silicon, organic semiconductors, and carbon nanostructures.

[0094] The information storage film 132 is interposed between the semiconductor pattern 130 and each of the cell gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2. For example, the information storage film 132 extends along the outer side of the semiconductor pattern 130. The information storage film 132 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high dielectric constant material having a dielectric constant greater than that of silicon oxide. The high dielectric constant material may include at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

[0095] In some embodiments, the information storage layer 132 is formed of multiple layers. For example, the information storage layer 132 includes a tunnel insulating layer 132a, a charge storage layer 132b, and a blocking insulating layer 132c, which are sequentially stacked on the outer surface of the semiconductor pattern 130. The tunnel insulating layer 132a is, for example, silicon oxide or a high dielectric constant material having a higher dielectric constant than silicon oxide (e.g., aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 The charge storage film 132b may include, for example, silicon nitride. The blocking insulating film 132c may include, for example, silicon oxide or a high-k material having a higher dielectric constant than silicon oxide (for example, aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 )).

[0096] In some embodiments, the channel structure CH further includes a fill pattern 134. The fill pattern 134 is formed to fill the interior of the cup-shaped semiconductor pattern 130. The fill pattern 134 may include an insulating material, such as, but not limited to, silicon oxide.

[0097] In some embodiments, the channel structure CH further includes a channel pad 136. The channel pad 136 is formed to connect with the upper portion of the semiconductor pattern 130. The channel pad 136 includes, but is not limited to, for example, polysilicon doped with impurities.

[0098] In some embodiments, the channel structures CH are arranged in a zigzag shape. For example, the channel structures CH are arranged alternately in a first direction X and a second direction Y parallel to the top surface of the cell substrate 100. The channel structures CH arranged in a zigzag shape can further improve the integration density of the semiconductor memory device. In some embodiments, the channel structures CH may be arranged in a honeycomb shape.

[0099] In some embodiments, dummy channel structures DCH are formed in the mold structures MS1, MS2 in the extension region EXT. The dummy channel structures DCH are formed in a shape similar to the channel structures CH and can reduce stress applied to the mold structures MS1, MS2 in the extension region EXT.

[0100] In some embodiments, first source structures 102, 104 are formed on the cell substrate 100. The first source structures 102, 104 are interposed between the cell substrate 100 and the mold structures MS1, MS2. For example, the first source structures 102, 104 extend along the top surface of the cell substrate 100. The first source structures 102, 104 are formed to be connected to the semiconductor pattern 130 of the channel structure CH. For example, as shown in FIG. 13, the first source structures 102, 104 penetrate the information storage layer 132 to contact the semiconductor pattern 130. The first source structures 102, 104 are provided as a common source line (e.g., CSL in FIG. 2) of the semiconductor memory device. The first source structures 102, 104 may include, but are not limited to, polysilicon or metal doped with impurities.

[0101] In some embodiments, the channel structure CH passes through the first source structures 102, 104. For example, a lower portion of the channel structure CH passes through the first source structures 102, 104 and is disposed within the cell substrate 100.

[0102] In some embodiments, the first source structures 102, 104 are formed of multiple layers. For example, the first source structures 102, 104 include a first source layer 102 and a second source layer 104 that are sequentially stacked on the cell substrate 100. The first source layer 102 and the second source layer 104 each include, but are not limited to, polysilicon doped with impurities or polysilicon not doped with impurities. The first source layer 102 contacts the semiconductor pattern 130 and serves as a common source line (e.g., CSL in FIG. 10) of the semiconductor memory device. The second source layer 104 is used as a support layer to prevent collapse or tipping of the mold stack during a replacement process for forming the first source layer 102.

[0103] Although not shown in the drawings, a base insulating film is interposed between the cell substrate 100 and the first source structures 102, 104. The base insulating film may include, but is not limited to, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0104] In some embodiments, the first source structures 102, 104 are not formed in the extension region EXT where the insulating substrate 101 is formed. Although the top surface of the insulating substrate 101 is only shown to be coplanar with the top surfaces of the first source structures 102, 104, this is merely an example. As another example, the top surface of the insulating substrate 101 may be higher than the top surfaces of the first source structures 102, 104.

[0105] In some embodiments, a source sacrificial layer 103 is formed on a portion of the cell substrate 100. For example, the source sacrificial layer 103 is formed on a portion of the cell substrate 100 in the extension region EXT. The source sacrificial layer 103 includes a material having an etch selectivity with respect to the mold insulating layers 110 and 115. For example, the mold insulating layers 110 and 115 include silicon oxide, and the source sacrificial layer 103 includes silicon nitride. The source sacrificial layer 103 is a layer that remains after a portion of the source structure 102 and 104 is replaced by the first source layer 102 during the manufacturing process of the first source structures 102 and 104.

[0106] The block isolation region WCf, the first partial isolation region WC1, and the second partial isolation region WC2 each extend in the first direction X to cut the mold structures MS1, MS2. The block isolation region WCf completely cuts the mold structures MS1, MS2. For example, the block isolation region WCf extends continuously in the first direction X. The first partial isolation region WC1 and the second partial isolation region WC2 each partially cut the mold structures MS1, MS2. For example, the first partial isolation regions WC1 in a row arranged along the first direction X are separated from each other to partially cut the mold structures MS1, MS2, and the second partial isolation regions WC2 in a row arranged along the first direction X are separated from each other to partially cut the mold structures MS1, MS2.

[0107] The bit lines BL are formed on the mold structures MS1 and MS2. The bit lines BL extend in the second direction Y and intersect with the block isolation region WCf. The bit lines BL also extend in the second direction Y and are connected to a plurality of channel structures CH arranged along the second direction Y. For example, bit line contacts 182 connected to upper portions of the respective channel structures CH are formed in the second interlayer insulating film 140b. The bit lines BL are electrically connected to the channel structures CH via the bit line contacts 182.

[0108] The cell contacts 162 are connected to the respective cell gate electrodes ECL, GSL1, GSL2, WL11-WL1n, WL21-WL2n, SSL1, and SSL2. For example, the cell contacts 162 extend in the third direction Z in the interlayer insulating films 140a and 140b and are connected to the respective cell gate electrodes ECL, GSL1, GSL2, WL11-WL1n, WL21-WL2n, SSL1, and SSL2. In some embodiments, the cell contacts 162 have a bent portion between the first mold structure MS1 and the second mold structure MS2.

[0109] The source contact 164 is connected to the first source structures 102, 104. For example, the source contact 164 extends in the interlayer insulating films 140a, 140b in the third direction Z to be connected to the cell substrate 100. In some embodiments, the source contact 164 has a bent portion between the first mold structure MS1 and the second mold structure MS2. The through via 166 is disposed within the through region THR. For example, the through via 166 extends in the third direction Z within the mold structures MS1, MS2 in the through region THR. In some embodiments, the through via 166 has a bend between the first mold structure MS1 and the second mold structure MS2. Although the through via 166 is shown only passing through the mold structures MS1, MS2, this is merely exemplary. As another example, the through via 166 may be disposed outside the mold structures MS1, MS2 and not pass through the mold structures MS1, MS2.

[0110] The cell contact 162, the source contact 164, and the through via 166 are each connected to a first wiring structure 180 on the interlayer insulating films 140a and 140b. For example, a second interlayer insulating film 142 is formed on the second interlayer insulating film 140b. The first wiring structure 180 is formed in the second interlayer insulating film 142. The cell contact 162, the source contact 164, and the through via 166 are each connected to the first wiring structure 180 by a contact via 184. Although not specifically shown, the first wiring structure 180 is connected to a bit line BL.

[0111] The peripheral circuit region PERI includes a substrate 200 , a peripheral circuit element PT, and a second wiring structure 270 .

[0112] The peripheral circuit elements PT are formed on the substrate 200. The peripheral circuit elements PT constitute peripheral circuits (e.g., 30 in FIG. 10) that control the operation of the semiconductor memory device. For example, the peripheral circuit elements PT include a control logic (e.g., 37 in FIG. 10), a row decoder (e.g., 33 in FIG. 10), and a page buffer (e.g., 35 in FIG. 10). In the following description, the surface of the substrate 200 on which the peripheral circuit elements PT are disposed is referred to as the front side of the substrate 200. Conversely, the surface of the substrate 200 opposite to the front side of the substrate 200 is referred to as the back side of the substrate 200.

[0113] The peripheral circuit elements PT may include, for example, the transistors described with reference to Figures 1 to 9. However, the present invention is not limited to this. For example, the peripheral circuit elements PT may include, in addition to the transistors described with reference to Figures 1 to 9, various active elements and various passive elements such as a capacitor, a resistor, and an inductor.

[0114] In some embodiments, the rear surface of the cell substrate 100 faces the front surface of the substrate 200. For example, a first inter-wiring insulating film 240 covering the peripheral circuit elements PT is formed on the front surface of the substrate 200. The cell substrate 100 and / or the insulating substrate 101 are stacked on the upper surface of the first inter-wiring insulating film 240.

[0115] The first wiring structure 180 is connected to the peripheral circuit element PT through the through via 166. For example, a second wiring structure 270 connected to the peripheral circuit element PT is formed in the first inter-wiring insulating film 240. The through via 166 extends in the third direction Z to connect the first wiring structure 180 and the second wiring structure 270. As a result, the bit line BL, the respective cell gate electrodes ECL, GSL1, GSL2, WL11-WL1n, WL21-WL2n, SSL1, SSL2, and / or the first source structures 102, 104 are electrically connected to the peripheral circuit element PT.

[0116] In some embodiments, the through via 166 penetrates the insulating substrate 101 to connect the first wiring structure 180 to the second wiring structure 270. This allows the through via 166 to be electrically isolated from the cell substrate 100.

[0117] 14 is a diagram illustrating a semiconductor memory device according to some embodiments. For convenience of explanation, the following description will focus on differences from the contents described with reference to FIGS.

[0118] 14, in a semiconductor memory device according to some embodiments, a front surface of a cell substrate 100 faces a front surface of a substrate 200. In the embodiment shown in FIG.

[0119] For example, the semiconductor memory device according to some embodiments has a C2C (chip to chip) structure. The C2C structure means that an upper chip including a memory cell region CELL is fabricated on a first wafer (e.g., cell substrate 100), a lower chip including a peripheral circuit region PERI is fabricated on a second wafer (e.g., substrate 200) different from the first wafer, and then the upper chip and the lower chip are connected to each other by a bonding method.

[0120] As an example, the bonding method refers to a method of electrically connecting a first bonding metal 190 formed on the top metal layer of an upper chip and a second bonding metal 290 formed on the top metal layer of a lower chip to each other. For example, if the first bonding metal 190 and the second bonding metal 290 are made of copper (Cu), the bonding method is a Cu-Cu bonding method. However, this is only an example, and the first bonding metal 190 and the second bonding metal 290 may be made of various other metals such as aluminum (Al) or tungsten (W).

[0121] The first bonding metal 190 and the second bonding metal 290 are bonded to connect the first wiring structure 180 to the second wiring structure 270. As a result, the bit line BL, the respective cell gate electrodes ECL, GSL1, GSL2, WL11-WL1n, WL21-WL2n, SSL1, SSL2, and / or the first source structures 102, 104 are electrically connected to the peripheral circuit elements PT.

[0122] 15 is a diagram illustrating a semiconductor memory device according to some embodiments. For convenience of explanation, the following description will focus on differences from the contents described with reference to FIGS.

[0123] Referring to FIG. 15, a semiconductor memory device according to some embodiments includes a memory cell area CELL and a peripheral circuit area PERI.

[0124] Unlike the illustration in FIG. 12, the peripheral circuit region PERI is arranged around the cell region CELL. The peripheral region PERI includes peripheral circuit elements PT. Although not shown, through vias are arranged on the peripheral region PERI. The peripheral circuit elements PT are electrically connected to the bit lines BL, the respective cell gate electrodes ECL, GSL1, GSL2, WL11-WL1n, WL21-WL2n, SSL1, SSL2, and / or the first source structures 102, 104 through the through vias.

[0125] Fig. 16 is an exemplary block diagram for explaining an electronic system according to some embodiments. Fig. 17 is an exemplary perspective view for explaining an electronic system according to some embodiments. Fig. 18 is a schematic cross-sectional view taken along II in Fig. 17.

[0126] 16, an electronic system 1000 according to some embodiments includes a semiconductor memory device 1100 and a controller 1200 electrically connected to the semiconductor memory device 1100. The electronic system 1000 is a storage device including one or more semiconductor memory devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 is a solid state drive device (SSD device), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor memory devices 1100.

[0127] The semiconductor memory device 1100 is a non-volatile memory device (e.g., a NAND flash memory device), such as the semiconductor memory device described above with reference to Figures 10 to 15. The semiconductor memory device 1100 includes a first structure 1100F and a second structure 1100S on the first structure 1100F.

[0128] The first structure 1100F is a peripheral circuit structure including a decoder circuit 1110 (eg, row decoder 33 in FIG. 10), a page buffer 1120 (eg, page buffer 35 in FIG. 10), and a logic circuit 1130 (eg, control logic 37 in FIG. 10).

[0129] The second structure 1100S includes a common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR, as described above with reference to Fig. 2. The cell strings CSTR are coupled to a decoder circuit 1110 via word lines WL, at least one string select line SSL, and at least one ground select line GSL. The cell strings CSTR are also coupled to a page buffer 1120 via bit lines BL.

[0130] In some embodiments, the common source line CSL and the cell string CSTR are electrically connected to the decoder circuit 1110 via a first interconnection 1115 extending from the first structure 1100F to the second structure 1100S. The first interconnection 1115 corresponds to the through vias 166 described above with reference to Figures 10 to 15. That is, the through vias 166 electrically connect the cell gate electrodes ECL, GSL, WL, SSL to the decoder circuit 1110 (for example, the row decoder 33 in Figure 10).

[0131] In some embodiments, the bit line BL is electrically connected to the page buffer 1120 via a second connection wire 1125 extending from the first structure 1100F to the second structure 1100S. The second connection wire 1125 corresponds to the through via 166 described above with reference to Figures 10 to 15. That is, the through via 166 electrically connects the bit line BL to the page buffer 1120 (e.g., the page buffer 35 in Figure 10).

[0132] The semiconductor memory device 1100 communicates with the controller 1200 through an I / O pad 1101 electrically connected to a logic circuit 1130 (e.g., the control logic 37 in FIG. 10). The I / O pad 1101 is electrically connected to the logic circuit 1130 through an I / O connection wiring 1135 extending to a second structure 1100S within the first structure 1100F.

[0133] The controller 1200 includes a processor 1210, a NAND controller 1220, and a host interface 1230. In some embodiments, the electronic system 1000 includes multiple semiconductor memory devices 1100, in which case the controller 1200 controls the multiple semiconductor memory devices 1100.

[0134] The processor 1210 controls the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 operates according to a predetermined firmware and controls the NAND controller 1220 to access the semiconductor memory device 1100. The NAND controller 1220 includes a NAND interface 1221 that processes communication with the semiconductor memory device 1100. A control command for controlling the semiconductor memory device 1100, data to be written to the memory cell transistor MCT of the semiconductor memory device 1100, data to be read from the memory cell transistor MCT of the semiconductor memory device 1100, etc. are transferred via the NAND interface 1221. The host interface 1230 provides a communication function between the electronic system 1000 and an external host. When a control command is received from the external host via the host interface 1230, the processor 1210 controls the semiconductor memory device 1100 in response to the control command.

[0135] 17 and 18, an electronic system according to some embodiments includes a main board 2001, a main controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 are connected to the main controller 2002 by a wiring pattern 2005 formed on the main board 2001.

[0136] The main board 2001 includes a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 vary depending on the communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 communicates with the external host through any one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). In some embodiments, the electronic system 2000 operates with power supplied from the external host via the connector 2006. The electronic system 2000 further includes a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the main controller 2002 and the semiconductor package 2003.

[0137] The main controller 2002 records data to or reads data from the semiconductor package 2003 to improve the operating speed of the electronic system 2000 .

[0138] The DRAM 2004 is a buffer memory for mitigating the speed difference between the semiconductor package 2003, which is a data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 also operates as a kind of cache memory, providing space for temporarily storing data in a control operation for the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, the main controller 2002 further includes a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

[0139] The semiconductor package 2003 includes a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. The first semiconductor package 2003a and the second semiconductor package 2003b are each a semiconductor package including a plurality of semiconductor chips 2200. The first semiconductor package 2003a and the second semiconductor package 2003b each include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each of the semiconductor chips 2200, a connection structure 2400 that electrically connects the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 that covers the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0140] Package substrate 2100 is a printed circuit board that includes package top pads 2130. Each semiconductor chip 2200 includes input / output pads 2210. Input / output pads 2210 correspond to input / output pads 1101 in FIG.

[0141] In some embodiments, the connecting structure 2400 is a bonding wire that electrically connects the I / O pad 2210 and the package top pad 2130. Thus, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 are electrically connected to each other in a bonding wire manner and electrically connected to the package top pad 2130 of the package substrate 2100. In some embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 are electrically connected to each other by a connecting structure including a through silicon via (TSV) instead of the connecting structure 2400 in a bonding wire manner.

[0142] In some embodiments, the main controller 2002 and the semiconductor chip 2200 are included in one package. In some embodiments, the main controller 2002 and the semiconductor chip 2200 are mounted on a main substrate 2001 and a separate interposer substrate, and the main controller 2002 and the semiconductor chip 2200 are connected to each other by wiring formed on the interposer substrate.

[0143] In some embodiments, the package substrate 2100 is a printed circuit board. The package substrate 2100 includes a package substrate body part 2120, a package upper pad 2130 disposed on an upper surface of the package substrate body part 2120, a lower pad 2125 disposed on or exposed through a lower surface of the package substrate body part 2120, and an internal wiring 2135 electrically connecting the upper pad 2130 and the lower pad 2125 inside the package substrate body part 2120. The upper pad 2130 is electrically connected to a connecting structure 2400. The lower pad 2125 is connected to a wiring pattern 2005 of a main substrate 2001 of the electronic system 2000 via a conductive connecting part 2800 as shown in FIG.

[0144] In an electronic system according to some embodiments, each of the semiconductor chips 2200 includes the semiconductor memory device described above with reference to Figures 10 to 15. For example, each of the semiconductor chips 2200 includes a peripheral circuit region PERI and a memory cell region CELL stacked on the peripheral circuit region PERI. Exemplarily, the peripheral circuit region PERI includes the transistors described above with reference to Figures 1 to 9. Also, exemplarily, the memory cell region CELL includes the cell substrate 100, mold structures MS1, MS2, and channel structure CH described above with reference to Figures 10 to 15.

[0145] Although the embodiments of the present invention have been described above with reference to the drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical idea or essential features of the present invention. Therefore, it should be understood that the above embodiments are illustrative in all respects and are not limiting. [Explanation of symbols]

[0146] 100 cell substrate 101 Insulating substrate 102, 104 First source structure 103 Source sacrificial film 110, 115 Mold insulating film 112, 117 Mold sacrificial film 130 Semiconductor Pattern 132 Information Storage Membrane 134 Filling Patterns 136 Channel Pad 140a, 140b Interlayer insulating film 162 Cell Contact 164 Source Contacts 166 Through Via 180 1st wiring structure 182 bit line contacts 184 Contact Vias 200 Substrates 210 1st impurity region 215 Second impurity region 220 Gate electrode 225 Gate insulating film 230 Source / Drain Region 232 Third impurity region 235 Element Isolation Film 240 First inter-wiring insulating film 250 Source / Drain Contacts 270 2nd wiring structure

Claims

1. a substrate including an active area; an isolation layer in the substrate that defines the active region; a first impurity region disposed on a lower surface of the element isolation film; a second impurity region disposed in the substrate; a gate electrode extending in a first direction on the substrate; a source / drain region disposed on at least one side of the gate electrode; a first group of source / drain contacts disposed on the source / drain regions; a first source / drain contact group and a second source / drain contact group spaced apart from each other in the first direction on the source / drain region; the second impurity region being disposed between the first source / drain contact group and the second source / drain contact group.

2. 2. The transistor of claim 1, wherein the second impurity region extends in the substrate in a second direction that intersects with the first direction.

3. 2. The transistor of claim 1, wherein the first impurity region and the second impurity region contain dopants of the same conductivity type.

4. 2. The transistor of claim 1, wherein a number of source / drain contacts in the first source / drain contact group is the same as a number of source / drain contacts in the second source / drain contact group.

5. Based on the upper surface of the substrate, 2. The transistor of claim 1, wherein a distance to the first impurity region is different from a distance to the second impurity region.

6. Based on the upper surface of the substrate, 2. The transistor of claim 1, wherein a distance to the first impurity region is the same as a distance to the second impurity region.

7. 2. The transistor of claim 1, wherein the first impurity region and the second impurity region each contain a P-type dopant.

8. The source / drain region is a third impurity region in contact with the first source / drain contact group; a fourth impurity region disposed between the third impurity region and the gate electrode; 2. The transistor according to claim 1, wherein the third impurity region has an N-type impurity concentration greater than an N-type impurity concentration of the fourth impurity region.

9. the first source / drain contact group includes a plurality of first source / drain contacts; 9. The transistor of claim 8, wherein the third impurity region includes sub-impurity regions corresponding to each of the first source / drain contacts.

10. a third source / drain contact group on the source / drain region and spaced apart from the second source / drain contact group in the first direction; 2. The transistor of claim 1, wherein a distance between the first source / drain contact group and the second source / drain contact group in the first direction is the same as a distance between the second source / drain contact group and the third source / drain contact group.

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