SiC WAFER, SINGLE CRYSTAL EPITAXIAL LAYER, AND METHOD FOR MANUFACTURING SiC WAFER

Abstract

To provide a SiC wafer with an epitaxial growth layer that can reduce variations in gate insulating film life after device formation by controlling the composition of the wafer surface in the SiC wafer before device formation.SOLUTION: A SiC wafer includes a SiC substrate, and a single crystal epitaxial layer formed on the SiC substrate and containing SiC, and a C-Si composition ratio of an upper surface of the single crystal epitaxial layer is 50 atm% or less and greater than 10 atm%.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a SiC wafer, and in particular, is applicable to a SiC wafer having an epitaxial layer formed thereon and a method for manufacturing the same. [Background technology]

[0002] Semiconductor power elements are required to have high breakdown voltage, low on-resistance, and low switching loss, but silicon (Si) power elements, which are currently the mainstream, are approaching their theoretical performance limits. Silicon carbide (SiC) has a dielectric breakdown field strength approximately one order of magnitude higher than Si, so by making the drift layer that maintains the breakdown voltage approximately one-tenth thinner and increasing the impurity concentration by approximately 100 times, it is theoretically possible to reduce element resistance by three orders of magnitude or more. In addition, because the band gap is approximately three times larger than that of Si, high temperature operation is also possible, and SiC semiconductor elements are expected to exceed the performance of Si semiconductor elements, and the development of SiC power devices is underway.

[0003] Patent Document 1 (JP 2012-142597 A) describes preventing the occurrence of step bunching on the substrate surface.

[0004] Patent Document 2 (JP 2010-258294 A) describes evaporating silicon atoms from the surface of a silicon carbide epitaxial layer to make the silicon carbide surface contain 95 at % or more of carbon atoms.

[0005] Patent Documents 3 to 7 describe adjusting the conditions during epitaxial growth to control the flow rate ratio (raw material supply ratio) or the composition ratio of the epitaxial growth layer. However, the techniques described in Patent Documents 3 to 7 do not make the surface of the epitaxial growth layer carbon-rich, and the flow rate ratio does not correlate with the composition ratio of the surface of the SiC wafer. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2012-142597 A [Patent Document 2] JP 2010-258294 A [Patent Document 3] JP 2003-282451 A [Patent Document 4] JP 2015-143168 A [Patent Document 5] JP 2009-239103 A [Patent Document 6] JP 2007-137689 A [Patent Document 7] International Publication No. 2015 / 159949 [Non-patent literature]

[0007] [Non-Patent Document 1] Senzaki, Junji, et al. "Challenges of High-Performance and High-Reliablity in SiC MOS Structures." Materials Science Forum. Vol. 717. Trans TechPublications, 2012. Summary of the Invention [Problem to be solved by the invention]

[0008] In the mass production process of SiC devices, multiple chip formation regions are simultaneously created on a wafer, and the wafer is divided into multiple chips in a dicing process. There would be no problem if the characteristics of each chip were all the same, but there will be a certain number of defective chips, and the device characteristics will vary greatly between chips. In particular, for power devices that require a large area, it is important to reduce the variation in device characteristics in order to improve yields. For example, Non-Patent Document 1 describes how the reliability of gate insulating films can be improved by preventing the occurrence of step bunching on the substrate surface.

[0009] An object of the present invention is to provide a SiC wafer with an epitaxially grown layer that can reduce variations in gate insulating film life by controlling the composition of the wafer surface.

[0010] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0011] A brief outline of a representative embodiment of the present invention will be described below.

[0012] An SiC wafer according to one embodiment includes a SiC substrate and an epitaxial layer containing SiC formed on the SiC substrate, the epitaxial layer having a C-Si composition ratio of an upper surface of the epitaxial layer being 50 atm % or less. Effect of the Invention

[0013] According to the representative embodiment, the reliability of the SiC wafer can be improved. [Brief description of the drawings]

[0014] [Figure 1] 1A to 1C are plan views showing a manufacturing process of a SiC wafer according to a first embodiment. [Diagram 2] 2A to 2C are cross-sectional views showing a manufacturing process of the SiC wafer according to the first embodiment. [Diagram 3] 3 is a cross-sectional view showing a manufacturing process following FIG. 2. [Figure 4] 4 is a cross-sectional view showing a manufacturing process following FIG. 3. [Diagram 5] FIG. 1 is a schematic diagram illustrating a surface composition analysis method using XPS. [Figure 6] FIG. 1 is a schematic diagram illustrating a surface composition analysis method using XPS. [Figure 7] 1 is a graph showing details of peak separation of a C1s spectrum obtained by surface composition analysis using XPS. [Figure 8]1 is a graph showing details of peak separation of a C1s spectrum obtained by surface composition analysis using XPS. [Figure 9] 1 is a graph showing details of peak separation of a C1s spectrum obtained by surface composition analysis using XPS. [Figure 10] 1 is a graph showing details of peak separation of a C1s spectrum obtained by surface composition analysis using XPS. [Figure 11] 1 is a table showing the relationship between the composition ratio of various bonds including carbon on the surface of a SiC wafer before carbon-rich processing and the take-off angle in XPS analysis. [Figure 12] 1 is a graph showing the relationship between the composition ratio of various bonds including carbon on the surface of a SiC wafer before carbon-rich processing and the take-off angle in XPS analysis. [Figure 13] 1 is a table showing the relationship between the composition ratio of various bonds including carbon on the surface of a SiC wafer after carbon-rich processing and the take-off angle in XPS analysis. [Figure 14] 1 is a graph showing the relationship between the composition ratio of various bonds containing carbon on the surface of a SiC wafer after carbon-rich processing and the take-off angle in XPS analysis. [Figure 15] 1 is a graph showing the composition ratio of C—Si bonds and the total composition ratio of bonds containing carbon other than C—Si before and after a carbon-rich treatment. [Figure 16] This is a formula showing the cumulative failure rate. [Figure 17] 13 is a graph showing the relationship between the dielectric breakdown injection charge amount and the cumulative failure rate in each of the SiC devices of the comparative example and the present embodiment. [Figure 18] 10A to 10C are cross-sectional views showing a manufacturing process of a DMOSFET on a SiC wafer according to a modification of the first embodiment. [Figure 19] 19 is a cross-sectional view showing a manufacturing process following FIG. 18. [Figure 20] 19A to 19C are cross-sectional views showing the manufacturing process following FIG. [Figure 21] 21 is a cross-sectional view showing a manufacturing process following FIG. 20. [Figure 22] 22 is a cross-sectional view showing a manufacturing process following FIG. 21. [Figure 23] 23 is a cross-sectional view showing a manufacturing process following FIG. 22. [Figure 24] 24 is a cross-sectional view showing a manufacturing process following FIG. 23. [Diagram 25] 25 is a cross-sectional view showing a manufacturing process following FIG. 24. [Figure 26] 26 is a cross-sectional view showing a manufacturing process following FIG. 25. [Figure 27] 10A to 10C are plan views showing a process for manufacturing a DMOSFET on a SiC wafer according to a modification of the first embodiment. [Figure 28] 1 is a graph showing the composition ratios of C—Si bonds and bonds containing carbon other than C—Si bonds on the upper surface of a SiC wafer that has been subjected to an oxidation treatment. [Figure 29] 1 is a graph showing the relationship between the dielectric breakdown injection charge amount and the cumulative failure rate in a SiC device of a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same reference numerals are used for the members having the same functions, and the repeated explanations are omitted. In addition, in the embodiments, the explanations of the same or similar parts are not repeated as a rule, except when it is particularly necessary.

[0016] In this application, a wafer consisting of only a SiC substrate, and a wafer including a SiC substrate and an epitaxial layer on a SiC substrate are each referred to as a SiC wafer. The SiC substrate referred to here is a bulk substrate that does not include an epitaxial layer.

[0017] (Embodiment 1) <Details of areas for improvement> SiC (silicon carbide) has a wider band gap than Si (silicon), and the insulating film formed on the SiC substrate has high dielectric breakdown strength. Taking advantage of such characteristics, it is possible to apply a high voltage to an element formed on a SiC substrate, but in that case, the electric field applied to the insulating film becomes a problem. For this reason, when designing a device using a SiC substrate, it is necessary to fully consider the electric field applied to the insulating film. In particular, in a device structure having a gate insulating film such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor), when the electric field strength applied to the gate insulating film becomes strong, a leakage current occurs in the gate insulating film. The occurrence of such a leakage current causes a decrease in the gate insulating film life and device malfunction such as dielectric breakdown of the gate insulating film.

[0018] Such defects do not occur equally in each chip separated from a single wafer, and the gate insulating film life varies from chip (device) to chip. That is, during mass production of devices, multiple chip formation areas are simultaneously created on a wafer, and then a dicing process is performed to separate multiple chips from the wafer. There would be no problem if the characteristics of each chip were all the same, but there will always be a certain number of defective chips. Causes of defective chips include the presence of foreign matter in the manufacturing process, as well as defects on the surface of the SiC substrate, for example.

[0019] One of the defects is step bunching caused by the step-flow growth method. Step bunching often occurs locally within the wafer surface, and the uneven shapes vary widely. When devices are fabricated on a wafer with step bunching, the device characteristics vary greatly. Therefore, in order to reduce the variation, it is important to reduce defects such as unevenness. In particular, in power devices that require a large area, it is important to reduce the variation in device characteristics in order to improve yield.

[0020] Figure 29 shows, as a comparative example, the Weibull plot of the results of fabricating a MOSFET (SiC device) on a wafer mainly composed of silicon carbide and evaluating the CCS-TDDB (Constant Current Stress Time Dependent Dielectric Breakdown) characteristics for a plurality of MOSFETs present in the same wafer plane. The horizontal axis (semi-logarithmic) of the graph shown in Figure 29 indicates the amount of charge injected into the insulating film, that is, the breakdown injection charge amount Qbd, until dielectric breakdown occurs in the insulating film formed on the SiC substrate. The vertical axis of the graph indicates the cumulative failure rate. That is, Figure 29 is a graph showing the relationship between the breakdown injection charge amount and the cumulative failure rate in the SiC device of the comparative example.

[0021] The Weibull plot is a graph in which the breakdown injection charge amounts Qbd of a plurality of devices are plotted in a Weibull distribution when a constant current stress (CCS) is applied to the gate in a MOS structure such as a MOS capacitor or a MOSFET. When a constant current stress (CCS) is applied to the gate, the breakdown injection charge amount Qbd can be calculated from the stress time and the stress current by measuring the stress time until the gate insulating film breaks down.

[0022] In the Weibull plot, when the variation in the time (lifetime) until dielectric breakdown is zero, the distribution of the plot becomes a straight line parallel to the vertical axis. However, in the comparative example shown in Figure 29, the Weibull plot has a slope. Such a slope of the Weibull plot indicates the presence of variation and means that there are defects that reduce the breakdown injection charge amount Qbd.

[0023] Thus, in the SiC wafer, there is room for improvement in suppressing characteristic variations such as the lifetime of the insulating film between devices formed thereon.

[0024] <Configuration of SiC Wafer> In the present embodiment 1, a device is implemented to solve the above-mentioned room for improvement. The technical idea of ​​the present embodiment in which this device is implemented will be described below.

[0025] As a result of the inventors' research, they found that the composition of the wafer surface affects the reliability of the gate insulating film, and that the variation in the gate insulating film life can be reduced by controlling the composition of the SiC wafer surface. Below, we will explain a SiC wafer with an epitaxial layer that can reduce the variation in the gate insulating film life by controlling the composition of the SiC wafer surface.

[0026] Here, the manufacturing process of the SiC wafer of the present embodiment will be described with reference to Figures 1 to 4. Figure 1 is a plan view showing the manufacturing process of the SiC wafer of the present embodiment, and Figures 2 to 4 are cross-sectional views showing the manufacturing process of the SiC wafer of the present embodiment.

[0027] When manufacturing the SiC wafer of this embodiment, first, as shown in FIG. 1 and FIG. 2, a SiC wafer 1 consisting of only a SiC substrate (SiC bulk substrate) 2 is prepared. The crystal type of the SiC substrate 2 is, for example, 4H-SiC, but may be 6H-SiC or 3C-SiC. The off-angle of the main surface of the SiC substrate 2 is, for example, greater than 0.5 degrees and preferably less than 8 degrees. Here, the off-angle of the main surface of the SiC substrate 2 is, for example, 4 degrees. The plane orientation of the main surface of the SiC substrate 2 may be any of the Si plane, the C plane, or other plane orientations, and here, the plane orientation of the main surface of the SiC substrate 2 is the Si plane.

[0028] The SiC substrate 2 may be a substrate produced by a sublimation method, a solution method, or a gas growth method. The concentration of n-type impurities in the SiC substrate 2 is, for example, 1×10 18 ~1×10 21 / cm -3 Here, for example, 1 × 10 18 / cm -3 It is.

[0029] Next, as shown in FIG. 3, an epitaxial layer (epitaxial growth layer, semiconductor layer) 3 is formed on the main surface of the SiC substrate 2 by epitaxial growth. Specifically, at a temperature of 1500° C. or higher, SiH4 (monosilane) and C3H8 (propane) are supplied to the SiC substrate 2 using H2 (hydrogen) as a carrier gas. Trichlorosilane or methane may also be used as the gas used for epitaxial growth. Hydrogen chloride may also be introduced to improve the growth rate. This causes epitaxial growth to form the epitaxial layer 3. At this time, the epitaxial layer 3 is mainly made of SiC.

[0030] The n-type impurity concentration of the epitaxial layer 3 varies depending on the device to be fabricated. For example, 14 ~1×10 18 / cm -3 The thickness of the epitaxial layer 3 varies depending on the device to be fabricated, but is, for example, several μm to several tens of μm.

[0031] It is also considered that basal plane dislocations (BPDs), which are defects that cause degradation due to electrical conduction, are present in the SiC substrate 2. BPDs that extend from the SiC substrate 2 side into the epitaxial layer 3 during epitaxial growth hinder electrical conduction and have the property of expanding when electrical conduction occurs. In contrast, it is considered that some of the BPDs in the SiC substrate 2 are converted into threading edge dislocations (TEDs) at the interface between the SiC substrate 2 and the epitaxial layer 3 and extend into the epitaxial layer 3. TEDs do not hinder electrical conduction within the substrate and do not expand even when electrical conduction occurs.

[0032] Therefore, before forming the epitaxial layer 3, a high-concentration buffer layer (semiconductor layer) made of SiC may be formed on the SiC substrate 2. The n-type impurity concentration of the buffer layer is, for example, 1×10 18 / cm -3The probability of BPDs expanding into the epitaxial layer 3 can be reduced by providing a buffer layer between the SiC substrate 2 and the epitaxial layer 3. That is, during epitaxial growth, the BPDs in the SiC substrate 2 are more likely to be converted to TEDs at the interface between the SiC substrate 2 and the buffer layer. Furthermore, the presence of the buffer layer can reduce the probability of holes reaching the BPDs in the SiC substrate 2. This can reduce the probability of electrical degradation occurring in a device formed on a laminated substrate including the SiC substrate 2 and the epitaxial layer 3.

[0033] Furthermore, before forming the epitaxial layer 3, the upper surface of the SiC substrate 2 or the upper surface of the buffer layer may be subjected to CMP (Chemical Mechanical Polishing).

[0034] Further, although the formation of the epitaxial layer 3 on the SiC substrate 2 has been described here, instead of the process described using Figures 1 to 3, a laminated substrate (SiC wafer 1) may be prepared in which the epitaxial layer 3 has already been laminated on the SiC substrate 2.

[0035] Next, as shown in FIG. 4, a carbon-rich process is performed. That is, a process is performed so that the surface composition of the epitaxial layer 3 becomes carbon-rich. Specifically, the surface composition is modified so that the ratio (atomic percent, atm%) of bonds other than C-Si, such as C-C or C-O, is higher than the ratio of C-Si bonds on the upper surface of the epitaxial layer 3. In other words, carbon-rich in the present application refers to a state in which the ratio of bonds other than C-Si, including C, is higher than the ratio of C-Si bonds. In other words, carbon-rich in the present application refers to a composition ratio of C-Si on the upper surface of the epitaxial layer of 50 atm% or less.

[0036] There are several possible methods for carbon-rich processing, but here, for example, the surface composition is modified by CMP. As a result, a carbon-rich layer 4 is formed on the upper surface of the epitaxial layer 3. The modification of the composition of the surface of the SiC wafer can be achieved by, for example, the CMP method.

[0037] The surface composition of the epitaxial layer 3 (the composition of the carbon-rich layer 4) is examined by, for example, surface composition analysis using XPS (X-ray Photoelectron Spectroscopy). Here, in the surface composition analysis using XPS, the conditions of the carbon-rich process are adjusted so that the proportion of bonds other than C-Si, such as C-C or C-O, is higher than the proportion of C-Si bonds when peak separation of the C1s spectrum is performed.

[0038] 5 and 6 are schematic diagrams for explaining a surface composition analysis method using XPS. Note that in FIG. 5 and FIG. 6, the carbon-rich layer formed on the upper surface of the epitaxial layer is omitted. Here, an XPS equipped with a detector 35 having an angle resolution function is used. When performing surface composition analysis using XPS, since the detector 35 has an angle resolution function, information at a depth of several nm (for example, 1 to 3 nm) from the wafer surface can be obtained by resolving information at a deeper position (for example, about 7 nm) from the wafer surface. In other words, if the detector 35 does not have an angle resolution function, it is not possible to distinguish and detect the surface composition of a relatively shallow region of the wafer surface from the surface composition of a relatively deep region of the wafer surface.

[0039] In the XPS measurement, the SiC wafer 1 is irradiated with X-rays 25 having a strong penetrating power, and photoelectrons (secondary electrons) generated by this are detected. Therefore, the detection depth is determined by the mean free path of the photoelectrons. In the XPS with an angle resolution function in the detector, the depth information can be obtained from the position in the detector plane where the photoelectrons are detected. That is, the photoelectrons generated in the shallow region of the wafer surface can be detected on the entire surface of the detector 35 as shown in FIG. 5. In contrast, the mean free path of the photoelectrons generated in the deep region of the wafer surface is short in the SiC wafer 1, so that they can only escape at a low angle as shown in FIG. 6, and cannot escape from the SiC wafer 1 at a high angle. Therefore, the composition analysis can be performed in a relatively shallow region of the wafer surface (for example, a region 1 to 3 nm from the wafer surface) from the photoelectrons that depart from the wafer toward the detector 35 at a low angle. In this way, by using the XPS with angle resolution function, the composition at a depth of several nm from the wafer surface can be resolved and obtained.

[0040] The angles such as high angle and low angle (take-off angle, secondary electron take-off angle) referred to here are the angle θ between a line perpendicular to the surface (main surface) of the SiC wafer 1 and the traveling direction of photoelectrons emitted from the surface of the SiC wafer 1 when irradiated with X-rays 25.

[0041] In this embodiment, the surface composition of the SiC wafer is adjusted by carbon-rich processing so that the surface composition ratio of C-Si is 43 atm% when the composition analysis is performed by XPS on the very near surface of the SiC wafer (for example, the region 1 to 3 nm from the wafer surface). However, if the composition of the very near surface of the SiC wafer (for example, the region 1 to 3 nm from the wafer surface) is not resolved and detected, the result of the XPS analysis also includes information on the bonding state at a depth of several nm (for example, 7 nm) from the wafer surface. In this case, the surface composition ratio of C-Si obtained by the XPS analysis is 83 atm%. This will be explained below with reference to FIGS. 7 to 13.

[0042] 7 to 10 are graphs showing details of peak separation of C1s spectrum obtained by surface composition analysis using XPS. In these graphs, the horizontal axis shows the binding energy of the composition on the wafer surface, and the vertical axis shows the energy of photoelectrons (emitted photoelectron intensity). Figs. 7 to 9 show the results of XPS analysis of SiC wafers subjected to the carbon-rich treatment of this embodiment, and Fig. 10 shows the results of XPS analysis of a comparative SiC wafer not subjected to the carbon-rich treatment of this embodiment.

[0043] 7 and 10 are graphs showing the analysis results when the detection angle of the detector 35 is 81.125 degrees, i.e., a high angle. That is, FIG. 7 and FIG. 10 show the composition of a relatively shallow region of the wafer surface. FIG. 9 is a graph showing the analysis results when the detection angle of the detector 35 is 24.875 degrees, i.e., a low angle. That is, FIG. 9 shows the composition of a relatively deep region of the wafer surface. FIG. 8 is a graph showing the analysis results when the detection angle of the detector 35 is 51.125 degrees. That is, FIG. 8 shows the composition in a region at a depth intermediate between FIG. 7 showing the composition of the shallow region and FIG. 9 showing the composition of the deep region. The composition of the relatively deep region of the wafer surface of the comparative example is almost the same as the composition of the relatively shallow region of the wafer surface of the comparative example shown in FIG. 10, and therefore is not shown here.

[0044] 7 to 10 show graphs of the analysis results of each of C-Si, which is a bond between carbon and silicon, CC, which is a bond between carbon and carbon, CO, which is a bond between carbon and oxygen, C=O, which is a double bond between carbon and oxygen, and OCO, which is an ether bond between oxygen and carbon. In Fig. 7 to Fig. 10, the graph of C-Si is shown by a solid line, the graph of CC is shown by a dashed line, the graph of CO is shown by a dashed line, the graph of C=O is shown by a dashed line, and the graph of OCO is shown by a dashed line.

[0045] As shown in Figs. 7 to 9, the composition ratio of each of the various bonds containing carbon has a depth dependency. This will be described below with reference to Figs. 11 to 15. Figs. 11 and 12 are a table and a graph showing the relationship between the composition ratio of each of the bonds containing carbon on the surface of the SiC wafer before the carbon-rich process and the take-off angle of the XPS analysis. Figs. 13 and 14 are a table and a graph showing the relationship between the composition ratio of each of the bonds containing carbon on the surface of the SiC wafer after the carbon-rich process and the take-off angle of the XPS analysis. In Figs. 12 and 14, the horizontal axis of the graph shows the take-off angle of the XPS analysis, and the vertical axis of the graph shows the composition ratio. The larger the take-off angle of the XPS analysis, which is the horizontal axis of these graphs, is, the closer the location of the XPS analysis is to the wafer surface.

[0046] Fig. 15 is a graph showing the composition ratio of C-Si bonds and the total composition ratio of bonds containing carbon other than C-Si before and after carbon-rich processing. In Fig. 15, the graph before carbon-rich processing is shown on the right side, and the graph after carbon-rich processing is shown on the left side. In Fig. 15, the composition ratio of C-Si bonds is shown in white bars, and the bar graph of the ratio of the total composition ratio of bonds containing carbon other than C-Si is hatched.

[0047] 12 and 14, the graph of C-Si is shown by a solid line, the graph of CC is shown by a dashed line, the graph of CO is shown by a dashed line, the graph of C=O is shown by a dashed line, and the graph of OCO is shown by a dashed line.

[0048] As shown in Figs. 11 to 12 and 15, before the carbon-rich process, most of the composition ratio near the wafer surface is occupied by C-Si bonds, and the total ratio of the composition ratio of bonds containing carbon other than C-Si bonds is equal to or less than the composition ratio of C-Si bonds. In contrast, as shown in Figs. 13 to 15, after the carbon-rich process, the composition ratio of C-Si bonds is about 43% and is the highest in the particularly shallow region near the wafer surface. However, as shown in Figs. 13 to 15, the total ratio of the composition ratio of bonds containing carbon other than C-Si bonds is about 57%, which is higher than the composition ratio of C-C bonds. In particular, the composition ratio of C-C bonds in a relatively shallow region of the wafer surface is close to the composition ratio of C-Si bonds.

[0049] Thus, on the wafer surface, the total ratio of the composition ratios of the bonds containing carbon other than the C-Si bond is greater than the composition ratio of the C-Si bond. In other words, the wafer is in a carbon-rich state. When the surface composition of the SiC wafer is adjusted by carbon-rich processing, the surface composition ratio of C-Si in the vicinity of the very surface of the SiC wafer (for example, a region 1 to 3 nm from the wafer surface) is 43 atm% by XPS. From this, when the measurement is performed using XPS with angle resolution function, if the composition ratio of C-Si in the vicinity of the very surface of the epitaxial layer is 50 atm% or less, it can be said that the wafer is in a carbon-rich state. On the other hand, the surface composition ratio of C-Si at a location several nm (for example, 7 nm) deep from the wafer surface is 83 atm% by the carbon-rich processing. Therefore, if the surface composition ratio of C-Si at a location several nm (for example, 7 nm) deep from the wafer surface is 83 atm% or less, the wafer is in a carbon-rich state. In other words, when measurements are made using an XPS that does not have angle resolution, even if the composition ratio of the wafer surface is measured, it is not possible to distinguish between shallow and deep regions of the wafer surface. Therefore, when measurements are made using such an XPS, a carbon-rich state can be said to exist when the C-Si composition ratio of the top surface of the epitaxial layer, which is the wafer surface, is 83 atm% or less.

[0050] Here, the inventors confirmed that when the XPS take-off angle was 24.875 degrees, the composition ratio of CC was 8.79 atm% and the composition ratio of CO was 3.6 atm% on the upper surface of the epitaxial layer. That is, when the XPS take-off angle is small and a relatively deep region of the epitaxial layer is analyzed, it is considered that the state is carbon-rich when the composition ratio of CC is 8.7 atm% or more and the composition ratio of CO is 3.6 atm% or more.

[0051] Furthermore, the inventors confirmed that when the XPS take-off angle was 81.125 degrees, the composition ratio of CC was 36.01 atm% and the composition ratio of CO was 10.55 atm% on the upper surface of the epitaxial layer. That is, when the XPS take-off angle was large and a relatively shallow region of the epitaxial layer was analyzed, it was considered that the state was carbon-rich when the composition ratio of CC was 35 atm% or more and the composition ratio of CO was 10 atm% or more.

[0052] <Effects of this embodiment> The inventors performed a TDDB characteristic evaluation on 68 DMOSFETs (Double-Diffused MOSFETs) fabricated on the SiC wafer of the present embodiment that was subjected to carbon-rich processing and on a SiC wafer that was not subjected to carbon-rich processing. Here, the potentials of the source and drain were set to 0V, and a voltage was applied to the gate so that a constant current flowed, and the time until the gate insulating film was broken down was measured. The temperature during the measurement was about 150°C, and the voltage was adjusted so that the current density was constant.

[0053] FIG. 17 shows a Weibull plot of the results of evaluating the TDDB characteristics. The horizontal and vertical axes of the graph shown in FIG. 17 indicate the dielectric breakdown injection charge Qbd and the cumulative failure rate, respectively, as in the horizontal and vertical axes of FIG. 29. FIG. 17 is a graph showing the relationship between the dielectric breakdown injection charge and the cumulative failure rate in each SiC device of the comparative example and the present embodiment. In FIG. 17, the plot of the evaluation results of the device of the comparative example that was not subjected to the carbon-rich treatment is shown by a diamond, and the plot of the evaluation results of the device using the wafer of the present embodiment that was subjected to the carbon-rich treatment is shown by a triangle.

[0054] In this evaluation, the shape parameter m was calculated for the analysis. In addition, the scale parameter is η. In general, when the cumulative failure rate F(t) follows the Weibull distribution, the cumulative failure rate F(t) is described by formula (1) shown in Figure 16.

[0055] Moreover, equation (1) can be rewritten as equation (2) below. ln(-ln(1-F(t))=mln(t)-mlnη) ···(2) In a Weibull plot, when y = ln(-ln(1-F(t)) and x = ln(t), the slope is m and the intercept is -mlnη. That is, an increase in m makes the distribution uniform and reduces the characteristic variation, and an increase in η increases the maximum value of the main distribution. That is, as shown in FIG. 17, the Weibull plot graph of the comparative example has a slope with respect to the vertical axis, but the Weibull plot graph of the present embodiment has a uniform distribution that is parallel to the vertical axis.

[0056] The shape parameter m was calculated for each of the specifications of the present embodiment in which the carbon-rich treatment was performed and the comparative example in which the carbon-rich treatment was not performed, and m=11.3 for the specification with the carbon-rich treatment and m=2.1 for the specification without the carbon-rich treatment. That is, the value of m increases due to the carbon-rich treatment. The inventors have also confirmed that the value of η also increases. This indicates that the slope of the main distribution becomes steeper and the maximum value of Qbd becomes higher. The increase in m and η due to the carbon-rich treatment is effective from the viewpoint of improving the yield.

[0057] As described above, in this embodiment, a SiC wafer having an epitaxial layer on a SiC substrate, the SiC wafer having a carbon-rich main surface is provided. That is, the C-Si composition ratio of the upper surface of the epitaxial layer is 50 atm% or less. The time (life) until dielectric breakdown occurs can be extended for elements such as MOSFETs having gate insulating films formed on such a SiC wafer, because the surface of the SiC wafer is carbon-rich. In addition, the characteristics such as the life of the gate insulating films of the elements formed in each chip region arranged in a matrix on the circular SiC wafer can be made uniform, and the occurrence of characteristic variations can be prevented. Therefore, the above-mentioned room for improvement can be eliminated. The reliability of the SiC wafer can be improved. In addition, since the occurrence of defective chips can be prevented, the product yield can be increased by using the SiC wafer subjected to the carbon-rich treatment of this embodiment.

[0058] However, it is necessary to pay attention to the composition ratio within the wafer surface after carbon-rich processing. If the SiC surface is completely carbonized by carbon-rich processing, that is, if the composition ratio of bonds other than C-Si on the wafer surface becomes 90 to 100 atm%, when devices such as MOSFETs or IGBTs are fabricated, graphene will be present at the interface between the layer made of SiC (epitaxial layer) and the gate insulating film. If graphene is present at the SiC / SiO2 interface, there is a risk that the source-drain will conduct electricity regardless of the gate voltage, and the element will not operate normally. Therefore, it is desirable for the C-Si composition ratio on the wafer surface to be greater than 10 atm%.

[0059] Thus, in order to obtain the effect of this embodiment, it is necessary to adjust the composition ratio of the C-Si bond to be greater than 10 atm %.

[0060] <Variation 1> The carbon-rich treatment described above may be a short-time heat treatment performed on the SiC wafer in an inert gas (e.g., Ar (argon)) atmosphere at a temperature of, for example, about 1300° C. The carbon-rich treatment can be performed by carbonizing the surface of the SiC wafer by such heat treatment.

[0061] However, even in this case, it is necessary to pay attention to the composition ratio within the wafer surface after carbon-rich processing. In other words, if the SiC surface is completely carbonized by high-temperature annealing in an Ar atmosphere, graphene is formed at the SiC / SiO2 interface, which may cause conduction between the source and drain regardless of the gate voltage, and the device may not operate normally. Therefore, it is desirable for the C-Si composition ratio on the wafer surface to be greater than 10 atm%.

[0062] <Variation 2> Hereinafter, as Modification 2 of the present embodiment, a process for forming a DMOSFET on a SiC wafer will be described with reference to Figs. 18 to 27. Figs. 18 to 26 are cross-sectional views showing the manufacturing process for a DMOSFET on a SiC wafer according to this modification. Fig. 27 is a plan view showing the manufacturing process for a DMOSFET on a SiC wafer according to this modification.

[0063] First, as described with reference to Figures 1 to 4, a SiC wafer 1 is formed having an epitaxial layer 3 that has been subjected to a carbon-rich treatment. Note that in Figures 18 to 26 used in the following description, the carbon-rich layer on the upper surface of the epitaxial layer 3 is not shown.

[0064] 18, Al (aluminum) ions are implanted into the surface layer of the epitaxial layer 3 using a mask (not shown) provided on the epitaxial layer 3. This forms a p-type semiconductor region, p-body region 5, on the upper surface of the epitaxial layer 3. The depth of the impurity implantation is, for example, about 1 μm. The p-type impurity concentration of the p-body region 5 is, for example, 5×10 16 ~1×10 19 cm -3 The ions implanted to form p body region 5 may be B (boron) ions. A p-type epitaxial layer made of SiC may be further formed on epitaxial layer 3, and this epitaxial layer may be used as the p body region. In this case, the carbon-rich treatment described with reference to FIG. 4 is performed after the formation of the epitaxial layer, not before, but before the formation of the gate insulating film described below. Thereafter, the mask is removed.

[0065] 19, N (nitrogen) ions are implanted into the upper surface of the epitaxial layer 3 using a mask (not shown) provided on the epitaxial layer 3. As a result, a source region 6, which is an n-type semiconductor region shallower than the p-body region 5, is formed on the upper surface of the p-body region 5. The implantation depth of the impurity is, for example, in the range of 0.1 to 0.5 μm. The n-type impurity concentration of the source region 6 is, for example, 1×1018 ~1×10 21 cm -3 The range is 0.1 to 1.0 μm. Furthermore, the ions implanted to form the source region 6 may be P (phosphorus) ions. After that, the mask is removed.

[0066] 20, Al ions are implanted into the upper surface of the epitaxial layer 3 using a mask (not shown) provided on the epitaxial layer 3. As a result, a potential fixing region 7, which is a p-type semiconductor region shallower than the p-body region 5 and adjacent to the source region 6, is formed on the upper surface of the p-body region 5. The impurity is implanted to a depth in the range of, for example, 0.1 to 0.5 μm. The p-type impurity concentration of the potential fixing region 7 is, for example, 1×10 18 ~1×10 21 cm -3 The implantation temperature is set to about 100° C. The ions implanted to form the potential clamp region 7 may be B ions. After that, the mask is removed.

[0067] 21, N ions are implanted into the back surface of the SiC substrate 2 to form the drain region 8, which is an n-type semiconductor region. The n-type impurity concentration of the drain region 8 is, for example, 1×10 16 ~1×10 19 cm -3 In addition, the ions implanted to form the drain region 8 may be P ions.

[0068] In this modification, a process for forming a minimum configuration for operating the MOSFET will be described, but a structure that adds a function such as a termination region may also be formed.

[0069] Next, although not shown, a carbon film is deposited as a cap material covering the periphery of the SiC wafer 1 consisting of the SiC substrate 2 and the epitaxial layer 3, and then impurity activation annealing is performed at a temperature of, for example, 1600 to 1800° C. The carbon film is then removed by oxygen plasma ashing. After this, in order to obtain a cleaner surface, a thermal oxide film may be formed and removed using a diluted hydrofluoric acid solution.

[0070] 22, a gate insulating film 9 is formed on the epitaxial layer 3. In this embodiment, a deposited oxide film having a thickness of about 10 to 100 nm is formed by using, for example, a CVD (Chemical Vapor Deposition) method.

[0071] 23, a gate electrode 10 made of an n-type polycrystalline silicon film having a thickness of about 100 to 300 nm is deposited on the epitaxial layer 3. The gate electrode 10 can be formed by forming the silicon film by, for example, a CVD method, and then patterning the silicon film. The upper surfaces of the source region 6 and the potential fixing region 7 are exposed from the gate electrode 10. In this way, a MOSFET including the gate electrode 10, the source region 6, and the drain region 8 is formed.

[0072] 24, an interlayer film (interlayer insulating film) 11 is formed to cover the gate electrode. The interlayer film 11 can be formed by forming a silicon oxide film on the gate electrode 10 by, for example, a CVD method, and then patterning the silicon oxide film. By this patterning, contact holes exposing the upper surfaces of the source region 6 and the potential fixing region 7 are formed.

[0073] Next, as shown in Figure 25, + Source region 6 and p + To enable electrical conduction with the potential fixed region 7 of the source region 6, a silicide layer 12 is formed on each of the source region 6 and the potential fixed region 7. That is, a metal film for silicide is deposited on the epitaxial layer 3, and silicide is performed by annealing at, for example, 700°C to 1000°C. This forms the silicide layer 12, which is a source-base common connection portion. Thereafter, in a region not shown, the interlayer film is etched to form a gate contact hole in order to ensure electrical conduction with the gate electrode.

[0074] Subsequently, a source electrode 13 covering the interlayer film 11 and the silicide layer 12 is formed on the epitaxial layer 3. The source electrode 13 is electrically connected to the source region 6 and the potential fixing region 7 via the silicide layer 12.

[0075] Next, as shown in FIG. 26, the lower surface of the drain region 8 is silicided to form a silicide layer 14. Thereafter, a drain contact electrode 15 is formed under the silicide layer 14. Metal materials such as Ni (nickel) or Al are used for each of the silicide metal film, the source electrode 13, and the drain contact electrode 15. Thereafter, a semiconductor device is completed through a process of forming a surface protection film made of an insulator on the upper surface of the SiC wafer 1 to protect the device, and a process of wiring each electrode. As a result, a SiC wafer shown in FIG. 27 is obtained. The SiC wafer has chip regions arranged in a matrix in a plan view. A dicing process is performed to cut between the chip regions to obtain multiple semiconductor chips from the SiC wafer.

[0076] In the MOSFET formed in this modification, a carbon-rich layer is formed on the upper surface of the epitaxial layer 3 in contact with the gate insulating film 9. This extends the time (life) until dielectric breakdown occurs in the gate insulating film 9 between the gate electrode 10 and the epitaxial layer 3. In addition, the characteristics such as the life of the gate insulating film of the elements formed in each of the chip regions arranged in a matrix on the circular SiC wafer can be made uniform, preventing the occurrence of characteristic variations. This can increase the reliability of the SiC wafer and further increase the product yield.

[0077] Here, the carbon-rich layer (see FIG. 3) is formed after the epitaxial layer is formed and before the p-body region is formed. However, the carbon-rich process is not limited to this time and may be performed at any time after the epitaxial layer that constitutes the top surface of the SiC wafer is formed and before the gate insulating film is formed.

[0078] In the case of forming a trench-gate MOSFET, a trench is formed on the upper surface of the epitaxial layer, and then a gate electrode is embedded in the trench via a gate insulating film. In this case, a carbon-rich treatment is performed after the trench is formed and before the gate insulating film is formed.

[0079] (Embodiment 2) The carbon-rich treatment can also be achieved by oxidizing the surface of a SiC wafer having an epitaxial layer, and then removing the oxide film formed by the oxidation using a chemical such as hydrofluoric acid.

[0080] FIG. 28 is a graph showing the composition ratio of C-Si bonds and bonds containing carbon other than C-Si bonds on the upper surface of a SiC wafer before carbon-rich processing, a SiC wafer from which an oxide film has been removed after oxidation processing at 1300°C, and a SiC wafer from which an oxide film has been removed after oxidation processing at 1150°C. In FIG. 28, the graphs are arranged from right to left for the cases before carbon-rich processing, oxidation processing at 1300°C, and oxidation processing at 1150°C. That is, FIG. 28 shows a comparison of the surface composition ratios of each SiC wafer obtained by performing oxidation processing at temperatures of 1150°C and 1300°C in a dry oxygen atmosphere to form an oxide film of about 50 nm, and then removing the oxide film with hydrofluoric acid. In FIG. 28, the composition ratio of C-Si bonds is shown in white bars, and the bar graph showing the total ratio of the composition ratio of bonds containing carbon other than C-Si is hatched.

[0081] 28, the composition ratio of C-Si bonds is smaller and the composition ratio of bonds containing carbon other than C-Si bonds is larger when the oxidation treatment is performed at 1300°C than before the carbon-rich treatment. Also, the composition ratio of C-Si bonds is smaller and the composition ratio of bonds containing carbon other than C-Si bonds is larger when the oxidation treatment is performed at 1150°C than when the oxidation treatment is performed at 1300°C.

[0082] That is, in order to reduce the composition ratio of C-Si bonds, it is important to carry out oxidation at a lower temperature.

[0083] The invention made by the present inventors has been specifically described above based on the embodiments thereof. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the invention. [Explanation of symbols]

[0084] 1. SiC wafer 2. SiC substrate 3 Epitaxial layer 4 Carbon-rich layer

Claims

1. A SiC substrate; a single crystal epitaxial layer including SiC formed on the SiC substrate; Including, Among the carbon-containing bonds present on the extreme surface up to 3 nm from the top surface of the single crystal epitaxial layer, the composition ratio of C—Si is 50 atomic % or less and is greater than 10 atomic %; SiC wafer.

2. A single crystal epitaxial layer for use in a semiconductor device, comprising: the single crystal epitaxial layer comprises SiC; Among the carbon-containing bonds present on the extreme surface up to 3 nm from the top surface of the single crystal epitaxial layer, the composition ratio of C—Si is 50 atomic % or less and is greater than 10 atomic %; Single crystal epitaxial layer.

3. (a) providing a SiC substrate; (b) forming a single crystal epitaxial layer comprising SiC on the SiC substrate; (c) modifying the composition of the top surface of the single crystal epitaxial layer; Including, Among the bonds containing carbon present on the extreme surface up to 3 nm from the top surface, the composition ratio of C—Si is 50 atomic % or less and more than 10 atomic %; A method for manufacturing a SiC wafer.

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