Chip with pitch of upper metal pad adjusted

Abstract

To provide a method for packaging an integrated circuit for adjusting the pitch of an upper metal pad, and an integrated circuit.SOLUTION: A first part of an integrated circuit including a transistor and other devices includes a first pitch 130 related to an internal connection part. The first pitch does not need to coincide with a pitch 115 of a desired external connection part. Therefore, a group of masks is used in order to add a second part (for example, metal wire) of the integrated circuit to the integrated circuit so that the integrated circuit obtains a second pitch 140 different from the first pitch. The first part of the integrated circuit may have consistency in one or more integrated circuits, and the second part of the integrated circuit may be customized for the desired external connection part related to that integrated circuit.SELECTED DRAWING: Figure 1B

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application No. 63 / 539,327, filed September 19, 2023, which is incorporated by reference in its entirety and for all purposes. [Background technology]

[0002] A chip must meet certain spacing requirements between its external contacts in order to be compatible with an external system, such as connections on a printed circuit board to which the chip is attached. In a typical system, the spacing between the chip's external contacts is too small for the external system to which the chip is attached, so a substrate is placed between the chip's external contacts and the external system. The substrate has a set of contacts that are compatible with the chip, another set of contacts that are compatible with the external system, and a set of wires that connect the two sets of contacts.

[0003] In situations where the external contacts of a chip have a spacing that is too small relative to the substrate to which the chip is attached, an intermediate system such as an interposer can be introduced that has one set of contacts compatible with the chip, another set of contacts compatible with the substrate, and a set of wiring connecting the two sets of contacts.

[0004] Chiplet are miniature integrated circuits with packaging that can have a finer pitch than traditional chip packaging. The finer pitch of chiplets means that they often require an interposer in addition to the substrate to interface with other external systems. This adds complexity to some packaging and assembly configurations and can lead to yield issues. Summary of the Invention [Means for solving the problem]

[0005] The present disclosure relates to integrated circuit chips and packages with pitch-aligned on-chip top metal pads. Related methods are disclosed. The pitch alignment of the top metal pads may be formed by top metal wiring in an integrated circuit that routes internal connections to external chip connections. The internal connections may be pads in a metal layer of the integrated circuit. The external chip connections may be pads, solder balls, bumps, pillars, leads, or other conductive connections. The internal connections may have a finer pitch than the external chip connections. The top metal wiring in an integrated circuit may vary from one production run of the chip to another. The variations in the top metal wiring affect the connections between the internal connections and the external connections, and the same chip may be connected to a package substrate or interposer at different pitches. For example, one variation may connect each internal connection to an external connection at a first pitch, while another variation may connect every other internal connection to an external connection at a double-wide pitch. The top metal wiring may be defined by different sets of masks, with different sets selected as part of different production runs of back-end-of-line processing of the integrated circuit. The top metal wiring may be varied within an integrated circuit. Continuing with the above example, another variation would be to connect each internal connection on one side of the chip to an external connection at a first pitch, while all other sides of the chip are connected to external connections at a double-wide pitch.

[0006] A method for packaging an integrated circuit is disclosed, the method including forming a group of integrated circuit devices, forming a group of integrated circuit interconnects coupled to the group of integrated circuit devices, selecting a group of masks from a mask group library, forming a group of metal wiring layers of the integrated circuit using the group of masks, and coupling a group of external connections of the integrated circuit to the group of interconnects via the metal wiring layers, where (i) the groups of masks in the mask group library are each configured to form a different group of metal wiring layers, and (ii) the different groups of metal wiring layers differ from one another in how they connect the internal connections of the integrated circuit to the external connections of the integrated circuit.

[0007] Disclosed is an integrated circuit that includes a group of devices, a group of interconnects coupled to the group of devices and having a first pitch, the group of interconnects being a group of metal layer pads, a group of external connections coupled to the group of interconnects and having a second pitch, and a group of metal wiring layers of the integrated circuit coupling the group of internal connections to the group of external connections, where a subgroup of the group of internal connections is not connected to the group of external connections.

[0008] A method is disclosed that includes forming a first group of devices of a first integrated circuit, forming a first group of internal connections of the first integrated circuit coupled to the first group of devices of the first integrated circuit, selecting a first group of masks from a mask group library based at least in part on the first group of external connections, forming a first group of metal wiring layers of the first integrated circuit using the first group of masks, and forming a second group of devices of a second integrated circuit, the second group of devices being of the same configuration as the first group of devices. forming a second group of internal connections of the second integrated circuit coupled to the second group of devices; selecting a second group of masks from a mask group library based at least in part on the second group of external connections, the second group of masks being different from the first group of masks, the second group of external connections having a different configuration than the configuration of the first group of external connections; and forming a second group of metal wiring layers of the second integrated circuit using the second group of masks, the second integrated circuit having a different configuration than the configuration of the first group of metal wiring layers.

[0009] The accompanying drawings illustrate various embodiments of the systems, methods, and various other aspects of the present disclosure. Those skilled in the art will appreciate that the boundaries of the illustrated elements in the drawings (e.g., boxes, boxes, or other shapes) are illustrative of example boundaries. In some examples, an element may be designed as multiple elements, or multiple elements may be designed as an element. In some examples, an element shown as an internal component of one element may be implemented as an external component of another element, and vice versa. Also, elements may not be illustrated to scale. A non-limiting and non-exhaustive description is provided with reference to the following drawings. The components in the drawings are not necessarily to scale, with emphasis instead being placed on illustrating principles. [Brief description of the drawings]

[0010] [Figure 1A] 1 illustrates an integrated circuit in accordance with certain embodiments of the invention disclosed herein. [Figure 1B] 1 illustrates an integrated circuit in accordance with certain embodiments of the invention disclosed herein. [Diagram 2] 1 shows a cross-sectional view of an integrated circuit on a substrate in accordance with certain embodiments of the invention disclosed herein; [Diagram 3] 1 shows a conceptual diagram of pitch modification in accordance with certain embodiments of the invention disclosed herein; [Figure 4] 1 shows a conceptual diagram of pitch modification in accordance with certain embodiments of the invention disclosed herein; [Diagram 5] 1 shows a conceptual diagram of pitch modification in accordance with certain embodiments of the invention disclosed herein; [Figure 6] 1 shows a conceptual diagram of pitch modification in accordance with certain embodiments of the invention disclosed herein; [Figure 7A] 1 illustrates an intellectual property (IP) block according to a particular embodiment of the invention disclosed herein. [Figure 7B] 1 illustrates an intellectual property (IP) block according to a particular embodiment of the invention disclosed herein. [Figure 8]1 illustrates a die-to-die (D2D) connection according to certain embodiments of the invention disclosed herein. [Figure 9] 1 illustrates a method for packaging an integrated circuit in accordance with certain embodiments of the invention disclosed herein. [Figure 10] 1 illustrates a method for packaging an integrated circuit in accordance with certain embodiments of the invention disclosed herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Reference will now be made in detail to implementations and embodiments of the various aspects and variations of the systems and methods described herein. Although several example variations of the systems and methods are described herein, other variations of the systems and methods may include aspects of the systems and methods described herein combined in any suitable manner having a combination of all or a portion of the described aspects.

[0012] The integrated circuit package with pitch-aligned top metal pads and related methods according to the above outline are disclosed in detail herein. The methods and systems disclosed in this section are non-limiting embodiments of the present invention, provided for illustrative purposes only, and should not be used to limit the overall scope of the present invention. It should be understood that the disclosed embodiments may or may not overlap with each other. Thus, a portion of one embodiment, or a specific embodiment thereof, may or may not be included within the scope of another embodiment, or a specific embodiment thereof, and vice versa. Various embodiments from different aspects may be combined or implemented separately. Many different combinations and subcombinations of the representative embodiments shown within the broad framework of the present invention will be apparent to those skilled in the art, but may not be explicitly shown or described and should not be construed as excluded.

[0013] FIG. 1 illustrates a packaged integrated circuit. The packaged integrated circuit may be a chiplet or a conventional chip. Diagram 100-a1 of FIG. 1A includes a chip 101-a. Diagram 100-a1 is a top view of the packaged integrated circuit, and diagram 100-a2 is a side cross-sectional view of the packaged integrated circuit. The single chip 101-a is connected to an external system.

[0014] Diagram 100-b1 of FIG. 1B includes two chiplets 101-b1 and 101-b2. FIG. 100-b1 is a top view of the packaged integrated circuit, and FIG. 100-b2 is a side cross-sectional view of the packaged integrated circuit. In FIG. 1B, the two chiplets 101-b1 and 101-b2 are connected to the same external system through an interposer 160, similar to chip 101-a. The chiplets may be connected (e.g., communicate) with each other through die-to-die (D2D) connections 103.

[0015] The external system, i.e., substrate 105, has connections 110 (e.g., copper pillar bump connections) with a pitch 115. In some examples, the pitch 115 may be 110 microns. Chip 101-a has external connections 120 with a pitch 123. Chiplet 101-b has external connections 125 (e.g., bump connections). In some examples, the pitch 130 associated with connections 125 may be 55 microns. Interposer 160 has connections 135 with a pitch 140. In some examples, the pitch 140 may be between pitch 130 (e.g., 55 microns) and pitch 115 (e.g., 110 microns).

[0016] The external connections 120 may be coupled to the external connections 110 via conductors 145 (e.g., metal traces fabricated integrally with the internal connections). In some examples, only a subset of the internal connections 120 may be coupled to a subset of the external connections 110.

[0017] External connections 125 may be coupled to connections 135 via conductors 150 (e.g., metal traces fabricated integrally with the internal connections). In some examples, only a subset of internal connections 125 may be coupled to a subset of connections 135. Connections 135 may be coupled to external connections 110 via conductors 155 (e.g., metal traces fabricated integrally with the internal connections). In some examples, only a subset of connections 135 may be coupled to a subset of external connections 110.

[0018] The external connections may be external contacts such as pads, solder balls, bumps, pillars, leads, or other conductive connections. The integrated circuits of FIGS. 1A and 1B may be connected to one or more substrates as part of the process of packaging the integrated circuits. The integrated circuits may generally be connected to a substrate along with other chips or chiplets as part of the process of packaging the integrated circuits. The substrate may be an organic substrate. The substrate 105 may be a substrate for various packaging types. The integrated circuits may generally be connected to an interposer as part of the process of packaging the integrated circuits. An interposer, such as interposer 160, may include multiple chips and auxiliary devices with connections to both external systems and other devices on the interposer.

[0019] The integrated circuit of Figures 1A and 1B may have groups of internal connections with different pitches. For example, two chiplets may have similar base circuits but differ in the pitch of their external connections. This may be referred to as the chiplet pitch of the chiplet. Different chiplet pitches may be made for similar chiplets to comply with different packaging constraints.

[0020] Some chiplets require many independent connections between chiplets. For example, the illustrated chiplet 101-b may be a computational chiplet configured to operate in parallel with other chiplets to perform complex calculations. Chiplet 101-b may include many external connections on a bottom surface of chiplet 101-b. However, because the speed of communication between integrated circuits in general, and more specifically between chiplets performing parallel processing of complex calculations, is very important, chiplet 101-b may be designed with many direct contacts between adjacent chiplets on at least one side of the chiplet. The side of the chiplet that includes this requirement may be referred to as the D2D interface and provides the contacts for D2D connections 103.

[0021] Chiplets, and integrated circuits in general, according to certain embodiments of the invention may have different pitches for the external connections while having the same internal connections. For example, in some instances, a chiplet may have a pitch for its internal connections (e.g., 65 microns). This pitch may be maintained at 65 microns for the external connections using a first top-level metal wiring pattern. Or, this pitch may be increased (e.g., to 130 microns) using a second top-level metal wiring pattern that connects only every other internal connection to an external connection. For example, chiplet 101-a may be essentially the same as chiplet 101-b, except that chiplet 101-a has another metal wiring layer between the internal connections to the base layer of the chip and the external connections. This allows chiplet 101-b to be used in applications that require a high density of external connections in the D2D interface. This same chiplet may also be used as chiplet 101-a in a simpler external system that does not require as many connections.

[0022] In a particular embodiment of the present invention, a method for packaging an integrated circuit 100 is provided. The method includes forming a set of devices for the integrated circuit. The devices may be passive or active devices, such as logic transistors used in a processor or capacitors and resistors used in analog circuits. The method may also include forming a set of internal connections of the integrated circuit that are coupled to the set of devices of the integrated circuit. The set of internal connections may be pads of conductive material formed in a layer above the devices of the integrated circuit. The set of internal connections may be connected to the devices by vias coupled to highly doped regions of semiconductor material of the integrated circuit. The method may also include selecting a set of masks from a mask set library. The set of masks may define a top-level wiring pattern to be formed on the integrated circuit. Each set of masks in the mask set library may be configured to form different sets of metal wiring layers. The mask set library may be configured to allow a designer to modify the integrated circuit during back-end-of-line processing to enable the integrated circuit to interoperate with packages having different configurations for the external connections of the integrated circuit. The different configurations may be set by a top-level metal wiring pattern. The method may continue by forming a set of metal wiring layers of the integrated circuit using the set of masks. The various sets of metal wiring layers may differ from one another in how they connect the internal connections of the integrated circuit 100 to the external connections of the integrated circuit 100. The sets of metal wiring layers may vary the pitch of the internal connections so that the device can interface with packages that have different spacing for the external connections. The method may continue by bonding a set of external connections of the integrated circuit 100 to a set of internal connections through the metal wiring layers.

[0023] In certain embodiments of the present invention, a group of metal wiring layers leaves a portion of a group of internal connections uncoupled from a group of external connections. The internal connections may still be connected to internal circuit elements, but the pads are left floating with respect to the external connections that would otherwise be connected to the pads. In these same embodiments, another group of metal wiring layers applied to the same underlying integrated circuit 100 may use all of the internal connections and couple them all to a group of external connections. Thus, the various groups of metal wiring layers that may be used with a given integrated circuit 100 and that are associated with various groups of masks may differ from one another in the number of internal connections in the group of internal connections that remain uncoupled from the group of external connections.

[0024] By changing the mask for forming the conductors (e.g., metal lines) between the internal and external connections, the chiplet may be more easily adapted to different packaging requirements. For example, only the top layer of the chiplet may be tailored for packaging purposes while preserving the main circuitry (e.g., including devices such as transistors). Different wire stacks may also be used. Post tape-out modifications are also possible. Top layer modifications may be relatively inexpensive and may require less time from inventory to final processing than traditional methods. Selection of the mask for the metal lines based on the packaging requirements allows for configurable package designs.

[0025] FIG. 2 illustrates a packaged device 200 in which a chiplet 205 is disposed on a substrate 210. The substrate 210 may be an organic substrate. The substrate 210 may be a package substrate. The chiplet 205 has external connections 215 with a pitch 220. In some examples, the pitch 220 may be 130 microns. The substrate 210 may include connections 225 with a pitch 230. The pitch 230 may be different than the pitch 220. The chiplet 205 may be connected to the substrate 210 via solder balls that cover the bottom surface of the chiplet and have a pitch 220 of 130 microns. Shown here is one embodiment of a method for connecting the chiplet to a substrate (e.g., an organic substrate). There are also methods for connecting the chiplet to a substrate using different pitches and different connection types.

[0026] In certain embodiments of the invention, packaged device 200 may include integrated circuit interconnects 215 coupled to devices of integrated circuit 200. The devices may be logic transistors. For example, in situations where integrated circuit 200 is a processor, the devices may form the computational units of the processor. The interconnects may be pads of an integrated circuit within chiplet 205. They may be, for example, flat areas of metal formed during fabrication of the integrated circuit to provide contacts to higher metal layers by vias or other conductive connections.

[0027] The interconnects (e.g., within an integrated circuit within chiplet 205) may have a variety of configurations. For example, the interconnects (e.g., connections 215) may be formed along a strip of the integrated circuit periphery that borders the integrated circuit. Alternatively, the interconnects may be found across the top or bottom surface of the integrated circuit. If the interconnects are formed on the bottom surface of the integrated circuit through the semiconductor, vias may be used to couple the device to the interconnects. The interconnects (e.g., connections 215) may have a pitch (e.g., pitch 220) that is set by the processing requirements of the integrated circuit and the size of the interconnects required by the metal wiring layers disclosed herein. The pitch of the interconnects may be referred to as the first pitch of the overall structure that is packaged device 200. The interconnects may be laid out in a regular rectangular array, checkerboard, or other pattern on one or more layers of the integrated circuit within chiplet 205.

[0028] In certain embodiments of the invention, an integrated circuit may include external connections coupled to the internal connections through a set of wiring layers. The external connections may be formed from a higher metal layer of the integrated circuit. As used herein, the term "higher" is used to refer to a layer formed after other layers, regardless of the relative positions of the layers to each other. For example, in a flip-chip configuration, the metal wiring may be below the device set of the original device from the perspective of when the device was originally manufactured. However, the metal wiring layer may still be formed subsequent to the device layers and may be referred to as a "higher" layer. The external connections may have a second pitch that is different from the first pitch. The first and second pitches may differ by any factor, such as by a factor of two or more. For example, the first pitch may be 65 microns and the second pitch may be 130 microns. In certain embodiments of the invention, an integrated circuit may include or be packaged in a package that includes a second set of external connections in addition to the first set of external connections. The second set of external connections may have a third pitch. Metal traces may connect the internal connections to both the first group of external connections and the second group of external connections.

[0029] In certain embodiments, a given circuit design may be capable of being combined with different sets of metal wiring layers to form different finished chips. Different sets of metal wiring layers may be selected such that the internal connections of the integrated circuit are coupled with different connections and external connections having different pitches. The pitch of the external connections may differ from the pitch of the internal connections and may also differ within a given integrated circuit. Due to the different sets of metal wiring layers, a given integrated circuit design may be combined with different packages. The decision to combine an integrated circuit with a given package having a particular pitch may be determined during back-end-of-line processing of the integrated circuit when the top metal wiring layer of the integrated circuit is being formed. The term "set" of metal wiring layers is used herein because wiring is likely to run through multiple layers, allowing for the routing of complex connection patterns where one wiring route may go under or over another wiring route. However, in certain embodiments of the present invention, the set of metal wiring layers may be a set of one layer. These groups of metal wiring layers can similarly be formed using standard lithography or similar approaches with a group of masks, which can include a single mask in the case of a single layer of wiring.

[0030] 3-6 show conceptual diagrams of pitch change from internal connections to ball grid array connections of a substrate. 3-6 may be fabricated using various groups of masks. FIG. 3 shows examples of connections between an integrated circuit and external connections. Packaged device 300 includes silicon 305, redistribution layer 310, and substrate 320 (e.g., an organic substrate of a package). The silicon may contain internal connections 325 and external connections 330 coupled via conductors 335 (e.g., metal traces fabricated integrally with the internal connections). In some examples, subgroups of connections 325 may be coupled to subgroups of connections 330. Connections 325 may have pitch 340 and connections 330 may have pitch 345. In some examples, pitch 340 may be the same as pitch 345. In other examples, pitch 340 may be different from pitch 345. Redistribution layer 310 may include connections 350 having pitch 355. The re-distribution layer 310 may be an interposer. The pitch 355 may be different from the pitch 345. The substrate 320 may include a connection 360 having a pitch 365. The substrate 320 may be a substrate of a package. The pitch 365 may be different from the pitch 355.

[0031] 3, the lowest level of connections on the page are internal connections 325 (e.g., 65 micron pitch pads in a metal layer), the next lower level are external connections 330 (e.g., 65 micron pitch bump metal for an integrated circuit), the next level are connections 350 (e.g., 150 micron pitch bump metal) in the redistribution layer 310, and the top level are connections 360 (e.g., ball grid array contacts) for the package substrate 320 (e.g., an organic substrate). The internal connections may connect to semiconductor layers of the integrated circuit (e.g., connecting to terminals of passive devices or transistors formed in the semiconductor layers).

[0032] FIG. 4 illustrates an example of a connection between an integrated circuit and an external connection. The packaged device 400 includes silicon 405 and a package substrate 420 (e.g., an organic substrate). The silicon may house internal connections 425 and external connections 430 coupled via conductors 435 (e.g., metal wiring integrally fabricated with the internal connections). In some examples, a subgroup 427 of the connections 425 may be coupled to a subgroup of the connections 430. Another subgroup 429 of the connections 425 may not be coupled to the connections 430. The connections 425 may have a pitch 440 and the connections 430 may have a pitch 445. The pitch 440 may be different from the pitch 445. The substrate 420 may include a connection 460 having a pitch 465. The pitch 465 may be different from the pitch 445.

[0033] In FIG. 4, external connections 430 have the same pitch as external connections 350 discussed above (e.g., 130 micron pitch bump metal for an integrated circuit). As can be seen from a comparison of FIG. 3 and FIG. 4, by changing the top wiring layer of the integrated circuit, the same integrated circuit can be used with different external connections to be compatible with different external systems. FIG. 4 also shows how multiple internal connections 425 can be coupled to the same external connection 430 (i.e., multiple 65 micron pitch metal layer pads are connected to the same 130 micron pitch package bump). For example, power or ground traces can be routed from a single external connection 430 to multiple internal connections 425.

[0034] The pitch 440 of the interconnects 425 may vary from one integrated circuit to the next. For example, in Figure 5, the interconnects are metal layer pads with a 45 micron pitch, as opposed to the metal layer pads of Figures 3 and 4, which have a 65 micron pitch.

[0035] FIG. 5 illustrates an example of a connection between an integrated circuit and an external connection. The packaged device 500 includes silicon 505 and a package substrate 520 (e.g., an organic substrate). The silicon may house internal connections 525 and external connections 530 coupled via conductors 535 (e.g., metal wiring integrally fabricated with the internal connections). In some examples, a subgroup 527 of connections 525 may be coupled to a subgroup of connections 530. Another subgroup 529 of connections 530 may not be coupled to connections 530. Subgroups 527 and 529 may be organized such that portions of subgroup 527 alternate with portions of subgroup 529 as one moves along the row of connections 525. For example, every third connection 525 (as shown) may belong to subgroup 527. Alternatively, every other connection 525 may belong to subgroup 527. The amount of connections 525 in subgroup 527 may or may not be the same as the amount of connections 525 in subgroup 529. In some examples, there may not be a particular patterned relationship between subgroup 527 and subgroup 529. Connections 525 may have a pitch 540 and connections 530 may have a pitch 545. Pitch 540 may be different from pitch 545. Substrate 520 may include connections 560 having pitch 565. Pitch 565 may be different from pitch 545.

[0036] FIG. 6 illustrates an example of a connection between an integrated circuit and an external connection. The packaged device 600 includes silicon 605 and a package substrate 620 (e.g., an organic substrate). The silicon may house internal connections 625 and external connections 630 coupled via conductors 635 (e.g., metal wiring integrally fabricated with the internal connections). In some examples, a subgroup 627 of connections 625 may be coupled to a subgroup of connections 630. Another subgroup 629 of connections 630 may not be coupled to connections 630. Subgroups 627 and 629 may be organized such that, moving along a row of connections 625, the entire subgroup 627 is first, followed by the entire subgroup 629. Connections 625 may have a pitch 640 and connections 630 may have a pitch 645. Pitch 640 may be different from pitch 645. Substrate 620 may include connections 660 having a pitch 665. The pitch 665 may be different from the pitch 645 .

[0037] In certain embodiments, a set of external connections are provided to connect the integrated circuit to a package for the integrated circuit. For example, in FIGS. 3 and 4, the external connections may be solder bumps formed on the chiplet package. In certain embodiments, a set of metal wiring layers form a set of conductive paths that couple to the external connections, and the pitch of the set of conductive paths is equal to the pitch of the external connections to the package. FIG. 3 above is in accordance with these embodiments. In certain embodiments, a set of metal wiring layers form a set of conductive paths that couple to the external connections, and the pitch of the set of conductive paths is not equal to the pitch of the external connections on the package. FIG. 4 above is in accordance with these embodiments.

[0038] Certain embodiments of the invention provide an integrated circuit. The integrated circuit includes a group of devices and a group of internal connections coupled to the group of devices and having a first pitch. The group of internal connections may be a group of metal layer pads. The integrated circuit also includes a group of external connections coupled to the group of internal connections and having a second pitch, and a group of metal wiring layers of the integrated circuit coupling the group of internal connections to the group of external connections. A subgroup of the group of internal connections is not connected to the group of external connections. FIG. 4 is in accordance with these embodiments. In certain embodiments, a subgroup of the group of internal connections is not connected to any of the metal wiring layers in the group of metal wiring layers. The group of external connections may be package contacts, such as solder balls, bumps, pillars, leads, etc., formed in a package for the integrated circuit.

[0039] In certain embodiments, the integrated circuit may also include a second group of external connections having a third pitch. A group of metal wiring layers of the integrated circuit may couple a group of internal connections to the second group of external connections. The pitches of the various groups of external connections may be different, and the same wiring layer may connect the internal connections to both groups. In certain embodiments, the group of internal connections covers the periphery of the integrated circuit. For example, a group of metal layer pads may be formed around the entire edge of the integrated circuit. The group of external connections may be on different sides of the integrated circuit. In these embodiments, the integrated circuit may be configured to couple to an external system having a first pitch on one side, or a portion of one side, and to couple to another external system having a different pitch on another side.

[0040] In certain embodiments, the underlying circuitry (i.e., the circuitry below the interconnects and metal layers that enable the pitch adjustments disclosed herein) may be an IP block that is configured to interface with different bump pitches using the approaches disclosed herein. In this way, a single circuit design of an IP block can be bundled with different bump pitches without the need to redesign the circuit when the bump pitch of the IP block changes.

[0041] An example of this approach is shown in FIG. 7, which shows how a single IP block can be interfaced with packages having three different bump pitches. A side view (FIG. 700-a1) and a top view (FIG. 700-a2) are shown for circuit system 700-a. A side view (FIG. 700-b1) and a top view (FIG. 700-b2) are shown for circuit system 700-b. IP block 715 houses circuit 705. Circuit 705 may be the same between the two IP blocks 715-a and 715-b. Block 710 may be a substrate or an interposer. Connection 723 has a pitch 720, which may be the same between circuit systems 700-a and 700-b. Connections 728-a and 728-b may have pitches 725-a and 725-b, respectively. The pitches 725-a and 725-b may be different between the circuit systems 700-a and 700-b. The connection portion 723 may be coupled to the connection portion 728-a via a conductor 730-a (e.g., a group of metal traces). The connection portion 723 may be coupled to the connection portion 728-b via a conductor 730-b (e.g., a group of metal traces) having a different layout or configuration than the conductor 730-a.

[0042] In one example, the pitch of the connections (e.g., packages) is 45 microns for pitch 720 and 110 microns for pitch 725-a and 110 microns for pitch 725-b, although various pitch values ​​are possible. A top view is shown for circuit systems 700-a and 700-b to illustrate how the same circuit 705 in IP block 715-a or 715-b is utilized in each case, and only the distribution of conductors 730 (e.g., wiring) from internal connections to external connections needs to be changed.

[0043] FIG. 8 illustrates an example of a D2D connection 800 according to certain embodiments of the invention disclosed herein. Chiplet 805-a and 805-b include connections 810-a and 810-b, respectively. Connections 810-a and 810-b are coupled via conductors 815 (e.g., metal traces on a substrate or interposer). Both chiplets can be fabricated using the approaches disclosed herein and include fine pitch to maximize the number of connections available for die-to-die communication. Importantly, each chiplet can be designed to communicate with alternate chiplets having a particular interconnect pitch without having to reserve space in the D2D interface for alternate pitch connections. For example, an approach that does not utilize certain embodiments of the invention disclosed herein may require that half of the illustrated D2D interface be reserved for connections with dies using different contact pitches. Accordingly, certain embodiments of the invention disclosed herein enable maximizing the amount of connections that can be provided at the D2D interface of a chiplet system by tailoring the top metal layers of the chip to a desired pitch density throughout the D2D interface of the chiplet system, thereby tending to densify the required connections.

[0044] FIG. 9 illustrates a method 900 for packaging an integrated circuit. At 905, a group of integrated circuit devices are formed. The devices may be transistors, capacitors, other devices, or a combination of devices. At 910, a group of integrated circuit interconnects are bonded to the group of integrated circuit devices. At 915, a group of masks is selected from a mask group library. Each group of masks in the mask group library is configured to form a different group of metal wiring layers. At 920, a group of integrated circuit metal wiring layers are formed using the group of masks selected at 915. The different groups of metal wiring layers differ from one another in how they connect the integrated circuit internal connections to the integrated circuit external connections. At 925, the integrated circuit external connections are bonded to the group of interconnects via the metal wiring layers formed at 920.

[0045] FIG. 10 illustrates a method 1000 for packaging an integrated circuit. At 1005, a first group of devices of the integrated circuit is formed. The devices may be transistors, capacitors, other devices, or a combination of devices. At 1010, a first group of internal connections of the first integrated circuit is formed. The first group of internal connections is coupled to the first group of devices of the first integrated circuit. At 1015, a first group of masks is selected from a mask group library based at least in part on the first group of external connections. At 1020, a first group of metal wiring layers of the first integrated circuit is formed using the first group of masks selected at 1015. At 1025, a second group of devices of a second integrated circuit is formed. The second group of devices may be of the same configuration as the first group of devices. At 1030, a second group of internal connections of the second integrated circuit is formed. The second group of internal connections is coupled to the second group of devices of the second integrated circuit. At 1035, a second group of masks is selected from the mask group library based at least in part on the second group of external connections. The second group of masks may be different from the first group of masks. The second group of external connections has a configuration different from the configuration of the first group of external connections. At 1040, a second group of metal wiring layers of a second integrated circuit is formed using the second group of masks, the second integrated circuit having a configuration different from the configuration of the first group of metal wiring layers.

[0046] Although the present specification has been described in detail with respect to specific embodiments of the present invention, it will be understood that those skilled in the art, upon understanding the foregoing, will be able to readily conceive of modifications, variations, and equivalents of these embodiments. For example, although chiplets are referred to herein, any form of integrated circuit may be used in place of the chiplets in these examples in accordance with the approach disclosed herein. As another example, although integrated circuits are referred to in the examples herein as being constructed from silicon, the teachings disclosed herein are more broadly applicable to any integrated circuit, including those made from other semiconductor materials such as silicon carbide and gallium nitride. These and other modifications and variations to the present invention may be implemented by those skilled in the art without departing from the scope of the present invention, which is more particularly set forth in the appended claims.

Claims

1. 1. A method of packaging an integrated circuit, the method comprising: forming a population of devices of the integrated circuit; forming a group of interconnects of the integrated circuit coupled to the group of devices of the integrated circuit; selecting a collection of masks from a mask collection library; forming a set of metal wiring layers of the integrated circuit using the set of masks; coupling a set of external connections of the integrated circuit to a set of internal connections through the metallization layer; Including, (i) each of the groups of masks in the mask group library is configured to form a different group of metal wiring layers; (ii) the various groups of metal wiring layers differ from one another in how they connect the internal connections of the integrated circuit to the external connections of the integrated circuit; A method for packaging an integrated circuit.

2. the group of metal wiring layers leaving a portion of the group of internal connections uncoupled from the group of external connections; the various groups of metal wiring layers differ from one another in the number of the internal connections in the group of internal connections that remain uncoupled from the group of external connections; The method of claim 1.

3. 2. The method of claim 1, wherein the set of external connections is provided as part of a package for the integrated circuit.

4. the group of metal wiring layers forms a group of leads coupled to the external connection portion; the pitch of the group of leads is equal to the pitch of the external connections on the package; The method according to claim 3.

5. A group of devices, a group of interconnects coupled to the group of devices, the group of interconnects having a first pitch, the group of interconnects being a group of metal layer pads; a group of external connections coupled to the group of internal connections and having a second pitch; a group of metal wiring layers of the integrated circuit coupling the group of internal connections to the group of external connections; Including, a subgroup of the group of internal connections is not connected to the group of external connections; Integrated circuits.

6. 6. The integrated circuit of claim 5, wherein said subset of said group of interconnects is not connected to any of said metal wiring layers in said group of metal wiring layers.

7. 6. The integrated circuit of claim 5, wherein the group of external connections are package contacts.

8. 6. The integrated circuit of claim 5, wherein the group of external connections is one of solder balls, bumps, pillars, and leads.

9. 6. The integrated circuit of claim 5, further comprising a second group of external connections having a third pitch, said group of metal wiring layers of said integrated circuit coupling said group of internal connections to said second group of external connections.

10. the group of interconnects covering a periphery of the integrated circuit; the group of external connections is on a first side of the integrated circuit; a second group of the external connections are on a second side of the integrated circuit; 10. The integrated circuit of claim 9.

11. the integrated circuit is a chiplet; the group of devices being transistors; The first pitch and the second pitch differ by a factor of 2 or more.

6. The integrated circuit of claim 5.

12. forming a first group of devices of a first integrated circuit; forming a first group of interconnects of the first integrated circuit coupled to a first group of the devices of the first integrated circuit; selecting a first group of masks from a mask group library based at least in part on the first group of external connections; forming a first set of metal wiring layers of the first integrated circuit using the first set of masks; forming a second group of devices of a second integrated circuit, the second group of devices being of the same configuration as the first group of devices; forming a second group of interconnects of the second integrated circuit coupled to a second group of devices of the second integrated circuit; selecting a second group of masks from the mask group library based at least in part on a second group of external connections, the second group of masks being different from the first group of masks, the second group of external connections having a configuration that is different from a configuration of the first group of external connections; forming a second group of metal wiring layers of the second integrated circuit using the second group of masks, the second integrated circuit having a configuration different from the configuration of the first group of metal wiring layers; A method comprising:

13. coupling a first group of the external connections of the first integrated circuit to a first group of the internal connections through the first group of metal wiring layers; coupling a second group of the external connections of the second integrated circuit to a second group of the internal connections through a second group of the metal wiring layers; The method of claim 12 further comprising:

14. 14. The method of claim 13, wherein forming the first group of metal wiring layers includes leaving a sub-group of the first group of internal connections uncoupled from the first group of external connections in a first metal wiring configuration.

15. 15. The method of claim 14, wherein forming the second group of metal wiring layers includes leaving a portion of the second group of internal connections uncoupled to the second group of external connections in a second metal wiring configuration, and an amount of the portion of the first group of internal connections that is not coupled to the first group of external connections differs from an amount of the portion of the second group of internal connections that is not coupled to the second group of external connections.

16. a first group of the external connections associated with a first package; a second group of the external connections is associated with a second package; The method of claim 12.

17. The method of claim 16 , wherein the first package is different from the second package.

18. the first group of external connections being one of solder balls, bumps, pillars, and leads; the second group of external connections being one of solder balls, bumps, pillars, and leads; 13. The integrated circuit of claim 12.

19. the first and second integrated circuits are chiplets; the first and second groups of devices are transistors; The method of claim 12.

20. a first group of the internal connections associated with a first pitch, a second group of the internal connections associated with a second pitch, a first group of the external connections associated with a third pitch, and a second group of the external connections associated with a fourth pitch; the first pitch is different from the third pitch; the second pitch is different from the fourth pitch; the third pitch is different from the fourth pitch; The method of claim 12.

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