Low voltage signal level shifter circuit

Abstract

To provide a level shifter that operates at low voltage with a smaller circuit structure.SOLUTION: A low voltage signal level shifter circuit includes a combination of a signal amplitude multiplication circuit to which a low voltage clock signal generated in a low voltage circuit is input, and a level shifter to which its output is input. The signal amplitude multiplication circuit includes a capacitor, an NMOS transistor, and two PMOS transistors. Between a power source of the signal amplitude multiplication circuit and a ground, sources and drains of a first PMOS transistor, a second PMOS transistor, and the NMOS transistor are connected in series in the order from the power source. The low voltage clock signal is input to one terminal of the capacitor and the other terminal thereof is connected to a connection point between the first and second PMOS transistors. An inversion signal of the low voltage clock signal is input to gates of the second PMOS transistor and the NMOS transistor. A connection point of these two transistors is connected to a gate of the first PMOS transistor and becomes an output of the signal amplitude multiplication circuit.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a level shifter that operates with a low voltage clock signal. [Background technology]

[0002] In recent years, in LSIs that have internal circuits and system circuits, the CMOS circuits that make up the internal circuits have become increasingly miniaturized, and the maximum operating voltage of these miniaturized CMOS circuits has become low, at 1V or less. On the other hand, the operating voltage on the system circuit side is often a normal voltage (3.3V to 5.5V). For this reason, it is necessary to convert the signal level from the miniaturized CMOS circuit to match the voltage on the system circuit side, and various level shifter circuits are used to convert from low voltage to high voltage.

[0003] Fig. 5 is a diagram showing a typical conventional level shifter circuit. The level shifter 11 shown in Fig. 5 is composed of a resistor 12 (resistance value RL) and an NMOS transistor 13 connected in series, the source of the NMOS transistor 13 is grounded (Vss = 0V), the drain of the NMOS transistor 13 is connected to the resistor 12 (RL) and serves as an output (CKOZ), and the other terminal of the resistor 12 is connected to a voltage power supply (Vdd). A voltage (Vdd1) from a constant voltage power supply 14 serves as the power supply for a (clock) signal generating source 15, and a clock signal CK from the output (OUT) is input to the gate of the NMOS transistor. When the output CK from the signal generating source 15 is at a HIGH level (Vdd1), the NMOS transistor 13 operates (ON), and the output signal (CKOZ) of the level shifter 11 becomes a LOW level (ground voltage Vss). When the output from the signal generating source 15 is at a low level (ground voltage Vss), the NMOS transistor 13 is turned off and the output signal (CKOZ) of the level shifter 11 becomes a high level (Vdd). The level shifter 11 outputs a signal CKOZ (Vss to Vdd) with a high voltage amplitude relative to the input signal voltage amplitude (Vss to Vdd1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2013-187712 Summary of the Invention [Problem to be solved by the invention]

[0005] When the fine CMOS circuit (signal generating source 15) operates at a low voltage (for example, Vdd1 is 1V or less), if the signal level output from the fine CMOS circuit is close to the threshold voltage of the input NMOS transistor 13 on the level shifter 11 side, it becomes difficult to obtain a sufficient drain current to drive the load of the input NMOS transistor 13. If the resistance value (RL) of the load resistor 12 is increased, it becomes possible to operate it as a level shifter, but signal propagation delay becomes a problem for high-frequency input signals. Conversely, if the resistance value (RL) of the load resistor 12 is reduced to speed up signal propagation, it leads to an increase in the size of the level shifter 11. The present invention provides a low-voltage clock level shifter that enables level conversion of a low-voltage signal with fewer circuit elements and less current consumption, and overcomes the above problem by inserting a signal multiplication circuit in front of the input of the level shifter. [Means for solving the problem]

[0006] The present invention provides a level shifter that operates on a low-voltage signal with a small circuit configuration, and specifically has the following features. The present invention is a low-voltage signal level shifter circuit characterized by being composed of a combination of a signal amplitude multiplier circuit to which a low-voltage clock signal generated by a low-voltage circuit is input, and a level shifter to which an output of the signal amplitude multiplier circuit is input. The signal amplitude multiplier circuit is composed of one capacitance, one NMOS transistor, and two PMOS transistors, first and second, the sources and drains of the first PMOS transistor, the second PMOS transistor, and the NMOS transistor are connected in series between a power supply and a ground of the low-voltage signal amplitude multiplier circuit in this order from the power supply, the low-voltage clock signal is input to one terminal of the capacitance, and the other terminal is connected to a connection point of the first and second PMOS transistors, an inverted clock signal of the low-voltage clock signal is input to the gates of the second PMOS transistor and the NMOS transistor, and the connection point of these two transistors is connected to the gate of the first PMOS transistor and serves as the output of the signal amplitude multiplier circuit. The signal amplitude multiplier circuit includes two signal amplitude multiplier circuits to which low-voltage clock signals of opposite phases are input, and a level shifter to which the output signals of the two signal amplitude multiplier circuits are input. Effect of the Invention

[0007] In an integrated circuit including a low-voltage driven fine CMOS circuit with a maximum operating voltage of 1V or less and a system circuit driven by a high voltage of 3V or more, the low-voltage signal from the fine CMOS circuit can be easily converted to a voltage signal level required by the system side by inserting the circuit of the present invention, which combines a low-voltage signal amplitude multiplier circuit and a level shifter circuit, between the fine CMOS circuit and the system circuit. That is, the signal amplitude multiplier circuit placed in front of the level shifter circuit enhances the driving capability of the input transistor of the level shifter, thereby making the operation of the level shifter circuit smooth. In addition, since the low-voltage signal amplitude multiplier circuit of the present invention is composed of only four elements (a capacitance, two PMOS transistors, and an NMOS transistor), the increase in the area occupied by the entire circuit can be reduced. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing a signal amplitude multiplier circuit according to the present invention. [Diagram 2] FIG. 2 is a diagram showing an example of a timing chart at each portion of the signal amplitude multiplying circuit shown in FIG. [Diagram 3] FIG. 3 is a diagram showing a first embodiment of a level shifter incorporating a signal amplitude multiplier circuit of the present invention. [Figure 4] FIG. 4 is a diagram showing a second embodiment of a level shifter incorporating the signal amplitude multiplier circuit of the present invention. [Diagram 5] FIG. 5 is a diagram showing a conventional level shifter circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] FIG. 1 is a diagram showing a signal amplitude multiplier circuit of the present invention, which is composed of one capacitor 22, two PMOS transistors 23 and 24, and one NMOS transistor 25. In the signal amplitude multiplier circuit of the present invention, the drain of the first PMOS transistor 23 is connected to a constant voltage power supply 21, and the source of the NMOS transistor 25 is grounded. A clock signal ck is input to one terminal of the capacitor 22, and the other terminal of the capacitor 22 is connected to the source of the first PMOS transistor 23 and the source of the second PMOS transistor 24. An inverted clock signal ckz of the clock signal is input to the gates of the second PMOS transistor 24 and the NMOS transistor 25. That is, the second PMOS transistor 24 and the NMOS transistor 25 form an inverter, and the input of the inverter is the inverted clock signal ckz of the clock signal. The output of this inverter is connected (input) to the gate of the first PMOS transistor, and is the output DB of the signal amplitude multiplier circuit. In the present invention, the maximum amplitude of the clock signal ck and the inverted clock signal ckz is a low voltage of 1V or less, so they may be called the low-voltage clock signal ck and the inverted low-voltage clock signal ckz. The voltage of the constant-voltage power supply 21 is also 1V or less, so it may be called a low-voltage power supply. Therefore, the signal amplitude multiplier circuit shown in FIG. 1 may be called a low-voltage signal amplitude multiplier circuit. In general, the constant-voltage power supply 21 is the same as the power supply of the low-voltage circuit that generates the low-voltage clock signal ck and the inverted low-voltage clock signal ckz, but it goes without saying that they do not have to be the same power supply as long as the voltages are approximately the same.

[0010] 2 is a diagram showing an example of a timing chart at each part of the signal amplitude multiplier circuit shown in FIG. 2, the input signals ck and ckz to the signal amplitude multiplier circuit are shown to have a signal amplitude of 0.7V, and the voltage of the constant voltage power supply 21 is also set to 0.7V. In the signal amplitude multiplier circuit of FIG. 1, the clock signal ckz is input to the gates of the PMOS transistor 24 and the NMOS transistor 25 (which constitute a CMOS inverter), so that when the clock signal ckz is a HIGH level signal, the PMOS transistor 24 is turned off and the NMOS transistor 25 is turned on. Therefore, the output signal DB becomes a LOW level (ground voltage Vss=0V), and this DB signal is input to the PMOS transistor 23, so that the PMOS transistor 23 is turned on and the voltage on the drain side of the PMOS transistor 23 (constant voltage power supply 21) becomes equal to the source side of the PMOS transistor 23. That is, the signal ck1 becomes 0.7V. When the clock signal ckz is at a high level (0.7V), the clock signal ck is at a low level (0V), so that the capacitance 22 is charged with a charge equivalent to a voltage of 0.7V. Next, when the clock signal ck changes from a low level (0V) to a high level (0.7V), ck1 rises from 0.7V to 1.4V. At this time, since the clock signal ckz is at a low level (0V), the NMOS transistor 25 is turned off and the PMOS transistor 24 is turned on, so that the voltage of DB rises toward 1.4V. Therefore, since the gate of the PMOS transistor 23 is connected to DB, the PMOS transistor 23 is turned off. If the change in the clock signals ck and ckz is steep, the charge charged in the capacitance 22 is hardly lost and is held, and if the floating capacitance of the node of DB is sufficiently small compared to the capacitance 22, the signal level of DB is held at approximately 1.4V. This circuit operation is repeated in accordance with the voltage change of the clock signals ck and ckz, and the timing chart of FIG. 2 is generated. That is, a clock signal DB having twice the amplitude of the input clock signal ck is output.

[0011] 3 is a diagram showing a first embodiment of a level shifter incorporating a signal amplitude multiplier circuit of the present invention. The level shifter 30 of the present invention shown in FIG. 3 (part surrounded by a dashed line) is a level shifter including a resistor 12 (RL) and an NMOS transistor 13 shown in FIG. 5, and a (clock) signal source 15, and a signal amplitude multiplier circuit 31 of the present invention is disposed between the level shifter. That is, the signal amplitude multiplier circuit 31 is the signal amplitude multiplier circuit shown in FIG. 1. The signal amplitude multiplier circuit outputs a synchronous signal DB obtained by multiplying the amplitude of the output signals ck and ckz (inverted signal of ck) of the signal source 15 to the NMOS transistor 13. As a result, even if the voltage on the HIGH level side of the signal ck from the fine MOS circuit operating at a low voltage in the signal amplitude multiplier circuit 31 is close to the threshold voltage of the input NMOS transistor 13 on the level shifter side, the actual input voltage to the input NMOS transistor 13 can be set high, so that a drain current sufficient to drive the load of the NMOS transistor 13 can be obtained. In addition, it is no longer necessary to increase the resistance value of the load resistor 12 of the level shifter, and the size of the level shifter is not increased. The voltage Vdd1 output from the constant voltage source 14 shown in Fig. 3 is a low voltage (for example, 1 V or less), and the clock signal ck output from the clock signal generating source 15 is also a low-voltage clock signal (0 V to Vdd1).

[0012] FIG. 4 is a diagram showing a second embodiment of a level shifter 40 (part surrounded by a dashed line (outside)) incorporating a signal amplitude multiplier circuit of the present invention. The level shifter 41 (circuit part surrounded by a dashed line (inside)) shown in FIG. 4 is composed of two PMOS transistors 45, 46 and two NMOS transistors 47, 48. A signal amplitude multiplier circuit 42 is disposed between the gate of the NMOS transistor 47 and the signal source 15, and a signal amplitude multiplier circuit 43 is similarly disposed between the gate of the NMOS transistor 48 and the signal source 15. However, while the signals ck and ckz from the signal source 15 are input to the inputs in and inz of the signal amplitude multiplier circuit 42, respectively, the signals ckz and ck from the signal source 15 are input to the two inputs in and inz of the signal amplitude multiplier circuit 43, respectively. Therefore, the output signal DBz of the signal amplitude multiplier circuit 43 input to the NMOS transistor 48 becomes an inverted signal synchronized with the output signal DB of the signal amplitude multiplier circuit 42 input to the NMOS transistor 47 .

[0013] In the level shifter 41, when a HIGH level signal DB is input to the gate of the NMOS transistor 47, the NMOS transistor 47 is turned ON and the source side ground voltage Vss (LOW level, i.e. 0V) is input to the gate of the PMOS transistor 46, turning the PMOS transistor 46 ON. On the other hand, the output DBz of the signal amplitude multiplier circuit 43 is an inverted signal of DB, and is therefore at LOW level. When this LOW level signal DBz is input to the gate of the NMOS transistor 48, the NMOS transistor 48 is turned OFF. As a result, a HIGH level voltage (Vdd) is output as a signal CKO from the connection point between the drain of the PMOS transistor 46 and the drain of the NMOS transistor 48. In addition, since the connection point between the drain of the PMOS transistor 46 and the drain of the NMOS transistor 48 is connected to the gate of the PMOS transistor 45, the PMOS transistor 45 is turned OFF by the HIGH level signal CKO. Therefore, the voltage on the ground side of the NMOS transistor 47 in the ON state (ground voltage, ie, 0 V) ​​is input to the gate of the PMOS transistor 46, and the PMOS transistor 46 is reliably turned ON. In order for the above operation to be performed smoothly, when the signal CKO is 0V, i.e., when the PMOS transistor 45 is ON, and the DB signal transitions to a HIGH level to turn on the NMOS transistor 47, the gate voltage of the PMOS transistor 46 must be driven until the PMOS transistor 45 turns on. That is, the ON current of the NMOS transistor 47 must be greater than the ON current of the PMOS transistor 45. If the HIGH level voltage of the DB signal approaches the threshold voltage of the NMOS transistor 47, a very large NMOS transistor must be prepared to satisfy the above condition, which is not practical. The signal amplitude multiplier circuit 42 plays the role of avoiding such problems.

[0014] When the signal DB is at a LOW level, the above is reversed. That is, in the level shifter 41, when the LOW level signal DB from the signal amplitude multiplier circuit 42 is input to the gate of the NMOS transistor 47, the NMOS transistor 47 is turned OFF. On the other hand, the output DBz of the signal amplitude multiplier circuit 43 is an inverted signal of DB, and is therefore at a HIGH level. When this HIGH level signal DB is input to the gate of the NMOS transistor 48, the NMOS transistor 48 is turned ON, and the ground voltage (LOW level) on the source side is input to the gate of the PMOS transistor 45, turning the PMOS transistor 45 ON. When the PMOS transistor 45 is turned ON, the HIGH level voltage (Vdd) on the source side of the PMOS transistor 45 is input to the gate of the PMOS transistor 46, turning the PMOS transistor 46 OFF. As a result, a LOW level voltage (Vss: ground voltage 0V) is output as the signal CKO from the connection point between the drain of the PMOS transistor 46 and the drain of the NMOS transistor 48. Incidentally, an inverted signal CKOZ of the signal CKO can also be output from the connection point between the drain of the PMOS transistor 45 and the drain of the NMOS transistor 47. In this case as well, the signal amplitude multiplier circuit 43 plays the same role as the signal amplitude multiplier circuit .

[0015] Since the synchronous signal DB or DBz multiplied with respect to the output signal CK of the signal generating source 15 is input to the NMOS transistor 47 or 48, the actual input voltage to the input NMOS transistors 47 and 48 can be set high even if the voltage on the HIGH level side of the signal ck from the fine MOS circuit (signal generating source 15) operating at a low voltage approaches the threshold voltage of the input NMOS transistors 47 and 48 on the level shifter side. Therefore, a drain current sufficient to drive the load of the NMOS transistors 47 and 48 can be obtained in a short time, and the gates of the PMOS transistors 45 and 46 connected to the NMOS transistors 47 and 48 can be operated at high speed.

[0016] As described above in detail, the low-voltage signal amplitude multiplier circuit of the present invention is composed of one capacitor, two PMOS transistors, and one NMOS transistor. With such a small element configuration, the low-voltage signal amplitude multiplier circuit can convert, for example, a signal level of 0.7V to a signal of 1.4V, which is double the signal level, as shown in the timing chart of FIG. 2. By using this signal, even if the input MOS transistor threshold of the level shifter receiving the signal is close to 0.7V, a drain current sufficient to drive the load can be obtained, and the operation of the level shifter can be facilitated. In this specification, it goes without saying that the contents described and explained in a certain part of the specification can be applied to other parts that are not described without contradiction, and the contents can be applied to the other parts. Furthermore, the above embodiment is an example, and various modifications can be made within the scope of the gist of the present invention, and it goes without saying that the scope of the present invention is not limited to the above embodiment. [Explanation of symbols]

[0017] 11 level shifter (circuit), 12 resistor, 13 NMOS transistor, 14 constant voltage power supply, 15 (clock) signal source, 21 constant voltage power supply, 22 capacitance, 23 PMOS transistor, 24 PMOS transistor, 25 NMOS transistor, 30 level shifter (circuit), 31 signal amplitude multiplier circuit, 40 level shifter (circuit), 41 level shifter (circuit), 42 signal amplitude multiplier circuit, 43 signal amplitude multiplier circuit, 45 PMOS transistor, 46 PMOS transistor, 47 NMOS transistor, 48 NMOS transistor,

Claims

1. A low-voltage signal level shifter circuit comprising a signal amplitude multiplier circuit to which a low-voltage clock signal generated by a low-voltage circuit is input, and a level shifter to which the output of the signal amplitude multiplier circuit is input.

2. 2. The low-voltage signal level shifter circuit according to claim 1, wherein the signal amplitude multiplier circuit is composed of one capacitance, one NMOS transistor, and two PMOS transistors, first and second, and the sources and drains of the first PMOS transistor, the second PMOS transistor, and the NMOS transistor are connected in series between a power supply and a ground of the low-voltage signal amplitude multiplier circuit in this order from the power supply, the low-voltage clock signal is input to one terminal of the capacitance, and the other terminal is connected to a connection point of the first and second PMOS transistors, an inverted clock signal of the low-voltage clock signal is input to the gates of the second PMOS transistor and the NMOS transistor, and the connection point of these two transistors is connected to the gate of the first PMOS transistor and serves as an output of the signal amplitude multiplier circuit.

3. 3. The low-voltage signal level shifter circuit according to claim 1, further comprising: two signal amplitude multiplier circuits to which low-voltage clock signals of opposite phases are input; and a level shifter to which output signals of the two signal amplitude multiplier circuits are input.

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