Method for manufacturing display device

Abstract

To improve the efficiency of manufacturing a display panel including a light emitting element that is used in virtual reality devices.SOLUTION: According to one embodiment, the method for manufacturing a display device includes steps of: manufacturing an epitaxial wafer including an epitaxial thin-film; dividing the epitaxial wafer into wafer dies of a size corresponding to an area of each cell region of a backplane substrate; transferring the wafer dies to a carrier substrate; forming a conductive bonding layer on the epitaxial die of the wafer dies; placing the carrier substrate on the backplane substrate so that the epitaxial dies are located in the respective cell regions of the backplane substrate; removing the carrier substrate from the top of the epitaxial dies; etching the epitaxial dies and forming respective light emitting elements in light emission regions included in the respective cell regions.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] An embodiment of the present invention relates to a method for manufacturing a display device. [Background technology]

[0002] Display devices are becoming increasingly important with the development of multimedia. In response to this, various display devices such as liquid crystal display devices and light emitting display devices have been developed. Among them, light emitting display devices include a display panel including light emitting elements, and are applied to various types of electronic devices including portable electronic devices, televisions, virtual reality (VR) devices, and augmented reality (AR) devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Korean Patent Publication 10-2023-0033056 (KR2023-0033056A) [Patent Document 2] Korean Patent Publication No. 10-2020-0022575 (KR2020-0022575A) [Patent Document 3] Korean Patent Publication 10-2022-0116182 (KR2022-0116182A) [Patent Document 4] Korean Patent 10-2468518 (KR2468518B) Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a method for manufacturing a display device that can improve the manufacturing efficiency of a display panel including light-emitting elements.

[0005] The objectives of the present invention are not limited to the technical objectives mentioned above, and other technical objectives not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] A method for manufacturing a display device according to one embodiment includes the steps of: manufacturing an epitaxial wafer including an epitaxial thin film; dividing the epitaxial wafer into wafer dies having a size corresponding to an area of ​​each cell region of a backplane substrate including arranged cell regions; transferring the wafer dies to a carrier substrate; forming a conductive bonding layer on the epitaxial die of the wafer die; positioning the carrier substrate on the backplane substrate such that the epitaxial die is located in each cell region of the backplane substrate, and bonding the epitaxial die to the backplane substrate; removing (removing) the carrier substrate from over the epitaxial die; and etching the epitaxial die to form respective light-emitting elements in light-emitting regions included in each of the cell regions.

[0007] In one embodiment, the carrier substrate may have a size corresponding to an area of ​​the backplane substrate and may include a cell area corresponding to the cell area of ​​the backplane substrate.

[0008] In one embodiment, transferring the wafer dies to the carrier substrate may include aligning the wafer dies to respective cell areas of the carrier substrate.

[0009] In one embodiment, the wafer dies may be fabricated to include respective wafer substrates and respective epitaxial dies separated from the epitaxial wafer.

[0010] In one embodiment, the manufacturing method of the display device may further include a step of applying a filler onto the carrier substrate on which the wafer die is provided to fill gaps between the wafer dies and planarizing the wafer die and the top surface (upper surface) of the carrier substrate on which the filler is provided after transferring the wafer die to the carrier substrate and before forming the conductive bonding layer.

[0011] In one embodiment, the step of planarizing the top surface of the carrier substrate may include removing the respective wafer substrates from the wafer dies to expose the epitaxial dies, and applying a conductive bonding material onto the top surface of the carrier substrate where the epitaxial dies are exposed to form the conductive bonding layer.

[0012] In one embodiment, the method for manufacturing a display device may further include evaluating the wafer die and selecting a pass-through product before transferring the wafer die to a carrier substrate, and transferring the wafer die selected as a pass-through product to the carrier substrate.

[0013] In one embodiment, the backplane substrate may include pixel electrodes provided individually in the light emitting areas of each of the cell regions.

[0014] In one embodiment, etching the epitaxial die may form the respective light emitting element on the pixel electrode.

[0015] In an embodiment, the backplane substrate may further include a first bonding electrode disposed on the pixel electrode.

[0016] In one embodiment, in bonding the carrier substrate and the backplane substrate, the epitaxial die may be bonded onto the first bonding electrode by a Transient Liquid Phase (TLP) bonding method or a Thermal Compression (TC) bonding method.

[0017] In an embodiment, the method for manufacturing a display device may further include etching the conductive bonding layer to form a second bonding electrode between the first bonding electrode and the light emitting element.

[0018] In an embodiment, in the removing of the carrier substrate, the carrier substrate may be removed from above the epitaxial die by a Laser Lift Off (LLO) method.

[0019] In an embodiment, the method for manufacturing a display device may further include forming a common electrode on the light emitting element in each of the cell regions.

[0020] In an embodiment, the method of manufacturing a display device may further include forming a lens-type optical structure on a light emitting device layer including the light emitting device and the common electrode.

[0021] In an embodiment, the method for manufacturing a display device may further include separating each cell corresponding to the cell region into an individual display panel by cutting the backplane substrate based on the cell region.

[0022] A method for manufacturing a display device according to one embodiment includes the steps of: preparing a backplane substrate including cell regions and pixel electrodes provided individually in light-emitting regions located in each of the cell regions; fabricating a wafer die including respective epitaxial dies having a size corresponding to each of the cell regions; preparing a carrier substrate including cell regions having a size corresponding to the backplane substrate and corresponding to the cell regions of the backplane substrate; transferring the wafer dies to the carrier substrate; planarizing a top surface of the carrier substrate to expose the epitaxial dies of the wafer dies and forming a conductive bonding layer on the epitaxial dies; bonding the epitaxial dies to the pixel electrodes using the conductive bonding layer; and etching the epitaxial dies to form respective light-emitting elements on the pixel electrodes.

[0023] In one embodiment, transferring the wafer dies to the carrier substrate may include aligning the wafer dies to respective cell areas of the carrier substrate.

[0024] In one embodiment, the backplane substrate may further include a first bonding electrode disposed on the pixel electrode, and the epitaxial die may be bonded onto the first bonding electrode by a Transient Liquid Phase (TLP) bonding method or a Thermal Compression (TC) bonding method.

[0025] In an embodiment, the method for manufacturing a display device may further include etching the conductive bonding layer to form a second bonding electrode between the first bonding electrode and the light emitting element.

[0026] Specific details of other embodiments are included in the detailed description and drawings. Effect of the Invention

[0027] According to an embodiment, an epitaxial wafer is divided into pieces of a size corresponding to each cell region of a backplane substrate, and transferred to a carrier substrate. An epitaxial die is bonded onto each cell region of the backplane substrate, and then the epitaxial die is etched to form a pixel light-emitting element.

[0028] According to the method for manufacturing a display device according to the embodiment, it is possible to increase the utilization efficiency of a wafer substrate used for growing an epitaxial thin film, thereby reducing the manufacturing cost of a display panel. In addition, it is possible to facilitate and / or simplify the manufacturing process of a display panel, thereby preventing or reducing alignment errors related to the position where a light emitting element is formed, etc. As a result, it is possible to increase the manufacturing efficiency of a display panel including a light emitting element and a display device including the same, thereby improving the yield.

[0029] The effects of the embodiments are not limited to the above examples, and more diverse effects are included in the present specification. [Brief description of the drawings]

[0030] [Figure 1] 1 is a perspective view showing a display device according to an embodiment; [Diagram 2] FIG. 2 is a plan view showing an embodiment of region A of FIG. [Diagram 3] 3 is a cross-sectional view showing an embodiment of a cross section of a display panel corresponding to line X1-X1' in FIG. 2. [Figure 4] 1 is a cross-sectional view illustrating a light emitting device according to an embodiment. [Diagram 5] 1 is a cross-sectional view illustrating a light emitting device according to an embodiment. [Figure 6] 1 is a cross-sectional view illustrating a light emitting device according to an embodiment. [Figure 7] 1 is a flow chart showing a method of manufacturing a display device according to an embodiment. [Figure 8] 1A to 1C are diagrams illustrating a method for manufacturing a display panel according to an embodiment. [Figure 9] 1A to 1C are diagrams illustrating a method for manufacturing a display panel according to an embodiment. [Figure 10] 1A to 1C are diagrams illustrating a method for manufacturing a display panel according to an embodiment. [Figure 11] 1A to 1C are diagrams illustrating a method for manufacturing a display panel according to an embodiment. [Figure 12] 1A to 1C are diagrams illustrating a method for manufacturing a display panel according to an embodiment. [Figure 13] 1A to 1C are diagrams illustrating a method for manufacturing a display panel according to an embodiment. [Figure 14] 1A to 1C are diagrams illustrating a method for manufacturing a display panel according to an embodiment. [Figure 15] 1A to 1C are diagrams illustrating a method for manufacturing a display panel according to an embodiment. [Figure 16] 1A to 1C are diagrams illustrating a method for manufacturing a display panel according to an embodiment. [Figure 17] 1A to 1C are diagrams illustrating a method for manufacturing a display panel according to an embodiment. [Figure 18] 1A to 1C are diagrams illustrating a method for manufacturing a display panel according to an embodiment. [Figure 19] 1A to 1C are diagrams illustrating a method for manufacturing a display panel according to an embodiment. [Figure 20] 1A to 1C are diagrams illustrating a method for manufacturing a display panel according to an embodiment. [Figure 21] 1A to 1C are diagrams illustrating a method for manufacturing a display panel according to an embodiment. [Figure 22] 1A to 1C are diagrams illustrating a method for manufacturing a display panel according to an embodiment. [Figure 23] 1 is an exemplary diagram illustrating a virtual reality device including a display device according to an embodiment. [Figure 24] 1 is an exemplary diagram illustrating a smart device including a display device according to an embodiment. [Diagram 25] 1 is an exemplary diagram illustrating a vehicle instrument panel and a center fascia including a display device according to an embodiment; [Figure 26] 1 is an exemplary view illustrating a transparent display device including a display device according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] The advantages and features of the present invention, as well as the methods for achieving the same, will become clearer with reference to the following detailed embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be realized in various different forms, and the present embodiments are provided merely to complete the disclosure of the present invention and to fully inform those skilled in the art of the invention of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0032] When elements or layers are referred to as "on" other elements or layers, this includes all cases where other layers or other elements are directly on or between the other elements. The same reference numerals refer to the same components throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are merely examples, and the present invention is not limited to the illustrated matters.

[0033] The respective features of the various embodiments of the present invention can be partially or fully combined or combined with each other, and various technical interlocking and driving are possible, and each embodiment can be implemented independently of each other, or can be implemented in conjunction with each other.

[0034] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0035] Fig. 1 is a perspective view showing a display device 10 according to an embodiment. Fig. 2 is a plan view showing an embodiment of a region A in Fig. 1. Fig. 3 is a cross-sectional view showing an embodiment of a cross section of a display panel 100 corresponding to line X1-X1' in Fig. 2.

[0036] 1 to 3 show an embodiment of a light emitting diode on silicon (LEDoS) display device 10 in which light emitting diodes are arranged as light emitting elements LE on a semiconductor circuit substrate (for example, a backplane substrate 110 of a display panel 100 in which pixel circuits PXC and the like are formed based on a silicon wafer) formed by a semiconductor process using a silicon wafer. However, a device including the light emitting element LE according to the embodiment is not limited thereto. For example, the light emitting element LE manufactured according to the embodiment may be applied to a display device of a different type and / or structure, or may be applied to a device of a different type and / or structure, such as a lighting device. As an example, the embodiment described with reference to FIGS. 4 to 19 may also be applied to the manufacture of a device of a different type and / or structure including the light emitting element LE.

[0037] 1 to 3, a first direction DR1 indicates the horizontal direction of the display panel 100, and a second direction DR2 indicates the vertical direction of the display panel 100. A third direction DR3 indicates the thickness direction of the display panel 100.

[0038] 1 and 2, a display device 10 according to an embodiment may include a display panel 100 including a display area DA and a non-display area NDA.

[0039] The display panel 100 may have a rectangular planar shape having a long side in a first direction DR1 and a short side in a second direction DR2. However, the planar shape of the display panel 100 is not limited thereto, and the display panel 100 may have a different shape. For example, the display panel 100 may have a polygonal shape other than a rectangle, a circle, an ellipse, or an irregular planar shape.

[0040] The display area DA may be an area where an image is displayed, and the non-display area NDA may be an area where an image is not displayed. In one embodiment, the planar shape of the display area DA may conform to the planar shape of the display panel 100. FIG. 1 illustrates an example in which the planar shape of the display area DA is a rectangle. The display area DA may be disposed in a central area of ​​the display panel 100. The non-display area NDA may be disposed around the display area DA. As an example, the non-display area NDA may surround the display area DA.

[0041] The display area DA may include pixels PX. Each pixel PX may include at least two light-emitting elements LE.

[0042] In one embodiment, each pixel PX may include three light emitting elements LE. For example, each pixel PX may include a first light emitting element LE1, a second light emitting element LE2, and a third light emitting element LE3. The number and / or type of light emitting elements LE provided in the pixel PX may be variously changed according to the embodiment.

[0043] In one embodiment, each pixel PX may include a light emitting element LE that emits light of different colors, for example, a first light emitting element LE1, a second light emitting element LE2, and a third light emitting element LE3 may emit light of different colors.

[0044] The first light emitting element LE1 emits a first light. The first light may be red light. For example, the main peak wavelength (R-peak) of the first light may be located in the range of about 600 nm to 750 nm, but the embodiment is not limited thereto.

[0045] The second light emitting element LE2 emits the second light. The second light may be green light. For example, the main peak wavelength (G-peak) of the second light may be located in the range of about 480 nm to 560 nm, but the embodiment is not limited thereto.

[0046] The third light emitting element LE3 emits a third light. The third light may be blue light. For example, the main peak wavelength (B-peak) of the third light may be located in the range of about 370 nm to 460 nm, but the embodiment is not limited thereto.

[0047] In another embodiment, the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 may emit light of the same color, and a light conversion layer including a light conversion element (e.g., quantum dots) for converting the color (or a corresponding wavelength band) of light emitted from the at least one light emitting element LE into light of another color (or a corresponding wavelength band) may be disposed on at least one light emitting element LE among the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3.

[0048] In one embodiment, the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 of each pixel PX may be sequentially arranged in a first direction DR1. In one embodiment, the first light emitting element LE1 may be arranged in a second direction DR2. The second light emitting element LE2 may be arranged in the second direction DR2. The third light emitting element LE3 may be arranged in the second direction DR2. For example, the first light emitting element LE1, the second light emitting element LE2, or the third light emitting element LE3 may be arranged in each pixel column extending along the second direction DR2. In addition, the arrangement structure of the pixel PX and the light emitting elements LE provided in the pixel PX may be variously changed depending on the embodiment.

[0049] In one embodiment, the light emitting elements LE may be arranged in the display area DA at substantially equal intervals, but is not limited thereto. For example, the positions of the light emitting elements LE and / or the intervals between the light emitting elements LE may be variously changed depending on the embodiment.

[0050] In one embodiment, the sizes (for example, areas) of the light emitting elements LE may be substantially the same as each other. For example, the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 may have substantially the same size. However, the embodiment is not limited thereto, and the size of each light emitting element LE and / or the area of ​​the light emitting region corresponding to the light emitting element LE may be variously changed depending on the embodiment.

[0051] In one embodiment, the light emitting element LE may have a circular planar shape, but the embodiment is not limited thereto. For example, the light emitting element LE may have a rectangular or other polygonal, elliptical, or irregular shape. The light emitting elements LE may have substantially the same planar shape or may have different planar shapes for each group.

[0052] The non-display area NDA may include a first common voltage supply area CVA1, a second common voltage supply area CVA2, a first pad area PDA1, a second pad area PDA2, and a peripheral area PHA.

[0053] The first common voltage supply region CVA1 may be disposed between the first pad region PDA1 and the display region DA. The second common voltage supply region CVA2 may be disposed between the second pad region PDA2 and the display region DA. Each of the first common voltage supply region CVA1 and the second common voltage supply region CVA2 may include a common electrode connection part CVS coupled to a common electrode (for example, the common electrode CME in FIG. 3). For example, the common electrode may extend from the display region DA to the first common voltage supply region CVA1 and the second common voltage supply region CVA2 and be electrically connected to the common electrode connection part CVS. A common voltage may be supplied to the common electrode via the common electrode connection part CVS.

[0054] The common electrode connector CVS may be disposed in a common voltage supply region (for example, a first common voltage supply region CVA1 and / or a second common voltage supply region CVA2) of the non-display area NDA. The common electrode connector CVS may include a conductive material (for example, a metal material such as aluminum (Al)). Although FIGS. 1 and 2 disclose a display device 10 in which the common electrode connector CVS is located in the non-display area NDA, the embodiment is not limited thereto. For example, the common electrode connector CVS may be located in the display area DA. For example, the common electrode connector CVS may be located in a pixel area or between pixel areas.

[0055] The common electrode connector CVS of the first common voltage supply region CVA1 may be electrically connected to any one of the first pads PD1 of the first pad region PDA1. For example, the common electrode connector CVS of the first common voltage supply region CVA1 may receive a common voltage from any one of the first pads PD1 of the first pad region PDA1.

[0056] The first pad PD1 may be disposed in the first pad area PDA1. The first pad PD1 may be connected to a circuit board (not shown) via a conductive connecting member. For example, the first pad PD1 may be electrically connected to a circuit pad provided on the circuit board via a wire.

[0057] The common electrode connector CVS of the second common voltage supply region CVA2 may be electrically connected to any one of the second pads of the second pad region PDA2. For example, the common electrode connector CVS of the second common voltage supply region CVA2 may receive a common voltage from any one of the second pads of the second pad region PDA2. In one embodiment, the display panel 100 may not include the second common voltage supply region CVA2.

[0058] The first pad area PDA1 may be disposed on one side (for example, the upper side) of the display panel 100. The first pad area PDA1 may include a first pad PD1 that is connected to an external circuit board.

[0059] The second pad area PDA2 may be disposed on another side (for example, the bottom side) of the display panel 100. The second pad area PDA2 may include a second pad coupled to an external circuit board. In some embodiments, the display panel 100 may not include the second pad area PDA2.

[0060] The second pad may be disposed in a second pad area PDA2 of the non-display area NDA. The second pad may be coupled to a circuit board (not shown) via a conductive coupling member. For example, the second pad may be electrically connected to a circuit pad provided on the circuit board via a wire.

[0061] The peripheral area PHA may be a remaining area in the non-display area NDA excluding the first common voltage supply area CVA1, the second common voltage supply area CVA2, the first pad area PDA1, and the second pad area PDA2. The peripheral area PHA may surround not only the display area DA, but also the first common voltage supply area CVA1, the second common voltage supply area CVA2, the first pad area PDA1, and the second pad area PDA2.

[0062] 1 and 2, and further referring to FIG 3, the display panel 100 may include a backplane substrate 110 and a light emitting device layer 120. In one embodiment, the display panel 100 may further include an optical structure (or light output structure), such as a lens-type optical structure LS, provided on the light emitting device layer 120.

[0063] The display panel 100 may further include additional components according to the embodiment. For example, the display panel 100 may further include a light conversion layer for converting the color and / or wavelength of light emitted from at least some of the light emitting elements LE, and / or a color filter layer for controlling each light emitting area EA to emit light of a specific color.

[0064] The display panel 100 may include light-emitting areas EA located in the display area DA. Each of the light-emitting areas EA may include at least one light-emitting element LE. For example, the light-emitting area EA may include a first light-emitting area EA1 provided with at least one first light-emitting element LE1, a second light-emitting area EA2 provided with at least one second light-emitting element LE2, and a third light-emitting area EA3 provided with at least one third light-emitting element LE3. In one embodiment, the first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3 may emit first light, second light, and third light, respectively.

[0065] The backplane substrate 110 may include a display area DA including a light emitting area EA. In one embodiment, the backplane substrate 110 may be a semiconductor circuit substrate formed by a semiconductor process using a silicon wafer. For example, a silicon wafer may be used as a base member for forming the display panel 100.

[0066] The backplane substrate 110 may include pixel circuits PXC and pixel electrodes PXE provided in the display area DA. For example, at least one light-emitting element LE may be provided in each light-emitting area EA of the display panel 100, and the backplane substrate 110 may include pixel circuits PXC and pixel electrodes PXE coupled (for example, electrically connected) to each light-emitting element LE arranged in each light-emitting area EA.

[0067] In one embodiment, the backplane substrate 110 may further include a first bonding electrode BOE1 (also referred to as a "first contact electrode" or "first connecting electrode") disposed on each pixel electrode PXE. In one embodiment, the backplane substrate 110 may further include a first insulating layer INS1 disposed around the pixel electrode PXE and / or a second insulating layer INS2 disposed around the first bonding electrode BOE1.

[0068] The pixel circuits PXC may be provided in the display area DA corresponding to the areas in which the respective pixels PX and / or light-emitting areas EA are formed. In one embodiment, each of the pixel circuits PXC may include a complementary metal-oxide semiconductor (CMOS) circuit formed using a semiconductor process.

[0069] Each of the pixel circuits PXC may include at least one transistor formed by a semiconductor process, and each of the pixel circuits PXC may further include at least one capacitor formed by a semiconductor process.

[0070] The pixel circuits PXC can be electrically connected to the respective pixel electrodes PXE. For example, the pixel circuits PXC and the pixel electrodes PXE can be connected in one-to-one correspondence. Each of the pixel circuits PXC can apply a pixel voltage to the pixel electrode PXE connected thereto.

[0071] The pixel electrodes PXE may be connected to the respective pixel circuits PXC. The pixel electrodes PXE may be provided in the respective light-emitting areas EA individually and electrically connected to the light-emitting elements LE located in the respective light-emitting areas EA. Therefore, the light-emitting elements LE located in the respective light-emitting areas EA may be individually and / or independently controlled.

[0072] Each of the pixel electrodes PXE may be disposed on a corresponding pixel circuit PXC. In one embodiment, each of the pixel electrodes PXE may be an electrode formed integrally with the pixel circuit PXC and exposed from the pixel circuit PXC. For example, each of the pixel electrodes PXE may protrude from the upper surface of the pixel circuit PXC. Each of the pixel electrodes PXE may receive a pixel voltage from the pixel circuit PXC. The pixel electrodes PXE may include a conductive material (for example, a metal material such as aluminum (Al)).

[0073] In one embodiment, a first insulating layer INS1 may be disposed around the pixel electrode PXE. The first insulating layer INS1 may be provided on an upper surface of a semiconductor circuit substrate on which the pixel circuit PXC is formed. In one embodiment, the first insulating layer INS1 may be disposed between the pixel electrodes PXE in a form surrounding the pixel electrodes PXE.

[0074] The first insulating layer INS1 may expose at least a portion of each of the pixel electrodes PXE. For example, the first insulating layer INS1 may include an opening corresponding to the pixel electrode PXE and expose the upper surface of the pixel electrode PXE. The first insulating layer INS1 may be made of silicon oxide (SiOx), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al x O y ), aluminum nitride (AlN), or other inorganic insulating materials.

[0075] The first bonding electrodes BOE1 may be provided in each light emitting area EA individually so as to be located on each pixel electrode PXE. The first bonding electrodes BOE1 may be electrically connected to each pixel electrode PXE. The first bonding electrodes BOE1 may also be electrically connected to the light emitting elements LE located in each light emitting area EA. The light emitting elements LE may be coupled to the respective pixel circuits PXC via the first bonding electrodes BOE1.

[0076] The first bonding electrodes BOE1 may include a conductive bonding material suitable for bonding or adhering the light emitting element LE onto the pixel electrodes PXE. For example, each of the first bonding electrodes BOE1 may be a single-layer or multi-layer electrode including gold (Au), copper (Cu), aluminum (Al), tin (Sn), or other metal material (for example, a bonding metal). In another embodiment, when the backplane substrate 110 does not include the first bonding electrodes BOE1 and directly bonds or adheres the light emitting element LE onto the pixel electrodes PXE, the pixel electrodes PXE may include a conductive material (for example, a metal material suitable for use as a bonding metal) that can be appropriately connected to the light emitting element LE by a bonding or adhering process or the like.

[0077] In one embodiment, a second insulating layer INS2 may be disposed around the first bonding electrode BOE1. The second insulating layer INS2 may be provided on an upper surface of a semiconductor circuit substrate on which the pixel circuit PXC, the pixel electrode PXE, and / or the first insulating layer INS1 are formed. In one embodiment, the second insulating layer INS2 may be disposed between the first bonding electrodes BOE1 in a form surrounding the first bonding electrodes BOE1.

[0078] The second insulating layer INS2 may expose at least a portion of each of the first bonding electrodes BOE1. For example, the second insulating layer INS2 may include openings corresponding to the first bonding electrodes BOE1 and expose the top surfaces of the first bonding electrodes BOE1. The second insulating layer INS2 may be made of silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al x O y ), inorganic insulating materials such as aluminum nitride (AlN), or other insulating materials.

[0079] The backplane substrate 110 may further include a non-display area NDA as shown in Figures 1 and 2. In one embodiment, the backplane substrate 110 may further include a common electrode connector CVS, a first pad PD1, and / or a second pad, etc., located in the non-display area NDA.

[0080] The light emitting device layer 120 may include a second bonding electrode BOE2, a light emitting element LE, and a common electrode CME. In one embodiment, the light emitting device layer 120 may further include an organic film ORL disposed around the light emitting element LE and / or a third insulating layer INS3 disposed on the common electrode CME.

[0081] In an embodiment, the light-emitting element layer 120 may further include additional components. For example, the light-emitting element layer 120 may further include a reflective layer and / or a light-shielding layer provided between the light-emitting elements LE and / or on the side surfaces of the light-emitting elements LE.

[0082] The second bonding electrodes BOE2 may be provided at positions corresponding to the pixel electrodes PXE and electrically connected to the pixel electrodes PXE. For example, the second bonding electrodes BOE2 may be disposed on the first bonding electrodes BOE1 provided on the pixel electrodes PXE. The second bonding electrodes BOE2 may be individually patterned in shapes corresponding to the pixel electrodes PXE and / or the first bonding electrodes BOE1. For example, the second bonding electrodes BOE2 may be patterned in shapes having sizes and / or shapes corresponding to the pixel electrodes PXE and / or the first bonding electrodes BOE1, may be separated from each other, and may be disposed on the first bonding electrodes BOE1.

[0083] The second bonding electrodes BOE2 may include a conductive bonding material suitable for bonding or adhering the light emitting element LE onto the first bonding electrodes BOE1 (or pixel electrodes PXE). As an example, each of the second bonding electrodes BOE2 may be a single layer or multi-layer electrode including gold (Au), copper (Cu), aluminum (Al), tin (Sn), or other metallic material (as an example, a bonding metal).

[0084] The light emitting elements LE may be disposed on the respective second bonding electrodes BOE2. The light emitting elements LE may be electrically connected between the respective pixel electrodes PXE and the common electrode CME.

[0085] The light-emitting element LE may include semiconductor layers grown on a semiconductor substrate (e.g., a wafer substrate) by epitaxial growth. For example, the light-emitting element LE may include a first semiconductor layer doped to a first conductive type, a second semiconductor layer doped to a second conductive type, and an active layer interposed between the first and second semiconductor layers.

[0086] The light-emitting element LE may be formed from an epitaxial thin film of a wafer die separated from an epitaxial wafer, and may be patterned in a cell region corresponding to each display panel 100 to form each light-emitting area EA. A detailed description of the structure and manufacturing method of the light-emitting element LE according to the embodiment will be provided later.

[0087] An organic film ORL may be provided around the light-emitting element LE. For example, the organic film ORL may be disposed between the light-emitting areas EA so as to surround the light-emitting areas EA in which the light-emitting element LE is provided, and may surround the light-emitting element LE and the second bonding electrode BOE2. In one embodiment, the organic film ORL may be a filler (gap filling material) that fills the gap between the light-emitting elements LE. The organic film ORL may expose a portion of the light-emitting element LE, for example, the upper surface.

[0088] The organic film ORL may include an insulating material, for example, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or a single-layer or multi-layer organic insulating film including other organic insulating materials.

[0089] The common electrode CME may be disposed on an upper portion of the light emitting element LE that is not covered by the organic film ORL. In one embodiment, the common electrode CME may be disposed over the entire display area DA to cover the light emitting element LE and the organic film ORL. The common electrode CME may be a common layer formed and / or connected in common to the light emitting element LE and the pixel PX including the light emitting element LE in the display area DA.

[0090] The common electrode CME may be electrically connected to a common electrode connector CVS disposed in a first common voltage supply region CVA1 and / or a second common voltage supply region CVA2 in Figures 1 and 2. Therefore, the common electrode CME may be supplied with a common voltage via the common electrode connector CVS.

[0091] The common electrode CME may include a transparent conductive material capable of transmitting light. For example, the common electrode CME may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), or other transparent conductive materials. In one embodiment, the common electrode CME may function as a cathode electrode (or an anode electrode) of the light emitting element LE.

[0092] The third insulating layer INS3 may be disposed on the common electrode CME. For example, the third insulating layer INS3 may be a capping layer disposed over the entire display area DA so as to cover the common electrode CME. The third insulating layer INS3 may be a silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Alx O y ), inorganic insulating materials such as aluminum nitride (AlN), or other insulating materials.

[0093] In an embodiment, the display panel 100 may include a lens-type optical structure LS provided on the light-emitting device layer 120. The display panel 100 may further include a protective layer PSV covering the lens-type optical structure LS.

[0094] The lens-type optical structure LS may be disposed in each light-emitting area EA so as to overlap the light-emitting element LE. In one embodiment, the lens-type optical structure LS may be a convex lens-shaped optical structure provided on the upper part of the light-emitting element LE, but the type and / or shape of the optical structure is not limited thereto. By disposing the lens-type optical structure LS on the upper part of the light-emitting element LE, the light output characteristics of the pixel PX may be adjusted and / or improved.

[0095] The lens-type optical structure LS may be made of a transparent material so that the light incident from the light emitting element LE can be transmitted therethrough. For example, the lens-type optical structure LS may be made of glass, plastic, ceramic, or other materials, and may be made of an optical material having a high refractive index.

[0096] The protective layer PSV may be disposed on the lens-type optical structure LS so as to cover the lens-type optical structure LS. The protective layer PSV may be formed of a transparent and durable material (e.g., plastic, organic glass, optical glass, ceramic, etc.), and the material is not particularly limited as long as it is suitable for protecting the lens-type optical structure LS, etc. In FIG. 3, an embodiment in which the protective layer PSV has a bend corresponding to the shape of the lens-type optical structure LS is disclosed, but the embodiment is not limited thereto. For example, the protective layer PSV may be formed in a shape that can flatten the upper surface of the display panel 100 on which the lens-type optical structure LS, etc. are formed.

[0097] Fig. 4 is a cross-sectional view showing a light-emitting element LE according to an embodiment. Fig. 5 is a cross-sectional view showing a light-emitting element LE according to an embodiment. Fig. 6 is a cross-sectional view showing a light-emitting element LE according to an embodiment. For example, Fig. 5 shows an embodiment different from the embodiment of Fig. 4 in relation to the shape of the light-emitting element LE, and Fig. 6 shows an embodiment different from the embodiment of Fig. 4 in relation to the arrangement direction of the light-emitting element LE.

[0098] 4 to 6, the light emitting element LE may include a first semiconductor layer SEM1, an active layer MQW, and a second semiconductor layer SEM2, which are sequentially arranged and / or stacked along a third direction DR3. In one embodiment, the light emitting element LE may further include a contact electrode CTE provided at one end. For example, the light emitting element LE may further include a contact electrode CTE provided at one end where the first semiconductor layer SEM1 is located.

[0099] The light-emitting element LE may further include additional layers according to the embodiment. For example, the light-emitting element LE may further include an electron blocking layer disposed between the first semiconductor layer SEM1 and the active layer MQW, and / or a superlattice layer disposed between the active layer MQW and the second semiconductor layer SEM2.

[0100] In an embodiment, the light emitting device LE may be an inorganic light emitting device formed of an inorganic material, for example, an inorganic light emitting diode formed of a nitride-based semiconductor material such as GaN, AlGaN, InGaN, AlInGaN, AlN, or InN, a phosphide-based semiconductor material such as GaP, GaInP, AlGaP, AlGaInP, AlP, or InP, or other inorganic material.

[0101] The contact electrode CTE may be provided and / or formed at one end of the light emitting element LE on which the first semiconductor layer SEM1 is disposed. For example, the contact electrode CTE may be provided and / or formed on one surface of the first semiconductor layer SEM1. The contact electrode CTE may be an electrode for protecting the first semiconductor layer SEM1 and smoothly connecting the first semiconductor layer SEM1 to at least one circuit element, electrode, wiring, and / or conductive layer. The contact electrode CTE may include a metal, a metal oxide, or other conductive material.

[0102] The first semiconductor layer SEM1 may be disposed on the contact electrode CTE. In one embodiment, the first semiconductor layer SEM1 may include a nitride-based semiconductor material or a phosphide-based semiconductor material. For example, the first semiconductor layer SEM1 may include a nitride-based semiconductor material including at least one of GaN, AlGaN, InGaN, AlInGaN, AlN, and InN, or a phosphide-based semiconductor material including at least one of GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. The first semiconductor layer SEM1 may also include other materials.

[0103] The first semiconductor layer SEM1 may include a semiconductor material doped with a first conductive type dopant. For example, the first semiconductor layer SEM1 may be formed of GaN (for example, p-GaN) doped with a first conductive type dopant (for example, a p-type dopant) such as Mg, Zn, Ca, Se, Ba, etc.

[0104] The active layer MQW may be disposed on the first semiconductor layer SEM1. The active layer MQW may emit light by recombination of electron-hole pairs in response to an electrical signal applied via the first semiconductor layer SEM1 and the second semiconductor layer SEM2. For example, the active layer MQW may be a light-emitting layer of the light-emitting element LE.

[0105] The active layer MQW may include a material having a single or multiple quantum well structure. When the active layer MQW includes a material having a multiple quantum well structure, the active layer MQW may have a structure in which a plurality of well layers and barrier layers are alternately stacked. The active layer MQW may also include other Group 3 to Group 5 semiconductor materials depending on the wavelength band of the emitted light.

[0106] In an embodiment, the active layer MQW may include a nitride-based semiconductor material or a phosphide-based semiconductor material. For example, the active layer MQW may include a nitride-based semiconductor material including at least one of GaN, AlGaN, InGaN, InGaAlN, AlN, InN, and AlInN, or a phosphide-based semiconductor material including at least one of GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. As an example, the well layer is formed of InGaN, and the barrier layer is formed of GaN or AlGaN, but the embodiment is not limited thereto. When the active layer MQW includes InGaN, the content of indium (In) may be adjusted to control the color of light emitted from the light emitting element LE. The active layer MQW may include other materials.

[0107] In one embodiment, the active layers MQW of the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 shown in Figures 2 and 3 can emit light of the same color (for example, blue light). In another embodiment, the active layers MQW of the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 can emit light of different colors (for example, red light, green light, and blue light, respectively).

[0108] The second semiconductor layer SEM2 may be disposed on the active layer MQW. In one embodiment, the second semiconductor layer SEM2 may include a nitride-based semiconductor material or a phosphide-based semiconductor material. For example, the second semiconductor layer SEM2 may include a nitride-based semiconductor material including at least one of GaN, AlGaN, InGaN, AlInGaN, AlN, and InN, or a phosphide-based semiconductor material including at least one of GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. The second semiconductor layer SEM2 may also include other materials.

[0109] The second semiconductor layer SEM2 may include a semiconductor material doped with a second conductive type dopant. For example, the second semiconductor layer SEM2 may be formed of GaN (for example, n-GaN) doped with a second conductive type dopant (for example, an n-type dopant) such as Si, Ge, or Sn.

[0110] In one embodiment, the first semiconductor layer SEM1 and the second semiconductor layer SEM2 may have different thicknesses in a thickness direction (for example, a third direction DR3) of the light emitting device LD. For example, the second semiconductor layer SEM2 may have a thickness greater than that of the first semiconductor layer SEM1 in the thickness direction of the light emitting device LD. Therefore, the active layer MQW may be located closer to a first end (for example, a p-type end) of the light emitting device LE in which the first semiconductor layer SEM1, etc. are provided than a second end (for example, an n-type end) of the light emitting device LE in which the second semiconductor layer SEM2 is provided.

[0111] In one embodiment, the light emitting element LE may be a vertical micro LED that is elongated and / or stacked in the third direction DR3. For example, the light emitting element LE may be a micro LED having a length in the first direction DR1, a length in the second direction DR2, and a length in the third direction DR3 of several micrometers (μm) to several hundred micrometers (μm). In one embodiment, the length of the light emitting element LE in the first direction DR1, the length in the second direction DR2, and the length in the third direction DR3 may be approximately 100 μm or less.

[0112] In one embodiment, the light-emitting element LE may include substantially vertical sides as shown in Fig. 4. For example, the light-emitting element LE may be patterned by vertical etching and may have a rectangular or square cross-sectional shape in which the width of the top surface and the width of the bottom surface are substantially the same.

[0113] The shape of the light emitting element LE may be variously changed according to the embodiment For example, the light emitting element LE may have a cross-sectional shape in which the width of the upper surface is different from the width of the lower surface.

[0114] In an embodiment, the light emitting element LE may have a cross-sectional shape of an inverted taper as shown in Fig. 5. For example, the light emitting element LE may have a cross-sectional shape of an inverted trapezoid in which the width of the upper surface is greater than the width of the lower surface.

[0115] In one embodiment, the light-emitting element LE may be disposed on the backplane substrate 110 such that the first semiconductor layer SEM1 is located at the bottom (below) of the active layer MQW and the second semiconductor layer SEM2 is located at the top (above) of the active layer MQW as shown in Fig. 4. For example, the light-emitting element LE may be disposed in each light-emitting area EA such that the contact electrode CTE (or the first semiconductor layer SEM1) contacts the second bonding electrode BOE2 in Fig. 3 and the second semiconductor layer SEM2 (or another contact electrode provided on the second semiconductor layer SEM2) contacts the common electrode CME. In this case, the common electrode CME may be a cathode electrode.

[0116] In one embodiment, the light-emitting element LE may be disposed on the backplane substrate 110 such that the second semiconductor layer SEM2 is located at the bottom (below) of the active layer MQW and the first semiconductor layer SEM1 is located at the top (above) of the active layer MQW as shown in Fig. 6. For example, the light-emitting element LE may be disposed in each light-emitting area EA such that the second semiconductor layer SEM2 (or another contact electrode provided on the second semiconductor layer SEM2) contacts the second bonding electrode BOE2 in Fig. 3 and the contact electrode CTE (or the first semiconductor layer SEM1) contacts the common electrode CME. In this case, the common electrode CME may be an anode electrode.

[0117] In one embodiment, the arrangement direction of the light emitting element LE disposed on the second bonding electrode BOE2 can be adjusted by adjusting the direction in which each wafer die (or epitaxial die) for forming the light emitting element LE is transferred to the carrier substrate. For example, a surface on which a bonding material is formed can be selected by a process of transferring the wafer die (or epitaxial die) to the carrier substrate once or more than once.

[0118] The structure, material, size and / or shape of the light emitting device LE are not limited to those in the above-described embodiment, and may be modified in various ways depending on the embodiment.

[0119] Fig. 7 is a flow chart showing a method for manufacturing the display device 10 according to an embodiment. For example, Fig. 7 is a flow chart showing a method for manufacturing the display panel 100 of the display device 10 according to an embodiment. Figs. 8 to 22 are views for explaining a method for manufacturing the display panel 100 according to an embodiment. For example, each of Figs. 8 to 22 is a perspective view, a cross-sectional view, or a plan view showing a specific stage for forming the display panel 100.

[0120] Referring to FIGS. 7 to 9 in addition to FIGS. 1 to 6, an epitaxial wafer EWF including an epitaxial thin film EPIL can be manufactured (S110 in FIG. 7).

[0121] For example, as shown in Fig. 8, a wafer substrate WAF (or a different type of substrate suitable for epitaxial growth) can be prepared, and an epitaxial thin film EPIL can be formed on the wafer substrate WAF. Fig. 8 is a perspective view showing a schematic configuration of an epitaxial wafer EWF.

[0122] The wafer substrate WAF may be a semiconductor substrate suitable for epitaxial growth of a semiconductor. For example, the wafer substrate WAF may be a substrate including a material such as silicon (Si), sapphire, SiC, GaN, GaAs, or ZnO. As long as the epitaxial growth for manufacturing the light-emitting element LD is smoothly performed, the type, material, and shape of the wafer substrate WAF are not particularly limited.

[0123] As shown in Fig. 9, the epitaxial thin film EPIL may include a second semiconductor layer SEM2, an active layer MQW, and a first semiconductor layer SEM1 arranged in sequence on a wafer substrate WAF. Fig. 9 is a cross-sectional view showing a cross-sectional shape of a portion of an epitaxial wafer EWF according to one embodiment.

[0124] For example, the second semiconductor layer SEM2, the active layer MQW, and the first semiconductor layer SEM1 may be sequentially formed by epitaxial growth on the wafer substrate WAF. In one embodiment, the second semiconductor layer SEM2, the active layer MQW, and the first semiconductor layer SEM1 may be formed by epitaxial growth using a process technology such as MOCVD (Metal-organic Chemical Vapor Deposition), MOVPE (Metal-organic Vapor Phase Epitaxy), MBE (Molecular Beam Epitaxy), LPE (Liquid Phase Epitaxy), or VPE (Vapor Phase Epitaxy).

[0125] The second semiconductor layer SEM2 may be formed of the material of the second semiconductor layer SEM2 exemplified above. For example, the second semiconductor layer SEM2 may be formed of at least one nitride-based semiconductor material or phosphide-based semiconductor material, and may be formed of a single layer or multiple semiconductor layers. The second semiconductor layer SEM2 may be doped to include a second conductive type dopant (e.g., an n-type dopant).

[0126] The active layer MQW may be formed of the material of the active layer MQW exemplified above. For example, the active layer MQW may be formed of at least one nitride-based semiconductor material or phosphide-based semiconductor material. In one embodiment, a barrier layer and a quantum well layer may be alternately and / or repeatedly formed on the second semiconductor layer SEM2 to form an active layer MQW having a multiple quantum well structure.

[0127] The first semiconductor layer SEM1 may be formed of the material of the first semiconductor layer SEM1 exemplified above. For example, the first semiconductor layer SEM1 may be formed of a nitride-based semiconductor material or a phosphide-based semiconductor material and may be formed of a single layer or multiple semiconductor layers. The first semiconductor layer SEM1 may be doped to include a first conductive type dopant (e.g., a p-type dopant).

[0128] In one embodiment, when manufacturing a light emitting element LE including a contact electrode CTE as in the embodiment of Figures 4 to 6, a process of forming a contact electrode CTE (or a conductive layer for forming the contact electrode CTE) on the epitaxial thin film EPIL may be additionally performed. For example, the epitaxial wafer EWF may further include a contact electrode CTE formed on the second semiconductor layer SEM2 as illustrated in Figure 9.

[0129] The contact electrode CTE may be formed of the material of the contact electrode CTE exemplified above. The contact electrode CTE may be formed by a process such as coating (e.g., vapor deposition) of a conductive material on the epitaxial thin film EPIL, and the method of forming the contact electrode CTE is not particularly limited.

[0130] Referring to FIG. 10 in addition to FIG. 1 to FIG. 9, the epitaxial wafer EWF can be divided into wafer dies EWFD (also referred to as "epitaxial wafer dies"). (S120 in FIG. 7) As an example, the epitaxial wafer EWF can be diced to produce a number of wafer dies EWFD. FIG. 10 is a perspective view showing a schematic form of the wafer die EWFD.

[0131] The wafer die EWFD may be a smaller piece separated from the epitaxial wafer EWF, and the cross-sectional structure may be substantially the same as the cross-sectional structure of the epitaxial wafer EWF. For example, each wafer die EWFD may include a wafer substrate (for example, the wafer substrate WAF' in FIG. 12) (or a small piece of the wafer substrate WAF) separated into a smaller size and an epitaxial thin film EPIL separated into a smaller size. Hereinafter, the small piece of the separated epitaxial thin film EPIL is referred to as an "epitaxial die". For example, the wafer die EWFD may include each wafer substrate WAF' and each epitaxial die separated from the epitaxial wafer EWF.

[0132] Each of the wafer dies EWFD may or may not include a contact electrode CTE depending on the embodiment. For convenience, the contact electrode CTE is omitted in FIGS.

[0133] In one embodiment, each of the wafer dies EWFD may have a size (for example, an area corresponding to the area of ​​each cell region) corresponding to the area of ​​each cell region of a backplane substrate (for example, a backplane mother substrate divided into backplane substrates 110 of each display panel 100) including a plurality of cell regions for forming a plurality of display panels 100. For example, by dividing an epitaxial wafer EWF into a size corresponding to the area of ​​each cell region in a backplane substrate including a plurality of cell regions, a wafer die EWFD having a size corresponding to the area of ​​each cell region may be manufactured. In one embodiment, each of the wafer dies EWFD may have a size equal to or larger than the area of ​​a display area DA located in each cell region.

[0134] In one embodiment, after dividing the epitaxial wafer EWF into wafer dies EWFD, each wafer die EWFD may be evaluated (e.g., a quality test) to select a good product. The wafer die EWFD selected as a good product may be used to form a light emitting element LE in each cell region by a subsequent process.

[0135] Referring to FIG. 11 in addition to FIGS. 1-10, a carrier substrate CWAF can be provided (S130 in FIG. 7).

[0136] The carrier substrate CWAF may have a size and / or a shape corresponding to a backplane substrate including a plurality of cell regions (for example, the backplane substrate 110′ of FIG. 15 to FIG. 22 divided into the backplane substrates 110 of each display panel 100, also referred to as a “backplane mother substrate”). For example, the carrier substrate CWAF may be a wafer substrate having a size corresponding to the area of ​​the backplane substrate (for example, an area corresponding to the area of ​​the backplane substrate) and a shape corresponding to the shape of the backplane substrate so that the wafer die EWFD can be arranged on the cell regions in the backplane substrate used to simultaneously manufacture a plurality of display panels 100. In one embodiment, when a pixel process or the like for the display panel 100 is to be performed on a backplane substrate including a plurality of cell regions formed on a circular semiconductor substrate having a diameter of 12 inches and divided into the backplane substrates 110 of each display panel 100, a circular carrier substrate CWAF having a diameter of approximately 12 inches may be prepared. The carrier substrate CWAF may include a cell region CELAc corresponding to the cell region of the backplane substrate.

[0137] In one embodiment, an adhesive layer ADH may be provided and / or formed on one side of the carrier substrate CWAF, which is used to bond the wafer die EWFD and the carrier substrate CWAF in a subsequent process.

[0138] In an embodiment, the adhesive layer ADH may be formed of a material suitable for a process method applied in a process of separating the wafer die EWFD (or the epitaxial die EPID of the wafer die EWFD) from the carrier substrate CWAF. For example, when the epitaxial die EPID is to be separated from the carrier substrate CWAF by a laser lift off (LLO) method, the adhesive layer ADH may be formed of a material that can easily separate the epitaxial die EPID from the carrier substrate CWAF by the LLO method. For example, when the adhesive layer ADH is formed of a material that can be weakened by sensitively reacting to a laser, such as a thermoplastic adhesive, a thermally decomposable adhesive, or an incompletely cured adhesive, the epitaxial die EPID and the carrier substrate CWAF may be easily separated by the LLO method. The method of separating the epitaxial die EPID from the carrier substrate CWAF is not limited to the LLO method, and the adhesive layer ADH may be formed of a material suitable for the selected separation method.

[0139] In the embodiment, a wafer die EWFD (or epitaxial die EPID) is first manufactured to a size corresponding to the cell region CELA, transferred to a carrier substrate CWAF, and the epitaxial die EPID of the wafer die EWFD is bonded to a backplane substrate, and then each epitaxial die EPID can be patterned into a light emitting element LE of a finer size by an etching process or the like. Therefore, restrictions on process methods and materials (for example, adhesives) used therein that can be utilized in each process for bonding and separating the epitaxial die EPID from the carrier substrate CWAF are reduced, and the range of selection is widened. Therefore, the adhesive layer ADH can be formed from various materials.

[0140] Referring to FIG. 12 in addition to FIGS. 1-11, the wafer die EWFD may be transferred to the carrier substrate CWAF (S140 in FIG. 7).

[0141] The wafer die EWFD may be transferred to the carrier substrate CWAF at positions and / or intervals corresponding to the cell regions of the backplane substrate. For example, as shown in FIG. 12, the wafer die EWFD may be aligned on one side of the carrier substrate CWAF to be located in each cell region CELAc of the carrier substrate CWAF. In one embodiment, the wafer die EWFD may be bonded to the carrier substrate CWAF by an adhesive layer ADH. In one embodiment, the wafer die EWFD may undergo an evaluation step before being transferred to the carrier substrate CWAF, and only the wafer die EWFDs selected as non-defective may be transferred to the carrier substrate CWAF.

[0142] Referring to FIG. 13 in addition to FIGS. 1 to 12, after the wafer die EWFD is transferred to the carrier substrate CWAF, a filler FIL application and planarization process may be performed (S150 in FIG. 7).

[0143] For example, the gaps between the wafer dies EWFDs can be filled by applying a filler FIL onto the carrier substrate CWAF on which the wafer dies EWFDs are provided, and the top surface of the carrier substrate CWAF on which the wafer dies EWFDs and the filler FILs are provided can be planarized. In one embodiment, the planarization process can be performed by a polishing process such as a CMP (Chemical Mechanical Polishing) process, but the method of planarizing the top surface of the carrier substrate CWAF is not limited thereto. For example, the top surface of the carrier substrate CWAF can also be planarized by an etching process or the like.

[0144] In the process of planarizing the top surface of the carrier substrate CWAF, each wafer substrate WAF' may be removed from the wafer die EWFD. Therefore, the epitaxial die EPID may be exposed. For example, a planarization process may be performed on the carrier substrate CWAF provided with the wafer die EWFD to expose the top surface of the epitaxial die EPID. The filler FIL may remain on one side of the carrier substrate CWAF in a form filled in the gaps between the epitaxial dies EPID.

[0145] In an embodiment, a wafer die EWFD of a size corresponding to the cell area CELA is transferred to a carrier substrate CWAF and the top surface of the carrier substrate CWAF is planarized, thereby making it possible to facilitate and / or simplify the planarization process compared to the comparative example planarization process in which the wafer die EWFD (or epitaxial die EPID) is etched to a fine size corresponding to the light-emitting element LE, and to prevent or minimize defects that may occur during the manufacturing process of the light-emitting element LE.

[0146] Referring to FIG. 14 in addition to FIGS. 1-13, a bonding material may be applied onto the epitaxial die EPID (S160 of FIG. 7).

[0147] For example, a conductive bonding layer BDL can be formed on the epitaxial die EPID and the filler FIL by blanket-spreading a conductive bonding material on the top surface of the carrier substrate CWAF on which the epitaxial die EPID is exposed. As an example, the conductive bonding layer BDL can be formed by blanket-spreading (for example, vapor-depositing) gold (Au), copper (Cu), aluminum (Al), tin (Sn), or other bonding metal on the top surface of the carrier substrate CWAF.

[0148] 1 to 14, and further referring to Fig. 15 and Fig. 16, a backplane substrate 110' including a number of cell areas CELA may be provided (S170 in Fig. 7). Fig. 15 is a cross-sectional view showing a schematic configuration of the backplane substrate 110', and Fig. 16 is a cross-sectional view showing each cell area CELA of the backplane substrate 110'.

[0149] Each of the cell regions CELA of the backplane substrate 110' may include a light-emitting region EA in which a light-emitting element LE is formed. The backplane substrate 110' may include a pixel electrode PXE provided in the light-emitting region EA located in each of the cell regions CELA. For example, the backplane substrate 110' may include a pixel electrode PXE provided in the light-emitting region EA of each of the cell regions CELA, a pixel circuit PXC connected to each pixel electrode PXE, a first bonding electrode BOE1 disposed on each pixel electrode PXE, a first insulating layer INS1 disposed around the pixel electrode PXE, and / or a second insulating layer INS2 disposed around the first bonding electrode BOE1. The cell region CELA of the backplane substrate 110' may be later divided into the backplane substrate 110 of the display panel 100.

[0150] The step of providing the backplane substrate 110' can be performed independently of the steps of fabricating the wafer die EWFD and / or providing the carrier substrate CWAF, for example, the step of providing the backplane substrate 110' can be performed simultaneously with the steps of fabricating the wafer die EWFD and / or providing the carrier substrate CWAF, or can be performed before or after the steps of fabricating the wafer die EWFD and / or providing the carrier substrate CWAF.

[0151] Referring to FIG. 17 in addition to FIGS. 1-16, an epitaxial die EPID may be bonded onto a backplane substrate 110' (S180 in FIG. 7).

[0152] For example, the epitaxial die EPID may be aligned to be located in each cell area CELA of the backplane substrate 110', and the carrier substrate CWAF may be disposed on the backplane substrate 110', and the carrier substrate CWAF and the backplane substrate 110' may be bonded using a conductive bonding layer BDL. Thus, the epitaxial die EPID may be bonded on each cell area CELA of the backplane substrate 110'. The epitaxial die EPID may be bonded on the pixel electrode PXE and the first bonding electrode BOE1 located in the light emitting area EA of each cell area CELA.

[0153] In one embodiment, the backplane substrate 110' and the carrier substrate CWAF may each have an align key. Therefore, the backplane substrate 110' and the carrier substrate CWAF may be easily and / or appropriately aligned and bonded to each other. For example, the epitaxial die EPID of the carrier substrate CWAF may be aligned with the display area DA defined in the cell area CELA of the backplane substrate 110' and bonded onto the backplane substrate 110'.

[0154] In one embodiment, the epitaxial die EPID may be bonded on the first bonding electrode BOE1 of the backplane substrate 110' by a bonding process between the backplane substrate 110' and the carrier substrate CWAF using a transient liquid phase (TLP) bonding method or a thermal compression (TC) bonding method. By bonding the epitaxial die EPID on the backplane substrate 110' using the TLP bonding method or the TC bonding method, electrical resistance between the epitaxial die EPID and the backplane substrate 110' (for example, the first bonding electrode BOE1 on the backplane substrate 110') may be reduced or minimized, and the performance and stability of the light emitting element LE formed from the epitaxial die EPID in a subsequent process may be ensured. The bonding (or adhesion) method between the backplane substrate 110' and the carrier substrate CWAF is not limited thereto, and the backplane substrate 110' and the carrier substrate CWAF may be bonded by other methods.

[0155] 18 and 19 in addition to FIGS. 1 through 17, the carrier substrate CWAF may be removed over the epitaxial die EPID (S190 in FIG. 7).

[0156] For example, the carrier substrate CWAF and the adhesive layer ADH can be removed from the epitaxial die EPID bonded to the first bonding electrode BOE1 (or pixel electrode PXE) of the backplane substrate 110'. In one embodiment, the carrier substrate CWAF can be easily and / or appropriately removed from the epitaxial die EPID by a laser lift off (LLO) method. When the carrier substrate CWAF is separated using the LLO method, damage to the epitaxial die EPID can be prevented or minimized, and the reliability of the light emitting element LE formed from the epitaxial die EPID in a subsequent process can be ensured.

[0157] However, the method of removing or separating the carrier substrate CWAF is not limited thereto, and the carrier substrate CWAF may be removed by other methods. For example, the carrier substrate CWAF may be removed by a polishing process such as a CMP process or an etching process.

[0158] Referring to FIG. 20 in addition to FIGS. 1 to 19, the light emitting device LE can be formed (S200 of FIG. 7).

[0159] For example, the epitaxial die EPID may be etched to form the light emitting element LE in the light emitting area EA included in each cell area CELA. The light emitting element LE may be formed on the pixel electrode PXE and the first bonding electrode BOE1 located in each light emitting area EA.

[0160] Also, the conductive bonding layer BDL may be etched to form the second bonding electrode BOE2 between the first bonding electrode BOE1 and the light emitting element LE. In one embodiment, the light emitting element LE and the second bonding electrode BOE2 may be formed to have a size and / or a shape corresponding to the pixel electrode PXE and / or the first bonding electrode BOE1. For example, the light emitting element LE and the second bonding electrode BOE2 may be formed to have an area corresponding to the area of ​​the pixel electrode PXE and the first bonding electrode BOE1 and to have a planar shape according to the planar shapes of the pixel electrode PXE and the first bonding electrode BOE1. However, the embodiment is not limited thereto, and the size and shape of the light emitting element LE and the second bonding electrode BOE2 may be variously changed according to the embodiment.

[0161] 1 to 20, and further referring to FIGS. 21 and 22, a process for forming the common electrode CME and subsequent processes for forming the light emitting device layer 120 may be performed (S210 of FIG. 7).

[0162] For example, as shown in Fig. 21, an organic layer ORL can be formed between the light-emitting elements LE in each cell region CELA. As an example, the organic layer ORL can be embedded between the light-emitting elements LE at least in the display region DA. Then, as shown in Fig. 22, a common electrode CME and a third insulating layer INS3 can be sequentially formed on the light-emitting elements LE in each cell region CELA.

[0163] In one embodiment, when manufacturing a display panel 100 including a light conversion layer and / or a color filter layer, a process of forming a light conversion layer and / or a color filter layer on top of the light emitting element layer 120 or inside the light emitting element layer 120 may be additionally performed.

[0164] In one embodiment, when manufacturing a display panel 100 including a lens-type optical structure LS as shown in FIG. 3, a process of attaching and / or forming the lens-type optical structure LS and a protective layer PSV on the light-emitting element layer 120 may be additionally performed.

[0165] When the substantial manufacturing process of the display panel 100 is completed, a cell separation process can be performed (S220 in FIG. 7).

[0166] For example, the display panels 100 formed based on (from) one backplane substrate 110' can be separated into individual ones by cell separation. As an example, by cutting the backplane substrate 110' based on the cell area CELA, each cell located in the cell area CELA can be separated into an individual display panel 100.

[0167] Thereafter, a module process or the like may be further performed to manufacture the display device 10 including each display panel 100.

[0168] As described above, in the embodiment, the epitaxial wafer EWF is divided into cells (for example, into each cell area CELA or into a size corresponding to each cell), transferred to the carrier substrate CWAF, and the epitaxial die EPID is bonded to each cell area CELA of the backplane substrate 110', and then the epitaxial die EPID is etched in each cell area CELA to be patterned into individual light emitting elements LE. Therefore, light emitting elements LE of minute sizes can be efficiently formed in the light emitting areas EA included in each cell area CELA.

[0169] According to this embodiment, there is substantially no restriction on the size of the wafer substrate WAF used for growing the epitaxial thin film EPIL, and the efficiency of using the wafer substrate WAF can be improved. For example, the epitaxial wafer EWF can be divided into a size corresponding to the area of ​​the display area DA included in each cell area CELA (for example, the epitaxial wafer EWF can be divided into a size equal to or larger than the area of ​​the display area DA, including a process error) to manufacture the light emitting element LE. Therefore, since it is not necessary to match the size of the wafer substrate WAF to the size (for example, the area) of the backplane substrate 110', the range of choices for the wafer substrate WAF is widened, and the area of ​​the wafer substrate WAF used can be increased or maximized to reduce costs. For example, a wafer die EWFD can be manufactured using a 4-inch or 8-inch wafer substrate WAF, and the wafer die EWFD can be transferred to a 12-inch carrier substrate CWAF to form the light emitting element LE on the 12-inch backplane substrate 110'. Alternatively, a wafer substrate WAF having substantially the same size as the backplane substrate 110' (for example, 12 inches) can be used to manufacture a wafer die EWFD, and the epitaxial die EPID of the wafer die EWFD can be used to form a light-emitting element LE.

[0170] In addition, by aligning and bonding each epitaxial die EPID on each cell area CELA of the backplane substrate 110' in cell units, and then patterning the epitaxial die EPID into a light emitting element LE, the difficulty of the panel process for manufacturing the display panel 100 can be reduced and alignment errors can be prevented or reduced. For example, during the bonding process, high-precision alignment according to the minute pixels PX and / or light emitting areas EA is not required, and after bonding the epitaxial die EPID on the backplane substrate 110', each light emitting element LE is formed in the light emitting area EA by an etching process or the like, so that the light emitting element LE can be easily and / or stably formed at an appropriate position. As a result, the process efficiency of the display panel 100 and the display device 10 including the same can be increased and the yield can be improved.

[0171] FIG. 23 is an exemplary diagram showing a virtual reality device 1 including a display device 10_1 according to an embodiment.

[0172] 23, the virtual reality device 1 according to an embodiment may be a device in the form of glasses. The virtual reality device 1 according to an embodiment may include a display device 10_1, a left eye lens 10a, a right eye lens 10b, a support frame 20, temples 30a and 30b, a reflective member 40, and a display device housing 50.

[0173] 23 illustrates a virtual reality device 1 including temples 30a and 30b, but the virtual reality device 1 according to an embodiment may also be applied to a head mounted display including a head mounting band that can be worn on the head instead of temples 30a and 30b. For example, the virtual reality device 1 according to an embodiment is not limited to the form shown in FIG 23 and may be applied in various forms in various other electronic devices.

[0174] The display device housing 50 may include a display device 10_1 and a reflective member 40. An image displayed on the display device 10_1 may be reflected by the reflective member 40 and provided to the right eye of the user through the right eye lens 10b. This allows the user to view the virtual reality image displayed on the display device 10_1 through the right eye.

[0175] 23 illustrates an example in which the display device storage unit 50 is disposed at the right end of the support frame 20, but the embodiment is not limited thereto. For example, the display device storage unit 50 may be disposed at the left end of the support frame 20, in which case the image displayed on the display device 10_1 may be reflected by the reflecting member 40 and provided to the left eye of the user through the left eye lens 10a. This allows the user to view the virtual reality image displayed on the display device 10_1 through the left eye. Alternatively, the display device storage unit 50 may be disposed at both the left and right ends of the support frame 20, in which case the user may view the virtual reality image displayed on the display device 10_1 through both the left and right eyes.

[0176] FIG. 24 is an exemplary diagram showing a smart device including a display device 10_2 according to an embodiment.

[0177] Referring to FIG. 24, the display device 10_2 according to an embodiment can be applied to a smart watch 2, which is one of smart devices. The planar shape of the clock display unit of the smart watch 2 may follow the planar shape of the display device 10_2. For example, when the display device 10_2 according to an embodiment has a circular or elliptical planar shape, the clock display unit of the smart watch 2 may have a circular or elliptical planar shape. Or, when the display device 10_2 according to an embodiment has a rectangular planar shape, the clock display unit of the smart watch 2 may have a rectangular planar shape. However, the embodiment is not limited thereto, and the clock display unit of the smart watch 2 does not have to follow the planar shape of the display device 10_2.

[0178] 25 is an exemplary view showing a vehicle dashboard and a center fascia including display devices 10_a, 10_b, 10_c, 10_d, and 10_e according to an embodiment of the present invention. In FIG. 25, a vehicle to which the display devices 10_a, 10_b, 10_c, 10_d, and 10_e according to an embodiment of the present invention are applied is shown.

[0179] 25, the display devices 10_a, 10_b, and 10_c according to an embodiment may be applied to a vehicle instrument panel, a center fascia, or a CID (Center Information Display) arranged on a dashboard of a vehicle. Alternatively, the display devices 10_d and 10_e according to an embodiment may be applied to a Room Mirror Display replacing a side mirror of a vehicle.

[0180] FIG. 26 is an exemplary view showing a transparent display device including a display device 10_3 according to an embodiment.

[0181] Referring to FIG. 26, the display device 10_3 according to an embodiment can be applied to a transparent display device. The transparent display device can display an image IM and transmit light at the same time. Therefore, a user positioned in front of the transparent display device can not only view the image IM displayed on the display device 10_3, but also view an object RS or a background positioned behind the transparent display device. When the display device 10_3 is applied to a transparent display device, the display panel 100 can include a light-transmitting portion that transmits light, or can be formed on a substrate member made of a material that transmits light.

[0182] Although the embodiment of the present invention has been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical idea or essential features of the present invention. Therefore, it should be understood that the above embodiment is illustrative in all respects and is not limiting.

[0183] According to one preferred specific embodiment, it is as follows.

[0184] The background and objectives of this case are as follows (i) to (vii).

[0185] (i) Display panels with an array of micro LEDs are being considered for use in transparent displays, etc. For example, they are being considered for use as display panels that are attached to or formed integrally with glasses, vehicle front glass (windshield), window glass, etc.

[0186] (ii) To manufacture a display panel with an array of micro LEDs, a laminate film for forming the micro LED elements is formed on a semiconductor substrate such as a silicon wafer, in particular by epitaxial growth, and the semiconductor substrate after the laminate film formation is then diced to separate the semiconductor substrate into small pieces ("wafer dies" (EWFD)) that correspond to each pixel.

[0187] (iii) On the other hand, a "backplane substrate (110)" is formed on which a pixel circuit is formed for each pixel.

[0188] (iv) In order to arrange the semiconductor substrate pieces ("wafer dies" (EWFD)) on the "backplane substrate (110)", they are arranged on a carrier substrate (CWAF) and then the gaps between the semiconductor substrate pieces ("wafer dies" (EWFD)) are filled with a gap filler.

[0189] (v) Then, on this carrier substrate (CWAF), the film stack on the semiconductor substrate piece ("wafer die" (EWFD)) is patterned to form micro LEDs for each pixel.

[0190] (vi) Here, after the laminated film was patterned to form a micro LED substrate, it was attached to a “backplane substrate (110)” and then the carrier substrate (CWAF) was peeled off.

[0191] (vii) However, such conventional manufacturing methods have limitations in terms of improving manufacturing efficiency, as they require surface planarization using techniques such as chemical mechanical polishing (CMP) before and after the patterning process to form micro-LEDs.

[0192] Therefore, according to one embodiment, A1 to A4 or A1 to A5 are as follows.

[0193] A1 Semiconductor substrate pieces ("wafer dies" (EWFD)) are arranged on a carrier substrate (CWAF) via an adhesive layer ADH, and then the gaps are filled with a gap filler (organic film ORL), followed by planarization (CMP). (Figures 11-13)

[0194] A2 Following planarization (CMP), a conductive bonding layer (BDL) is formed, which is made of a metal material with relatively low hardness, such as gold (Au), copper (Cu), aluminum (Al), or tin (Sn). (Figure 14)

[0195] A3: Attach it to the "backplane substrate (110)" via the "conductive bonding layer (BDL)". (Figures 16-17)

[0196] A4 After this attachment, the carrier substrate (CWAF) is peeled off, and then patterning to form the micro LED element and formation of the common electrode (CME) are performed (Figures 17 to 22).

[0197] A5 After patterning on the mother substrate and forming electrodes and wiring, the individual display panels are cut out and separated. [Explanation of symbols]

[0198] 10 Display device 100 Display Panel 110,110' backplane board 120 Light emitting element layer BDL Conductive Bonding Layer BOE1 First bonding electrode BOE2 Second bonding electrode CELA, CELAc Cell Area CME common electrode CWAF Carrier Board EA Light Emitting Area EPID Epitaxial Die EPIL Epitaxial Thin Film EWF epitaxial wafer EWFD Wafer Die FIL Filler LE Light Emitting Element LS Lens-type optical structure PXE pixel electrode WAF,WAF' wafer substrate

Claims

1. fabricating an epitaxial wafer including an epitaxial thin film; Dividing the epitaxial wafer into wafer dies having a size corresponding to an area of ​​each cell region in a backplane substrate including the arrayed cell regions; transferring the wafer die to a carrier substrate; forming a conductive bonding layer on an epitaxial die of the wafer die; placing the carrier substrate on the backplane substrate such that the epitaxial die are located in respective cell regions of the backplane substrate, and bonding the epitaxial die onto the backplane substrate; removing the carrier substrate from over the epitaxial die; and Etching the epitaxial die to form respective light emitting devices in light emitting regions included in each of the cell regions.

2. The method of claim 1 , wherein the carrier substrate has a size corresponding to an area of ​​the backplane substrate, and includes a cell area corresponding to the cell area of ​​the backplane substrate.

3. The method of claim 2 , wherein transferring the wafer dies to the carrier substrate comprises aligning the wafer dies with respective cell areas of the carrier substrate.

4. The method of claim 1 , wherein the wafer dies are fabricated to include respective wafer substrates and respective epitaxial dies separated from the epitaxial wafer.

5. 5. The method for manufacturing a display device according to claim 4, further comprising the steps of: applying a filler onto the carrier substrate on which the wafer dies are provided, to fill gaps between the wafer dies, and planarizing an upper surface of the carrier substrate on which the wafer dies and the filler are provided, after transferring the wafer dies to the carrier substrate and before forming the conductive bonding layer.

6. planarizing a top surface of the carrier substrate to remove the respective wafer substrate from the wafer die to expose the epitaxial die; The method of claim 5 , further comprising applying a conductive bonding material onto the upper surface of the carrier substrate on which the epitaxial die is exposed to form the conductive bonding layer.

7. The method further includes evaluating the wafer dies to select good products before transferring the wafer dies to a carrier substrate; The method for manufacturing a display device according to claim 1 , further comprising transferring the wafer die selected as a non-defective product onto the carrier substrate.

8. The method of claim 1 , wherein the backplane substrate includes pixel electrodes provided individually in the light-emitting areas of the cell regions.

9. The method of claim 8 , wherein the step of etching the epitaxial die forms each of the light emitting elements on the pixel electrodes.

10. The method of claim 8 , wherein the backplane substrate further comprises a first bonding electrode disposed on the pixel electrode.

11. 11. The method of claim 10, wherein in bonding the carrier substrate and the backplane substrate, the epitaxial die is bonded onto the first bonding electrode by a Transient Liquid Phase (TLP) bonding method or a Thermal Compression (TC) bonding method.

12. The method of claim 10, further comprising: etching the conductive bonding layer to form a second bonding electrode between the first bonding electrode and the light emitting element.

13. The method of claim 1 , wherein in the removing of the carrier substrate, the carrier substrate is removed from the epitaxial die by a Laser Lift Off (LLO) method.

14. The method of claim 1 , further comprising forming a common electrode on the light emitting device in each of the cell regions.

15. The method of claim 14 , further comprising forming a lens-type optical structure on a light emitting device layer including the light emitting device and the common electrode.

16. The method of claim 1 , further comprising: separating each cell corresponding to the cell region into an individual display panel by cutting the backplane substrate based on the cell region.

17. providing a backplane substrate including cell regions and pixel electrodes provided in light-emitting regions located in each of the cell regions; fabricating a wafer die having a size corresponding to each of the cell areas and including a respective epitaxial die; providing a carrier substrate having a size corresponding to the backplane substrate and including a cell area corresponding to the cell area of ​​the backplane substrate; transferring the wafer die to the carrier substrate; planarizing a top surface of the carrier substrate to expose the epitaxial die of the wafer die and forming a conductive bonding layer on the epitaxial die; bonding the epitaxial die onto the pixel electrode using the conductive bonding layer; and The method includes etching the epitaxial die to form respective light emitting elements on the pixel electrodes.

18. The method of claim 17 , wherein transferring the wafer dies to the carrier substrate comprises aligning the wafer dies to respective cell areas of the carrier substrate.

19. The backplane substrate further includes a first bonding electrode disposed on the pixel electrode; 20. The method of claim 17, wherein the epitaxial die is bonded onto the first bonding electrode by a TLP (Transient Liquid Phase) bonding method or a TC (Thermal Compression) bonding method.

20. 20. The method of claim 19, further comprising: etching the conductive bonding layer to form a second bonding electrode between the first bonding electrode and the light emitting element.

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