Method for building module

Abstract

To provide a method for building modules.SOLUTION: A method (100) for building modules (30) which are each provided with at least two electronic components (50). The method includes: Step (101) of defining a removal pattern that specifies a specific removal path (60) for component positions on at least one wafer (40) on which the components (50) for building the modules are provided; Step (102) of initiating a removal process in which the components (50) are removed from the at least one wafer (40) along the removal path (60); and Step (103) of initiating a building process in which the modules (30) are provided with the removed components (50). The removal path (60) is defined taking into account at least one correlation of electrical properties of the components (50) and the component positions on the at least one wafer (40).SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a method for constructing modules each provided with at least two electronic components, and furthermore to a computer program, an apparatus and a system for this purpose. [Background technology]

[0002] It is known from the prior art that a picking pattern can be used to optimize the chip removal procedure during the manufacture of symmetrical modules, where for example a die bonder machine is used to automatically remove chips from a wafer in a pick-and-place process and insert them into a given module, where the picking pattern defines for example the order and orientation of the chips in the pick-and-place process, where a symmetrical module can be an assembly or a component with similar chips. Summary of the Invention

[0003] After wafer fabrication, chips are typically picked from the wafer and assembled into modules, but the wafer fabrication processes (e.g., slicing, polishing, lithography, etching, etc.) often cause chip-related degradation.

[0004] The subject of the present invention is a method having the features of claim 1, a computer program having the features of claim 9, an apparatus having the features of claim 10 and a system having the features of claim 11. Further features and details of the invention emerge from the respective dependent claims, the description and the drawings. Features and details stated here in relation to the method according to the invention naturally also apply in relation to the computer program according to the invention, the apparatus according to the invention and the system according to the invention and vice versa, respectively, and therefore are or can always be cross-referenced with respect to the disclosure of the individual aspects of the invention.

[0005] The subject of the invention is in particular a method for constructing modules, each of which is provided with at least two electronic components, in particular semiconductor components, preferably power semiconductors. The modules can be, for example, power modules and the components can correspondingly be semiconductors, such as power semiconductors (for example MOSFETs). These modules can be used, for example, in inverters with a number of power modules.

[0006] Basically, one goal may be to reduce the size of the components (hereafter also referred to as chips). However, with the reduction of chip size comes an increase in temperature, and therefore this optimization goal is limited by temperature changes in the module. That is, components on the module may affect the performance of the module, for example due to the effect of temperature changes. In particular, here, the more dissimilar the components mounted on the module are, the more likely they are to generate higher temperatures. Here, it may be useful to artificially optimize the takeout pattern in order to select components with similar electrical properties.

[0007] First, according to a first method step of the method according to the invention, a removal pattern can be defined, which defines a unique removal path for component positions on at least one wafer, on which components are manufactured and / or provided for the construction of the module. For example, the removal path can be stored digitally to be called up, in particular during an automated removal process. Based on the removal path, for example, a control command for at least one motor can be generated. The removal process can then be started according to further method steps. Here, the components can be removed from the at least one wafer along the removal path, in particular automatically.

[0008] The method according to the invention comprises a further method step by which a building process can be started (possibly also proceeding automatically), in which the removed parts are provided in a module. This step can also be carried out automatically.

[0009] According to the invention, it can be envisaged that the take-out path is defined taking into account at least one correlation between the electrical characteristics of the components and the component position on at least one wafer. As electrical characteristics, parameters such as RDSON, threshold voltage VTH and / or QGD can be taken into account. RDS(ON) can mean in particular the "drain-source on resistance" and can indicate the resistance between the drain and the source of a metal oxide semiconductor field effect transistor (MOSFET) in the on-state. QGD can mean in particular the "gate-drain charge" and can indicate the charge transferred between the gate and the drain of a metal oxide semiconductor field effect transistor (MOSFET) or similar transistor type during a switching procedure. The electrical characteristics can be specific, for example with respect to switching losses and conduction losses. Here, the invention is based in particular on the recognition that since the components are similar, the switching losses are also more similar. This is advantageous in many cases. On the other hand, the greater the differences between the components, the worse the operation of the module may be due to temperature changes. In particular, the take-out path can be defined in such a way that the modules are provided with similar components so that the temperature can be reduced during the operation of the modules.

[0010] Furthermore, within the scope of the present invention, the pick-up path can be considered as being defined as a path going in alternating opposite directions and defining a continuous and / or repetitive and / or zigzag-shaped and / or sawtooth-shaped trajectory on at least one wafer. In other words, by defining the pick-up path as a path going in alternating opposite directions, the pick-up path can be defined taking into account at least one correlation between the electrical properties of the components and the component positions on at least one wafer. This has the advantage that, with such a defined pick-up path, the components that are successively picked during the pick-up process have similar electrical properties, possibly even during the transition between the two wafers. Thus, electrically similar components are provided in the module, and a temperature optimization can be achieved during the operation of the module. Here, the pick-up pattern, i.e. the picking pattern, can also have the effect that possible error zones on the wafer are taken into account, thus ensuring that only the highest quality chips are selected for assembly.

[0011] Furthermore, within the scope of the present invention, it may be advantageous for the removal path to be defined as a path proceeding in a circular manner from an outer component location to an inner component location of the at least one wafer, defining a continuous and / or spiral-shaped trajectory on the at least one wafer, whereby it is possible to define the removal path taking into account at least one correlation between electrical characteristics of the components and component locations on the at least one wafer, such that components successively removed in the removal process have similar electrical characteristics.

[0012] Within the scope of the present invention, it can be envisaged that the removal path is defined as a path that includes a turn when a transition (from a current wafer) to a subsequent wafer is envisaged during removal, thereby making it possible to define the removal path taking into account at least one correlation between the electrical characteristics of the components and their position on at least one wafer, such that the components successively removed in the removal process have similar electrical characteristics even when transitioning between wafers.

[0013] In a further possible embodiment, the removal path is defined as a path proceeding in a circle with several turns on each wafer, and it is possible to define a continuous semi-spiral shaped trajectory on at least one wafer, again allowing the removal path to be defined taking into account at least one correlation between the electrical characteristics of the components and the component positions on at least one wafer, so that the components successively removed in the removal process have similar electrical characteristics.

[0014] Furthermore, within the scope of the present invention, at the start of the removal process: - removing parts from the current wafer along a removal path until removal of parts for the current wafer is completed; - performing a transition from a current wafer to a subsequent wafer; - removing components from subsequent wafers along a removal path until removal of components for the subsequent wafer is completed. It may be envisaged that the process may be started repeatedly.

[0015] Here, a pick path can be defined as a path where picking of a component ends after completion of picking at the same component location for a current wafer as the component location where picking continues for a subsequent wafer, again making it possible to exploit correlations between electrical properties of the components and their location on at least one wafer.

[0016] Furthermore, it is advantageous within the scope of the present invention if a removal machine, for example in the form of a die bonder device, is controlled for the removal of the components along the removal path. Alternatively or additionally, the electronic components may be designed as semiconductor components, preferably power semiconductors, with at least three components being mounted in each module. These components can thus form a functional structure, for example for power electronics, which is optimized by the removal pattern according to the invention.

[0017] The subject of the invention is also a system for building a module provided with at least two electronic components. The system can comprise a device for defining a pick-up pattern, where, as in the method according to the invention, the pick-up pattern can define a unique pick-up path for the component locations on at least one wafer. In the system according to the invention, the components can be provided on at least one wafer for building the module. Furthermore, the system according to the invention can comprise a pick-up machine for picking the components from the at least one wafer in a pick-up process.

[0018] According to the invention, it can be provided that in the removal process the components are removed along a removal path, the removal path being defined taking into account at least one correlation between the electrical properties of the components and the component positions on at least one wafer. The system according to the invention thus provides the same advantages as detailed with reference to the method according to the invention. Furthermore, the device can also be designed as a device for data processing according to the invention.

[0019] A subject of the invention is likewise a computer program, in particular a computer program product, comprising instructions which cause a computer to carry out the method according to the invention when the computer program is executed by a computer. The computer program according to the invention therefore offers the same advantages as those detailed with reference to the method according to the invention.

[0020] The subject of the invention may also be an apparatus for data processing, designed to carry out the method according to the invention. As an apparatus, for example, a computer for executing the computer program according to the invention may be considered. The computer may comprise at least one processor for executing the computer program. A non-volatile data memory may also be considered, in which the computer program is stored and from which the processor can read and execute the computer program.

[0021] Likewise, a subject of the invention may also be a computer-readable storage medium which is part of the system according to the invention and / or which comprises a computer program according to the invention and / or which contains instructions which, when executed by a computer, cause the computer to carry out the method according to the invention. The storage medium is for example configured as a data memory, such as a hard disk and / or a non-volatile memory and / or a memory card. The storage medium may for example be integrated into the computer.

[0022] The steps of the method according to the invention can be performed iteratively and / or automatically and / or with computer assistance, wherein the method can also be performed as a computer-implemented method.

[0023] Further advantages, features and details of the invention emerge from the following description, in which exemplary embodiments of the invention are described in detail with reference to the drawings. The features claimed and described in this specification may be of importance to the invention individually or in any combination. [Brief description of the drawings]

[0024] [Figure 1] 1 is a schematic diagram of a method, a system, a storage medium, and a computer program according to an exemplary embodiment of the present invention. [Diagram 2] FIG. 13 is a schematic diagram of the temperature distribution for a manufactured module. [Diagram 3] FIG. 13 shows a zigzag extraction pattern. [Figure 4] FIG. 1 illustrates a take-off pattern according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] In Fig. 1, a system 1 is shown in a schematic manner, comprising an apparatus 10, a storage medium 15 and a computer program 20 according to an exemplary embodiment of the invention. Furthermore, Fig. 1 shows a method 100 for building a module 30, each provided with at least two electronic components 50, in particular semiconductor components, preferably power semiconductors, according to an exemplary embodiment of the invention. First, according to a first method step 101, a removal pattern, also called a picking pattern, can be defined, which defines a unique removal path 60 for the component positions on at least one wafer 40, on which the components 50 were manufactured and provided for the building of the module 30 (see Fig. 4, in which an exemplary removal path 60 is shown). Then, according to a second method step 102, a removal process can be started, in which the components 50 are removed from the at least one wafer 40 along the removal path 60. Furthermore, according to a third method step 103, a building process can be started, in which the removed components 50 are provided, for example mounted, in the module 30. Here, it can be contemplated that the take-out path 60 is defined taking into account at least one correlation between the electrical characteristics of the components 50 and the component positions on at least one wafer 40 .

[0026] 1 also shows a system 1 for building a module 30 according to an alternative embodiment of the invention. The system 1 may include an apparatus 10 for defining 101 a pick-up pattern and a pick-up machine 70 for picking up parts 50 from at least one wafer 40 in a pick-up process. In other words, the system 1 may be designed to perform a method 100 according to the invention.

[0027] The present invention is based in particular on the observation that it should not be simply assumed that adjacent components 50 (hereafter also referred to as chips) have uncorrelated characteristics. Instead, statistics and patterns found in on-wafer measurement data can be used to define a picking approach, thereby reducing tolerances within a module. jAn exemplary graph is shown in which T is plotted against the number of modules 30. j Value and large T j The distribution of values ​​shows decreasing numbers and increasing costs. In particular, the extreme values ​​of this distribution lead to significant cost increases and should therefore be minimized. Additionally, at 201, the tip limit is shown as a limit value.

[0028] According to the invention, an improved picking pattern for the wafer can be proposed. In Fig. 3 an exemplary measurement of a quality parameter of a chip as a function of the chip's position on the wafer is shown. Here, curve 301 can represent a quality parameter of the manufactured chip, i.e. for example a measured quantity or characteristic. The quality parameter can thus be specific to the manufacturing process and / or the quality of the manufactured chip. This measured quantity is for example "Qgd", i.e. in particular the gate-drain charge of the chip, or R DS(ON) . Curve 302 can represent the radius on the wafer on which the chips are located. Curve 303 can represent the vertical position in a Cartesian coordinate system of the point on the wafer on which the chips are located. The correlation of the electrical characteristics, especially the quality parameters, with the position of the chips on the wafer can be clearly seen from the measurement results. Here, the measurements were performed with respect to a conventional zigzag pattern. The "zigzag pattern" in "wafer picking pattern" is in particular a prescription of an order for picking or inspecting the chips on the wafer. For example, this is a prescription that the chips are picked or inspected in a zigzag order across the wafer.

[0029] According to alternative embodiments of the invention, modifications or alternatives to the conventional zigzag pattern are proposed. Figure 4 first shows a conventional zigzag pattern 401. Instead, according to alternative embodiments of the invention, modified zigzag patterns 402 with alternating y-directions, i.e. turns, coil patterns 403 or half coil patterns 404 can be defined. Thus, taking into account the correlations mentioned above, new picking patterns (also called ejection patterns) can be defined, thus building symmetrical modules and achieving a narrower distribution and therefore also a higher performance.

[0030] In FIG. 4, in the removal pattern 402 , the removal paths 60 are defined as paths going in alternating opposite directions, defining a continuous, repeating, zigzag, or sawtooth trajectory over at least one wafer 40 .

[0031] In the removal pattern 403, the removal path 60 is defined as a path that proceeds in a circular manner from an outer component position 41 to an inner component position 42 of the at least one wafer 40, defining a continuous spiral-shaped trajectory on the at least one wafer 40.

[0032] In the pick-up pattern 404 , the pick-up path 60 is defined as a path that proceeds in a circular fashion with several turns over each wafer 40 to define a continuous semi-spiral shaped trajectory over at least one wafer 40 .

[0033] In the above description of the embodiments, the present invention is described merely by way of example. Naturally, the individual features of the embodiments can be freely combined with one another, as far as this is technically reasonable, without departing from the scope of the present invention. [Explanation of symbols]

[0034] 1 System 10 equipment 15 Storage medium 20 Computer Programs 30 Modules 40 Wafers 41 Outer part position 42 Inner part position 50 (Electronic) Parts 60 Extraction route 70 Extraction Machine 100 Methods for building modules 30 101 Steps to define take-out pattern 102 Step to start the retrieval process 103 Steps to start the building process 201 Tip Limit 301 Quality parameters of manufactured chips 302 Radius of the wafer on which the chip is mounted 303 Vertical position of the point on the wafer on which the chip is located 401 Traditional Zigzag Pattern 402 Modified ZigZag Pattern with Directional Change 403 coil pattern 404 Half coil pattern

Claims

1. A method (100) for constructing modules (30) each provided with at least two electronic components (50), comprising: - defining (101) a pick-up pattern defining a unique pick-up path (60) for component locations on at least one wafer (40) on which the components (50) are provided for said building of said module; initiating (102) a removal process in which the part (50) is removed from the at least one wafer (40) along the removal path (60); starting (103) a building process in which the removed parts (50) are provided in the module (30); In a method comprising: The take-out path (60) is defined taking into account at least one correlation between an electrical characteristic of the component (50) and the component location on the at least one wafer (40).

1. A method (100) comprising:

2. The removal paths (60) are defined as paths going in alternating opposite directions and define a continuous, repetitive, zigzag, or sawtooth trajectory on the at least one wafer (40).

2. The method (100) of claim 1 .

3. The removal path (60) is defined as a path that proceeds in a circular manner from an outer component location (41) to an inner component location (42) of the at least one wafer (40) and defines a continuous spiral-shaped trajectory on the at least one wafer.

3. The method (100) of claim 1 or 2.

4. The removal path (60) is defined as a path that includes a turn when a transition to a subsequent wafer (40) is intended during the removal. The method (100) according to any one of claims 1 to 3.

5. The removal path (60) is defined as a path that proceeds in a circular fashion with several turns on each of the wafers (40) to define a continuous semi-spiral shaped trajectory on the at least one wafer (40). The method (100) according to any one of claims 1 to 4.

6. At the start (102) of the removal process, removing said parts (50) from said current wafer (40) along said removal path (60) until said removal of said parts (50) for said current wafer (40) is completed; making a transition from the current wafer to a subsequent wafer (40); removing said parts (50) from said subsequent wafer (40) along said removal path (60) until said removal of said parts (50) for said subsequent wafer (40) is completed; is started repeatedly, The removal path (60) is defined as a path where removal of the part (50) ends after the removal is completed at the same part location for the current wafer (40) as the part location where the removal for the subsequent wafer (40) continues. The method (100) according to any one of claims 1 to 5.

7. A removal machine (70) is controlled for said removal of said parts (50) along said removal path (60). The method (100) according to any one of claims 1 to 6.

8. The electronic components (50) are designed as semiconductor components, and at least three components (50) are mounted on each of the modules (30). The method (100) according to any one of claims 1 to 7.

9. A computer program (20) comprising instructions which, when executed by a computer (10), cause the computer (10) to carry out a method (100) according to any one of claims 1 to 8.

10. An apparatus (10) for processing data, designed to carry out a method (100) according to any one of claims 1 to 8.

11. A system (1) for constructing a module (30) provided with at least two electronic components (50), comprising: an apparatus (10) for defining (101) a pick-up pattern defining a unique pick-up path (60) for component locations on at least one wafer (40) on which said components (50) are provided for said building of said module (30); a removal machine (70) for removing the component (50) from the at least one wafer (40) in a removal process in which the component (50) is removed along the removal path (60), the removal path (60) being defined taking into account at least one correlation between an electrical characteristic of the component (50) and a component position on the at least one wafer (40). System (1).

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