High-frequency circuit component

Abstract

To provide a high-frequency circuit component which allows downsizing, and which can also suppress degradation of high-frequency properties.SOLUTION: A first chip includes: a first insulating layer; a first device layer laminated on the first insulating layer; a first multilayer wiring layer laminated on the first device layer; and a first anchor. The first chip is provided with a high-frequency circuit. The second chip includes: a substrate; a second multilayer wiring layer disposed on the substrate; and a second anchor. The second chip is provided with a control circuit for controlling the high-frequency circuit. The first anchor is embedded in the first device layer and the first insulating layer, and it is exposed from the surface of the first insulating layer. The second anchor is embedded in the second multilayer wiring layer, and it is exposed from the surface of the second multilayer wiring layer. The first anchor and the second anchor are made of the same metallic material. A portion, of the first anchor, exposed from the surface of the first insulating layer and a portion, of the second anchor, exposed from the surface of the second multilayer wiring layer are connected to each other.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a high-frequency circuit component. [Background Art]

[0002] A high-frequency module in which a high-frequency switch element and a decoder element are mounted on a dielectric multilayer substrate is known (Patent Document 1). This high-frequency module is mounted on the main board of a wireless communication device such as a mobile terminal. A transmission signal from a transmission / reception system is transmitted to an antenna terminal via a high-frequency switch, and a reception signal input from the antenna terminal is transmitted to the transmission / reception system via a high-frequency switch.

Prior art documents

Patent documents

[0003]

Patent document 1

Summary of the invention

Problems to be Solved by the Invention

[0004] In addition to high-frequency modules including high-frequency switches, power amplifiers that amplify the power of transmission signals, low-noise amplifiers that amplify reception signals, and control circuits that control the power amplifiers and low-noise amplifiers are mounted on the main board of a wireless communication device. For this reason, an area for mounting these individual circuit components must be secured on the mounting surface of the main board. In order to miniaturize wireless communication devices, miniaturization of high-frequency circuit components is desired.

[0005] In addition, in order to improve the operating speed of transistors that compose low-noise amplifiers, power amplifiers, etc., a semiconductor-on-insulator (SOI) substrate may be used instead of a bulk silicon substrate. As the operating frequency of high-frequency circuits increases, the nonlinearity of the parasitic capacitance between the transistor formed in the SOI layer and the silicon substrate under the buried oxide film becomes apparent, reducing the effect of improving high-frequency characteristics.​

[0006] An object of the present invention is to provide a high-frequency circuit component capable of achieving miniaturization and further suppressing a decrease in high-frequency characteristics.

Means for Solving the Problems

[0007] According to one aspect of the present invention, a first chip including a first insulating layer, a first device layer laminated on the first insulating layer, a first multilayer wiring layer laminated on the first device layer, and a first anchor, in which a high-frequency circuit is formed; and a second chip including a substrate, a second multilayer wiring layer disposed on the substrate, and a second anchor, in which a control circuit for controlling the high-frequency circuit is formed are provided, the first anchor is embedded in the first device layer and the first insulating layer and exposed on the surface of the first insulating layer, the second anchor is embedded in the second multilayer wiring layer and exposed on the surface of the second multilayer wiring layer, the first anchor and the second anchor are formed of the same metal material, and a high-frequency circuit component is provided in which a portion of the first anchor exposed on the surface of the first insulating layer and a portion of the second anchor exposed on the surface of the second multilayer wiring layer are connected to each other.

Effects of the Invention

[0008] Since the first chip is stacked on the second chip, it is possible to miniaturize the high-frequency circuit component as compared with a configuration in which the first chip and the second chip are separately mounted on a mounting substrate. Since the first anchor exposed on the surface of the first insulating layer of the first chip is connected to the second anchor of the second chip, a support substrate for mechanically supporting the first chip individually is unnecessary. In a configuration in which the first chip includes a support substrate such as silicon, the high-frequency characteristics deteriorate due to the influence of the parasitic capacitance between the high-frequency circuit of the first chip and the support substrate. However, since the support substrate is unnecessary, a decrease in the high-frequency characteristics can be suppressed.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

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Figure 11

Best Mode for Carrying Out the Invention

[0010] [First Embodiment] Referring to the drawings from FIG. 1A to FIG. 4B, a high-frequency circuit component according to the first embodiment will be described. FIG. 1A is a schematic cross-sectional view of a high-frequency circuit component according to the first embodiment. The high-frequency circuit component according to the first embodiment includes a first chip 10 and a second chip 30. In FIG. 1A, the numbers, sizes, positional relationships, etc. of various components constituting the high-frequency circuit component, such as transistors, wirings, vias, bumps, etc., do not represent the actual numbers, sizes, and positional relationships.

[0011] The first chip 10 includes a first insulating layer 11, a first device layer 12 laminated on the first insulating layer 11, a first multilayer wiring layer 13 laminated on the first device layer 12, and a plurality of first anchors 14. The first insulating layer 11 and the first device layer 12 respectively correspond to the buried oxide film and the SOI layer of a silicon-on-insulator (SOI) substrate. That is, by removing the silicon support substrate of the SOI substrate, a laminated structure of the first insulating layer 11 and the first device layer 12 is obtained.

[0012] An element isolation region 12I is formed in a part of the first device layer 12, and an active region made of a semiconductor (e.g., silicon) surrounded by the element isolation region 12I is defined. A source region, a drain region, and a body region are formed in each of the active regions of the first device layer 12, and a gate electrode is disposed on the body region. The transistor 15 is constituted by the source region, the drain region, the body region, and the gate electrode. The transistor 15 is, for example, a MOSFET.

[0013] In the first multilayer wiring layer 13, a plurality of wirings 13W and a plurality of vias 13V are arranged. A high-frequency circuit is configured by the plurality of transistors 15, the wirings 13W and the vias 13V in the first multilayer wiring layer 13. The first anchor 14 has a columnar shape and is formed of metal. Further, the first anchor 14 is embedded in the element isolation region 12I of the first device layer 12 and the first insulating layer 11, and one end thereof is exposed on the surface of the first insulating layer 11 (the surface facing away from the first device layer 12 side). The other ends of some of the plurality of first anchors 14 reach the wiring 13W, and the other ends of the other first anchors 14 reach the interface between the element isolation region 12I and the first insulating layer 11.

[0014] The second chip 30 includes a substrate 31, a second multilayer wiring layer 32 laminated on the substrate 31, and a second anchor 33 embedded in the second multilayer wiring layer 32. The substrate 31 is a semiconductor substrate (for example, a silicon substrate). A plurality of active regions are defined by an element isolation region 34 formed in the surface layer portion of the substrate 31. A plurality of transistors 35 are arranged on the plurality of active regions and the active regions. The transistor 35 is, for example, a MOSFET. In the second multilayer wiring layer 32, a plurality of wirings 32W, a plurality of vias 32V, and the second anchor 33 are arranged. A part of the plurality of wirings 32W is a ground wiring 32GND.

[0015] A control circuit for controlling a high-frequency circuit provided in the first chip 10 is constituted by a plurality of transistors 35, a plurality of wirings 32W, and a plurality of vias 32V. The second anchor 33 has a columnar shape and is formed of the same metal material as the first anchor 14. Note that an alloy composed of a plurality of metal elements or an alloy composed of at least one metal element and a non-metal element may be used for the first anchor 14 and the second anchor 33. In this case, the configuration in which the first anchor 14 and the second anchor 33 are formed of "the same metal material" includes a configuration in which the composition and composition ratio of the elements constituting the first anchor 14 and the second anchor 33 are the same, and a configuration in which the compositions are the same but the composition ratios are different. Further, the second anchor 33 is embedded in the second multilayer wiring layer 32 and exposed on its surface (the surface facing away from the substrate 31 side). The second anchor 33 is insulated from the control circuit provided in the second chip 30. That is, the second anchor 33 is in an electrically floating state. Note that the first anchor 14 is also insulated from the control circuit provided in the second chip 30.

[0016] The first chip 10 is fixed to the second chip 30 by connecting the portion of the first anchor 14 exposed on the surface of the first insulating layer 11 and the portion of the second anchor 33 exposed on the surface of the second multilayer wiring layer 32 to each other. The first anchor 14 and the second anchor 33 are connected by, for example, metal bonding. The portion of the first anchor 14 exposed on the surface of the first insulating layer 11 and the portion of the second anchor 33 exposed on the surface of the second multilayer wiring layer 32 do not necessarily completely coincide with each other in a plan view of the surface of the first insulating layer 11. At least a part of the region of the portion of the first anchor 14 exposed on the surface of the first insulating layer 11 and at least a part of the region of the portion of the second anchor 33 exposed on the surface of the second multilayer wiring layer 32 may be connected to each other. For example, the portion of the first anchor 14 exposed on the surface of the first insulating layer 11 and the portion of the second anchor 33 exposed on the surface of the second multilayer wiring layer 32 may be the same size and slightly displaced in the in-plane direction, or the sizes of both may be different.

[0017] A plurality of first bumps 51 protrude from the upper surface of the first chip 10, and a plurality of second bumps 52 protrude from a region of the upper surface of the second chip 30 that does not overlap with the first chip 10. As the first bumps 51 and the second bumps 52, for example, Cu pillar bumps can be used. A region on the upper surface of the first chip 10 where the first bumps 51 are not provided and a region on the upper surface of the second chip 30 where the second bumps 52 are not provided are covered with an insulating protective film 50. The first bumps 51 are connected to a high-frequency circuit provided in the first chip 10, and the second bumps 52 are connected to a control circuit provided in the second chip 30. By connecting the first bumps 51 and the second bumps 52 to the lands of the mounting substrate, the high-frequency circuit components are mounted on the mounting substrate.

[0018] FIG. 1B is a diagram showing the arrangement of the first anchor 14 and the second anchor 33 in a plan view. Here, "in a plan view" means "when the upper surface of the substrate 31 is viewed in a plan view". The first anchor 14 and the second anchor 33 are discretely arranged along a closed line arranged along the outer peripheral line, slightly inside the outer peripheral line of the first chip 10 in a plan view. The first anchor 14 and the second anchor 33 are provided in a sufficient number to fix the first chip 10 to the second chip 30.

[0019] FIG. 1C is a schematic cross-sectional view showing a configuration example of a connection portion between the first anchor 14 and the second anchor 33. The surface of the first insulating layer 11 of the first chip 10 and the end surface of the first anchor 14 are substantially flush, and the surface of the second multilayer wiring layer 32 of the second chip 30 and the end surface of the second anchor 33 are substantially flush. Therefore, when the exposed portion of the first anchor 14 and the exposed portion of the second anchor 33 are connected, the first insulating layer 11 of the first chip 10 and the second multilayer wiring layer 32 of the second chip 30 come into contact.

[0020] FIG. 1D is a schematic cross-sectional view showing another configuration example of the connection portion between the first anchor 14 and the second anchor 33. The end of the first anchor 14 protrudes from the surface of the first insulating layer 11 of the first chip 10. The tip of the protruding portion of the first anchor 14 is connected to the end face of the second anchor 33. In this case, a minute gap is formed between the first insulating layer 11 of the first chip 10 and the second multilayer wiring layer 32 of the second chip 30.

[0021] In any of the configurations of FIGS. 1C and 1D, by bringing the first anchor 14 into contact with the second anchor 33 and applying pressure, the two are metallically joined. As shown in FIG. 1D, when the end of the first anchor 14 protrudes from the surface of the first insulating layer 11, the force pressing the first chip 10 against the second chip 30 during joining concentrates on the contact portion between the first anchor 14 and the second anchor 33, making it easier for the two to be metallically joined.

[0022] FIG. 2A is a block diagram of a high-frequency circuit component according to the first embodiment. A high-frequency circuit 100 including an output-side switch 101, two low-noise amplifiers 102, two impedance matching circuits 103, and an antenna switch 104 is formed on the first chip 10. A control circuit 110 including an input / output buffer circuit 111, a digital logic circuit 112, and an analog control circuit 113 is formed on the second chip 30.

[0023] The output-side switch 101, the low-noise amplifier 102, and the antenna switch 104 are constituted by transistors 15 (FIG. 1A), a plurality of wirings 13W and vias 13V in the first multilayer wiring layer 13 (FIG. 1A), etc. The impedance matching circuit 103 is constituted by a capacitor and an inductor constituted by wirings 13W and vias 13V in the first multilayer wiring layer 13, etc. The input / output buffer circuit 111, the digital logic circuit 112, and the analog control circuit 113 are constituted by transistors 35 (FIG. 1A), a plurality of wirings 32W and vias 32V in the second multilayer wiring layer 32 (FIG. 1A), etc.

[0024] Each of the output-side switch 101 and the antenna switch 104 is, for example, an spdt (Single-Pole Double-Throw) switch. The output-side switch 101 connects the output node of one of the two low-noise amplifiers 102 to the output terminal RFout. The antenna switch 104 connects one antenna terminal ANT to one of the two impedance matching circuits 103. The two impedance matching circuits 103 are respectively connected to the input nodes of the two low-noise amplifiers 102.

[0025] Power is supplied from the power supply terminal Vdd to the control circuit 110. A control signal is input from the control terminal CNTL to the input / output buffer circuit 111. The digital logic circuit 112 decodes the control signal input to the input / output buffer circuit 111 and operates the analog control circuit 113. The analog control circuit 113 controls the operations of the output-side switch 101, the antenna switch 104, and the low-noise amplifier 102 of the high-frequency circuit 100 according to the control signal input from the control terminal CNTL.

[0026] The high-frequency signal input from the antenna terminal ANT is amplified through the impedance matching circuit 103 and the low-noise amplifier 102 selected by the output-side switch 101 and the antenna switch 104, and is output from the output terminal RFout.

[0027] FIG. 2B is a diagram showing the positional relationship in a plan view of the high-frequency circuit 100, the input / output buffer circuit 111, the digital logic circuit 112, and the analog control circuit 113. A first chip 10 smaller than the second chip 30 is fixed to the second chip 30. The input / output buffer circuit 111 and the analog control circuit 113 are arranged in a region that does not overlap with the first chip 10. The digital logic circuit 112 is arranged in a region that overlaps with the first chip 10.

[0028] The digital logic circuit 112 is less susceptible to the electromagnetic noise generated from the high-frequency circuit 100 compared to the input / output buffer circuit 111 and the analog control circuit 113. By arranging the digital logic circuit 112, which is less susceptible to the influence of electromagnetic noise, in a region overlapping with the first chip 10 where the high-frequency circuit 100 is provided, and arranging the digital logic circuit 112 and the input / output buffer circuit 111, which are relatively more susceptible to the influence of electromagnetic noise, in a region not overlapping with the first chip 10, a decrease in the electromagnetic compatibility (EMC) of the high-frequency circuit components is suppressed.

[0029] Next, a method for manufacturing a high-frequency circuit component according to the first embodiment will be described with reference to the drawings from FIG. 3A to FIG. 4B. The drawings from FIG. 3A to FIG. 4B are schematic cross-sectional views of the intermediate manufacturing stages of the high-frequency circuit component according to the first embodiment.

[0030] As shown in FIG. 3A, an SOI substrate 20 including a support substrate 21, a first insulating layer 11 (buried oxide film), and a first device layer 12 (SOI layer) is prepared. On the SOI substrate 20, an element isolation structure, a plurality of transistors 15, and a plurality of first anchors 14 reaching the interface between the first insulating layer 11 and the support substrate 21 are formed. Note that the first anchors 14 may penetrate from the interface between the first insulating layer 11 and the support substrate 21 to the surface layer portion of the support substrate 21. A first multilayer wiring layer 13 is formed on the SOI substrate 20.

[0031] As shown in FIG. 3B, a temporary substrate 23 is adhered to the surface of the first multilayer wiring layer 13, and the support substrate 21 is ground and polished to be removed. In FIG. 3B, the removed support substrate 21 is shown by a dashed line. When the first anchors 14 extend to the surface layer portion of the support substrate 21, due to the difference in the polishing rate between the support substrate 21 and the first anchors 14, a structure in which the tips of the first anchors 14 protrude from the surface of the first insulating layer 11 as shown in FIG. 1D can be obtained.

[0032] As shown in FIG. 3C, by dicing the first insulating layer 11, the first device layer 12, and the first multilayer wiring layer 13, these laminated structures are divided into a plurality of first chips 10. The plurality of first chips 10 are supported by the temporary substrate 23.

[0033] As shown in FIG. 4A, an element isolation region 34 is formed in the surface layer portion of a substrate 31 such as silicon to define a plurality of active regions, and transistors 35 are formed in the active regions and on the active regions. Further, a second multilayer wiring layer 32 is formed on the substrate 31. At this time, a plurality of second anchors 33 embedded in the second multilayer wiring layer 32 are formed.

[0034] The first chip 10 is separated from the temporary substrate 23 (FIG. 3C), and the first chip 10 is fixed on the second multilayer wiring layer 32 by bringing the first anchor 14 into contact with the second anchor 33 and applying pressure.

[0035] As shown in FIG. 4B, an insulating protective film 50 covering the first chip 10 and the second multilayer wiring layer 32 is formed. A plurality of openings are formed in the protective film 50, and first bumps 51 and second bumps 52 are formed in these openings. Thereafter, the substrate 31 and the second multilayer wiring layer 32 are diced to obtain a plurality of high-frequency circuit components (FIG. 1A).

[0036] Next, the excellent effects of the first embodiment will be described. In the first embodiment, the first chip 10 on which the high-frequency circuit is formed is stacked and fixed on the second chip 30 on which the control circuit for controlling the high-frequency circuit is formed. Therefore, it is possible to reduce the size of the high-frequency circuit component as compared with a configuration in which the chip on which the high-frequency circuit is formed and the chip on which the control circuit is formed are separately mounted on the mounting substrate.

[0037] In the first embodiment, the first chip 10 is fixed to the second chip 30 by bringing the first anchor 14 of the first chip 10 into contact with and pressing the second anchor 33 of the second chip 30. Therefore, there is no need to use a polymer adhesive or the like for fixing the first chip 10 to the second chip 30. Further, since the first anchor 14 and the second anchor 33 are formed of the same pure metal or alloy, they can be easily metal-bonded to each other. As the first anchor 14 and the second anchor 33, for example, copper, tungsten, aluminum, titanium, tantalum, or an alloy mainly composed of these metal elements can be used.

[0038] Also, in the first embodiment, after the first chip 10 is singulated, each of the plurality of first chips 10 is fixed to the second chip 30 before singulation. Therefore, after inspecting the quality of each of the plurality of first chips 10 and the quality of each of the plurality of second chips 30, high-frequency circuit components can be manufactured by combining good products with each other. Thereby, the yield can be improved.

[0039] Furthermore, in the first embodiment, in the first chip 10 in which a high-frequency circuit is formed, since the support substrate 21 (FIG. 3A) of the SOI substrate 20 is removed, the distortion caused by the parasitic capacitance between the transistor 15 of the high-frequency circuit and the support substrate 21 can be reduced. Thereby, the high-frequency characteristics of the high-frequency circuit component can be improved. In order to enhance the effect of improving the high-frequency characteristics of the high-frequency circuit component, it is desirable to suppress an increase in the parasitic capacitance between the transistor 15 of the high-frequency circuit and the substrate 31 of the second chip 30. In order to suppress this increase in the parasitic capacitance, it is preferable that the thickness-direction interval from the first insulating layer 11 of the first chip 10 to the substrate 31 be 10 μm or more.

[0040] In a semiconductor process using an SOI substrate, in order to avoid the potential of the silicon substrate being in a floating state, a through electrode (substrate contact) that penetrates the buried oxide film and reaches the silicon substrate is formed. In a configuration where the silicon substrate is finally removed, there can be a problem that moisture enters the elements on the device layer side through this through electrode. In the first embodiment, since the second chip 30 to which the first chip 10 is fixed blocks the moisture intrusion path, it is possible to suppress a decrease in moisture resistance.

[0041] Further, in the first embodiment, since the first anchor 14 and the second anchor 33 are in a floating state, the second anchor 33 does not restrict the freedom of routing of the wiring 32W in the second multilayer wiring layer 32 (FIG. 1A).

[0042] Next, a modification of the first embodiment will be described. In the first embodiment, the high-frequency circuit 100 formed on the first chip 10 includes a low-noise amplifier 102 (FIG. 2A), but may also include a power amplifier. The power amplifier amplifies the power of the transmission signal transmitted from the antenna.

[0043] [Second Embodiment] Next, a high-frequency circuit component according to the second embodiment will be described with reference to FIG. 5. Hereinafter, description of configurations common to the high-frequency circuit component according to the first embodiment described with reference to the drawings from FIG. 1A to FIG. 4B will be omitted.

[0044] FIG. 5 is a schematic cross-sectional view of a high-frequency circuit component according to the second embodiment. In the high-frequency circuit component according to the first embodiment, the first anchor 14 is embedded in the element isolation region 12I of the first device layer 12. On the other hand, in the second embodiment, the first anchor 14 is disposed within the source region 15S of the transistor 15 and is electrically connected to the source region 15S. A ground potential is applied to the source region 15S. The second anchor 33 is electrically connected to the ground wiring 32GND within the second multilayer wiring layer 32 of the second chip 30. Therefore, the source region 15S of the transistor 15 is connected to the ground wiring 32GND via the first anchor 14 and the second anchor 33. The ground wiring 32GND is connected to the ground conductor of the mounting substrate via the second bump 52.

[0045] Next, the excellent effects of the second embodiment will be described. Also in the third embodiment, similar to the first embodiment, improvement of high-frequency characteristics and improvement of yield can be achieved. Further, in the second embodiment, the first anchor 14 and the second anchor 33 that fix the first chip 10 to the second chip 30 have a function of electrically connecting the region where the ground potential of the first chip 10 is applied to the ground potential of the second chip 30. Thus, the first anchor 14 and the second anchor 33 that mechanically connect the first chip 10 to the second chip 30 are also used as an electrical connection path.

[0046] The first anchor 14 can be used as a substrate contact for fixing the potential of the support substrate 21 (FIG. 3A) made of silicon during the manufacturing process of the first chip 10. Therefore, it is not necessary to provide a substrate contact separately from the first anchor 14.

[0047] The ground wiring 32GND and the second bump 52 function as a heat dissipation path from the second chip 30 to the ground conductor of the mounting substrate. The heat generated by the transistor 15 of the first chip 10 is dissipated to the mounting substrate through the wiring 13W in the first multilayer wiring layer 13 and the first bump 51. In addition to this heat dissipation path, the first anchor 14, the second anchor 33, the ground wiring 32GND, and the second bump 52 also function as a heat dissipation path for dissipating the heat generated by the transistor 35 of the first chip 10 to the mounting substrate. Therefore, an excellent effect of improving the heat dissipation property from the first chip 10 is obtained.

[0048] [Third Embodiment] Next, the high-frequency circuit component according to the third embodiment will be described with reference to FIGS. 6A and 6B. Hereinafter, the description of the configuration common to the high-frequency circuit component according to the first embodiment described with reference to FIGS. 1A to 4B will be omitted.

[0049] FIG. 6A is a diagram showing the positional relationship in plan view of the first chip 10, the second chip 30, the first anchor 14, and the second anchor 33 of the high-frequency circuit component according to the third embodiment, and FIG. 6B is a schematic cross-sectional view of the first chip 10. In the first embodiment (FIGS. 1A and 1B), the columnar first anchor 14 and second anchor 33 are discretely arranged slightly inside the outer peripheral line of the first chip 10 in plan view. In contrast, in the third embodiment, the first anchor 14 and the second anchor 33 are arranged so as to continuously surround the high-frequency circuit 100 (FIG. 2A) formed on the first chip 10 in plan view.

[0050] Also, as shown in FIG. 6B, a shield ring 13S is arranged in the first multilayer wiring layer 13 so as to surround the high-frequency circuit 100 in plan view. The shield ring 13S is composed of a plurality of layers of wiring in the first multilayer wiring layer 13 and vias connecting the wiring layers. The shield ring 13S is connected to the first anchor 14. The shield ring 13S is connected to the ground potential.

[0051] Next, the excellent effects of the third embodiment will be described. Also in the third embodiment, similar to the first embodiment, improvement in high-frequency characteristics and improvement in yield can be achieved. Further, in the third embodiment, since the first anchor 14 has an electromagnetic shielding function together with the shield ring 13S, electromagnetic compatibility (EMC) can be enhanced.

[0052] [Fourth Embodiment] Next, the high-frequency circuit component according to the fourth embodiment will be described with reference to FIG. 7. Hereinafter, the description of the configuration common to the high-frequency circuit component according to the first embodiment described with reference to FIGS. 1A to 4B will be omitted.

[0053] FIG. 7 is a schematic cross-sectional view of the high-frequency circuit component according to the fourth embodiment. In the first embodiment (FIG. 1A), the first anchor 14 and the second anchor 33 are in an electrically floating state. On the other hand, in the fourth embodiment, the first anchor 14 is connected to the high-frequency circuit 100 (FIG. 2A) in the first chip 10, and the second anchor 33 is connected to the control circuit 110 (FIG. 2A) in the second chip 30. Therefore, the high-frequency circuit 100 in the first chip 10 and the control circuit 110 in the second chip 30 are interconnected via the first anchor 14 and the second anchor 33.

[0054] For example, the first anchor 14 and the second anchor 33 are used for the connection between the analog control circuit 113 shown in FIG. 2A and the low-noise amplifier 102, the output-side switch 101, and the antenna switch 104.

[0055] Next, the excellent effects of the fourth embodiment will be described. Also in the fourth embodiment, similar to the first embodiment, improvement in high-frequency characteristics and improvement in yield can be achieved. Further, in the fourth embodiment, since the first anchor 14 and the second anchor 33 electrically connect the high-frequency circuit 100 of the first chip 10 and the control circuit 110 of the second chip 30, there is no need to provide wiring for connecting the high-frequency circuit 100 and the control circuit 110 externally.

[0056] [Fifth Embodiment] Next, a high-frequency circuit component according to a fifth embodiment will be described with reference to FIG. 8. Hereinafter, descriptions of configurations common to the high-frequency circuit component according to the first embodiment described with reference to FIGS. 1A to 4B will be omitted.

[0057] FIG. 8 is a schematic cross-sectional view of a high-frequency circuit component according to the fifth embodiment. In the first embodiment (FIG. 1A), the substrate 31 used for the second chip 30 is a bulk silicon substrate. In contrast, in the fifth embodiment, an SOI substrate is used for the second chip 30. The SOI substrate includes a support substrate 37 made of silicon, a buried oxide film 38, and a second device layer 39. The source region and drain region of the transistor 35 are formed in the second device layer 39. In the first chip 10, as shown in FIG. 3B, the support substrate 21 of the SOI substrate 20 is removed, but in the second chip 30, the support substrate 37 is not removed and is used as a substrate for mechanically supporting the first chip 10.

[0058] Next, the excellent effects of the fifth embodiment will be described. Also in the fifth embodiment, similar to the first embodiment, improvement in high-frequency characteristics and improvement in yield can be achieved. Further, in the fifth embodiment, by using an SOI substrate for the second chip 30, the operating speed of the control circuit formed in the second chip 30 can be improved.

[0059] [Sixth Embodiment] Next, a high-frequency circuit component according to a sixth embodiment will be described with reference to FIG. 9. Hereinafter, descriptions of configurations common to the high-frequency circuit component according to the first embodiment described with reference to FIGS. 1A to 4B will be omitted.

[0060] FIG. 9 is a schematic cross-sectional view of a high-frequency circuit component according to the sixth embodiment. In the first embodiment (FIG. 1A), no particular mention is made of the film thickness of the wiring 13W in the first multilayer wiring layer 13 of the first chip 10 and the wiring 32W in the second multilayer wiring layer 32 of the second chip 30. In the high-frequency circuit component according to the sixth embodiment, the film thickness T1 of the wiring 13W in the first multilayer wiring layer 13 of the first chip 10 is thicker than the film thickness T2 of the wiring 32W in the second multilayer wiring layer 32 of the second chip 30.

[0061] The heat generated by the transistor 15 provided in the first chip 10 is mainly dissipated to the mounting substrate via the wiring 13W, via 13V, and the first bump 51 in the first multilayer wiring layer 13. The heat generated by the transistor 35 provided in the second chip 30 is mainly dissipated to the mounting substrate via the wiring 32W, via 32V, and the second bump 52 in the second multilayer wiring layer 32. The amount of heat generated from the plurality of transistors 15 constituting the low-noise amplifier 102 (FIG. 2A) of the high-frequency circuit 100 is larger than the amount of heat generated from the transistor 35 provided in the second chip 30 constituting the control circuit 110 (FIG. 2A).

[0062] Also in the sixth embodiment, similar to the first embodiment, improvement in high-frequency characteristics and improvement in yield can be achieved. Further, in the sixth embodiment, since the film thickness of the wiring 13W in the first multilayer wiring layer 13 used as a heat dissipation path from the transistor 15 is relatively thick, the heat dissipation performance from the transistor 15 with a relatively large amount of heat generation can be improved. Also, by relatively thinning the film thickness of the wiring 32W in the second multilayer wiring layer 32, the formation process of the wiring formed by the damascene method or the like can be simplified. When a plurality of wiring layers are arranged in each of the first multilayer wiring layer 13 and the second multilayer wiring layer 32, the total value of the film thickness T1 of each wiring layer of the first multilayer wiring layer 13 may be made larger than the total value of the film thickness T2 of each wiring layer of the second multilayer wiring layer 32.

[0063] [Seventh Embodiment] Next, a high-frequency circuit component according to the seventh embodiment will be described with reference to FIG. 10. Hereinafter, descriptions of configurations common to the high-frequency circuit component according to the first embodiment described with reference to FIGS. 1A to 4B will be omitted.

[0064] FIG. 10 is a schematic cross-sectional view of a high-frequency circuit component according to the seventh embodiment. In the first embodiment (FIG. 1A), the number of wiring layers of the first multilayer wiring layer 13 of the first chip 10 and the number of wiring layers of the second multilayer wiring layer 32 of the second chip 30 are not particularly mentioned. In the high-frequency circuit component according to the seventh embodiment, the number of wiring layers of the second multilayer wiring layer 32 of the second chip 30 is larger than the number of wiring layers of the first multilayer wiring layer 13 of the first chip 10. FIG. 10 shows an example in which the number of wiring layers of the first multilayer wiring layer 13 is 1 layer and the number of wiring layers of the second multilayer wiring layer 32 is 2 layers, but the number of wiring layers is not limited to this number. For example, the number of wiring layers of the first multilayer wiring layer 13 may be 2 layers, and the number of wiring layers of the second multilayer wiring layer 32 may be 3 layers or more.

[0065] Next, the excellent effects of the seventh embodiment will be described. Also in the seventh embodiment, similar to the first embodiment, improvement of high-frequency characteristics and improvement of yield can be achieved. Further, in the seventh embodiment, by relatively reducing the number of wiring layers of the first multilayer wiring layer 13, the heat dissipation from the transistor 15 provided in the first chip 10 to the mounting substrate via the wiring 13W, the via 13V, and the first bump 51 can be enhanced. By relatively increasing the number of wiring layers of the second multilayer wiring layer 32, the degree of freedom in the layout of the wiring 32W can be increased.

[0066] [Eighth Embodiment] Next, a high-frequency circuit component according to the eighth embodiment will be described with reference to FIGS. 11A and 11B. Hereinafter, descriptions of configurations common to the high-frequency circuit component according to the first embodiment described with reference to FIGS. 1A to 4B will be omitted.

[0067] FIG. 11A is a schematic cross-sectional view of a high-frequency circuit component according to the eighth embodiment, and FIG. 11B is a diagram showing the positional relationship of various components of the high-frequency circuit component in a plan view. In the first embodiment (FIGS. 1A and 2A), a high-frequency circuit 100 including a low-noise amplifier 102 or the like is formed on the first chip 10. On the other hand, in the eighth embodiment, the first chip 10 is an integrated passive device (IPD). For example, a filter circuit including a capacitor 13C and an inductor 13L is formed on the first chip 10.

[0068] The first chip 10 includes a first insulating layer 11, a first device layer 12, a first multilayer wiring layer 13, and a first anchor 14, similar to the first embodiment (FIG. 1A). The first device layer 12 is insulated, and a capacitor 13C is disposed thereon. The inductor 13L is constituted by a wiring 13W and a via 13V in the first multilayer wiring layer 13.

[0069] The first anchor 14 and the second anchor 33 (FIG. 11B) are arranged so as to continuously surround the capacitor 13C and the inductor 13L in a plan view. A plurality of transistors 35 are formed on the second chip 30, and a control circuit 110 is constituted by the plurality of transistors 35 or the like.

[0070] Next, the excellent effects of the eighth embodiment will be described. In the eighth embodiment, since the first chip 10, which is an integrated passive device, is stacked and fixed on the second chip 30 on which the control circuit 110 is formed, it is possible to miniaturize the high-frequency circuit component including the integrated passive device and the control circuit.

[0071] The above-described embodiments are illustrative, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. The same operational effects due to the same configurations of the plurality of embodiments will not be sequentially mentioned for each embodiment. Furthermore, the present invention is not limited to the above-described embodiments. For example, various changes, improvements, combinations, etc. will be obvious to those skilled in the art.

[0072] Based on the above-described embodiments described in this specification, the following inventions are disclosed. <1> A first chip including a first insulating layer, a first device layer laminated on the first insulating layer, a first multilayer wiring layer laminated on the first device layer, and a first anchor, in which a high-frequency circuit is formed; A second chip including a substrate, a second multilayer wiring layer disposed on the substrate, and a second anchor, in which a control circuit for controlling the high-frequency circuit is formed and comprising The first anchor is embedded in the first device layer and the first insulating layer and is exposed on the surface of the first insulating layer, The second anchor is embedded in the second multilayer wiring layer and is exposed on the surface of the second multilayer wiring layer, The first anchor and the second anchor are formed of the same metal material, and a portion of the first anchor exposed on the surface of the first insulating layer and a portion of the second anchor exposed on the surface of the second multilayer wiring layer are connected to each other, a high-frequency circuit component.

[0073] <2> The high-frequency circuit component according to <1>, wherein a total value of film thicknesses of a plurality of wirings of the first multilayer wiring layer is larger than a total value of film thicknesses of a plurality of wirings of the second multilayer wiring layer.

[0074] <3> The first anchor is connected to a region where a ground potential is applied in the first device layer, The second multilayer wiring layer includes a ground wiring, The high-frequency circuit component according to <1> or <2>, wherein the second anchor is connected to the ground wiring.

[0075] <4> The high-frequency circuit component according to <1> or <2>, wherein the first anchor is connected to the high-frequency circuit and the second anchor is connected to the control circuit.

[0076] <5> The high-frequency circuit component according to any one of <1> to <4>, wherein the number of layers of the second multilayer wiring layer is larger than the number of layers of the first multilayer wiring layer.

[0077] <6> When the substrate is viewed in plan view, the second chip extends to the outside of the first chip. A first bump protruding from the first multilayer wiring layer. A second bump protruding from a portion of the second multilayer wiring layer that does not overlap with the first chip in plan view. And further includes. The high-frequency circuit component according to any one of <1> to <5>, wherein the second anchor is connected to the second bump via the wiring of the second multilayer wiring layer.

[0078] <7> The high-frequency circuit component according to <1> or <2>, wherein the first anchor and the second anchor are insulated from the control circuit.

Explanation of symbols

[0079] 10 First chip 11 First insulating layer 12 First device layer 12I Element isolation region 13 First multilayer wiring layer 13C Capacitor 13L Inductor 13S Shield ring 13V Via 13W Wiring 14 First anchor 15 Transistor 15S Source region 20 SOI substrate 21 Support substrate 23 Temporary substrate 30 Second chip 31 Substrate 32 Second multilayer wiring layer 32GND Ground wiring 32V Via 32W Wiring 33 Second Anchor 34 Element Isolation Region 35 Transistor 37 Support Substrate 38 Buried Oxide Film 39 Second Device Layer 50 Protective Film 51 First Bump 52 Second Bump 100 High-Frequency Circuit 101 Output-Side Switch 102 Low-Noise Amplifier 103 Impedance Matching Circuit 104 Antenna Switch 110 Control Circuit 111 Input / Output Buffer Circuit 112 Digital Logic Circuit 113 Analog Control Circuit

Claims

1. a first chip including a first insulating layer, a first device layer stacked on the first insulating layer, a first multilayer wiring layer stacked on the first device layer, and a first anchor, and having a high-frequency circuit formed thereon; a second chip including a substrate, a second multilayer wiring layer disposed on the substrate, and a second anchor, the second chip having a control circuit formed thereon for controlling the high frequency circuit; Equipped with the first anchor is embedded in the first device layer and the first insulating layer and is exposed on a surface of the first insulating layer; the second anchor is embedded in the second multilayer wiring layer and exposed on a surface of the second multilayer wiring layer; A high-frequency circuit component in which the first anchor and the second anchor are formed of the same metal material, and a portion of the first anchor exposed on the surface of the first insulating layer and a portion of the second anchor exposed on the surface of the second multilayer wiring layer are interconnected.

2. 2. The high-frequency circuit component according to claim 1, wherein a total thickness of the plurality of wirings in the first multilayer wiring layer is greater than a total thickness of the plurality of wirings in the second multilayer wiring layer.

3. the first anchor is connected to a region in the first device layer to which a ground potential is applied; the second multilayer wiring layer includes a ground wiring, The high-frequency circuit component according to claim 1 , wherein the second anchor is connected to the ground wiring.

4. 3. The high frequency circuit component according to claim 1, wherein the first anchor is connected to the high frequency circuit, and the second anchor is connected to the control circuit.

5. 3. The high-frequency circuit component according to claim 1, wherein the number of layers in the second multilayer wiring layer is greater than the number of layers in the first multilayer wiring layer.

6. When the substrate is viewed in a plan view, the second chip extends to an outside of the first chip, a first bump protruding from the first multilayer wiring layer; a second bump protruding from a portion of the second multilayer wiring layer that does not overlap the first chip in a plan view; Further equipped with 3. The high-frequency circuit component according to claim 1, wherein the second anchor is connected to the second bump via a wiring of the second multilayer wiring layer.

7. 3. The high-frequency circuit component according to claim 1, wherein the first anchor and the second anchor are insulated from the control circuit.

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