Indium phosphide substrate and semiconductor epitaxial wafer

Abstract

To provide an indium phosphide substrate and a semiconductor epitaxial wafer which achieve reduced surface waviness.SOLUTION: The present invention provides an indium phosphide substrate which has a diameter of 50 mm or more and in which the waviness Wa of the entire surface of the substrate excluding an edge part is 150 nm or less.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to indium phosphide substrates and semiconductor epitaxial wafers. [Background technology]

[0002] Indium phosphide (InP) is a III-V compound semiconductor material consisting of indium (In) of group III and phosphorus (P) of group V. Its properties as a semiconductor material are a band gap of 1.35 eV and an electron mobility of up to 5400 cm. 2 / V·s, and its electron mobility under high electric fields is higher than that of other common semiconductor materials such as silicon and gallium arsenide.In addition, its stable crystal structure at room temperature and pressure is a cubic zinc blende structure, and its lattice constant is larger than that of compound semiconductors such as gallium arsenide (GaAs) and gallium phosphide (GaP).

[0003] In silicon photonics, a method is used in which epitaxial growth is performed on an InP substrate, and then the substrate is bonded to a Si substrate to create a device. In the bonding process, adhesion between the InP epitaxial growth layer and the Si device is extremely important for the device characteristics, but undulations on the substrate surface propagate to the film surface after epitaxial growth and are thought to affect the bonding accuracy. Thus, it is extremely important to control the undulations on the surface of the InP epitaxial growth layer when bonding to the Si device.

[0004] Patent Document 1 discloses a technique for suppressing surface waviness of an InP wafer by performing mirror polishing using a predetermined InP wafer mirror polishing liquid on a rotating polishing disk equipped with an abrasive cloth.

[0005] Patent Document 2 discloses a technique for grinding semiconductor wafers, which is characterized in that a semiconductor wafer is chucked onto the surface of a plurality of disk-shaped chucks rotatably arranged on a circle, a disk-shaped grindstone having at least the size of the circle is rotated in the opposite direction to the rotation direction of the chucks, and water and then a drying gas are sprayed from a nozzle provided in the center of the grindstone to grind the semiconductor wafers, and the chuck and the grindstone are brought relatively close to each other in the direction of the rotation axis to keep the contact area between the wafer and the grindstone constant, while grinding the multiple wafers together to a predetermined thickness. In this technique, the chuck and the grindstone are brought relatively close to each other in the direction of the rotation axis to bring them into contact with each other, water and then a drying gas are sprayed from the nozzle, and the grindstone grinds the multiple wafers together to a predetermined thickness, thereby suppressing waviness of the substrate.

[0006] Patent Document 3 discloses a method for polishing indium phosphide, which is characterized by using a mixed solution of a solution in which bromine is dissolved in methyl alcohol and an aqueous solution of silica colloid. By polishing the substrate by adjusting the mixed solution in this way, waviness of the substrate caused by etch pits is suppressed. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Special Publication No. 07-027881 [Patent Document 2] Patent No. 3316939 [Patent Document 3] Japanese Unexamined Patent Publication No. 58-145604 Summary of the Invention [Problem to be solved by the invention]

[0008] As mentioned above, when epitaxial growth is performed on an InP substrate and then bonded to a Si substrate to form a device, the adhesion between the InP epitaxial growth layer and the Si device is extremely important for the device characteristics, but the waviness of the substrate surface propagates to the film surface after epitaxial growth and is thought to affect the bonding accuracy. For this reason, when epitaxial growth is performed using an InP substrate with a large waviness over the entire surface, there is a problem of poor bonding.

[0009] The techniques disclosed in Patent Documents 1 and 2 are intended to suppress waviness in a substrate, but there is no disclosure as to what extent waviness is suppressed over the entire substrate.

[0010] Furthermore, the technology disclosed in Patent Document 3 suppresses waviness of a substrate caused by etch pits, and focuses on local waviness of the substrate to suppress the local waviness. Thus, Patent Document 3 does not disclose a technology for suppressing waviness over the entire substrate.

[0011] The present invention has been made to solve the above-mentioned problems, and has an object to provide an indium phosphide substrate and a semiconductor epitaxial wafer with suppressed surface waviness. [Means for solving the problem]

[0012] The above problems are solved by the embodiments of the present invention, which are specified as follows: (1) The diameter is 50 mm or more. An indium phosphide substrate having a waviness (Wa) of 150 nm or less over the entire substrate surface excluding the edges. (2) The indium phosphide substrate according to (1), wherein the waviness Wa of the entire substrate surface excluding the edges is 70 to 150 nm. (3) The indium phosphide substrate according to (1) or (2), wherein the diameter is 50 to 150 mm. (4) A semiconductor epitaxial wafer comprising: an indium phosphide substrate according to any one of (1) to (3); and an epitaxial crystal layer provided on a primary surface of the indium phosphide substrate. Effect of the Invention

[0013] According to the embodiments of the present invention, it is possible to provide an indium phosphide substrate and a semiconductor epitaxial wafer with reduced surface waviness. [Brief description of the drawings]

[0014] [Figure 1] 1 is a schematic diagram of a surface of an indium phosphide substrate according to an embodiment of the present invention. [Diagram 2] 1 is a schematic diagram of a wafer surface for explaining a method of calculating waviness Wa. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Next, the embodiments of the present invention will be described in detail with reference to the drawings. It should be understood that the present invention is not limited to the following embodiments, and that appropriate changes and improvements in the design may be made based on the ordinary knowledge of those skilled in the art without departing from the spirit of the present invention.

[0016] [Indium phosphide substrate] The configuration of the indium phosphide substrate of this embodiment will be described below. The indium phosphide (InP) substrate of this embodiment includes a substrate front surface (main surface), a substrate back surface, and an edge portion. The edge portion may have an orientation flat (OF) indicating the crystal orientation, and an index flat (IF) for distinguishing the substrate's main surface from its back surface.

[0017] The main surface of the indium phosphide substrate can be a surface for forming an epitaxial crystal layer. The surface for forming an epitaxial crystal layer is a surface on which epitaxial growth is actually performed when the indium phosphide substrate of the present embodiment is used as a substrate for epitaxial growth to form a semiconductor device structure.

[0018] The main surface of the indium phosphide substrate is formed to have a diameter of 50 mm or more. The diameter of the main surface of the indium phosphide substrate may be 50 to 150 mm. The planar shape of the indium phosphide substrate may be circular or rectangular, such as a square.

[0019] The thickness of the indium phosphide substrate is not particularly limited, but is preferably, for example, 300 to 900 μm, and more preferably 300 to 700 μm. In particular, when the diameter (caliber) of the indium phosphide substrate is large, if the thickness of the indium phosphide substrate is less than 300 μm, it may be cracked, and if it exceeds 900 μm, there may be a problem that the base crystal is wasted.

[0020] The indium phosphide substrate of this embodiment uses Zn (zinc) as a dopant (impurity) with a carrier concentration of 1×10 16 cm -3 More than 1×10 19 cm -3 S (sulfur) may be included so that the carrier concentration is 1×10 16 cm -3 More than 1×10 19 cm -3 Sn (tin) may be contained so that the carrier concentration is 1×10 16 cm -3 More than 1×10 19 cm -3 Fe (iron) may be included so that the resistivity is 1×10 5 Ωcm or more 1×10 8 It may be contained so as to be Ωcm or less.

[0021] Fig. 1 shows a schematic diagram of the surface of an indium phosphide substrate according to an embodiment of the present invention. The indium phosphide substrate is formed in a substantially disk shape and has an OF and an IF. Note that Fig. 1 is a diagram for understanding the edge portion of the indium phosphide substrate according to an embodiment of the present invention, and the indium phosphide substrate according to an embodiment of the present invention is not limited to such a shape. In particular, it is not necessary for the indium phosphide substrate to have an OF and an IF.

[0022] In the indium phosphide substrate according to the embodiment of the present invention, the waviness Wa of the entire substrate surface excluding the edge portion is controlled to 150 nm or less. Here, in the present invention, the area within approximately 5 mm from the outer periphery of the wafer to the center excluding the effects of roll-off is defined as the "edge portion", and the entire wafer surface excluding the area within 5 mm from the outer periphery of the wafer to the center excluding the effects of roll-off is defined as the "entire substrate surface excluding the edge portion". That is, in the present invention, the "entire substrate surface excluding the edge portion" refers to the circular area in the center shown as the "waviness measurement area" in FIG. 1.

[0023] Since the entire surface of the wafer is ground at the same time, the measurement of the center portion represents the waviness of the entire wafer, excluding the edge portion (the area within about 5 mm from the outer circumference to the center) where roll-off occurs due to polishing. In addition, since the waviness is periodic, it is considered to be constant regardless of the diameter.

[0024] In the present invention, the "waviness Wa" of the entire substrate surface excluding the edge portions is the "arithmetic mean waviness" defined in JIS B 0601: 2013. By measuring the waviness Wa, it is possible to quantify the average value of the waviness of the entire substrate surface excluding the edge portions.

[0025] The waviness Wa of the entire substrate surface excluding the edges of the indium phosphide substrate can be measured using the white light interference measurement function of the VKX-3000 laser microscope manufactured by Keyence Corp. When measuring the waviness Wa of the entire substrate surface excluding the edges of the indium phosphide substrate, a 10x interference measurement lens is used to measure the waviness (Wa: arithmetic mean waviness) curve as a contour curve in an area of ​​approximately 1mm x 40mm, with the center of the wafer being the center of the measurement area, and the waviness is calculated with a cutoff wavelength λc = 25mm. In calculating the waviness Wa, as shown in Figure 2, the center of the short side direction on the substrate surface in an area of ​​about 1 mm x 40 mm is set as a reference line, and 20 lines at intervals of about 4.5 μm (basic interval specified by the laser microscope VKX-3000) are set as one measurement interval (about 4.5 μm x 20 lines = about 90 μm interval), and the waviness over 40 mm in the long direction of a total of 11 lines, including 10 surrounding lines moved parallel to the short side direction and the reference line, is calculated, and the average value is taken as Wa. Note that this average value is automatically measured by the white light interference measurement function of the laser microscope VKX-3000 manufactured by Keyence Corporation. The measurements are carried out in a clean room with a controlled room temperature of 22±5°C so that the effects of thermal expansion, etc. can be ignored. The various setting conditions for the white light interference measurement function of the VKX-3000 laser microscope are as follows: Tilt correction: Automatic DCL / BCL: None Measurement type: Waviness Cutoff wavelength: λs and λf are not set. λc is 25 mm. End effect compensation: Enabled Double Gaussian: OFF -Stylus mode: OFF ·Number of reference wavelengths: 1 Number of profiles: 11 Since the entire surface of the wafer is ground simultaneously, there is no position dependency on the surface, and if the waviness curve of the above-mentioned part is evaluated, it is a representative measurement of the waviness of the entire wafer required for the bonding process. In addition, since the waviness is periodic, it is considered to be constant regardless of the diameter.

[0026] When the waviness Wa of the entire substrate surface excluding the edge portion of the indium phosphide substrate is 150 nm or less, the surface waviness after epitaxial growth is reduced, and even when the indium phosphide substrate is bonded to a Si substrate including a Si device, poor adhesion caused by the waviness can be effectively suppressed. The waviness Wa of the entire substrate surface excluding the edge portion of the indium phosphide substrate is preferably 120 nm or less, more preferably 100 nm or less, and even more preferably 80 nm or less. The lower limit of the waviness Wa is not particularly limited, but Wa may be 70 to 150 nm.

[0027] [Method for manufacturing indium phosphide substrate] Next, a method for manufacturing an indium phosphide substrate according to an embodiment of the present invention will be described. In a method for producing an indium phosphide substrate, first, an ingot of indium phosphide is produced by a known method. Next, the ingot of indium phosphide is ground into a cylinder, and an orientation flat (OF) and an index flat (IF) may be formed at predetermined positions on the outer periphery of the wafer. Next, wafers having a main surface and a back surface are cut out from the ground ingot of indium phosphide. At this time, both ends of the crystal of the ingot of indium phosphide are cut along a predetermined crystal plane using a wire saw or the like, and a plurality of wafers having a thickness of 750 to 850 μm are cut out.

[0028] In the process of cutting out the wafers, it is preferable to constantly feed new wire while reciprocating the wire in the horizontal direction, and to move a stage carrying an ingot of indium phosphide in the vertical direction toward the wire.

[0029] The conditions for cutting the ingot with a wire saw are as follows. -Wire feed speed: 10~60m / min Wire reciprocating speed: 300~350m / min Vertical movement speed of the stage carrying the ingot of indium phosphide: 200-400μm / min Wire saw abrasive grain management: The abrasive grains used are GC #1200 and cutting oil is PS-LP-500D, and the abrasive grains are controlled so that the viscosity is 300-400 mPa s when the rotor shaft of the viscometer rotates at 60 rpm. The viscosity can be measured using a TVB-10 viscometer manufactured by Toki Sangyo Co., Ltd.

[0030] Next, in order to remove the process-affected layer generated in the cutting process using the wire saw, the cut wafer is etched on both sides with a predetermined etching solution (primary etching). The wafer can be etched by immersing the entire wafer in the etching solution. As the etching solution, for example, a mixed solution of 85 mass% phosphoric acid aqueous solution and 30 mass% hydrogen peroxide solution is preferably used, and both sides are etched by a total of 5 to 15 μm.

[0031] Next, the outer periphery of the wafer is chamfered to a diameter of 50 mm or more. After chamfering, both sides of the wafer are roughly polished. This rough polishing process is also called the lapping process, and involves polishing with a specified abrasive to remove irregularities on the wafer surface while maintaining the wafer's flatness. When cutting with a wire saw as described above, undulations occur across the entire wafer due to the wire's vibration. The inventors have found that in order to remove this, it is necessary to remove the undulations by lapping after slicing (the process of cutting wafers from an ingot). Specifically, the wafer is polished with a pressure of 100 g / cm 2 While applying the above pressure, it is necessary to remove a total thickness of 100 μm or more from the front and back surfaces of the wafer by lapping. In order to obtain a large amount of lapping, it is preferable to increase the thickness of the wafer during slicing as necessary.

[0032] Next, the wafer is etched on both sides with a predetermined etching solution (secondary etching). The wafer can be etched by immersing the entire wafer in the etching solution. As the etching solution, for example, a mixed solution of 85 mass% phosphoric acid aqueous solution, 30 mass% hydrogen peroxide solution, and ultrapure water is preferably used, and both sides are etched to a total depth of 7 to 15 μm.

[0033] Next, both sides of the wafer are polished. This step is for removing waviness that cannot be completely removed by the lapping step described above, and from the viewpoint of productivity, it is preferable to polish multiple wafers simultaneously on both sides. In order to remove waviness uniformly across the surface of all wafers polished simultaneously, when polishing both sides of the wafer with the upper and lower plates, it is necessary to supply sufficient polishing liquid to the wafer from multiple polishing liquid supply ports so that the polishing liquid fully permeates the entire polishing pads provided on the upper and lower plates. Specifically, a flow rate of 0.07 mL / min·cm per area of ​​the upper or lower platen is required. 2 By supplying the polishing liquid at the above flow rate, both sides of the wafer can be polished uniformly. As a result, it becomes possible to remove waviness that cannot be completely eliminated by the lapping process. In this way, the waviness (Wa) of the entire substrate surface, excluding the edge, can be controlled to 150 nm or less.

[0034] Next, the main surface of the wafer is polished with an abrasive for mirror polishing to give a mirror finish. Next, cleaning is performed to produce the indium phosphide substrate according to the embodiment of the present invention. After the mirror finish described above, etching, mirror polishing, cleaning, etc. may be performed to produce the indium phosphide substrate.

[0035] [Semiconductor epitaxial wafers] By epitaxially growing a semiconductor thin film on the main surface of the indium phosphide substrate according to the embodiment of the present invention by a known method, an epitaxial crystal layer can be formed, and a semiconductor epitaxial wafer can be fabricated. As an example of the epitaxial growth, a HEMT structure may be formed by epitaxially growing an InAlAs buffer layer, an InGaAs channel layer, an InAlAs spacer layer, and an InP electron supply layer on the main surface of the indium phosphide substrate. When fabricating a semiconductor epitaxial wafer having such a HEMT structure, generally, an etching process is performed on a mirror-finished indium phosphide substrate using an etching solution such as sulfuric acid / hydrogen peroxide solution to remove impurities such as silicon (Si) attached to the substrate surface. With the back surface of the indium phosphide substrate after this etching process being supported in contact with a susceptor, an epitaxial crystal layer is formed on the main surface of the indium phosphide substrate by molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD).

[0036] The semiconductor epitaxial wafer according to the embodiment of the present invention is produced using the indium phosphide substrate according to the embodiment of the present invention in which waviness over the entire substrate surface is suppressed as described above. Therefore, surface waviness after epitaxial growth is reduced, and even when the wafer is bonded onto a Si substrate including a Si device, poor adhesion due to the influence of waviness is effectively suppressed. EXAMPLES

[0037] The following examples are provided to provide a better understanding of the present invention and its advantages, but the present invention is not limited to these examples.

[0038] (Examples 1 and 2) Examples 1 and 2 were prepared as follows. First, an ingot of indium phosphide was prepared. Next, the ingot of indium phosphide was ground into a cylinder, and an orientation flat (OF) and an index flat (IF) were formed at predetermined positions on the outer periphery of the wafer. Next, wafers having a main surface and a back surface were cut out from the ground ingot of indium phosphide. At this time, both ends of the crystal of the ingot of indium phosphide were cut along a predetermined crystal plane using a wire saw or the like, and a plurality of wafers were cut out to a thickness of 0.84 mm.

[0039] In the process of cutting out the wafers, the wire was moved back and forth horizontally while new wire was constantly being fed, and the stage carrying the ingot of indium phosphide was moved vertically toward the wire.

[0040] The conditions for cutting the ingot with a wire saw are as follows. -Wire feed speed: 10~60m / min Wire reciprocating speed: 320m / min Vertical movement speed of the stage carrying the indium phosphide ingot: 330 μm / min Wire saw abrasive grain management: The abrasive grains used were GC #1200 and the cutting oil was PS-LP-500D, and the abrasive grains were controlled so that the viscosity was 300-400 mPa s when the rotor shaft of the viscometer rotated at a speed of 60 rpm. The viscosity was measured using a TVB-10 viscometer manufactured by Toki Sangyo Co., Ltd.

[0041] Next, in order to remove the process-induced alteration layer that occurred during the cutting process using the wire saw, the cut wafer was etched from both sides to a total depth of 15 μm using a mixed solution of 85% by mass phosphoric acid aqueous solution and 30% by mass hydrogen peroxide solution (primary etching). The wafer was etched by immersing the entire wafer in the etching solution.

[0042] Next, the outer periphery of the wafer was chamfered to a diameter of 50 mm or more. After chamfering, both sides of the wafer were roughly polished (lapped). Specifically, the wafer was polished with a polishing force of 150 g / cm 2While applying pressure, a total thickness of 120 μm was removed from the front and back surfaces of the wafer by lapping.

[0043] Next, the wafer was etched by a total of 7 μm from both sides (secondary etching) using a mixed solution of an 85 mass% phosphoric acid aqueous solution, a 30 mass% hydrogen peroxide aqueous solution, and ultrapure water. The wafer was etched by immersing the entire wafer in the etching solution.

[0044] Next, both sides of the wafer were polished. This step is for removing undulations that cannot be completely removed in the above lapping step. In this double-sided polishing step, when polishing both sides of the wafer with the upper platen and the lower platen, sufficient polishing liquid was supplied to the wafer from a plurality of polishing liquid supply ports so that the polishing liquid would sufficiently penetrate the entire polishing pad provided on the upper platen and the lower platen. Specifically, the flow rate (total polishing liquid amount) of 0.072 mL / min·cm 2 was set to be supplied. The areas of the upper platen and the lower platen used were 5608 cm 2 respectively.

[0045] Next, the main surface of the wafer was polished with a polishing material for mirror polishing to finish it into a mirror surface. Next, by performing cleaning, a sample of an indium phosphide substrate with a diameter of 76.2 mm having the shape shown in FIG. 1 was produced.

[0046] (Comparative Examples 1 to 5) In Comparative Examples 1 to 5, in the lapping step, a total thickness of 40 μm was removed from the front and back surfaces of the wafer by lapping, and in the double-sided polishing step after the secondary etching, except that the above total polishing liquid amount was set to 0.065 mL / min·cm 2 Samples of indium phosphide substrates with a diameter of 76.2 mm having the shape shown in FIG. 1 were produced under the same conditions as in Examples 1 and 2.

[0047] (Evaluation of Undulation Wa) For each of the indium phosphide substrate samples of Examples 1 and 2 and Comparative Examples 1 to 5, the waviness Wa of the entire substrate surface excluding the edges was measured by the following method. That is, for each sample of indium phosphide substrate having a diameter of 76.2 mm and having IF and OF as shown in Figure 1 in Examples 1 and 2 and Comparative Examples 1 to 5, the area within approximately 5 mm from the outer periphery to the center was defined as the "edge portion," and the entire wafer surface excluding the area within 5 mm from the outer periphery to the center of the wafer, excluding the effects of roll-off, was defined as the "entire substrate surface excluding the edge portion." Next, the waviness Wa in the waviness measurement area was measured using a white light interference measurement function of a laser microscope VKX-3000 manufactured by Keyence Corporation. In this measurement, a 10x lens for interference measurement was used to measure the waviness curve in an area of ​​about 1mm x 40mm with the center of the wafer being the center of the measurement area, and the waviness was calculated with a cutoff wavelength λc = 25mm. In calculating the waviness Wa, as shown in Figure 2, the center of the short side direction on the substrate surface in an area of ​​about 1mm x 40mm was set as a reference line, and 20 lines with an interval of about 4.5μm (basic interval specified by the laser microscope VKX-3000) were set as one measurement interval (about 4.5μm x 20 lines = about 90μm interval), and the waviness over 40mm in the long direction of 11 lines in total, including 10 surrounding lines moved parallel to the short side direction and the reference line, was calculated, and the average value was taken as Wa. The average value was automatically measured by the white light interference measurement function of a laser microscope VKX-3000 manufactured by Keyence Corporation. The measurements were carried out in a clean room with a controlled room temperature of 22±5°C so that the effects of thermal expansion, etc. could be ignored. The various settings for the white light interference measurement function of the VKX-3000 laser microscope were as follows: Tilt correction: Automatic DCL / BCL: None Measurement type: Waviness Cutoff wavelength: λs and λf are not set. λc is 25 mm. End effect compensation: Enabled Double Gaussian: OFF -Stylus mode: OFF ·Number of reference wavelengths: 1 Number of profiles: 11 The above-mentioned production conditions and evaluation results are shown in Table 1.

[0048] [Table 1]

[0049] (Consideration) In both Examples 1 and 2, the waviness Wa of the entire substrate surface excluding the edges was 150 nm or less, and the surface waviness was well suppressed. In contrast, in all of Comparative Examples 1 to 5, the waviness Wa of the entire substrate surface excluding the edges exceeded 150 nm. In addition, in Example 1 and Example 2, the total lapping amount of the front and back surfaces of the wafer is the same, 120 μm, and the total amount of polishing liquid on the front and back surfaces of the wafer is also 0.072 mL / min cm 2 The total lapping amount of the front and back surfaces of the wafer was 40 μm, but the waviness Wa of the entire substrate surface excluding the edge was different, being 79.1 nm and 149.7 nm, respectively. Similarly, in Comparative Examples 1 to 5, the total lapping amount of the front and back surfaces of the wafer was the same, being 40 μm, and the total amount of polishing liquid on the front and back surfaces of the wafer was also 0.065 mL / min cm 2 The waviness Wa of the entire substrate surface excluding the edges was different, ranging from 186.1 to 257.8 nm. This is thought to be because the waviness after cutting differs due to variations in temperature during cutting with the wire saw.

Claims

1. The diameter is 50 mm or more, An indium phosphide substrate having a waviness Wa of 150 nm or less over the entire substrate surface excluding edges.

2. 2. The indium phosphide substrate according to claim 1, wherein the waviness Wa of the entire substrate surface excluding the edges is 70 to 150 nm.

3. 3. The indium phosphide substrate according to claim 1, wherein the diameter is from 50 to 150 mm.

4. 3. A semiconductor epitaxial wafer comprising: the indium phosphide substrate according to claim 1; and an epitaxial crystal layer provided on a primary surface of the indium phosphide substrate.

5. A semiconductor epitaxial wafer comprising: the indium phosphide substrate according to claim 3; and an epitaxial crystal layer provided on a primary surface of the indium phosphide substrate.

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