Bonded semiconductor substrate and method for manufacturing bonded semiconductor substrate

Abstract

To provide a bonded semiconductor substrate and a method for manufacturing a bonded semiconductor substrate, capable of preventing occurrence of peeling of a substrate from a bonding interface of the bonded semiconductor substrate.SOLUTION: There is provided a method for manufacturing a bonded semiconductor substrate that includes a first semiconductor substrate and a second semiconductor substrate that comes into contact with the first semiconductor substrate. The method includes: an amorphous layer formation step of forming, by amorphizing, an amorphous layer on at least one of a surface of a first bonding target surface, which is a surface of the first semiconductor substrate bonded to the second semiconductor substrate, and a surface of a second bonding target surface, which is a surface of the second semiconductor substrate bonded to the first semiconductor substrate; a bonding step of bonding the first bonding target surface and the second bonding target surface after the amorphous layer formation step and forming a bonded substrate including a bonding interface; and a heat-treatment step of heat-treating the bonded substrate to set an undulation height of the bonding interface to 1.5 nm or higher. The thickness of the amorphous layer formed in the amorphous layer formation step is 5 nm or greater.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a bonded semiconductor substrate in which two or more substrates are bonded via a bonding interface by bonding, and a bonded semiconductor substrate and a method for manufacturing the bonded semiconductor substrate capable of preventing peeling at the bonding interface.

Background Art

[0002] As an example of manufacturing a bonded semiconductor substrate, a technique of bonding a SiC single crystal substrate and a SiC polycrystalline substrate is known. As a related technique, for example, the technique disclosed in Patent Document 1 is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When a SiC single crystal substrate and a SiC polycrystalline substrate are directly bonded, if the bonding strength at the bonding interface is low, there is a risk of peeling at the bonding interface even with a small impact. For example, inside the furnace of a growth furnace for growing an epitaxial film on the surface of the SiC single crystal substrate of the bonded semiconductor substrate, or inside a device manufacturing apparatus for manufacturing a semiconductor device using the bonded semiconductor substrate after forming the epitaxial film, if peeling occurs at the bonding interface of the bonded semiconductor substrate and dust is generated, the growth furnace or the apparatus may stop due to dust generation inside the furnace or the apparatus, and the operation rate of the growth furnace or the apparatus may decrease due to cleaning of the growth furnace or the apparatus inside the growth furnace or the apparatus, resulting in a decrease in production efficiency, which is not preferable.

[0005] In the method for manufacturing a semiconductor substrate of Patent Document 1, an amorphous layer is formed on the surfaces of a support substrate and a single crystal layer so as to obtain a bonding strength capable of withstanding a semiconductor process, and then these are brought into contact and heat-treated thereafter. According to this method, it can be expected to suppress peeling at the bonding interface in the process until an epitaxial film is grown on the bonded semiconductor substrate and then a semiconductor device is manufactured.

[0006] However, a semiconductor device formed with an electronic circuit and cut into chip form may be subjected to a greater impact after being incorporated into a mobile phone, a home appliance, or an industrial device, as compared with the impact received in the process until the semiconductor device is manufactured. It is important that peeling does not occur at the bonding interface of the bonded semiconductor substrate even due to such a large impact.

[0007] Therefore, in order to solve the above problems, an object of the present invention is to provide a bonded semiconductor substrate and a method for manufacturing a bonded semiconductor substrate that can prevent the occurrence of peeling of the substrate from the bonding interface of the bonded semiconductor substrate.

Means for Solving the Problems

[0008] In order to solve the above problems, a bonded semiconductor substrate of the present invention is a bonded semiconductor substrate including a first semiconductor substrate and a second semiconductor substrate bonded to the first semiconductor substrate via a bonding interface, wherein the undulation height of the bonding interface is 1.5 nm or more.

[0009] The breaking strength by a stud pull test in a direction perpendicular to the bonding interface may be 70 MPa or more.

[0010] The first semiconductor substrate and the second semiconductor substrate may be any one of silicon carbide (SiC), silicon (Si), carbon (C), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga 2 O 3 ), and diamond.

[0011] The first semiconductor substrate may be a single-crystalline silicon carbide substrate, and the second semiconductor substrate may be a polycrystalline silicon carbide substrate.

[0012] Also, in order to solve the above problems, a method for manufacturing a bonded semiconductor substrate according to the present invention is a method for manufacturing a bonded semiconductor substrate including a first semiconductor substrate and a second semiconductor substrate in contact with the first semiconductor substrate, wherein at least one of the surface of a first bonding target surface which is the surface of the first semiconductor substrate where it bonds with the second semiconductor substrate, or the surface of a second bonding target surface which is the surface of the second semiconductor substrate where it bonds with the first semiconductor substrate is amorphized to form an amorphous layer; a bonding step of bonding the first bonding target surface and the second bonding target surface to form a bonded substrate having a bonding interface; and a heat treatment step of heat-treating the bonded substrate to make the undulation height of the bonding interface 1.5 nm or more, and the thickness of the amorphous layer formed in the amorphous layer forming step is 5 nm or more.

[0013] The first semiconductor substrate and the second semiconductor substrate may each be any one of silicon carbide (SiC), silicon (Si), carbon (C), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga 2 O 3 ), and diamond.

[0014] At least one of silicon (Si), carbon (C), helium (He), neon (Ne), argon (Ar), xenon (Xe), hydrogen (H), nitrogen (N), phosphorus (P), boron (B), and aluminum (Al) may be present in the amorphous layer.

[0015] The amorphous layer forming step may be a step of forming the amorphous layer by performing plasma implantation treatment on at least one of the surface of the first bonding target surface or the surface of the second bonding target surface.

[0016] The heat treatment step may be a step of maintaining the temperature of the bonded substrate at 1100°C to 2200°C.

[0017] Before the amorphous layer formation step or after the amorphous layer formation step, an ion implantation step may be provided in which hydrogen ions or helium ions are implanted into the first bonding target surface to form an ion implantation layer inside the first semiconductor substrate.

[0018] After the bonding step and before the heat treatment step, a peeling step may be provided. The peeling step may be a step of peeling a part of the first semiconductor substrate using a microbubble layer formed by heating the ion implantation layer as a peeling surface.

Effect of the Invention

[0019] According to the present invention, it is possible to provide a bonded semiconductor substrate and a method for manufacturing a bonded semiconductor substrate that can prevent the occurrence of peeling of the substrate from the bonding interface of the bonded semiconductor substrate.

Brief Description of the Drawings

[0020]

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Figure 11

Embodiments for Carrying Out the Invention

[0021] In this specification, a bonded semiconductor substrate and a method for manufacturing the bonded semiconductor substrate are disclosed. This bonded semiconductor substrate is a substrate obtained by bonding a first semiconductor substrate and a second semiconductor substrate. After amorphizing either one, or both, of the bonding target surfaces of the first semiconductor substrate and the second semiconductor substrate to form an amorphous layer (amorphous layer forming step), the amorphous layer of the first semiconductor substrate and the amorphous layer of the second semiconductor substrate are bonded (bonding step) to generate a bonded substrate having a bonding interface, and then a heat treatment (heat treatment step) is performed to form a wavy bonding interface, whereby it can be manufactured.

[0022] When two semiconductor substrates are directly joined without forming an amorphous layer, if the bonding strength at the bonding interface is low, even if the impact applied to the bonded substrate is a small impact, the bonded substrate will be peeled off at the bonding interface due to that impact. To prevent this peeling, by amorphizing either one or both of the bonding target surfaces of the first semiconductor substrate and the second semiconductor substrate, the atoms constituting the semiconductor in the amorphous layer are made more mobile. Then, by bonding the amorphous layers to form a wavy bonding interface, the bonding area between the first semiconductor substrate and the second semiconductor substrate increases at the bonding interface and the bonding strength becomes stronger, so that peeling at the bonding interface of the bonded semiconductor substrate can be prevented.

[0023] Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings.

[0024] [Bonded Semiconductor Substrate] The bonded semiconductor substrate includes a first semiconductor substrate and a second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are bonded via a bonding interface.

[0025] <Configuration of Bonded Semiconductor Substrate> FIG. 2 is a perspective view showing an example of the bonded semiconductor substrate of the present invention. The bonded semiconductor substrate 10 of the present invention is formed, for example, in a disk shape having an orientation flat. Note that the shape is not limited to a disk shape (wafer shape), and may be a polygonal shape. The bonded semiconductor substrate 10 shown in FIG. 2 includes a single crystal substrate 13 which is an example of a first semiconductor substrate and a support substrate 11 which is an example of a second semiconductor substrate, and the single crystal substrate 13 is bonded to the support substrate 11 and has a bonding interface 14.

[0026] The single crystal substrate 13 is, for example, a compound semiconductor (e.g., silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga 2 O 3) It may be any of single-element semiconductors (e.g., silicon (Si), carbon (C)), and diamond. These elements are semiconductor materials that can be used in fabricating semiconductor devices. Note that the above carbon (C) is other than diamond, for example, graphite, etc.

[0027] Various materials can be used for the support substrate 11. The support substrate 11 preferably has resistance to various thermal processes applied to the single-crystalline substrate 13. Also, the support substrate 11 is preferably a material with a small difference in thermal expansion coefficient from the single-crystalline substrate 13. For example, for the support substrate 11, any of silicon carbide (SiC), silicon (Si), carbon (C), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga 2 O 3 ), diamond, sapphire (Al 2 O 3 ), and quartz (SiO 2 ) etc. can be used.

[0028] For example, the single-crystalline substrate 13, which is an example of the first semiconductor substrate, may be a single-crystalline silicon carbide substrate (single-crystalline SiC substrate), and the support substrate 11, which is an example of the second semiconductor substrate, may be a polycrystalline silicon carbide substrate (polycrystalline SiC substrate).

[0029] As the single-crystalline SiC substrate, for example, a 4H-SiC single-crystalline substrate fabricated by the sublimation method can be used. The shape of the single-crystalline SiC substrate is, for example, a substantially disk shape with an orientation flat, and a substrate with a diameter of 4 to 8 inches can be used. Note that the shape is not limited to a disk shape (wafer shape) and may be a polygonal shape.

[0030] In addition, as the polycrystalline SiC substrate, SiC crystals of various polytypes and plane orientations may be mixed. A polycrystalline SiC substrate in which various polytypes and plane orientations are mixed can be manufactured without performing strict temperature control, so that the cost of manufacturing the support substrate 11 can be reduced. For example, a 3C-SiC polycrystalline substrate obtained by forming a SiC polycrystal film by chemical vapor deposition can be used. Further, the shape of the polycrystalline SiC substrate may be substantially the same as that of the single-crystalline SiC substrate. For example, a substantially disk-shaped substrate having an orientation flat and a diameter of 4 to 8 inches can be used. Note that the shape is not limited to a disk shape and may be a polygonal shape.

[0031] The thickness TT1 of the support substrate 11 may be determined so as to obtain a mechanical strength capable of withstanding the formation of the epitaxial layer and subsequent processing such as forming a semiconductor element or a semiconductor device thereon. For example, when the diameter of the support substrate 11 is 6 inches (150 mm), the thickness TT1 may be about 350 μm, and a substrate having a thickness TT1 of 300 to 500 μm can be used.

[0032] (Breaking strength) The bonded semiconductor substrate preferably has a breaking strength of 70 MPa or more in the direction perpendicular to the bonding interface by a stud pull test. In the examples described later, when the breaking strength of only the single-crystalline SiC substrate was measured by a stud pull test, it was less than 70 MPa. That is, the fact that the breaking strength is 70 MPa or more indicates that the bonded semiconductor substrate has a strong bonding force that does not peel off at the bonding interface with a strength less than 70 MPa.

[0033] When the breaking strength by the stud pull test is 70 MPa or more, it is possible to prevent peeling at the bonding interface in the process of growing an epitaxial film on the bonded semiconductor substrate and then manufacturing a semiconductor device, and also to prevent peeling at the bonding interface even after forming an electronic circuit, cutting it into a chip shape, and incorporating it into a mobile phone, a home appliance product, or an industrial device.

[0034] If the breaking strength by the stud pull test is 70 MPa or more, peeling at the bonding interface can be prevented. As will be described later, since it may break with the adhesive, the upper limit of the breaking strength is not particularly limited. However, in the case of a bonded semiconductor substrate where a single crystal SiC substrate and a polycrystalline SiC substrate are bonded, the breaking strength by the stud pull test is preferably in the range of 70 MPa to 90 MPa.

[0035] Here, the stud pull test is a test in which two stud pins are bonded to the surfaces of the first semiconductor substrate and the second semiconductor substrate of the bonded semiconductor substrate using an adhesive, and then these stud pins are pulled in a direction perpendicular to the bonding interface to break the bonded semiconductor substrate. By this test, the breaking strength at the time of breakage can be measured, and it can also be evaluated whether the bonded semiconductor substrate breaks in the first semiconductor substrate, the second semiconductor substrate, or at the bonding interface. Note that when the strength of the first semiconductor substrate and the second semiconductor substrate is large and the bonding strength of the bonding interface is also large, it may break with the adhesive. However, since a strong adhesive is used, it can be said that the bonded semiconductor substrate itself has sufficient strength without problems when it breaks with the adhesive.

[0036] (Roughness height of the bonding interface) In the manufacturing process of the bonded semiconductor substrate, the elements of the amorphous layer are recrystallized by the heat treatment process described later. At this time, since the elements move and recrystallize, a wavy bonding interface is formed. Due to the waviness of the bonding interface, the bonding area between the first semiconductor substrate and the second semiconductor substrate at the bonding interface increases and the bonding strength becomes stronger, so peeling at the bonding interface of the bonded semiconductor substrate can be prevented.

[0037] The undulation height of the bonding interface is 1.5 nm or more. If the undulation height is 1.5 nm or more, the bonding area between the first semiconductor substrate and the second semiconductor substrate increases, and the bonding strength of the bonding interface becomes stronger. The bonding strength of the bonding interface becomes greater than the breaking strength of the first semiconductor substrate or the second semiconductor substrate. The upper limit of the undulation height is not particularly limited. However, if the undulation height is 5 nm, the bonding strength can be sufficiently increased, and the bonding strength of the bonding interface becomes clearly greater than the breaking strength of the first semiconductor substrate or the second semiconductor substrate, so that peeling at the bonding interface can be reliably prevented.

[0038] [Method for manufacturing bonded semiconductor substrate] Next, as an example of a method for manufacturing a bonded semiconductor substrate including a first semiconductor substrate and a second semiconductor substrate of the present invention, a method for manufacturing a bonded semiconductor substrate 10 in which a support substrate 11 as the second semiconductor substrate is a polycrystalline SiC substrate and a single crystal substrate 13 as the first semiconductor substrate is a single crystal 4H-SiC substrate will be described. Here, a case where the bonded semiconductor substrate 10 is manufactured using a technique for peeling the single crystal substrate 13 by ablation of hydrogen atoms will be described with reference to a flowchart or the like showing an example of the method for manufacturing the bonded semiconductor substrate shown in FIG. 1.

[0039] First, the support substrate 11 and the single crystal substrate 13 are prepared. As the support substrate 11 and the single crystal substrate 13, those having a bonding target surface that has already been planarized can be obtained. The planarization may be performed by grinding or cutting, or may be performed by the CMP method. Also, the bonding target surface may be planarized by oneself.

[0040] 〈Hydrogen ion implantation step (step S0)〉 In step S0 of FIG. 1, a hydrogen ion implantation step of implanting hydrogen ions from the bonding target surface 13a of the single crystal substrate 13 is performed. When hydrogen ions are implanted into the single crystal substrate 13, the hydrogen ions reach a depth corresponding to the incident energy and are distributed at a high concentration. As a result, as shown in the side schematic view of FIG. 3, a hydrogen implantation layer 15 indicated by a dotted line is formed at a predetermined depth from the bonding target surface 13a. For example, the hydrogen implantation layer 15 is formed at a position about 0.6 μm deep from the bonding target surface 13a.

[0041] Helium may be ion-implanted instead of hydrogen to form a helium implantation layer, or hydrogen and helium may be alternately ion-implanted to form an implantation layer, and a similar peeling effect in the peeling process described later can be expected.

[0042] Note that the hydrogen ion implantation step is not an essential step in the present invention, and the single crystal substrate 13 after hydrogen ion implantation may be obtained by purchasing it, etc., and the present invention may be implemented using it.

[0043] In addition, the hydrogen ion implantation step can be adopted including, for example, the case where the second semiconductor substrate is a SiC polycrystalline substrate and the first semiconductor substrate is a SiC single crystal substrate, or the case where the first semiconductor substrate is a Si substrate and the second semiconductor substrate is a Si substrate, and it can be performed before or after the amorphous layer forming step described later.

[0044] 〈Amorphous layer forming step (step S1)〉 This step is a step of amorphizing at least one of the surface of the first bonding target surface, which is the surface of the first semiconductor substrate where it bonds to the second semiconductor substrate, or the surface of the second bonding target surface, which is the surface of the second semiconductor substrate where it bonds to the first semiconductor substrate, to form an amorphous layer. That is, it is a step of forming an amorphous layer on at least one of the bonding target surface 11a or the bonding target surface 13a. When an amorphous layer is formed on the bonding target surface 11a and no amorphous layer is formed on the bonding target surface 13a, when no amorphous layer is formed on the bonding target surface 11a and an amorphous layer 12 is formed on the bonding target surface 13a, and when amorphous layers are formed on both the bonding target surface 11a and the bonding target surface 13a can be mentioned.

[0045] The amorphous layer aims to increase the bonding strength between the single-crystalline substrate 13 and the support substrate 11 by forming a wavy bonding interface 14, thereby increasing the bonding area between the single-crystalline substrate 13 and the support substrate 11 at the bonding interface 14 to be stronger than the breaking strength of the single-crystalline substrate 13. Therefore, when forming the amorphous layer on the bonding target surface 11a, it is preferable to form the amorphous layer on the entire surface of the bonding target surface 11a. When forming the amorphous layer on the bonding target surface 13a, it is preferable to form the amorphous layer on the entire surface of the bonding target surface 13a.

[0046] The thickness of the amorphous layer formed in the amorphous layer forming step is 5 nm or more. By setting the thickness of the amorphous layer to 5 nm or more, a bonding interface 14 with large undulations can be formed by the heat treatment step, and the bonding area between the single-crystalline substrate 13 and the support substrate 11 at the bonding interface 14 can be further increased. Therefore, the bonding strength between the single-crystalline substrate 13 and the support substrate 11 can be made stronger than the breaking strength of the single-crystalline substrate 13.

[0047] The upper limit of the thickness of the amorphous layer is not particularly limited, but depending on the performance of the apparatus for forming the amorphous layer, for example, 50 nm serves as a guideline for the upper limit of the thickness of the amorphous layer.

[0048] Hereinafter, as an example, the case where the amorphous layer 12 is formed on the bonding target surface 13a without forming the amorphous layer on the bonding target surface 11a will be described.

[0049] In FIG. 1, in step S1, the amorphous layer 12 is formed on the bonding target surface 13a of the single-crystalline substrate 13. The amorphous layer 12 only needs to be a layer in which the regularity of the element arrangement is absent, that is, it is not a crystal and the elements are arranged irregularly.

[0050] To form the amorphous layer 12, it is preferable to adopt plasma injection using a plasma injector. As shown in FIG. 4, the amorphous layer 12 can be effectively formed on the bonding target surface 13a by the plasma injector. Further, if a plasma injector is used, it is possible to easily control the depth of plasma injection and the like by the acceleration voltage, the dose amount, and the like.

[0051] Examples of the element of the ion injected by the plasma injector include silicon (Si), carbon (C), helium (He), neon (Ne), argon (Ar), xenon (Xe), hydrogen (H), nitrogen (N), phosphorus (P), boron (B), and aluminum (Al). As a result, when an amorphous layer is formed by the plasma injector, at least any one of silicon (Si), carbon (C), helium (He), neon (Ne), argon (Ar), xenon (Xe), hydrogen (H), nitrogen (N), phosphorus (P), boron (B), and aluminum (Al) may be present in the amorphous layer.

[0052] As an example of an embodiment of the amorphous layer forming step of the present invention, when nitrogen (N) is used as the plasma element used for forming the amorphous layer 12, specifically, the single crystal substrate 13 is placed on the plasma injector, and nitrogen (N) ions are injected using the plasma injector onto the surface of the bonding target surface 13a of the single crystal substrate 13, and then the amorphous layer 12 is formed on the surface layer of the single crystal substrate 13 (FIG. 4).

[0053] FIGS. 8(a) to (c) show observation images obtained by observing a cross section of the amorphous layer 12 formed by plasma-injecting nitrogen (N) at room temperature onto the bonding target surface 13a of the single crystal substrate 13 with a transmission electron microscope (TEM). In FIGS. 8(a) to (c), the injection temperature is room temperature, the voltage is 6 kV, and the dose amounts are 7.0×10 14 / cm 2 for FIG. 8(a), 3.5×10 15 / cm 2 for FIG. 8(b), and 7.0×10 15 / cm 2 for FIG. 8(c).

[0054] Since the amorphous layer 12 has no regularity in the arrangement of the constituent elements and the elements are arranged irregularly, the contrast of the TEM observation image is different from that of the single-crystalline substrate 13 in which the elements are regularly arranged, and the color becomes lighter than that of the single-crystalline substrate 13. Further, within the amorphous layer 12, since there is no diffraction contrast due to crystals and the color tone is uniform, the amorphous layer 12 and the single-crystalline substrate 13 can be visually distinguished and observed.

[0055] The region at a predetermined depth from the bonding target surface 13a in FIGS. 8(a) to 8(c) is a region with a uniform and light color tone compared to the underlying single-crystalline substrate 13, and this region is the amorphous layer 12 formed by nitrogen (N) plasma implantation. The depth of the amorphous layer 12 is 9 nm to 18 nm, and it is recognized that the amorphous layer tends to become deeper as the dose amount of nitrogen (N) increases.

[0056] When plasma-implanting nitrogen (N), the acceleration voltage can be set within the range of 0.1 to 1000 kV. For example, the plasma implantation process may be performed by controlling the acceleration voltage and the like so that the concentration of nitrogen (N) is maximized at the bonding target surface 13a of the single-crystalline substrate 13.

[0057] By forming such an amorphous layer 12 in advance, the elements in the amorphous layer 12 can easily move in the subsequent heat treatment process, so that a wavy bonding interface 14 can be formed.

[0058] FIGS. 9(a) to 9(c) also show observation images obtained by observing a cross-section of the amorphous layer 12 formed by plasma-implanting phosphorus (P) at room temperature on the bonding target surface 13a of the single-crystalline substrate 13 with a transmission electron microscope (TEM). In FIGS. 9(a) to 9(c), the implantation temperature is room temperature, the voltage is 10 kV, and the dose amounts are 3.6×10 14 / cm 2 in FIG. 9(a), 3.6×10 15 / cm 2 in FIG. 9(b), and 3.6×10 16 / cm 2 in FIG. 9(c).

[0059] The region at a predetermined depth from the bonding target surface 13a in FIGS. 9(a) to 9(c) is a region with a uniform and light color compared to the single-crystalline substrate 13 which is the base, and this region is the amorphous layer 12 formed by phosphorus (P) plasma implantation. The depth of the amorphous layer 12 is 8 nm to 30 nm, and as the dose amount of phosphorus (P) increases, the amorphous layer tends to become deeper.

[0060] Note that the method for forming the amorphous layer 12 is not limited to plasma implantation using a plasma implanter. For example, appropriate conditions may be set so that the amorphous layer 12 is formed on the bonding target surface 13a using an ion implantation device or the like to form the amorphous layer 12. However, since the plasma implantation method has a high injection current density of elements, if the same amount of elements is to be injected, the injection time can be shortened, and it is an injection method with high productivity. Therefore, by adopting the plasma implantation method, an amorphous layer 12 with a sufficient thickness can be efficiently formed.

[0061] 〈Irradiation step (step S2)〉 This step is a step of irradiating the first bonding target surface or the second bonding target surface with an argon beam after the amorphous layer forming step and before the bonding step. That is, it is a step of irradiating the bonding target surface 11a or the bonding target surface 13a with an argon beam, and the bonding target surface 11a and the bonding target surface 13a may both be irradiated with an argon beam.

[0062] In step S2 of FIG. 1, the irradiation step is performed. As shown in FIG. 5, the single-crystalline substrate 13 and the support substrate 11 are set in the chamber 101. Next, alignment of the relative positions of the single-crystalline substrate 13 and the support substrate 11 is performed. The alignment is performed so that the two substrates can come into contact in the correct positional relationship in the bonding step described later. Next, the inside of the chamber 101 is evacuated. The degree of vacuum inside the chamber 101 may be, for example, about 1×10 -4 ~1×10 -6 Pa.

[0063] Next, a neutral element beam 103 of argon (Ar) is irradiated onto the bonding target surface 11a of the support substrate 11 and the bonding target surface 13a of the single crystal substrate 13 using a first atomic beam gun (FAB gun) 102. The neutral element beam of argon (Ar) is uniformly irradiated onto the entire surface of the bonding target surface 11a and the entire surface of the bonding target surface 13a. Thereby, the oxide film and the adsorption layer on the bonding target surface 11a and the bonding target surface 13a can be removed to expose the bonding hands. This state is called an active state. Further, since the irradiation process is a process performed in a vacuum, the bonding target surface 11a and the bonding target surface 13a can be kept in an active state without being oxidized or the like.

[0064] Note that the irradiation process is not an essential process, and it is a process that can be omitted if the single crystal substrate 13 and the support substrate 11 can be bonded by a bonding process described later to form a bonded semiconductor substrate without problems. The irradiation process is a process of removing the oxide film and the adsorption layer on the surface by the sputtering phenomenon by colliding atoms or molecules with the surface. Instead of this process, a process of chemically reacting with the surface contaminants by a reactive gas and removing them by etching can be performed. Also, for adsorbates that are easy to sublimate, the adsorbates can be removed by sublimation simply by applying heat or light. By these processes instead of the irradiation process, the oxide film and the adsorption layer on the bonding target surface can be removed to expose the bonding hands.

[0065] 〈Bonding Process (Step S3)〉 This process is a process of bonding the first bonding target surface and the second bonding target surface after the amorphous layer forming process to form a bonded substrate having a bonding interface.

[0066] In step S3 of FIG. 1, a bonding process is performed. In the bonding process, the bonding target surface 11a of the support substrate 11 and the bonding target surface 13a of the single crystal substrate 13 are brought into contact with each other in a vacuum within the chamber 101. Then, the bonds existing on the active bonding target surface 11a and the bonding target surface 13a are connected to each other, and the support substrate 11 and the single crystal substrate 13 can be bonded. As a result, as shown in the schematic diagram of FIG. 6, a structure in which the support substrate 11 and the single crystal substrate 13 are bonded is formed.

[0067] 〈Peeling Process (Step S4)〉 This process is a process that can be performed after the bonding process and before the heat treatment process. When heat is applied during the peeling process, a microbubble layer is formed in the hydrogen implantation layer 15, and a part of the single crystal substrate 13 is peeled off using the microbubble layer as a peeling surface. That is, the single crystal substrate 13 is peeled off using the hydrogen implantation layer 15 in which the microbubble layer is formed in the single crystal substrate 13 as a peeling surface.

[0068] In step S4 of FIG. 1, a peeling process is performed. Specifically, the support substrate 11 and the single crystal substrate 13 bonded to each other are heated to about 800°C or higher. The atmosphere during peeling may be at least one of an inert gas such as argon (Ar) or nitrogen (N), or a vacuum. The degree of vacuum may be, for example, about 1×10 -4 ~1×10 -6 Pa. The peeling may be performed using rapid thermal annealing (RTA) or a furnace. As a result, the single crystal substrate 13 can be separated by the hydrogen implantation layer 15. Therefore, as shown in the schematic diagram of FIG. 7, a bonded substrate 30 having a structure in which a thin single crystal substrate 13 with a thickness of, for example, 0.6 μm is bonded on the support substrate 11 can be formed.

[0069] 〈Heat Treatment Process (Step S5)〉 This process is a process of heat-treating the bonded substrate to make the undulation height of the bonding interface 1.5 nm or more. The bonded semiconductor substrate 10 is completed by the heat treatment process.

[0070] In step S5 of FIG. 1, a heat treatment process is performed. In the heat treatment process, the bonded substrate 30 including the support substrate 11, the amorphous layer 12, and the single crystal substrate 13 is heat treated. The heat treatment temperature may be set such that the temperature of the bonded substrate 30 is 1100°C to 2200°C, preferably 1600°C to 1800°C, and more preferably about 1700°C. When the heat treatment temperature (i.e., the temperature of the bonded substrate 30) is 1100°C to 2200°C, the undulation height of the bonding interface can be made 1.5 nm or more without problems. If the heat treatment temperature is less than 1100°C, the undulation height may be less than 1.5 nm. Further, if the heat treatment temperature exceeds 2200°C, there is a risk that the material of the substrate will sublime and cause roughness on the surface of the bonded substrate 30.

[0071] The atmosphere of the heat treatment may be at least one of an inert gas such as argon (Ar) or nitrogen (N), or a vacuum. The degree of vacuum may be, for example, about 1×10 -4 ~1×10 -6 Pa. The heat treatment process may be performed in the furnace where the peeling process has been performed. Also, if the heat treatment temperature is maintained for 1 minute or more, the undulation height of the bonding interface can be made 1.5 nm or more. Note that the upper limit of the holding time of the heat treatment temperature is not particularly limited, but for example, 100 hours may be set as the upper limit of the holding time in consideration of manufacturing efficiency. For example, the holding time of the heat treatment temperature can be set between 1 minute and 10 hours.

[0072] Also, although the undulation height of the bonding interface varies depending on the thickness of the amorphous layer, the heat treatment temperature, and the holding time of the heat treatment temperature, if the upper limit of the undulation height is 5 nm, the object of the present invention can be sufficiently achieved.

[0073] The bonded semiconductor substrate manufactured by the above manufacturing method has a fracture strength of 70 MPa or more in the direction perpendicular to the bonding interface in a stud pull test. When the fracture strength of only the single crystal SiC substrate is measured by the stud pull test, it is less than 70 MPa. That is, the fact that the fracture strength is 70 MPa or more indicates that the bonded semiconductor substrate does not peel at the bonding interface, and the bonding interface shows the result that the single crystal SiC substrate breaks while maintaining the bonded state.

[0074] Since the fracture strength by the stud pull test is 70 MPa or more, an epitaxial film can be grown on the bonded semiconductor substrate, and peeling at the bonding interface in the process until a semiconductor device is manufactured thereafter can be prevented. Also, even after an electronic circuit is formed, cut into chip form, and incorporated into a mobile phone, home appliance, or industrial equipment, peeling at the bonding interface can be prevented.

[0075] If the fracture strength by the stud pull test is 70 MPa or more, peeling at the bonding interface can be prevented, so the upper limit of the fracture strength is not particularly limited. However, in the case of a substrate in which a single crystal SiC substrate and a polycrystalline SiC substrate are bonded, the fracture strength by the stud pull test is in the range of 70 MPa to 90 MPa.

[0076] <Modification Example> As described above in detail for one embodiment of the present invention, these are merely examples and do not limit the scope of the present invention. For example, as described below, the present invention includes various modifications and changes of the specific examples exemplified above.

[0077] As the element used for forming the amorphous layer 12, silicon (Si) may be used as an element other than nitrogen (N) and phosphorus (P). In this case, the composition ratio of the elements at the bonding interface 14 is such that the ratio of silicon is more than that of carbon, and the bonding interface 14 is composed of SiC rich in silicon. For example, the composition ratio of silicon and carbon at the bonding interface 14 is Si:C = 50 - 60 atomic%:40 - 50 atomic%.

[0078] Also, the element used to form the amorphous layer 12 may be carbon (C). In this case, the composition ratio of the elements at the bonding interface 14 will be such that the proportion of carbon is higher than that of silicon, and the bonding interface 14 will be composed of SiC rich in carbon. For example, the composition ratio of carbon will be in the range of 50 to 60 atomic%.

[0079] Also, the element used to form the amorphous layer 12 may be an element that is unlikely to become a carrier and has a high efficacy in forming the amorphous layer 12. For example, at least one of noble gases such as helium (He), neon (Ne), argon (Ar), xenon (Xe), or hydrogen (H) may be used.

[0080] Also, the element used to form the amorphous layer 12 may be an element that is likely to become a carrier and is likely to be amorphized. For example, in addition to nitrogen (N) and phosphorus (P) that have already appeared, boron (B) and aluminum (Al) can be mentioned, and at least one of these four elements may be used. In particular, using an element with a large mass such as P is more likely to break the crystal structure and amorphize than when using an element with a small mass.

[0081] The amorphous layer formation step (step S1) may be performed between the peeling step (step S4) and the heat treatment step (step S5). In this case, ions may be injected from the surface of the single crystal substrate 13 toward the bonding interface by the ion implantation method. At that time, various parameters in the ion implantation conditions such as the acceleration energy and the incident angle may be set so that the ions are maximized in the vicinity of the bonding interface. For example, by using a multi-step implantation method in which the acceleration energy is changed and the ion implantation is performed multiple times, the ion concentration may be controlled so that it is maximized in the vicinity of the bonding interface.

[0082] Further, in the present invention, after the heat treatment step (step S5), a single crystal layer having a required thickness may be formed by epitaxial growth on the single crystal substrate 13. This epitaxial layer becomes a region where various elements such as semiconductor elements, which are components of an electronic circuit, are formed. The thickness of the epitaxial layer required for forming various elements is not particularly limited. For example, when the epitaxial layer is single crystal SiC, it is generally 5 μm or more.

[0083] Also, when using SiC for the single crystal substrate 13, it is not limited to a single crystal of 4H-SiC. Various polytypes of single crystal SiC such as 3C-SiC and 6H-SiC can be used as the single crystal substrate 13. Further, when using polycrystalline SiC for the support substrate 11, it is not limited to polycrystalline 3C-SiC. It is possible to use various polytypes of polycrystalline SiC.

Example

[0084] Hereinafter, examples of the present invention will be shown and described more specifically, but the present invention is not limited to the following examples at all.

[0085] [Example 1] 〈Manufacture of bonded semiconductor substrate 10〉 As the single crystal substrate 13, a 4H-SiC single crystal substrate having a diameter of 6 inches, produced by the sublimation method, was used. As the support substrate 11, a 3C-SiC polycrystalline substrate having a diameter of 6 inches, obtained by depositing SiC polycrystal by chemical vapor deposition, was used. First, before the hydrogen ion implantation step, the bonding target surfaces 11a and 13a of the single crystal substrate 13 and the support substrate 11 were subjected to mirror polishing and cleaning.

[0086] (Hydrogen ion implantation step S0) Hydrogen ions were implanted into the bonding target surface 13a of the single crystal substrate 13 to a position about 0.6 μm deep from the bonding target surface 13a to form a hydrogen implantation layer 15. It is a layer that forms microbubbles and peels off due to the heat applied in the subsequent peeling step S5.

[0087] (Amorphous layer formation step S1) The single crystal substrate 13 was placed in a plasma injector (manufactured by ULVAC), and nitrogen (N) ions were implanted into the entire bonding target surface 13a of the single crystal substrate 13 to form an amorphous layer 12 with a thickness of 6 nm on the entire bonding target surface 13a. The plasma implantation conditions were such that the gas was N 2 , the plasma power supply output for nitrogen ion generation was kept constant, the plasma implantation temperature was room temperature (23 °C), the acceleration voltage of the implanted ions was 6 kV, and the dose amount was 5.5×10 14 / cm 2 .

[0088] (Irradiation step S2) The bonding target surfaces 11a and 13a were subjected to mirror polishing and cleaning, and then, the bonding target surface 11a and the bonding target surface 13a were irradiated with an argon beam.

[0089] Specifically, as shown in FIG. 5, the single crystal substrate 13 and the support substrate 11 were set in the chamber 101, and the alignment of the relative positions of the single crystal substrate 13 and the support substrate 11 was performed. Next, the inside of the chamber 101 was evacuated to a vacuum degree of 1×10 -4 ~1×10 -6 Pa.

[0090] Next, using the FAB gun 102, the bonding target surface 11a of the support substrate 11 and the bonding target surface 13a of the single crystal substrate 13 were irradiated with a neutral element beam of argon. The neutral element beam of argon was uniformly irradiated on the entire bonding target surface 11a and the entire bonding target surface 13a.

[0091] (Bonding step S3) After the irradiation step, the activated bonding target surface 11a of the support substrate 11 and the bonding target surface 13a of the single crystal substrate 13 were brought into contact with each other in the chamber 101 while maintaining the vacuum state, and further pressurized to obtain a bonded substrate of the support substrate 11 and the single crystal substrate 13.

[0092] (Peeling step S4) Using a furnace, the bonding substrate was heated in an inert atmosphere filled with nitrogen gas, and the single crystal substrate 13 was separated by the hydrogen implantation layer 15 to form a bonded substrate 30 in which a thin single crystal substrate 13 with a thickness of 0.6 μm was bonded.

[0093] (Heat treatment step S5) After the peeling step, the bonded substrate 30 was heated at 1700 °C in an inert atmosphere filled with argon gas in the furnace to recrystallize the amorphous layer 12, and a bonded semiconductor substrate 10 was obtained.

[0094] 〈Evaluation of the bonded semiconductor substrate 10〉 (Measurement of the undulation height of the bonding interface 14) The bonded semiconductor substrate 10 was cut so that the undulation height of the bonding interface 14 between the support substrate 11 and the single crystal substrate 13 could be confirmed, and the cut surface was observed with a transmission electron microscope (TEM). Fig. 10 shows the TEM observation image of the cut surface. The observation direction of the cross section by TEM is [1-100] in Miller indices. According to Fig. 10, it was observed that the support substrate 11 and the single crystal substrate 13 were bonded in a state of being completely in contact without a gap at the bonding interface 14. The bonding interface 14 was not linear but was a curved shape with a wide undulation as shown by the dotted line in Fig. 10. The width indicated by the dotted line is the undulation width of the bonding interface 14, and when this is taken as the undulation height, the undulation height was 1.5 nm.

[0095] The undulation height of the bonding interface 14 was calculated as follows. First, six points, namely three points at the top of the undulation and three points at the bottom of the undulation, were selected on the undulating curve with a length of 50 nm of the bonding interface 14 in the TEM observation image of the cut surface. Next, the slope was calculated using the least squares method at these six points, and with the slope fixed, the least squares method was used to calculate for the straight line of the three points at the top of the undulation and the straight line of the three points at the bottom of the undulation, and the difference in the intercepts was taken as the undulation height.

[0096] (Measurement of the fracture strength by the stud pull test) To confirm that the peel strength of the bonding interface 14 of the bonded semiconductor substrate 10 having the undulations observed in FIG. 10 is greater than the fracture strength of the single crystal substrate 13, a stud pull test was conducted.

[0097] First, a chip with a length of 10 mm and a width of 10 mm was cut out from the bonded semiconductor substrate 10 and used as a test piece. As shown in FIG. 11, the surface of the single crystal substrate 13 in the test piece and the stud pin 50 were bonded with an adhesive 40, and the surface of the support substrate 11 and the stud pin 51 were bonded with an adhesive 41. After the adhesives 40 and 41 were cured, using a precision universal testing machine AGX-50kNVD (manufactured by Shimadzu Corporation), each of the stud pins 50 and 51 was pulled in the directions of P1 and P2, thereby pulling and breaking the bonded semiconductor substrate 10 in a direction perpendicular to the bonding interface 14. Eight test pieces were prepared and the stud pull test was performed eight times. By the stud pull test, the load at the time of fracture of the bonded semiconductor substrate 10 was measured as the maximum point load. Then, the maximum point stress was the value obtained by dividing the maximum point load by the area of the surface where the stud pin 50 contacts the adhesive 40, and the average value of the maximum point stresses in the eight tests was taken as the fracture strength. Also, it was confirmed which of the support substrate 11, the bonding interface 14, and the single crystal substrate 13 the fractured part was.

[0098] Also, as a comparison target, a stud pull test was similarly performed using only the single crystal substrate 13 to break the single crystal substrate 13, and the average value of the maximum point stresses calculated from the eight measurements was taken as the fracture strength.

[0099] (Results of the stud pull test) The bonded semiconductor substrate 10 was broken by the polycrystalline substrate 11, and the bonding interface 14 after the stud pull test maintained a good bonding state without peeling. The fracture strength of the bonded semiconductor substrate 10 was 75.0 MPa. Also, the in-plane distribution of the maximum point stress of the bonded semiconductor substrate 10 was equivalent when comparing the center of the substrate and the end of the substrate, and no decrease in the maximum point stress due to the part of the substrate was observed.

[0100] On the other hand, the breaking strength of the single crystal substrate 13 was 64.8 MPa. The reason why the breaking strength of the single crystal substrate 13 became smaller than that of the bonded semiconductor substrate 10 is considered to be that in the case of the single crystal substrate 13, starting from the crack existing at the substrate end, the crack extended along the crystal plane and broke.

[0101] [Example 2] The amorphous layer formation process was carried out under the same conditions as in Example 1. An amorphous layer 12 with a thickness of 6 nm was formed on the entire bonding target surface 13a of the single crystal substrate 13, and an amorphous layer 12 with a thickness of 6 nm was formed on the entire bonding target surface 11a of the support substrate 11. The other processes were carried out under the same conditions as in Example 1 to manufacture a bonded semiconductor substrate.

[0102] Similar to Example 1, the cross-section was observed with a transmission electron microscope (TEM) and the undulation height of the bonding interface was measured. As a result, the undulation height was 3.0 nm. It was confirmed that increasing the thickness of the amorphous layer also increased the undulation height.

[0103] [Effect] In the present invention, by making either one or both of the bonding target surface 11a of the support substrate 11 and the bonding target surface 13a of the single crystal substrate 13 amorphous, the atoms constituting the substrate are made more mobile, and by forming a wavy bonding interface, the bonding area between the support substrate 11 and the single crystal substrate 13 increases and the bonding strength becomes stronger. Therefore, peeling at the bonding interface can be prevented.

[0104] [Summary] As described above, according to the present invention, a bonded semiconductor substrate capable of preventing peeling at the bonding interface and a method for manufacturing the bonded semiconductor substrate can be provided, which is industrially useful. [Explanation of Signs]

[0105] 10: Bonded semiconductor substrate, 11: Support substrate, 11a: Bonding target surface, 12: Amorphous layer, 13: Single crystal substrate, 13a: Bonding target surface, 14: Bonding interface, 15: Hydrogen implantation layer, 30: Bonded substrate, 40: Adhesive layer, 41: Adhesive layer, 50: Stud pin, 51: Stud pin, 101: Chamber, 102: FAB gun, 103: Neutral element beam, P1: Direction, P2: Direction

Claims

1. A bonded semiconductor substrate comprising a first semiconductor substrate and a second semiconductor substrate bonded via a bonding interface, wherein the bonded semiconductor substrate has a surface roughness height of the bonding interface of 1.5 nm or more.

2. The bonded semiconductor substrate according to claim 1, wherein the breaking strength by a stud pull test in a direction perpendicular to the bonding interface is 70 MPa or more.

3. The first semiconductor substrate and the second semiconductor substrate are any one of silicon carbide (SiC), silicon (Si), carbon (C), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga ２ O ３ ), and diamond. The bonded semiconductor substrate according to claim 1.

4. The bonded semiconductor substrate according to claim 1, wherein the first semiconductor substrate is a single crystal silicon carbide substrate and the second semiconductor substrate is a polycrystalline silicon carbide substrate.

5. A method for manufacturing a bonded semiconductor substrate comprising a first semiconductor substrate and a second semiconductor substrate in contact with the first semiconductor substrate, the method comprising: an amorphous layer forming step of amorphizing at least one of the surface of a first bonding target surface which is the surface of the first semiconductor substrate where the first semiconductor substrate is to be bonded to the second semiconductor substrate, or the surface of a second bonding target surface which is the surface of the second semiconductor substrate where the second semiconductor substrate is to be bonded to the first semiconductor substrate, to form an amorphous layer; a bonding step of bonding the first bonding target surface and the second bonding target surface to form a bonded substrate having a bonding interface; a heat treatment step of heat treating the bonded substrate to make the surface roughness height of the bonding interface 1.5 nm or more, wherein the method for manufacturing a semiconductor substrate, wherein the thickness of the amorphous layer formed in the amorphous layer forming step is 5 nm or more.

6. The first semiconductor substrate and the second semiconductor substrate are any one of silicon carbide (SiC), silicon (Si), carbon (C), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga ２ O ３ ), and diamond. The method for manufacturing a bonded semiconductor substrate according to claim 5.

7. The method for manufacturing a bonded semiconductor substrate according to claim 5, wherein at least one of silicon (Si), carbon (C), helium (He), neon (Ne), argon (Ar), xenon (Xe), hydrogen (H), nitrogen (N), phosphorus (P), boron (B), and aluminum (Al) is present in the amorphous layer.

8. The method for manufacturing a bonded semiconductor substrate according to claim 5, wherein the amorphous layer forming step is a step of forming the amorphous layer by performing plasma implantation treatment on at least one of the surface of the first bonding target surface or the surface of the second bonding target surface.

9. The method for manufacturing a bonded semiconductor substrate according to claim 5, wherein the heat treatment step is a step of maintaining the temperature of the bonded substrate at 1100°C to 2200°C.

10. Before the amorphous layer forming step or after the amorphous layer forming step, an ion implantation step of implanting hydrogen ions or helium ions into the first bonding target surface to form an ion implantation layer inside the first semiconductor substrate is provided. The method for manufacturing a bonded semiconductor substrate according to claim 5.

11. After the bonding step and before the heat treatment step, a peeling step is provided. The peeling step is a step of peeling a part of the first semiconductor substrate using a microbubble layer formed by heating the ion implantation layer as a peeling surface. The method for manufacturing a bonded semiconductor substrate according to claim 10.

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