Semiconductor integrated circuit device

Abstract

To provide a semiconductor integrated circuit device capable of correcting a reference of reset release before the reset release by a power-on reset circuit is executed.SOLUTION: A semiconductor integrated circuit device (1) includes: a reference voltage source (100) configured to output a reference voltage; and a nonvolatile memory device (103) configured to store correction data for correcting a value of the reference voltage in a nonvolatile manner, and to output the correction data before a power-on reset circuit (101) performs reset release based on the reference voltage at the time of power-on. The reference voltage source is configured to correct a value of the reference voltage based on the correction data.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The invention disclosed in this specification relates to a semiconductor integrated circuit device.

Background Art

[0002] Semiconductor integrated circuit devices such as IC (Integrated Circuit), LSI (Large Scale Integrated circuit), CPU (Central Processing Unit), and DSP (Digital Signal Processor) are driven by a power supply voltage supplied from the outside. If the power supply voltage supplied from the outside is too low, the operation of the powered circuit driven by the power supply voltage becomes unstable. Therefore, a power-on reset circuit is implemented in many semiconductor integrated circuit devices (see, for example, Patent Document 1).

[0003] When the power supply voltage is lower than the threshold value (release voltage), the power-on reset circuit stops the powered circuit (power-down) so as not to consume unnecessary power and resets the powered circuit. When the power supply voltage exceeds the threshold value, the power-on reset circuit releases the reset state (reset release) of the powered circuit.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] [Summary] If the accuracy of the threshold value in the power-on reset circuit is low, there is a possibility that the power-on reset circuit cannot appropriately execute the reset release of the powered circuit.

[0006] The semiconductor integrated circuit device disclosed in this specification includes a reference voltage source configured to output a reference voltage, and a non-volatile memory device configured to non-volatily store correction data for correcting the value of the reference voltage and output the correction data before a power-on reset circuit releases the reset based on the reference voltage when the power is turned on. The reference voltage source is configured to correct the value of the reference voltage based on the correction data.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

[0008] [Detailed Description] In this specification, a MOS (Metal Oxide Semiconductor) field effect transistor refers to a transistor whose gate structure consists of at least three layers: "a layer made of a conductor or a semiconductor such as polysilicon with a small resistance value", "an insulating layer", and "a P-type, N-type, or intrinsic semiconductor layer". That is, the gate structure of a MOS field effect transistor is not limited to a three-layer structure of metal, oxide, and semiconductor. Hereinafter, an N-channel MOS field effect transistor is referred to as an NMOS transistor, and a P-channel MOS field effect transistor is referred to as a PMOS transistor.

[0009] <Semiconductor integrated circuit device> FIG. 1 is a diagram showing the configuration of a semiconductor integrated circuit device according to an embodiment. The semiconductor integrated circuit device 1 shown in FIG. 1 includes a reference voltage source 100, a power-on reset circuit 101, a digital circuit 102, a non-volatile memory device 103, and a latch circuit 104.

[0010] The reference voltage source 100 generates a reference voltage Vref and outputs the reference voltage Vref to the power-on reset circuit 101 and the non-volatile memory device 103 respectively. The reference voltage source 100 receives correction data and corrects (adjusts) the value of the reference voltage Vref based on the correction data.

[0011] The reference voltage source 100 has a configuration including, for example, a voltage source VS1 that varies the output voltage based on correction data, and an operational amplifier OP1. The ground potential is applied to the negative electrode of the voltage source VS1. The positive electrode of the voltage source VS1 is connected to the non-inverting input terminal of the operational amplifier OP1. The inverting input terminal of the operational amplifier OP1 is connected to the output terminal of the operational amplifier OP1. The reference voltage Vref is output from the output terminal of the operational amplifier OP1. The power supply voltage VDD is applied to the positive power supply terminal of the operational amplifier OP1. The ground potential is applied to the negative power supply terminal of the operational amplifier OP1. The enable terminal of the operational amplifier OP1 receives an enable signal EN2. The operational amplifier OP1 is in an enabled state when the enable signal EN2 is at a high level, and the operational amplifier OP1 is in a disabled state when the enable signal EN2 is at a low level.

[0012] The reference voltage source 100 is not limited to the configuration example shown in FIG. 1. The reference voltage source 100 may have a configuration including, for example, a voltage source that outputs a fixed-value output voltage, an operational amplifier, a fixed resistor provided between the output terminal and the inverting input terminal of the operational amplifier, and a variable resistor provided between the ground potential and the inverting input terminal of the operational amplifier and having a variable resistance value based on correction data.

[0013] When the power supply voltage VDD is lower than the threshold value, the power-on reset circuit 101 stops the digital circuit 102 and resets the digital circuit 102. When the power supply voltage VDD exceeds the threshold value, the power-on reset circuit 101 releases the reset state of the digital circuit 102.

[0014] The power-on reset circuit 101 has a configuration including, for example, a comparator COMP1, resistors R1 and R2. A power supply voltage VDD is applied to the first terminal of resistor R1. The second terminal of resistor R1 and the first terminal of resistor R2 are connected to the non-inverting input terminal of comparator COMP1. Therefore, the non-inverting input terminal of comparator COMP1 receives a voltage division of the power supply voltage VDD. The inverting input terminal of comparator COMP1 receives a reference voltage Vref. A power-on reset signal XPOR is output from the output terminal of comparator COMP1. The power-on reset circuit 101 sets the power-on reset signal XPOR to a low level when the power supply voltage VDD is lower than the threshold value, and sets the power-on reset signal XPOR to a high level when the power supply voltage VDD is higher than the threshold value. The positive power supply terminal of comparator COMP1 is applied with the power supply voltage VDD. The negative power supply terminal of comparator COMP1 is applied with the ground potential. The enable terminal of comparator COMP1 receives an enable signal EN2. Comparator COMP1 is in an enabled state when the enable signal EN2 is at a high level, and comparator COMP1 is in a disabled state when the enable signal EN2 is at a low level.

[0015] The digital circuit 102 receives an enable signal EN1 supplied from outside the semiconductor integrated circuit device 1. The digital circuit 102 is in an enabled state when the enable signal EN1 is at a high level, and the digital circuit 102 is in a disabled state when the enable signal EN1 is at a low level. The positive power supply terminal of the digital circuit 102 is applied with the power supply voltage VDD. The negative power supply terminal of the digital circuit 102 is applied with the ground potential.

[0016] The digital circuit 102 includes an AND gate A1, AND gates AN1 and AN2, a delay circuit DLY1, and a digital signal processing circuit (not shown). The AND gate A1, AND gates AN1 and AN2, and the delay circuit DLY1 operate even when the enable signal EN1 is at a low level. Also, the AND gate A1, AND gates AN1 and AN2, and the delay circuit DLY1 operate even when the power-on reset signal XPOR is at a low level.

[0017] The AND gate A1 generates an enable signal EN2 which is the logical product of the enable signal EN1 and the signal S1, and outputs the enable signal EN2 to the operational amplifier OP1 and the comparator COMP1 respectively. The signal S1 is a signal that becomes high level, for example, when an abnormality occurs in the digital circuit 102. Note that the AND gate A1 may be omitted and the enable signal EN2 may be the same signal as the enable signal EN1.

[0018] The delay circuit DLY1 generates a delay signal D1 obtained by delaying the power-on reset signal XPOR by a first delay time, and a delay signal D2 obtained by delaying the power-on reset signal XPOR by a second delay time. The second delay time is set longer than the first delay time. The delay circuit DLY1 outputs the delay signal D1 to the latch circuit 104 and outputs the delay signal D2 to the AND gate AN1. The AND gate AN1 outputs the logical product of the power-on reset signal XPOR and the delay signal D2. The AND gate AN2 outputs an enable signal EN3, which is the logical product of the output signal of the AND gate AN1 and the enable signal EN1, to the non-volatile memory device.

[0019] The non-volatile memory device 103 stores non-volatilely correction data Sout1 to Soutk for correcting the value of the reference voltage Vref. When the correction data Sout1 to Soutk is, for example, 32-bit data, k becomes 32. The non-volatile memory device 103 outputs the correction data before the power-on reset circuit 101 releases the reset based on the reference voltage Vref when the power supply of the semiconductor integrated circuit device 1 is started (when the power supply voltage VDD supplied to the semiconductor integrated circuit device 1 increases from zero to a predetermined value (for example, +6.5 V)). It is desirable that the weights of the most significant bits of the correction data Sout1 to Soutk be excluded. That is, it is desirable that the most significant bits of the correction data Sout1 to Soutk be "0". For example, when the correction data is data indicating 256 in decimal, the data indicating 256 in decimal is divided into data indicating 64 in decimal, data indicating 64 in decimal, data indicating 64 in decimal, and data indicating 64 in decimal, and the non-volatile memory device 103 outputs four pieces of data indicating 64 in decimal, so that the most significant bits of the correction data Sout1 to Soutk can be set to "0". Thereby, even when the most significant bits of the correction data Sout1 to Soutk reach the reference voltage source 100 slightly later than other bits, it is possible to prevent the value of the correction data from changing greatly before and after the arrival, and the stability of the correction operation in the reference voltage source 100 is improved.

[0020] The latch circuit 104 is provided between the output terminal of the non-volatile memory device 103 and the reference voltage source 100. The correction data Sout1 to Soutk is output from the output terminal of the non-volatile memory device 103. The latch circuit 104 switches between a first operation of passing and outputting the correction data Sout1 to Soutk which is the input data and a second operation of latching and outputting the correction data Sout1 to Soutk which is the input data. The latch circuit 104 performs the first operation when the delay signal D1 is at a low level, and switches from the first operation to the second operation when the delay signal D1 switches from the low level to the high level.

[0021] When the enable signal EN1 is at a high level, the delay circuit DLY1, AND gate AN1, and AND gate AN2 cause the delay signal D1 to switch from a low level to a high level after the power-on reset signal XPOR switches from a low level to a high level, and further cause the delay signal D2 to switch from a low level to a high level, and then the enable signal EN3 to switch from a low level to a high level. When the enable signal EN3 is at a low level, the non-volatile memory device 103 is in an enabled state, and when the enable signal EN3 is at a high level, the non-volatile memory device 103 is in a disabled state. Therefore, after the latch circuit 104 switches from the first operation to the second operation, the non-volatile memory device 103 becomes disabled. Therefore, after the latch circuit 104 switches from the first operation to the second operation, the power consumption of the non-volatile memory device 103 can be reduced.

[0022] According to the semiconductor integrated circuit device 1 shown in FIG. 1, the reset release criterion (the value of the reference voltage Vref) can be corrected before the reset release by the power-on reset circuit 101 is executed. Thereby, the power-on reset circuit 101 can appropriately execute the reset release of the digital circuit 102.

[0023] <Memory element> The memory element used in the non-volatile memory device 103 of the configuration example shown in FIG. 7 to be described later is an element capable of executing a program operation and is composed of a transistor. The memory element is also called an OTP (One Time Programmable) element.

[0024] FIG. 2 is a diagram showing voltage application to the memory element MT during the program operation. The memory element MT is composed of an NMOS transistor. FIG. 3 is a longitudinal cross-sectional view of the memory element MT corresponding to FIG. 2.

[0025] As shown in FIGS. 2 and 3, during program operation, a high voltage Vpp is applied to the gate G of the memory element MT, a high voltage Vpp is applied to the source S, and a ground potential Vss (= 0V) is applied to the drain D. The high voltage Vpp is, for example, +6.5V.

[0026] Due to such voltage application, as shown by the arrow in FIG. 3, hot carriers (electrons) flowing from the drain D to the source S side are generated directly below the gate G. The hot carriers are attracted by the high voltage Vpp (positive voltage) applied to the gate G and trapped by the sidewall SSw on the source S side provided along the side surface of the gate G (the trapped hot carriers E are illustrated in FIG. 3).

[0027] FIG. 4 is a diagram showing voltage application to the memory elements MT1, MT2 (NMOS transistors) during read operation. FIG. 5 is a longitudinal cross-sectional view of the memory elements MT1, MT2 corresponding to FIG. 4.

[0028] As shown in FIGS. 4 and 5, during read operation, gate voltages Vg1, Vg2 are applied to the respective gates G of the memory elements MT1, MT2, drain voltages Vd1, Vd2 are applied to the respective drains D, and a ground potential Vs (= 0V) is applied to each source. The gate voltages Vg1, Vg2 are, for example, 2V. The drain voltages Vd1, Vd2 are, for example, +0.5V.

[0029] In FIGS. 4 and 5, as an example, a case is shown where the memory element MT1 is in a state before execution of the program operation (unprogrammed state) and the memory element MT2 is in a state after execution of the program operation (programmed state).

[0030] As shown in Fig. 5, in the memory element MT2 after the program operation is executed, since the hot carrier E is trapped in the sidewall SSw, the electric field due to the gate voltage Vg2 does not reach directly below the sidewall SSw, and the channel CN2 is interrupted on the source S side. Therefore, the gate threshold voltage becomes high and the drain current does not easily flow. On the other hand, as shown in Fig. 5, the memory element MT1 in which the program operation has not been executed is in the on state because the gate threshold voltage is low, and the drain current flows.

[0031] Data can be read by utilizing the magnitude of the drain current depending on the unprogrammed state or the programmed state of such a memory element. Here, in Fig. 6, the solid line waveform INI represents the gate-source voltage dependency of the drain current of the memory element in the unprogrammed state, and the dotted line waveform PRG represents the gate-source voltage dependency of the drain current of the memory element in the programmed state. Thus, the gate threshold voltage Vth increases due to the program operation.

[0032] <Non-volatile memory device> Fig. 7 is a diagram showing a configuration example of the non-volatile memory device 103. The non-volatile memory device 103 of the configuration example shown in Fig. 7 uses the memory element described above.

[0033] The non-volatile memory device 103 includes a constant current source 2, mirror elements 3 to 5, current mirrors 6 to 9, and inverters 10 and 11. The non-volatile memory device 103 also includes switches SS1, SS2, SD, and SH. In Fig. 7, the power supply voltage VDD is, for example, VDD = +6.5V.

[0034] The constant current source 2 includes input transistors 21 and 22, PMOS transistors 23 and 24, a resistor 25, a driving transistor 26, and a resistor 27. The input transistors 21 and 22 are both composed of NMOS transistors. A reference voltage Vref is applied to the gate of the input transistor 21. The source of the input transistor 21 is connected to one end of the resistor 25. The drain of the input transistor 21 is connected to the drain of the PMOS transistor 23. The source of the PMOS transistor 23 is connected to the applied end of the power supply voltage VDD. The gate of the PMOS transistor 23 is connected to the gate of the PMOS transistor 24. The source of the PMOS transistor 24 is connected to the applied end of the power supply voltage VDD. The drain of the PMOS transistor 24 is connected to the drain of the input transistor 22. The drain and gate of the PMOS transistor 24 are short-circuited. The source of the input transistor 22 is connected to one end of the resistor 25. The other end of the resistor 25 is connected to the grounded end (the applied end of the ground potential).

[0035] The driving transistor 26 is composed of a PMOS transistor. The source of the driving transistor 26 is connected to the applied end of the power supply voltage VDD. The gate of the driving transistor 26 is connected to the drain of the PMOS transistor 23. The drain of the driving transistor 26 is connected to one end of the resistor 27. The other end of the resistor 27 is connected to the grounded end. The node Nd1 to which the driving transistor 26 and the resistor 27 are connected is connected to the gate of the input transistor 22.

[0036] A current I21 corresponding to a reference voltage Vref flows through the input transistor 21. A current I22 corresponding to a sense voltage Vsns flows through the input transistor 22. The sense voltage Vsns is generated at a node Nd1 (gate of the input transistor 22). The current I22 is mirrored by a current mirror formed by PMOS transistors 23 and 24, and becomes a current I23 flowing through the PMOS transistor 23. The gate of the drive transistor 26 is driven according to the balance between the current I23 and the current I21, and the on-resistance of the drive transistor 26 is adjusted. Thereby, the sense voltage Vsns is controlled to match the reference voltage Vref. The sense voltage Vsns and the resistor 27 generate a current I20 as a constant current.

[0037] The current mirror 8 includes a reference element 81, a data element 82, a resistor 83, and a switch 84. Both the reference element 81 and the data element 82 are memory elements formed by NMOS transistors. As described above, the memory element is an element capable of executing a program operation. The data element 82 is the target of the program operation. That is, the data element 82 can take an unprogrammed state or a programmed state. The reference element 81 is maintained in an unprogrammed state.

[0038] The mirror element 4 is formed by a PMOS transistor. The source of the mirror element 4 is connected to the applied end of the power supply voltage VDD. The gate of the mirror element 4 is connected to the gate of the drive transistor 26. The drain of the mirror element 4 is connected to one end of the resistor 83.

[0039] The gate of the reference element 81 is connected to the other end of the resistor 83. A switch 84 is connected between the other end of the resistor 83 and the drain of the reference element 81. The source of the reference element 81 is connected to the ground terminal. The gate of the data element 82 is connected to one end of the resistor 83. A switch SS1 is connected between the source of the data element 82 and the ground terminal.

[0040] The drain of the data element 82 is connected to the output-side transistor 72 of the current mirror 7 at node Nd2 via the output-side transistor 92 included in the current mirror 9 described later.

[0041] The current I20 is mirror-ringed by the mirror element 4 to become the current I1. When the switch 84 is in the on state, the current I1 flows through the reference element 81 and the resistor 83. The Vgs (gate-source voltage) of the data element 82 becomes the voltage obtained by adding the voltage generated across both ends of the resistor 83 to the Vgs of the reference element 81.

[0042] The reference element 81 and the data element 82 have the same structure and have the same electrical characteristics as each other before the execution of the program operation. Therefore, in the state before executing the program operation on the data element 82 (the state where both the reference element 81 and the data element 82 are unprogrammed), the current (drain current) I2 flowing through the data element 82 satisfies I2 > I1.

[0043] Note that, for transistors, the structure is a concept that includes the size of the transistor. Therefore, for any plurality of transistors, the fact that their structures are the same means that the sizes of the plurality of transistors are also the same. When the structures of a certain plurality of transistors are the same, if hot carrier injection by a program operation is not performed on the plurality of transistors, the electrical characteristics (including the gate threshold voltage, etc.) of the plurality of transistors are also the same as each other. However, the fact that the structures and electrical characteristics of any plurality of transistors are the same means that they are the same in design, and actually may include errors (that is, the same is to be understood as a concept including errors).

[0044] Here, the mirror element 5 is composed of a PMOS transistor. The source of the mirror element 5 is connected to the applied end of the power supply voltage VDD. The gate of the mirror element 5 is connected to the gate of the drive transistor 26. The drain of the mirror element 5 is connected to the input side of a current mirror 6 composed of an NMOS transistor. The output side of the current mirror 6 is connected to the input side of a current mirror 7 composed of a PMOS transistor. Specifically, the current mirror 7 has an input side transistor 71 and an output side transistor 72. The drain of the input side transistor 71 is connected to the output side of the current mirror 6. The drain of the output side transistor 72 is connected to the drain of the output side transistor 92 at the node Nd2.

[0045] The current I20 is mirrored by the mirror element 5 to become the current I3. The current I3 is mirrored by the current mirror 6 to become the current I4. The current I4 is mirrored by the current mirror 7 to become the current I5. The current I5 flowing through the output side transistor 72 becomes a reference current (constant current). That is, the output side transistor 72 corresponds to a reference current generation unit. For example, if I1 = I3 = I4 = I5 = 1 μA, in the state before the data element 82 executes a program operation (unprogrammed state), for example, I2 = 3 μA.

[0046] The node Nd2 is connected to the input end of the inverter 10. The input end of the inverter 11 is connected to the output end of the inverter 10. The output signal Sout is output from the output end of the inverter 11. That is, the non-volatile memory device 103 does not need to receive a read command, and when the power supply voltage VDD becomes as high as about 1 V and a current flows through the resistor 27, the output signal Sout is output.

[0047] Switch SH is connected between the applied terminal of power supply voltage VDD and node Nd2. In the reset state with switch SH turned on, the voltage at the input terminal of inverter 10 is fixed at a high level, and output signal Sout is fixed at a high level. When switch SH is switched from the reset state to the off state, in the state before the program operation is executed on data element 82 (unprogrammed state), I2 > I5, current is drawn from node Nd2, and the voltage at the input terminal of inverter 10 drops to a low level. For example, in the case of the above current value example, since I2 = 3 μA and I5 = 1 μA, 2 μA of current is drawn from node Nd2. As a result, output signal Sout output from inverter 11 becomes a low level. That is, output signal Sout is output as a signal indicating a state in which "0" is stored.

[0048] Note that until the power supply voltage VDD reaches about 1.5 V, for example, since the gate voltage of data element 82 has not risen sufficiently, current I2 does not flow even in the state before the program operation is executed on data element 82 (unprogrammed state). Therefore, when the output of non-volatile memory device 103 is the initial value, each bit of the output of non-volatile memory device 103 becomes a signal indicating a state in which "1" is stored. And when the power supply voltage VDD reaches about 1.5 V, for example, the output of non-volatile memory device 103 becomes a value according to the data stored in non-volatile memory device 103. Therefore, when the output of non-volatile memory device 103 is the initial value, it is desirable that the value of reference voltage Vref is maximized and the reset release threshold of power-on reset circuit 101 is maximized. That is, when each bit of the correction data becomes a signal indicating a state in which "1" is stored, it is desirable that reference voltage source 100 corrects the value of reference voltage Vref so that the value of reference voltage Vref is maximized. Thereby, when the output of non-volatile memory device 103 is the initial value, it is possible to prevent the reset release threshold of power-on reset circuit 101 from becoming too low and power-on reset circuit 101 from erroneously executing reset release.

[0049] On the other hand, in the state after the data element 82 executes the program operation (programmed state), the gate threshold voltage of the data element 82 becomes high and I2 = 0. When the switch SH is switched from the reset state to the off state, in the state after the data element 82 executes the program operation, I5 > I2, and the voltage at the input terminal of the inverter 10 is maintained at a high level. Therefore, the output signal Sout output from the inverter 11 becomes a high level. That is, the output signal Sout is output as a signal indicating the state in which "1" is stored.

[0050] Thus, in this embodiment, before the data element 82 executes the program operation, the current mirror 8 generates a current I2 larger than the current I5 which is the reference current, and after the data element 82 executes the program operation, I2 < I5. Then, by detecting the magnitude relationship between the current I2 and the current I5 by the inverters 10 and 11, 1-bit data is read out.

[0051] When performing a program operation on the data element 82, the switch SS1 is in the off state, the switches SD and SS2 are in the on state, so that a ground potential is applied to the drain of the data element 82 and a power supply voltage VDD is applied to the source of the data element 82. At this time, the switch 84 is in the off state, and the power supply voltage VDD is applied to the gate of the data element 82. During the read operation, the switch SS1 is in the on state, and the switches SD and SS2 are in the off state. At this time, the switch 84 is in the on state.

[0052] Next, the current mirror 9 will be described. The current mirror 9 is provided to control the drain voltage of the data element 82 to a low voltage. Thereby, it is suppressed that the data element 82 is erroneously programmed during the read operation.

[0053] The current mirror 9 includes an input-side transistor 91, an output-side transistor 92, and a resistor 93. The mirror element 3 is composed of a PMOS transistor.

[0054] The source of the mirror element 3 is connected to the applied end of the power supply voltage VDD. The gate of the mirror element 3 is connected to the gate of the driving transistor 26. Both the input-side transistor 91 and the output-side transistor 92 are composed of NMOS transistors. The gate and drain of the input-side transistor 91 are short-circuited. The drain of the input-side transistor 91 is connected to the drain of the mirror element 3. The source of the input-side transistor 91 is connected to one end of the resistor 93. The other end of the resistor 93 is connected to the ground terminal. The gate of the output-side transistor 92 is connected to the gate of the input-side transistor 91. The source of the output-side transistor 92 is connected to the drain of the data element 82. The drain of the output-side transistor 92 is connected to the node Nd2.

[0055] The current I20 is mirrored by the mirror element 3 to become the current I6. The current I6 flows through the input-side transistor 91 and the resistor 93. The voltage applied to the drain of the data element 82 is the voltage that has dropped by only the Vgs of the output-side transistor 92 from the voltage obtained by adding the voltage generated across both ends of the resistor 93 to the Vgs of the input-side transistor 91.

[0056] Also, the nonvolatile memory device 103 has a storage circuit 15. The storage circuit 15 includes the data element 82, the output-side transistor 92, the output-side transistor 72, the switches SS1, SS2, SD, and SH, and the inverters 10 and 11. Thus, in this embodiment, it is possible to miniaturize the storage circuit 15 corresponding to one-bit data. Note that the nonvolatile memory device 103 actually corresponds to a plurality of bits (for example, 32 bits), and the storage circuit 15 is provided for each of the plurality of bits. Also, the configurations other than the storage circuit 15 in the configuration shown in FIG. 7 are common circuits for the plurality of bits.

[0057] The non-volatile memory device 103 further includes switches SW1 to SW5. A power supply voltage VDD is applied to the first terminal of switch SW1. The second terminal of switch SW1 is connected to the gates of PMOS transistors 23, the gates and drains of PMOS transistors 24, and the drain of input transistor 22. A power supply voltage VDD is applied to the first terminal of switch SW2. The second terminal of switch SW2 is connected to the drains of PMOS transistors 23, the gate of drive transistor 26, and the gates of mirror elements 3 to 5. The first terminal of switch SW3 is connected to the drains of mirror elements 3 to 5, the gates and drains of input-side transistor 91, and the gate of output-side transistor 92. A ground potential is applied to the second terminal of switch SW3. The first terminal of switch SW4 is connected to the drain of mirror element 4, the gate of data element 82, and the first terminal of resistor 83. A ground potential is applied to the second terminal of switch SW4. The first terminal of switch SW5 is connected to the drain and gate of one of the pair of NMOS transistors constituting current mirror 6 and the gate of the other. A ground potential is applied to the second terminal of switch SW5.

[0058] When the non-volatile memory device 103 is in the enabled state, switches SW1 to SW5 are in the off state. On the other hand, when the non-volatile memory device 103 is in the disabled state, switches SW1 to SW5 are in the on state.

[0059] <Others> In addition to the above-described embodiments, the configuration of the present invention can be variously modified without departing from the gist of the invention. It should be considered that the above-described embodiments are illustrative in all respects and not restrictive, and the technical scope of the present invention is indicated by the claims rather than the description of the above embodiments, and it should be understood that all modifications within the meaning and scope equivalent to the claims are included.

[0060] For example, the non-volatile memory device 103 may have a configuration in which correction data is output before the power-on reset circuit 101 releases the reset based on the reference voltage Vref when the semiconductor integrated circuit device 1 is powered on (when the power supply voltage VDD supplied to the semiconductor integrated circuit device 1 increases from zero to a predetermined value (for example, +6.5 V)), and is not limited to the configuration shown in FIG. 7. For example, as the memory element provided in the non-volatile memory device 103, something like a fuse may be used.

[0061] <Appendix> An appendix is provided for the present disclosure in which specific configuration examples were shown in the above-described embodiments.

[0062] The semiconductor integrated circuit device (1) of the present disclosure includes a reference voltage source (100) configured to output a reference voltage, and a non-volatile memory device (103) configured to non-volatily store correction data for correcting the value of the reference voltage and output the correction data before the power-on reset circuit (101) releases the reset based on the reference voltage when the power is turned on. The reference voltage source is configured to correct the value of the reference voltage based on the correction data (first configuration).

[0063] According to the semiconductor integrated circuit device having the first configuration, it is possible to correct the reset release reference before the reset release by the power-on reset circuit is executed. Thereby, the power-on reset circuit can appropriately execute the reset release of the power supply circuit.

[0064] In the semiconductor integrated circuit device having the first configuration, a latch circuit (104) may be provided between the output terminal of the non-volatile memory device and the reference voltage source and configured to be able to switch between a first operation of passing and outputting input data and a second operation of latching and outputting the input data (second configuration).

[0065] In the semiconductor integrated circuit device having the second configuration, the latch circuit may be configured (a third configuration) to switch from the first operation to the second operation based on a signal obtained by delaying the output of the power-on reset circuit.

[0066] In the semiconductor integrated circuit device having the second or third configuration, it may be configured (a fourth configuration) such that the nonvolatile memory device enters a disabled state after the latch circuit switches from the first operation to the second operation.

[0067] In the semiconductor integrated circuit device having any one of the first to fourth configurations, it may be configured (a fifth configuration) such that when the output of the nonvolatile memory device is at an initial value, the value of the reference voltage is maximized and the reset release threshold of the power-on reset circuit is maximized.

[0068] In the semiconductor integrated circuit device having any one of the first to fifth configurations, it may be configured (a sixth configuration) to exclude the weight of the most significant bit of the correction data.

[0069] In the semiconductor integrated circuit device having any one of the first to sixth configurations, the nonvolatile memory device may include a memory element (82) capable of executing a program operation by trapping charges in a sidewall, and may be configured (a seventh configuration) such that data can be read based on the magnitude relationship between a comparison target current and the current flowing through the memory element.

Explanation of Reference Numerals

[0070] 1 Semiconductor integrated circuit device 2 Constant current source 3 to 5 Mirror elements 6 to 9 Current mirrors 10, 11 Inverters 15 Memory circuit 21, 22 Input transistors 23, 24 PMOS transistors 25 Resistor 26 Drive Transistor 27 Resistor 71 Input-Side Transistor 72 Output-Side Transistor 81 Reference Element 82 Data Element 83 Resistor 84 Switch 91 Input-Side Transistor 92 Output-Side Transistor 93 Resistor 100 Reference Voltage Source 101 Power-On Reset Circuit 102 Digital Circuit 103 Non-Volatile Memory Device 104 Latch Circuit A1, AN1, AN2 AND Gate COMP1 Comparator DLY1 Delay Circuit MT Memory Element MT1, MT2 Memory Elements OP1 Operational Amplifier VS1 Voltage Source R1, R2 Resistors SS1, SS2, SD, SH, SW1~SW5 Switches SSw Sidewall

Claims

1. A reference voltage source configured to output a reference voltage, A non-volatile memory device configured to non-volatily store correction data for correcting the value of the reference voltage and output the correction data before a power-on reset circuit releases reset based on the reference voltage when power is turned on. Comprising: The reference voltage source is configured to correct the value of the reference voltage based on the correction data, a semiconductor integrated circuit device.

2. A latch circuit provided between an output terminal of the non-volatile memory device and the reference voltage source, configured to be able to switch between a first operation of passing and outputting input data and a second operation of latching and outputting the input data, the semiconductor integrated circuit device according to claim 1.

3. The latch circuit is configured to switch from the first operation to the second operation based on a signal obtained by delaying an output of the power-on reset circuit, the semiconductor integrated circuit device according to claim 2.

4. After the latch circuit switches from the first operation to the second operation, the non-volatile memory device is configured to be in a disabled state, the semiconductor integrated circuit device according to claim 2.

5. When the output of the non-volatile memory device is an initial value, the value of the reference voltage is maximized, and the reset release threshold of the power-on reset circuit is maximized, the semiconductor integrated circuit device according to claim 1.

6. The semiconductor integrated circuit device according to claim 1, configured to exclude the weight of the most significant bit of the correction data.

7. The non-volatile memory device, Comprises a memory element capable of executing a programming operation by trapping charges in a sidewall, Data can be read based on a magnitude relationship between a comparison target current and a current flowing through the memory element, the semiconductor integrated circuit device according to any one of claims 1 to 6.

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