Doherty amplifier circuit

Abstract

To provide a Doherty amplifier circuit capable of suppressing deterioration in characteristics.SOLUTION: A Doherty amplifier circuit includes: a distribution node N1 that distributes an input signal into a first signal and a second signal; a main amplifier 10 that includes a first GaN HEMT, amplifies the first signal and outputs the amplified signal as a fourth signal; a first peak amplifier 12 that includes a second GaN HEMT, amplifies the second signal and outputs the amplified signal as a fifth signal; and a combination node N2 that combines the fourth signal and the fifth signal and outputs the combined signal to an output terminal as an output signal. A first electrical length of a sum of the electrical length between the distribution node and the main amplifier and the electrical length between the main amplifier and the combination node is shorter than a second electrical length of a sum of the electrical length between the distribution node and the first peak amplifier and the electrical length between the first peak amplifier and the combination node.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present invention relates to a Doherty amplifier circuit.

Background Art

[0002] An N (N is 3 or more)-way Doherty amplifier circuit using a main amplifier and two or more peak amplifiers is known (for example, Patent Documents 1 and 2).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in a Doherty amplifier circuit, when the phases of the signals at the synthesis node where the signals amplified by each amplifier are synthesized are different, characteristics such as gain deteriorate.

[0005] The present disclosure aims to suppress deterioration of characteristics.

Means for Solving the Problems

[0006] One embodiment of the present disclosure includes a distribution node that distributes an input input signal into a first signal and a second signal, a main amplifier including a first GaN HEMT that amplifies the first signal and outputs the amplified signal as a fourth signal, a first peak amplifier including a second GaN HEMT that amplifies the second signal and outputs the amplified signal as a fifth signal, and a combining node that combines the fourth signal and the fifth signal and outputs the combined signal to an output terminal as an output signal. The total first electrical length of the electrical length between the distribution node and the main amplifier and the electrical length between the main amplifier and the combining node is shorter than the total second electrical length of the electrical length between the distribution node and the first peak amplifier and the electrical length between the first peak amplifier and the combining node. This is a Doherty amplifier circuit.

Advantages of the Invention

[0007] According to the present disclosure, deterioration of characteristics can be suppressed.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Embodiments for Carrying Out the Invention

[0009] [Description of Embodiments of the Present Disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure includes a distribution node that distributes an input input signal into a first signal and a second signal, a main amplifier including a first GaN HEMT that amplifies the first signal and outputs the amplified signal as a fourth signal, a first peak amplifier including a second GaN HEMT that amplifies the second signal and outputs the amplified signal as a fifth signal, and a combining node that combines the fourth signal and the fifth signal and outputs the combined signal to an output terminal as an output signal. The total first electrical length of the electrical length between the distribution node and the main amplifier and the electrical length between the main amplifier and the combining node is shorter than the total second electrical length of the electrical length between the distribution node and the first peak amplifier and the electrical length between the first peak amplifier and the combining node. This can reduce the phase difference between the fourth signal and the fifth signal at the combining node. Therefore, the characteristics can be improved. (2) In the above (1), the difference between the second electrical length and the first electrical length may be 2° or more and 20° or less in terms of the phase at the center frequency of the operating band. This can further improve the characteristics. (3) In the above (2), when the input power of the input signal is the power at which the main amplifier and the first peak amplifier operate, the difference between the amount of change in phase when the signal at the center frequency passes through the main amplifier and the amount of change in phase when the signal at the center frequency passes through the first peak amplifier, and the value obtained by converting the difference between the second electrical length and the first electrical length into the phase at the center frequency, the difference may be 2° or less. This can further improve the characteristics. (4) In the above (1), a second peak amplifier is provided which includes a third GaN HEMT, amplifies a third signal, and outputs the amplified signal as a sixth signal. The distribution node distributes the input signal to the first signal, the second signal, and the third signal. The combining node combines the fourth signal, the fifth signal, and the sixth signal, and outputs the combined signal as the output signal to the output terminal. The input power of the input signal when the second peak amplifier is turned on is greater than the input power when the first peak amplifier is turned on. The total third electrical length of the electrical length between the distribution node and the second peak amplifier and the electrical length between the second peak amplifier and the combining node may be longer than the second electrical length. Thereby, the phase difference between the fourth signal, the fifth signal, and the sixth signal at the combining node can be reduced. Therefore, the characteristics can be improved. (5) In the above (4), the difference between the second electrical length and the first electrical length, when converted to the phase at the center frequency of the operating band, may be 2° or more and 20° or less, and the difference between the third electrical length and the second electrical length, when converted to the phase at the center frequency, may be 2° or more and 20° or less. Thereby, the characteristics can be further improved. (6) In the above (5), the difference between the change amount of the phase when the signal at the center frequency passes through the main amplifier and the change amount of the phase when the signal at the center frequency passes through the first peak amplifier, and the value obtained by converting the difference between the second electrical length and the first electrical length to the phase at the center frequency, the difference therebetween is 2° or less. The difference between the change amount of the phase when the signal at the center frequency passes through the first peak amplifier and the change amount of the phase when the signal at the center frequency passes through the second peak amplifier, and the value obtained by converting the difference between the third electrical length and the second electrical length to the phase at the center frequency, the difference therebetween may be 2° or less. Thereby, the characteristics can be further improved. (7) In any one of (4) to (6) above, a first impedance converter connected between the first peak amplifier and the combining node, a second impedance converter connected between the second peak amplifier and the combining node, a first phase adjuster connected between the distribution node and the main amplifier, a second phase adjuster connected between the distribution node and the first peak amplifier, and a third phase adjuster connected between the distribution node and the second peak amplifier are provided, the electrical length of the second phase adjuster is 2° or more and 20° or less in terms of the phase of the signal at the center frequency of the operating band, and the electrical length of the third phase adjuster may be 4° or more and 40° or less in terms of the phase of the signal at the center frequency. Thereby, the design of the second phase adjuster and the third phase adjuster becomes easy. (8) In (7) above, no impedance converter is provided between the main amplifier and the combining node, and the electrical length of the first phase adjuster may be 67.5° or more and 112.5° or less in terms of the phase of the signal at the center frequency. Thereby, the design of the first phase adjuster becomes easy.

[0010] [Details of Embodiments of the Present Disclosure] A specific example of the Doherty amplifier circuit according to the embodiment of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, and is shown by the claims, and is intended to include all changes within the meaning and scope equivalent to the claims.

[0011] [Example 1] As a Doherty amplifier circuit, a high-power high-frequency amplifier circuit used in a base station for mobile communication will be described as an example. In this case, the frequency of the high-frequency signal is, for example, 0.5 GHz or more and 10 GHz or less. FIG. 1 is a block diagram of the Doherty amplifier circuit according to Example 1.

[0012] As shown in Fig. 1, in Doherty amplifier circuit 100, main amplifier 10, peak amplifier 12 (first peak amplifier) and 14 (second peak amplifier) are connected in parallel between distribution node N1 of distributor 16 and combining node N2 of combiner 18. Paths 25 to 27 are paths from distribution node N1 passing through main amplifier 10, peak amplifier 12 and 14 respectively to reach combining node N2. Thus, Doherty amplifier circuit 100 is a 3-way amplifier circuit. The Doherty amplifier circuit may be an N-way Doherty amplifier circuit having one or three or more peak amplifiers.

[0013] A high-frequency signal is input as input signal Sin to input terminal Tin. Distributor 16 distributes input signal Sin input to input terminal Tin into signal S1 (first signal), S2 (second signal) and S3 (third signal). Distributor 16 is, for example, a Wilkinson-type distributor. Distributor 16 has a distribution node N1 to which signals S1, S2 and S3 are distributed.

[0014] Path 25 includes phase adjuster 20 (first phase adjuster), matching circuit 30, bias circuit 36, main amplifier 10, bias circuit 39 and matching circuit 33. Path 26 includes phase adjuster 21 (second phase adjuster), matching circuit 31, bias circuit 37, peak amplifier 12, matching circuit 34 and impedance converter 23 (first impedance converter). Path 27 includes phase adjuster 22 (third phase adjuster), matching circuit 32, bias circuit 38, peak amplifier 14, matching circuit 35 and impedance converter 24 (second impedance converter).

[0015] Matching circuits 30 to 32 match the impedance seen from distributor 16 to matching circuits 30 to 32 with the impedance seen from matching circuits 30 to 32 to main amplifier 10, peak amplifier 12 and 14 respectively. Bias circuits 36 to 38 supply gate bias voltages VG1 to VG3 to gates G of main amplifier 10, peak amplifier 12 and 14 respectively.

[0016] The phase adjuster 20 adjusts the phase of the signal S1 in order to align the phases of the signals S5 and S6 that change due to the impedance converters 23 and 24 with the signal S4. The phase adjusters 21 and 22 adjust the phase differences among the main amplifier 10, the peak amplifiers 12 and 14, which will be described later. The phase adjusters 20 to 22 are transmission lines such as microstrip lines or coplanar lines, for example, and the phase can be adjusted by setting the electrical length of the transmission line to a desired length.

[0017] The main amplifier 10, the peak amplifiers 12 and 14 amplify the signals S1, S2 and S3 respectively, and output the amplified signals S4 (the fourth signal), S5 (the fifth signal) and S6 (the sixth signal) respectively. The bias circuit 39 supplies a drain bias voltage VD to the drains D of the main amplifier 10, the peak amplifiers 12 and 14. The matching circuits 33 to 35 match the impedances seen from the main amplifier 10, the peak amplifiers 12 and 14 to the impedances seen from the matching circuits 33 to 35 to the synthesizer 18 respectively.

[0018] The synthesizer 18 includes a synthesis node N2, and impedance converters 23 and 24. One end of the impedance converter 23 is electrically connected to the peak amplifier 12 via the matching circuit 34, and the other end is electrically connected to the synthesis node N2. One end of the impedance converter 24 is electrically connected to the peak amplifier 14 via the matching circuit 35, and the other end is electrically connected to the synthesis node N2. The synthesis node N2 synthesizes the signals S4 to S6 and outputs the synthesized signal as the output signal Sout to the output terminal Tout.

[0019] The impedance converters 23 and 24 convert the impedance on the real axis of the Smith chart as seen from the matching circuits 34 and 35 to the impedance at different positions on the real axis of the Smith chart as seen from the combined node N2 from the impedance converters 23 and 24. Also, the impedance converter 23 makes the impedance seen from the combined node N2 to the peak amplifier 12 infinite when the peak amplifier 12 is not operating. The impedance converter 24 makes the impedance seen from the combined node N2 to the peak amplifier 14 infinite when the peak amplifier 14 is not operating.

[0020] The impedance converters 23 and 24 are transmission lines such as microstrip lines or coplanar lines, for example, and are quarter-wavelength lines at the center frequency of the operating band. The electrical length of the quarter-wavelength line does not have to be exactly a quarter wavelength. The quarter-wavelength line only needs to have an electrical length that functions as the impedance converters 23 and 24. For example, the electrical length of the quarter-wavelength line may be not less than 3 / 16 wavelength and not more than 5 / 16 wavelength, or may be not less than 7 / 32 wavelength and not more than 9 / 32 wavelength. The impedance on the real axis in the Smith chart does not have to be exactly on the real axis (reactance component is 0). The absolute value of the reactance component of the impedance may be not more than 0.2 times the resistance component, or may be not more than 0.1 times the resistance component.

[0021] The main amplifier 10, peak amplifiers 12 and 14 each include transistors Q1 to Q3. The transistors Q1 to Q3 are, for example, GaN HEMT (Gallium Nitride High Electron Mobility Transistor). The sources S of the transistors Q1 to Q3 are grounded, signals S1 to S3 are input to the gates G respectively, and signals S4 to S6 are output from the drains D respectively.

[0022] FIG. 2 is a schematic diagram showing the probability with respect to Pout, the Pout of each amplifier with respect to Pin, the gain of each amplifier with respect to Pin, and the overall gain with respect to Pin in Example 1.

[0023] The probability is the probability of the modulated wave signal of the high-frequency signal for mobile communication amplified by the Doherty amplifier circuit 100. That is, it is the probability that the Doherty amplifier circuit 100 outputs a certain output power Pout. Each Pout is the output power Pout of the main amplifier 10, the peak amplifiers 12 and 14. Each gain is the power gain of each of the main amplifier 10, the peak amplifiers 12 and 14. The overall gain is the power gain of the output power Pout of the output signal Sout with respect to the input power Pin of the input signal Sin. Note that Pin and Pout are in dB display. The gain of the main amplifier 10 below the power P1 of the input power Pin is larger than the gain of the peak amplifier 12 above the power P1 and below the power P2. That is, the slope of Pout with respect to the input power Pin below the power P1 of the main amplifier 10 is larger than the slope of Pout with respect to the input power Pin above the power P1 and below the power P2 of the peak amplifier 12. However, FIG. 4 is a schematic diagram, and shows the slope of Pout with respect to the input power Pin below the power P1 of the main amplifier 10 to be smaller than the slope of Pout with respect to the input power Pin above the power P1 and below the power P2 of the peak amplifier 12.

[0024] As shown in FIG. 2, when the output power Pout is the power P0, the probability of the modulated wave is the highest. That is, when outputting the signal of the modulated wave, the time when the output power Pout is the power P0 is the longest. The main amplifier 10 is a class A or AB amplifier, and the peak amplifiers 12 and 14 are class C amplifiers. The input power Pin at which the peak amplifier 12 turns on is larger than the input power Pin at which the main amplifier 10 turns on, and the input power Pin at which the peak amplifier 14 turns on is larger than the input power Pin at which the peak amplifier 12 turns on. In order to operate in this way, it can be realized by making the gate bias voltage VG2 of the transistor Q2 larger negatively than the gate bias voltage VG1 of the transistor Q1, and making the gate bias voltage VG3 of the transistor Q3 larger negatively than the gate bias voltage VG2 of the transistor Q2.

[0025] As the input power Pin of the input signal Sin increases and the input power Pin exceeds the power P0 and reaches up to the power P1, the main amplifier 10 operates, but the peak amplifiers 12 and 14 do not operate. When the input power Pin is below the power P1, as the input power Pin increases, the output power Pout of the main amplifier 10 increases linearly. Therefore, when the input power Pin is below the power P0, each gain and the overall gain are almost constant.

[0026] When the input power Pin is equal to or greater than the power P1 and equal to or less than the power P2, the main amplifier 10 and the peak amplifier 12 operate, but the peak amplifier 14 does not operate. In this range, the main amplifier 10 saturates. Therefore, the gain of the main amplifier 10 decreases. Along with this, the overall gain also decreases. Since the peak amplifier 12 operates in class C, the gain of the peak amplifier 12 between the powers P1 and P2 is lower than the gain of the main amplifier 10 below the power P1. Also, the saturation power of the peak amplifier 12 is smaller than the saturation power of the main amplifier 10.

[0027] When the input power Pin is equal to or greater than the power P2 and equal to or less than P3, all of the main amplifier 10, the peak amplifiers 12 and 14 operate. In this range, in addition to the main amplifier 10, the peak amplifier 12 saturates. Therefore, the gain of the peak amplifier 12 decreases. Along with this, the overall gain also decreases. Since the operating point of the peak amplifier 14 is more negative than that of the peak amplifier 12, the gain of the peak amplifier 14 between the powers P2 and P3 is lower than the gain of the peak amplifier 12 between the powers P1 and P2. Also, the saturation power of the peak amplifier 14 is smaller than the saturation power of the peak amplifier 12.

[0028] When the input power Pin is equal to or greater than the power P3, in addition to the main amplifier 10 and the peak amplifier 12, the peak amplifier 14 saturates. Therefore, the gain of the peak amplifier 14 decreases. Along with this, the overall gain also decreases.

[0029] The product of the probability and the overall gain corresponds to the gain of the modulated wave. To improve the gain of the modulated wave, the overall gain at a high probability Pout is improved.

[0030] [Explanation of GaN HEMT] FIG. 3 is a cross-sectional view of the GaN HEMT of Example 1. As shown in FIG. 3, in the GaN HEMT, a source electrode 42, a gate electrode 44, and a drain electrode 46 are provided on a substrate 40. The substrate 40 includes a substrate 40a and a semiconductor layer 40b provided on the substrate 40a. The semiconductor layer 40b includes a running layer 40c provided on the substrate 40a and a barrier layer 40d provided on the running layer 40c. The substrate 40a is, for example, a silicon carbide (SiC) substrate, a sapphire substrate, or a gallium nitride (GaN) substrate. The semiconductor layer 40b is a nitride semiconductor layer, the running layer 40c is, for example, a gallium nitride layer, and the barrier layer 40d is, for example, a gallium aluminum nitride layer.

[0031] FIG. 4 is a diagram showing the phase with respect to the input power Pin in the GaN HMET and is a diagram showing AM (Amplitude Modulation)-PM (Phase Modulation) characteristics. The input power Pin is the power of a high-frequency signal at the center frequency of the operating band input to the gate of the GaN HEMT. The phase is the difference in phase between the high-frequency signal input to the gate and the high-frequency signal output from the drain, and the phase when the input power Pin is 0 dBm is set to 0°. FIG. 4 shows the measurement results and the simulation results. The values of the input power Pin and the phase are an example because they differ depending on the structure such as the gate width of the GaN HEMT.

[0032] As shown in FIG. 4, when the input power Pin increases from 0 dBm, the phase moves in the negative direction. When the input power Pin exceeds the power Pth (23 dBm), the phase moves in the positive direction. The absolute value of the slope of the phase with respect to the input power Pin is larger when the input power Pin is above Pth than when it is below Pth.

[0033] [Explanation of the Phase of Each Amplifier] FIG. 5 is a diagram showing the output power Pout of each amplifier with respect to the input power Pin, and the phase of each amplifier with respect to the input power Pin. The input power Pin corresponds to the input power of the input signal Sin in FIG. 1. Each Pout is the output power of the main amplifier 10, the peak amplifiers 12 and 14. The phases of the main amplifier 10, the peak amplifiers 12 and 14 correspond to the amounts of phase change θ1, θ2 and θ3 of the signals at the center frequency of the operating band when passing through the main amplifier 10, the peak amplifiers 12 and 14, respectively. The fact that the change amounts θ1 to θ3 are positively large indicates that the phase is advanced, which corresponds to an increase in the electrical length.

[0034] As shown in FIG. 5, the power Pth in the phase change amounts θ1 to θ3 is slightly smaller than the powers P1 to P3, respectively. Therefore, when the input power Pin is the power P2, the phase difference between the main amplifier 10 and the peak amplifier 12 is Δθ1. When the input power Pin is the power P3, the phase difference between the main amplifier 10 and the peak amplifier 12 is Δθ2a, and the phase difference between the main amplifier 10 and the peak amplifier 14 is Δθ2b. Δθ1 and Δθ2a may be approximately equal or different.

[0035] Thus, when there are phase differences Δθ1, Δθ2a and Δθ2b, when the signals S4 to S6 are combined at the combining node N2, the power of the output signal Sout decreases, and the overall gain decreases.

[0036] FIG. 6 is a diagram showing the output power Pout of each amplifier with respect to the input power Pin, and the phase of each amplifier with respect to the input power Pin. The thin broken line shows the state before the phases are adjusted by the phase adjusters 21 and 22.

[0037] As shown in FIG. 6, when the input power Pin is the power P2, the phase of path 26 is advanced by Δφ1. When the input power Pin is the power P3, the phases of paths 26 and 27 are advanced by Δφ2a and Δφ2b, respectively. Thereby, at the power P2, the phases of the main amplifier 10 and the peak amplifier 12 are substantially aligned. At the power P3, the phases of the main amplifier 10 and the peak amplifier 12 are substantially aligned, and the phases of the main amplifier 10 and the peak amplifier 14 are substantially aligned.

[0038] [Phase adjustment method] FIG. 7 is a diagram for explaining the phase adjustment method in the first embodiment. Each path 25 to 27 between the distribution node N1 and the synthesis node N2 is illustrated. The illustration of the matching circuits 30 to 35 and the bias circuits 36 to 39 is omitted.

[0039] When the amount of phase change θ1 increases, it corresponds to the phase being more rotated, that is, the phase being advanced, and corresponds to the electrical length of the signal passing through the main amplifier 10 becoming longer. The phases φ1A, φ2A, and φ3A are the amounts obtained by converting the electrical lengths between the distribution node N1 and the main amplifier 10, the peak amplifiers 12 and 14 into the phases at the center frequency of the operating band, respectively. The phases φ1B, φ2B, and φ3B are the amounts obtained by converting the electrical lengths between the main amplifier 10, the peak amplifiers 12 and 14 and the synthesis node N2 into the phases at the center frequency of the operating band, respectively. The amount of phase change φ1 is the sum of φ1A and φ1B, the amount of phase change φ2 is the sum of φ2A and φ2B, and the amount of phase change φ3 is the sum of φ3A and φ3B.

[0040] The amount of phase change when passing through the impedance converters 23 and 24 at the center frequency of the operating band of the impedance converters 23 and 24 is θ4. Therefore, the phase adjustment amount of the phase adjuster 20 is set to θ5. For example, when the phase adjuster 20 is formed by a transmission line, the electrical length of the transmission line is set to a length corresponding to the adjustment amount θ5. For example, θ5 is 90°. Thereby, the amount of phase change by the impedance converters 23 and 24 can be adjusted by the phase adjuster 20.

[0041] However, as shown in FIG. 5, the phases when passing through the main amplifier 10, the peak amplifiers 12 and 14 are different. Therefore, let the adjustment amount θ6 of the phase of the phase adjuster 21 be Δθ1 and Δθ2a. Let the adjustment amount θ7 of the phase of the phase adjuster 22 be Δθ2b. Thereby, as shown in FIG. 6, the difference in phase when passing through the main amplifier 10, the peak amplifiers 12 and 14 can be adjusted. When Δθ1 and Δθ2a are different, the adjustment amount θ6 may be set to a value between Δθ1 and Δθ2a. For improving the gain of the modulated wave, the adjustment of the phase at the power P2 is more important than the adjustment of the phase at the power P3. Therefore, the adjustment amount θ6 may be set to Δθ1.

[0042] According to the first embodiment, the total first electrical length (corresponding to φ1) of the electrical length (corresponding to φ1A) between the distribution node N1 and the main amplifier 10 and the electrical length (corresponding to φ1B) between the main amplifier 10 and the combining node N2 is shorter than the total second electrical length (corresponding to φ2) of the electrical length (corresponding to φ2A) between the distribution node N1 and the peak amplifier 12 and the electrical length (corresponding to φ2B) between the peak amplifier 12 and the combining node N2. In the GaN HEMT, as shown in FIG. 5, when the input power Pin is the power P2 and P3 at which the main amplifier 10 and the peak amplifier 12 operate, the amount of change θ1 in the phase of the main amplifier 10 is larger than the amount of change θ2 in the phase of the peak amplifier 12. Therefore, the first electrical length corresponding to φ1 of the path 25 is made shorter than the second electrical length corresponding to φ2 of the path 26. Thereby, the phase difference between the signals S4 and S5 at the combining node N2 can be reduced. Therefore, the overall gain when the input power Pin is the power P2 can be improved, and the characteristics can be improved.

[0043] The difference between the second electrical length and the first electrical length can be set to be 2° or more and 20° or less, and can be set to be 5° or more and 15° or less, in terms of the phase (φ2 - φ1) at the center frequency of the operating band. Thereby, the phase difference between the signals S4 and S5 at the combining node N2 can be made smaller. Therefore, the characteristics can be further improved.

[0044] When the input power Pin is P2 or P3, the difference Δθ1 between the amount of phase change θ1 when passing through the main amplifier 10 and the amount of phase change θ2 when passing through the peak amplifier 12, and the difference between the difference Δφ1 or Δφ2a can be 2° or less, can be 1.5° or less, and can be 1° or less. Thereby, the phase difference between the signals S4 and S5 at the synthesis node N2 can be made smaller. Therefore, the characteristics can be further improved.

[0045] The total third electrical length (corresponding to φ3) between the distribution node N1 and the peak amplifier 14 (corresponding to φ3A) and the electrical length between the peak amplifier 14 and the synthesis node N2 (corresponding to φ3B) is shorter than the first electrical length (corresponding to φ1) and longer than the second electrical length (corresponding to φ2). In a GaN HEMT, as shown in FIG. 5, when the input power Pin is the power P3 at which the main amplifier 10, the peak amplifiers 12 and 14 operate, the amount of phase change θ3 of the peak amplifier 14 is larger than the amount of phase change θ2 of the peak amplifier 12. Therefore, the third electrical length corresponding to φ3 of the path 27 is made longer than the second electrical length corresponding to φ2 of the path 26. Thereby, the phase difference between the signals S5 and S6 at the synthesis node N2 can be made smaller. Therefore, the overall gain when the input power Pin is the power P3 can be improved, and the characteristics can be improved.

[0046] The difference between the third electrical length and the second electrical length can be 2° or more and 20° or less, and can be 5° or more and 15° or less when converted to the phase (φ3 - φ2) at the center frequency of the operating band. Thereby, the phase difference between the signals S5 and S6 at the synthesis node N2 can be made smaller. Therefore, the characteristics can be further improved.

[0047] When the input power Pin is the power P3, the difference between the difference Δθ2b between the amount of phase change θ2 when passing through the peak amplifier 12 and the amount of phase change θ3 when passing through the peak amplifier 14, and the difference Δφ2b can be 2° or less, can be 1.5° or less, and can be 1° or less. Thereby, the phase difference between the signals S5 and S6 at the synthesis node N2 can be made smaller. Therefore, the characteristics can be further improved.

[0048] To achieve the above, the adjustment amount θ5 of the phase of the phase adjuster 20 corresponds to the change amount θ4 of the phases of the signals S5 and S6 by the impedance converters 23 and 24. The adjustment amount θ6 of the phase of the phase adjuster 21 corresponds to Δθ1 and Δθ2a when the input power Pin is the power P2 or P3. The adjustment amount of the phase of the phase adjuster 22 corresponds to Δθ2b when the input power Pin is the power P3.

[0049] When the impedance converters 23 and 24 are provided, the electrical length of the phase adjuster 21 can be 2° or more and 20° or less, and can be 5° or more and 15° or less, in terms of the phase in the signal of the center frequency. The electrical length of the phase adjuster 22 can be 4° or more and 40° or less, and can be 10° or more and 30° or less, in terms of the phase in the signal of the center frequency. Thereby, when designing the Doherty amplifier circuit, the electrical quantity of the phase adjuster 20 is set to adjust the phase difference corresponding to the difference between the phases φ1B, φ2B, and φ3B. Then, the electrical length of the phase adjuster 21 is set to adjust the phase differences Δθ1 and Δθ2a between the main amplifier 10 and the peak amplifier 12. The phase adjuster 22 is set to adjust the phase difference Δθ2b between the peak amplifiers 12 and 14. This facilitates the design of the phase adjusters 21 and 22.

[0050] When no impedance converter is provided between the main amplifier 10 and the synthesis node N2, the electrical length of the phase adjuster 20 can be 67.5° or more and 112.5° or less, can be 78.75° or more and 101.25° or less, and can be 85° or more and 95° or less, in terms of the phase in the signal of the center frequency of the operating band. Thereby, the electrical length of the phase adjuster 20 is set to adjust the electrical lengths of the impedance converters 23 and 24. Thus, the design of the phase adjuster 20 is facilitated.

[0051] Although the 3-way Doherty amplifier circuit has been described as an example, a 2-way Doherty amplifier circuit without the peak amplifier 14 and the impedance converter may also be used. Further, an N-way Doherty amplifier circuit with N being 4 or more may also be used. In this case, N-1 peak amplifiers may be provided.

[0052] The embodiments disclosed this time should be considered as illustrative in all respects and not restrictive. The scope of the present disclosure is shown not by the above description but by the claims, and it is intended that all modifications within the meaning and scope equivalent to the claims are included.

Explanation of Reference Numerals

[0053] 10 Main amplifier 12 (First peak amplifier), 14 (Second peak amplifier) Peak amplifiers 16 Distributor 18 Combiner 20 (First phase adjuster), 21 (Second phase adjuster), 22 (Third phase adjuster) Phase adjusters 23 (First impedance converter), 24 (Second impedance converter) Impedance converters 25, 26, 27 Paths 30, 31, 32, 33, 34, 35 Matching circuits 36, 37, 38, 39 Bias circuits 40, 40a Substrate 40b Semiconductor layer 40c Running layer 40d Barrier layer 42 Source electrode 44 Gate electrode 46 Drain electrode 100 Doherty amplifier circuit N1 Distribution node N2 Combining node Pin Input power S1 (First signal), S2 (Second signal), S3 (Third signal), S4 (Fourth signal), S5 (Fifth signal), S6 (Sixth signal) Sin Input signal Sout Output signal Differences of Δθ1, Δθ2a, Δθ2b, Δφ1, Δφ2a, Δφ2b Change amounts of θ1, θ2, θ3, θ4, φ1, φ2, φ3 Adjustment amounts of θ5, θ6, θ7 Input terminal Tin Output terminal Tout

Claims

1. A distribution node that distributes an input input signal into a first signal and a second signal, A main amplifier including a first GaN HEMT that amplifies the first signal and outputs the amplified signal as a fourth signal, A first peak amplifier including a second GaN HEMT that amplifies the second signal and outputs the amplified signal as a fifth signal, A combining node that combines the fourth signal and the fifth signal and outputs the combined signal to an output terminal as an output signal, comprising, A Doherty amplifier circuit in which a total first electrical length of an electrical length between the distribution node and the main amplifier and an electrical length between the main amplifier and the combining node is shorter than a total second electrical length of an electrical length between the distribution node and the first peak amplifier and an electrical length between the first peak amplifier and the combining node.

2. The Doherty amplifier circuit according to claim 1, wherein a difference between the second electrical length and the first electrical length is 2° or more and 20° or less in terms of phase at a center frequency of an operating band.

3. When an input power of the input signal is a power at which the main amplifier and the first peak amplifier operate, a difference between a change amount of a phase when a signal of the center frequency passes through the main amplifier and a change amount of a phase when the signal of the center frequency passes through the first peak amplifier, and a difference between the second electrical length and the first electrical length converted into a phase at the center frequency, the difference is 2° or less. The Doherty amplifier circuit according to claim 2.

4. Comprising a second peak amplifier including a third GaN HEMT that amplifies a third signal and outputs the amplified signal as a sixth signal, The distribution node distributes the input signal into the first signal, the second signal, and the third signal, The combining node combines the fourth signal, the fifth signal, and the sixth signal and outputs the combined signal to the output terminal as the output signal, An input power of the input signal at which the second peak amplifier turns on is greater than an input power at which the first peak amplifier turns on, The Doherty amplifier circuit according to claim 1, wherein a total third electrical length of an electrical length between the distribution node and the second peak amplifier and an electrical length between the second peak amplifier and the combining node is longer than the second electrical length.

5. A difference between the second electrical length and the first electrical length is 2° or more and 20° or less in terms of phase at a center frequency of an operating band, The Doherty amplifier circuit according to claim 4, wherein a difference between the third electrical length and the second electrical length is 2° or more and 20° or less in terms of a phase at the center frequency.

6. A difference between a change amount of a phase when a signal at the center frequency passes through the main amplifier and a change amount of a phase when the signal at the center frequency passes through the first peak amplifier, and a value obtained by converting a difference between the second electrical length and the first electrical length into a phase at the center frequency is 2° or less, The Doherty amplifier circuit according to claim 5, wherein a difference between a change amount of a phase when a signal at the center frequency passes through the first peak amplifier and a change amount of a phase when the signal at the center frequency passes through the second peak amplifier, and a value obtained by converting a difference between the third electrical length and the second electrical length into a phase at the center frequency is 2° or less.

7. A first impedance converter connected between the first peak amplifier and the combining node; A second impedance converter connected between the second peak amplifier and the combining node; A first phase adjuster connected between the distribution node and the main amplifier; A second phase adjuster connected between the distribution node and the first peak amplifier; A third phase adjuster connected between the distribution node and the second peak amplifier; comprising the electrical length of the second phase adjuster is 2° or more and 20° or less in terms of a phase in a signal at a center frequency of an operating band; The Doherty amplifier circuit according to any one of claims 4 to 6, wherein the electrical length of the third phase adjuster is 4° or more and 40° or less in terms of a phase in the signal at the center frequency.

8. No impedance converter is provided between the main amplifier and the combining node, The Doherty amplifier circuit according to claim 7, wherein the electrical length of the first phase adjuster is 67.5° or more and 112.5° or less in terms of a phase in a signal at the center frequency.

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