All-semiconductor josephson junction device for qubit applications

Abstract

To provide all-semiconductor Josephson junction device for qubit applications, and a method of producing a quantum device.SOLUTION: A quantum mechanical device 200 includes a monolithic crystalline structure 202. The monolithic crystalline structure includes a first region doped to provide a first superconducting region 204, and a second region doped to provide a second superconducting region 206, the second superconducting region being separated from the first superconducting region by an undoped crystalline region 208. The first and second superconducting regions and the undoped crystalline region form a Josephson junction.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Embodiments of the invention claimed herein relate to quantum mechanical devices, and more particularly to all-semiconductor Josephson junction devices for qubit applications.

Background Art

[0002] The coherence time of Josephson junction qubits is generally short, probably related to the number of processing steps and the use of defective materials. For example, aluminum oxide is commonly used to form Josephson junction dielectrics. However, aluminum oxide is known to have an open structure that can couple to Josephson junction qubits, reducing the qubit coherence time. Materials and methods for improving the coherence time in Josephson junction devices are sought.

Summary of the Invention

[0003] According to one embodiment of the invention, a quantum mechanical device includes a monolithic crystal structure. The monolithic crystal structure includes a first region doped to provide a first superconducting region and a second region doped to provide a second superconducting region, the second superconducting region being separated from the first superconducting region by an undoped crystal region. The first and second superconducting regions and the undoped crystal region form a Josephson junction.

[0004]

[0005] According to one embodiment of the invention, a method of manufacturing a quantum mechanical device includes providing a crystalline substrate and doping first and second regions of the crystalline substrate to form first and second superconducting regions and securing a region between the first and second superconducting regions as an undoped crystal region. The first and second superconducting regions and the undoped crystal region form a Josephson junction.According to one embodiment of the present invention, a method of manufacturing a quantum mechanical device includes providing a crystalline substrate and implanting dopants into first and second regions of the crystalline substrate, the first and second regions being separated by undoped crystalline regions. The method includes annealing the first and second regions to form first and second superconducting regions. Annealing includes directing the dopants laterally within the undoped crystalline regions to form conductive regions. The first and second superconducting regions and the conductive regions form Josephson junctions.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0007] Figures 1A and 1B are schematic plan and cross-sectional views of a quantum mechanical device 100 according to an embodiment of the present invention. The quantum mechanical device 100 includes a monolithic crystal structure 102. The monolithic crystal structure 102 includes a first region doped to provide a first superconducting region 104 and a second region doped to provide a second superconducting region 106. The second superconducting region 106 is separated from the first superconducting region 104 by an undoped crystal region 108. The first superconducting region 104, the second superconducting region 106, and the undoped crystal region 108 form a Josephson junction.

[0008] Figure 1C is a schematic view of the lateral dopant concentration profile across the first superconducting region 104, the undoped crystal region 108, and the second superconducting region 106. The concentration level 113 is the dopant concentration at which the dopant-semiconductor alloy becomes superconducting. For Si:B, this level is approximately 2 atomic percent (at.%), or equivalently 1e21 cm -3 above. The concentration level 114 is the dopant concentration at which the doped semiconductor exhibits a permanent metallic conductivity at low temperatures. For Si:B, this level is approximately 0.008 at.%, or equivalently 4e18 cm -3 above. The term "low temperature" may refer to the operating temperature of the quantum mechanical device 100.

[0009] The transition interface region between layer 104 and layer 108 has two boundaries labeled 104’ and 108’ across which the dopant concentrations cross concentration levels 113 and 114 respectively. The region 104 located to the left of boundary 104’ is superconducting at low temperatures. The region 108 located to the right of boundary 108’ is insulating at low temperatures. The region between boundary 104’ and boundary 108’ remains conductive at low temperatures and has a finite conductivity. Similarly, a transition interface region exists between layer 108 and layer 106 and has two boundaries labeled 108’’ and 106’ across which the dopant concentrations cross concentration levels 113 and 114 respectively. The region 106 located to the right of boundary 106’ is superconducting at low temperatures. The region between boundary 108’’ and boundary 106’ remains conductive at low temperatures and has a finite conductivity.

[0010] The transition interface regions between layer 104 and layer 108 and between layer 108 and layer 106 can be minimized in thickness. This is achieved by increasing the abruptness of the dopant concentration profiles labeled 115 and 116 for the left and right transition regions. The abruptness of the dopant concentration profile is represented by the dopant spatial decay in units of nm / decade. A higher abruptness of the concentration dopant profile results in a lower nm / decade number. According to some embodiments, the dopant concentration profile has an abruptness of less than 1 nm / decade.

[0011] The term "undoped crystalline region" can be used herein to refer to a semiconductor with a low enough doping such that its conductivity becomes zero at low temperatures and it becomes an insulator. This naturally occurs in a normally doped semiconductor where the doping level is below the critical value of the metal-insulator (Mott) transition. The Mott transition is where dopant orbitals overlap and form a sub-band with a metallic conductivity that persists at low temperatures. In the Si:B system, the Mott transition occurs at about 4e18 cm -3 -3. Thus, the undoped crystalline regions according to some embodiments of the present invention are 4e18 cm -3It is a Si layer having less B.

[0012] The term "monolithic crystal structure" may be used herein to refer to a substrate formed from a single material, including a reference substrate and a layer of another material deposited on the top surface of the reference substrate, and is not a substrate that forms the substrate step by step. The monolithic crystal structure can be doped or alloyed to incorporate various materials within the region of the substrate. The monolithic crystal structure can be any suitable substrate having a semiconductor crystal plane and two or more portions made from a semiconductor that exhibits superconductivity at low temperatures when doped at a high concentration. The substrate can include an insulating layer, other semiconductor structures, other metal structures, and other useful devices such as capacitors, inductors, pre-built transistors, circuits, etc. Substrates according to some embodiments can be bulk semiconductor substrates made from semiconductors that exhibit superconductivity, such as Si, Ge, SiC, diamond (C).

[0013] According to some embodiments of the present invention, the monolithic crystal structure 102 includes undoped crystalline Si, and the first superconducting region 104 and the second superconducting region 106 include superconducting Si. According to some embodiments, the first superconducting region 104 and the second superconducting region 106 include B-doped Si. According to some embodiments, the first superconducting region 104 and the second superconducting region 106 include Ga-doped Si. According to some embodiments, the monolithic crystal structure 102 includes undoped crystalline Ge, and the first superconducting region 104 and the second superconducting region 106 include Ga-doped Ge or Al-doped Ge. The highest amount of metastable dopant-semiconductor compound can be on the order of 10 to 30 at.%. More specifically, the highest amount of metastable dopant-semiconductor compound can be about 10 at.% for Ga and Al in Ge and 20 at.% for B in Si. In some embodiments, the first superconducting region 104 and the second superconducting region 106 include p-type superconducting Si or Ge. According to some embodiments, the first superconducting region 104 and the second superconducting region 106 are crystalline. According to some embodiments, the first superconducting region 104 is laterally separated from the second superconducting region 106 by an undoped crystal region 108.

[0014] According to some embodiments of the present invention, the monolithic crystal structure 102 includes an upper surface 110 and a lower surface 112 opposite the upper surface. As shown in FIG. 1A, the first superconducting region 104, the second superconducting region 106, and the undoped crystal region 108 may each include an upper surface that is coplanar with the upper surface of the monolithic crystal structure 102.

[0015] Figure 2 is a schematic diagram of a quantum mechanical device 200 according to an embodiment of the present invention. The quantum mechanical device 200 includes a monolithic crystal structure 202, a first superconducting region 204, a second superconducting region 206, and an undoped crystal region 208. The quantum mechanical device 200 includes a superconducting wire 214 disposed on the surface of the monolithic crystal structure 202 that contacts the first superconducting region 204. The superconducting wire 214 may include a superconducting material different from that of the first superconducting region 204. For example, the superconducting wire 214 may include Ni, Al, Ta, TaN, TiN, Ti, or V. The quantum mechanical device 200 according to some embodiments includes a second superconducting wire 216 disposed on the surface of the monolithic crystal structure 202 that contacts the second superconducting region 206. The quantum mechanical device 200 may include a first capacitor 218 that contacts the first-mentioned superconducting wire 214 and a second capacitor 220 that contacts the second superconducting wire 216. The quantum mechanical device 200 may be, for example, a Josephson junction qubit.

[0016] Figure 3 is a flowchart showing a method 300 for manufacturing a quantum mechanical device according to an embodiment of the present invention. The method 300 includes providing a crystalline substrate (302) and doping first and second regions of the crystalline substrate to form first and second superconducting regions and securing a region between the first and second superconducting regions as an undoped crystal region, wherein the first and second superconducting regions and the undoped crystal region form a Josephson junction (304).

[0017] Figures 4 to 9B schematically illustrate exemplary processes for forming a quantum mechanical device according to some embodiments of the present invention. Figure 4 is a schematic cross-sectional view of a substrate 400. The substrate 400 can be, for example, a crystalline substrate. The substrate 400 can be, for example, an undoped Si substrate or a lightly doped Si substrate. The process for forming a quantum mechanical device includes doping the first and second regions of the substrate 400 to form the first and second superconducting regions, and securing the region between the first superconducting region and the second superconducting region as an undoped crystal region. The process for doping the first and second regions can include forming a capping layer 402 on the substrate 400. The capping layer 402 can include, for example, SiO2.

[0018] The process can include depositing a resist on the capping layer and patterning the resist. Figures 5A and 5B are schematic plan and cross-sectional views of a substrate 500 and a capping layer 502 having a patterned resist 504 formed on the top surface of the capping layer 502. The patterned resist 504 exposes two portions of the capping layer 502.

[0019] The process may include etching a capping layer to expose a first portion and a second portion of a monolithic crystal structure. FIGS. 6A and 6B are schematic top and cross-sectional views of a substrate 600, a capping layer 602, and a resist 604. The etched capping layer 602 exposes a first portion 606 and a second portion 608 of the substrate 600 where first and second superconducting regions are to be formed. The capping layer 602 may be etched using, for example, chemical oxide removal (COR) or a diluted hydrofluoric acid solution (DHF). The resist 604 is undercut to reduce the size of a portion 610 of the capping layer 602 between the first portion 606 and the second portion 608. The portion 610 may be reduced to a sub-lithographic size. For example, the portion 610 may have a width of less than 5 nm. According to some embodiments, the portion 610 may have a width of 3 nm or less. The frequency of the Josephson junction device may be tuned by adjusting the image size of the portion 610. The portion 610 may be referred to herein as an oxide mandrel. In some embodiments, the width of the oxide mandrel 610 may be made wider to account for implantation lateral straggle or dopant diffusion or both, which are carried out in the next process step as detailed below. In some examples, the width of the oxide mandrel may be 15 nm to account for dopant implantation straggle and diffusion of 5-6 nm from each side of the mandrel.

[0020] The process may include removing the resist. FIGS. 7A and 7B are schematic top and cross-sectional views of a substrate 700 and an etched capping layer 702 after the resist has been removed.

[0021] The doping process may include implanting dopants into first and second regions of a crystalline substrate. The doping process may also include absorbing dopants within the first and second regions of the crystalline substrate and annealing the first and second regions. FIGS. 8A and 8B are schematic top and cross-sectional views of a substrate 800 and an etched capping layer 802 having a layer 804 of dopants where implantation and / or absorption of the dopants has been performed on the substrate 800 and the capping layer 802. The dopant can be, for example, B, Al, or Ga. After implantation and / or absorption of the dopant 804 into the substrate 800 and the capping layer 802, the substrate 800 is annealed, and first region 806 and second region 808 exhibiting superconductivity at low temperatures can be formed. For example, the implantation can include ion-beam implantation or plasma immersion implantation. Alternatively, the process of absorbing doping can utilize gas immersion laser doping. Alternatively, the doping process can include selective epitaxial growth of doped Si or Ge on a lattice-matched crystalline substrate. Selective epitaxial growth can also include using reactive ion etching (RIE) to recess regions 806 / 808 within the exposed substrate 800 and filling the recessed regions with a doped epitaxial material. The doping process can then be followed by laser annealing to form highly activated, highly doped regions 806 / 808 that exhibit superconductivity at low temperatures. In the case of gas immersion laser doping, absorption of the dopant and laser melt annealing are performed simultaneously, and the dopant is absorbed into the molten substrate surface during laser annealing and activated during surface solidification. Alternatively, a solid source of dopant can be deposited on the exposed substrate 800 and then absorbed into regions 806 / 808 during laser melt annealing.

[0022] The terms "epitaxial growth and / or deposition" and "epitaxially formed and / or grown" mean the growth of a semiconductor material (crystalline material) on the deposition surface of another semiconductor material (crystalline material), and the semiconductor material being grown (crystalline over-layer) has substantially the same crystal characteristics as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gas can be controlled, and the system parameters can be set such that the atoms to be deposited reach the surface with sufficient energy to move around on the deposition surface of the semiconductor substrate. Thus, the atoms to be deposited adapt themselves to the crystal arrangement of the atoms on the deposition surface. The semiconductor material grown epitaxially can have substantially the same crystal characteristics as the deposition surface on which the epitaxially grown material is formed. For example, an epitaxially grown semiconductor material deposited on the <100> oriented crystal surface of silicon can exhibit a <100> orientation with an atomic arrangement and spacing similar to that of silicon. In some embodiments of the present invention, the epitaxial growth process or the deposition process or both can be selective to form on a semiconductor surface, and the material may or may not be deposited on other exposed surfaces such as a silicon dioxide surface or a silicon nitride surface.

[0023] In some embodiments of the present invention, the gas source for epitaxial deposition of semiconductor materials includes a silicon-containing gas source, a germanium-containing gas source, a carbon-containing source, or a combination thereof. For example, a silicon layer can be epitaxially deposited or grown from a silicon-gas source selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, and combinations thereof. A germanium layer can be epitaxially deposited from a germanium-gas source selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. A carbon (diamond) layer can be epitaxially deposited from a carbon gas source selected from the group consisting of methane, ethylene, acetylene, propane, isobutane, and combinations thereof. A silicon-germanium alloy or silicon carbide layer can be epitaxially formed using such a combination of gas sources. Carrier gases such as hydrogen, nitrogen, helium, argon, etc. can be used. In some embodiments of the present invention, the epitaxial semiconductor material includes in-situ doping with boron, aluminum, or gallium. In this case, a gaseous precursor for B, Al, or Ga is added to the gas mixture. Such dopant gas sources include diborane for boron, trimethylaluminum TMA for aluminum, and trimethylgallium TMG for gallium.

[0024] Several suitable techniques such as shallow ion implantation or in-situ epitaxial growth can be used to dope the semiconductor layer with a p-type dopant at a high concentration. As used herein, "doped at a high concentration" means that the atomic concentration of the dopant is 10 21 cm -3(equivalent to about 2 atomic percent) can be exceeded. In some embodiments of the present invention, the dopant concentration ranges from 2 atomic percent to 30 atomic percent and is, for example, 10 atomic percent. A rapid anneal such as a nanosecond anneal can be used at a temperature tuned to melt the highly doped semiconductor layer to a desired depth. For melting of the semiconductor layer, the dopant is redistributed throughout the molten layer to form a uniform metastable semiconductor-dopant alloy. The atomic concentration of the dopant in the resulting alloy exceeds the dopant maximum solid solubility limit. The dopant solid solubility limit (the highest concentration of dopant that can be uniformly mixed into the solid semiconductor) is typically 1 to 2 atomic percent. Annealing on the nanosecond scale enables mixing of the dopant with the liquid semiconductor at a concentration exceeding each respective solid solubility limit and then quenching the solution on the nanosecond scale to retain a highly metastable dopant-semiconductor alloy. Epitaxially grown Si or Ge semiconductors can be doped by adding p-type dopants (e.g., B, Ga, Al) according to the maximum solid solubility in the semiconductor host. In an Si host, boron may be preferred due to its high solid solubility in Si, and in a Ge host, Ga or Al may be preferred dopants due to their high solid solubility in Ge. The semiconductor layer can be epitaxially formed and doped by various methods such as in-situ doped epitaxy (doping during deposition), implantation and plasma doping, or vapor phase doping including doping during nanosecond annealing also known as gas immersion laser doping. In-situ doped epitaxy utilizes gaseous precursors such as diborane B2H6 for B, trimethylaluminum TMA for Al, and trimethylgallium TGA for Ga to incorporate the dopant during epitaxial growth. Ion implantation is, 11 B, 27 Al, 69 Ga, 71Using purified ionized isotopes such as Ga, a selected dopant is implanted into the exposed substrate 800 to a predetermined depth at a predetermined dose. Plasma immersion doping includes implanting ionized gaseous precursors such as B2H6+, BF3+, BCl3+, TGA+, TMA+, and their ionized radicals. Gas immersion laser doping may use a B2H6, BF3, or BCl3 gas source to absorb B into the exposed substrate 800. A dopant solid source for laser-induced doping may use a pure solid material such as boron, aluminum, gallium, etc. on the exposed substrate 800. Each of these doping techniques may have limitations regarding the amount and purity of the dopant that can be incorporated into the underlying semiconductor material. One of the chemical limitations regarding incorporating a dopant into a host solid material is a physical quantity called the solubility of a particular dopant in a particular host material.

[0025] Solubility is a function of ambient temperature and often peaks slightly below the melting point of the host material (e.g., 100 - 200 °C below). In Si-based semiconductors, a typical maximum solubility limit is reached at about 1100 - 1250 °C, and the maximum solubility limit is usually less than 2 - 3 atomic percent for common dopants such as B, or equivalently 1.5×10 21 cm -3 . Solubility is low at low ambient temperatures, and thus uniform incorporation of common dopants into Si-based semiconductors is, for example, about 1 at.% or 5×10 20 cm -3 or less at about 1000 °C. In-situ doped epitaxy may be able to confine dopants within the growing host material beyond the maximum solubility limit. However, such non-equilibrium incorporation of dopants into the growing host material usually does not exceed an amount equal to some maximum solubility limit for the dopant-host pair. In Si-based semiconductors, in-situ doped epitaxy can incorporate some dopants up to several at.% (e.g., 4 - 6 at.%), or equivalently 3×10 21 cm -3can be incorporated up to. Furthermore, such highly metastable materials cannot be maintained at high temperatures for long periods. For example, by holding such a material at 600 °C for a few seconds, an excess dopant exceeding the dopant solubility limit at 600 °C, which is usually less than 10 20 cm -3 precipitates. Dopant precipitates and clusters in a doped uniform semiconductor can act as scattering centers and may increase quantum decoherence in a superconducting device, so their presence may be undesirable.

[0026] Ion implantation and plasma doping can also introduce dopants sufficiently beyond their maximum solid solubility limit, but may require high-temperature annealing to improve the semiconductor material damaged by implantation, diffuse and redistribute the dopants in the implanted material, and place the dopants within lattice substitutional sites. Ion implantation has the advantage of providing isotopically purified dopants without any inadvertent contamination such as carbon, fluorine, chlorine, hydrogen, nitrogen, etc. Contamination and inhomogeneities are undesirable as they can contribute to quantum decoherence that reduces the quantum bit coherence time. Ion implantation parameters are selected to implant or place a selected dopant isotope within a predetermined surface layer depth and up to a predetermined concentration level. 11 For implanting B+ into Si, the implantation energy ranges from 200 eV to 10 keV to enable an implanted surface layer from 5 nm to 80 nm, and the implantation dose ranges from 1e15 cm -2 to 5e16 cm -2 and from 1e21 cm -3 to 1e22 cm -3Enables the average boron concentration within the implanted layer up to. Dopant implantation can be assisted by a pre - amorphous implantation (PAI) consisting of elements that are electrically neutral with respect to the conductivity within the substrate. The purpose of PAI is to intentionally damage or amorphize the exposed crystal to suppress dopant - ion channeling and set up boundaries for dopant redistribution as discussed below. To avoid any crystal contamination that contributes to quantum decoherence, the PAI species is chosen to be a substrate - native ion, e.g., Si+ for a Si crystal. The PAI energy is chosen to set a certain depth of the amorphous or damaged crystal layer. The PAI dose is chosen to produce the desired level of damage, e.g., amorphization, within the implanted layer. Both the PAI energy and the PAI dose depend on the implant species and the substrate constituents. PAI is generally performed before dopant implantation. To implant Si+ into Si, the implant energy ranges from 3 keV to 50 keV, enabling an amorphous surface layer from 10 nm to 100 nm, and the implant dose ranges from 1e15 cm -2 to 5e15 cm -2 up to. During implantation, the dopant is redistributed by an annealing process and results in a lower dopant concentration after redistribution. Therefore, the target dopant implant dose should reflect the volume change of the doped region during dopant redistribution. For example, a shallow 11 B+ implantation into Si at 500 eV implant energy produces a doped region with a depth of 7 nm, but during dopant redistribution, the doped region becomes 30 nm deep. In this example, the implanted 11 B+ dose of 1.2e16 cm -2 results in a boron doping level of approximately 4e21 cm -3 or 8 at.% after redistribution. The redistribution of the implanted dopant is particularly difficult because it requires a long - term high - temperature anneal. Such an anneal can cause precipitation of excess dopants, which can adversely affect the conductivity and device operation.

[0027] In some embodiments, laser annealing is utilized to form a semiconductor layer doped to a high concentration exhibiting superconductivity. As used herein, the term "laser annealing" refers to an annealing method that induces heat at the surface being processed using a laser. A laser is an electro-optical device that emits coherent radiation. In some embodiments, a typical laser emits light in a narrow, low-divergence beam having a defined wavelength. In some examples, the advantage of using a laser for the annealing process is that the light can be easily shaped, focused onto a specific area of the annealing surface, and a very high radiation intensity can be achieved with a short exposure duration.

[0028] In some embodiments, a short exposure duration is achieved by raster scanning a focused laser beam across the substrate surface. In this case, the exposure duration measured at the full width at half maximum (FWHM) of the incident intensity is the beam width in the scanning direction divided by the scanning speed. In an alternative embodiment, a short exposure duration is achieved by using a pulsed laser. In this case, the laser beam is shaped to achieve the required peak intensity across a selected substrate area, such as the entire product die, and the laser operates in a pulsed mode, such as in the case of a Q-switched laser. The pulse duration of the Q-switched laser at the intensity FWHM determines the substrate exposure time. The exposure process can be repeated for the entire wafer surface using a step-and-repeat technique. In some embodiments, the exposure to light, i.e., laser annealing, for example by the application of a laser beam, includes exposures from 1 pulse to 100 pulses.

[0029] In some embodiments, the laser type used in the laser annealing method is selected from a solid-state Nd:YAG laser that emits at 1064 nm and frequency-doubles or -triples at 532 nm or 355 nm, respectively, or an excimer laser that emits below 400 nm. The excimer laser can operate by a chemical reaction involving an excited dimer, i.e., an excimer, which is a short-lived dimer or heterodimer molecule formed from two species (atoms) at least one of which is in an excited electronic state. Commonly used excimer molecules include F2 (fluorine, emits at 157 nm), and noble gas compounds such as ArF (193 nm), KrCl (222 nm), KrF (248 nm), XeCl (308 nm), XeF (351 nm). The excimer laser typically operates in a Q-switched pulse mode suitable for step-and-repeat pulse wafer exposure. The solid-state Nd:YAG laser can be efficiently frequency-doubled or -tripled and provides an alternative to the excimer laser due to its stable high-power output at 1,064 nm, emitting at 532 nm or 355 nm. The solid-state laser can be configured in continuous mode, pulse mode, or Q-switched pulse mode, suitable for both raster scanning and step-and-repeat pulse operation. In some embodiments, a XeCl laser (308 nm) that couples about 40 - 60% of the incident radiation to the semiconductor layer within about 10 - 20 nm of the surface can be utilized.

[0030] When a substrate having a semiconductor layer doped to a high concentration is exposed to laser radiation either by raster scanning or by laser pulses, its surface temperature begins to rise from its reference value and then immediately drops. A typical temperature-time trace of a nanosecond laser annealing process includes four distinct temperature regions: an initial or reference substrate temperature, a heating portion, a temperature peak point, and a cooling portion. The initial or reference substrate temperature is in the range of 23 °C (room temperature) to 400 °C. This temperature is usually set by a hot plate on which the substrate lies. The laser beam raises the surface temperature of the substrate from the reference temperature to the peak at a rate of rise from about 1,000,000,000 °C / second to about 100,000,000,000 °C / second. After the laser radiation exposure, the surface temperature rapidly drops back to the reference temperature at a rate of fall from about 300,000,000 °C / second to about 30,000,000,000 °C / second. The annealing duration measured around the temperature peak point typically ranges from about 1 nanosecond to about 500 nanoseconds, usually in the range of about 10 to 100 nanoseconds at a level 50 °C below the peak point. It has become customary to specify the process duration of laser annealing by the radiation exposure duration at FWHM rather than by the annealing duration at a temperature level 50 °C below the peak temperature. These durations are related to each other, and in some embodiments, the annealing duration is a small fraction (e.g., about 1 / 3) of the radiation exposure duration.

[0031] The surface temperature rise induced by the laser is set by the laser incident radiation intensity, the laser pulse or exposure duration, and the thermal and optical properties of the substrate. Short front-side laser exposure causes non-uniform heating. The depth of heat penetration in the case of nanosecond-scale laser pulses ranges from about 1 micron to about 3 microns in semiconductors such as Si and Ge, and from about 100 nanometers to about 500 nanometers in typical dielectrics. Thus, a relatively thin, highly doped semiconductor layer is heated relatively uniformly throughout its thickness with a small top-to-bottom temperature gradient of about 0.1 - 0.3 °C / nm. The required radiation intensity for the highly doped semiconductor layer to reach its melting point (e.g., 1412 °C for Si or 940 °C for Ge) will be understood to depend on the underlying substrate, the laser pulse duration and energy density, and the selected laser wavelength. In some embodiments, the highly doped semiconductor layer is Si doped with B, the nanosecond laser wavelength is 308 nm, the substrate reference temperature is 250 °C, the pulse duration at FWHM is 160 nanoseconds, and the combined laser energy density at which the highly doped Si begins to melt is 0.6 J / cm 2 2 (which corresponds to an incident laser energy density of 1.4 J / cm 2 2). This calibration point can be converted to the required incident laser energy density for a particular choice of semiconductor layer by appropriately normalizing for the 308 nm light reflectivity and the difference in melting point for the semiconductor layer. For example, the incident laser energy density required to melt a highly doped Ge layer (having a light reflectivity of about 0.47 at 308 nm) is about 0.68 J / cm 2 2. The type of highly doped semiconductor layer, the substrate structure, and the laser parameters can vary and affect the choice of incident laser energy density, but incident laser energy densities in the range from about 0.1 J / cm 2 2 to about 3 J / cm 2 2, and laser radiation exposure durations in the range from about 5 to 500 nanoseconds can be utilized to melt the highly doped semiconductor layer.

[0032] The dopant diffusion rate in the liquid phase is about 10 9 (one billion) times higher than that in the solid phase. Therefore, the dopants within the highly doped region disperse throughout the entire liquid layer, defining a region made of a metastable semiconductor-dopant alloy. Importantly, due to the extremely short duration of the anneal, any dopants in the adjacent solid layer do not diffuse. Depending on the exact dopant and semiconductor materials, an anneal duration above the melting point may be selected to allow sufficient processing time for dopant redistribution. In some embodiments of the present invention, selecting an appropriate anneal duration can be achieved by performing a plurality of consecutive short-duration anneals.

[0033] After redistributing the dopants throughout the liquid phase of the molten semiconductor layer, the semiconductor structure can be quenched to prevent excess dopant precipitation and clustering. Quenching subjects the liquid layer to rapid solidification and the resulting solid phase to rapid cooling, whereby the dopants within the resulting solid phase are unable to move to their nearest neighbors, thus preventing the dopants from aggregating into clusters and precipitates. The rate of quenching is related to the anneal duration, with longer anneals resulting in lower quenching rates, which for a 100 ns anneal is about 10 10 (ten billion) degrees per second. Since high-speed quenching is desirable, it may be advantageous to perform several consecutive short anneals, each with high-speed quenching, rather than one long anneal with an equivalent duration but a lower quenching rate. High-speed quenching produces a uniformly doped, metastable, highly doped p-type semiconductor alloy. Such alloys exhibit superconductivity at low temperatures and are suitable for superconducting devices.

[0034] The atomic percentage or concentration of dopants within the resulting highly doped semiconductor layer exceeds the dopant solid solubility limit within the material and is about 1×10 21 cm -3Higher. The implantation, annealing, and quenching processes can be repeated any number of times to further increase the dopant concentration that is distributed throughout the highly doped semiconductor layer. The resulting dopant-semiconductor metastable alloy enables a low film resistivity at room temperature and superconductivity at low temperatures. In some embodiments of the present invention, the electrical resistivity at room temperature of the resulting dopant-semiconductor metastable alloy is 1.5×10 -4 Ω cm or less, or equivalently, approaches the electrical resistivity of a metal film.

[0035] The process of forming a quantum mechanical device according to some embodiments of the present invention includes annealing a first and a second region to form a first and a second superconducting region. FIGS. 9A and 9B are schematic top and cross-sectional views of a substrate 900 in which the first and second regions are annealed to form a first superconducting region 906 and a second superconducting region 908. A region 910 of the substrate between the first superconducting region 906 and the second superconducting region 908 remains undoped. This is because the capping layer 902 prevents a layer of dopant 904 from being implanted or absorbed within that region. The process may include annealing the first and second regions multiple times to form a crystalline superconductor. The first and second regions may be implanted and annealed multiple times to form the first superconducting region 906 and the second superconducting region 908. The annealing can be, for example, laser annealing. The width of the region 910 can also be adjusted by changing the implantation conditions and the annealing conditions. Shallow implantation at an implantation energy of less than 1 keV can be utilized to limit lateral dopant diffusion or implanted scatter. By annealing the doped regions, the depth as well as the width of the first superconducting region 906 and the second superconducting region 908 can increase, thereby reducing the separation between the first superconducting region 906 and the second superconducting region 908. However, excessive solid-phase dopant diffusion may be undesirable as it can lead to dopant precipitation and the formation of dopant clusters in heavily doped metastable semiconductor-dopant alloys. Dopant clusters can contribute to quantum decoherence that reduces the quantum bit coherence time.

[0036] According to some embodiments, annealing is used to direct dopants laterally into region 910 without inducing dopant precipitation in regions 906 and 908. A very short anneal (<1 msec) cannot move / diffuse dopants in a solid material over any appreciable distance exceeding 1 - 3 nm, and an extremely short anneal (<1 microsec) cannot enable dopants to move to their nearest neighbors (at a distance of about 1 nm). Such short anneals can be utilized to activate dopants and direct them laterally by only 1 - 3 nanometers without excessive dopant precipitation in regions 906 / 908. A more efficient method of doing both activating dopants and diffusing dopants laterally without precipitation is the aforementioned nanosecond-scale laser melt annealing. To utilize such extremely short laser annealing, the doped regions 806 / 808 must be selectively melted relative to the undoped regions 810 / 910. This is achieved when the doped regions 806 / 808 have a lower melting point than the internal undoped regions 810 / 910. For example, the implanted regions 806 / 808 can exhibit a suppression of their melting point of 200 - 250 °C relative to the unimplanted crystal due to implantation-induced crystal damage and amorphization. Further, the implantation-induced crystal damage extends under the oxide mandrel 610 due to the lateral spread of the implanted ions. Thus, the melting points of the damaged crystalline material under the oxide mandrel are classified, being high in the internal regions of 810 / 910 and low at the edges of 810 / 910. By tuning the laser incident energy density, the extent of melting under the oxide mandrel 610 can be controlled. The dopants will have sufficient time to redistribute laterally within the molten layer to the lateral solid boundary during the nanosecond-scale laser pulse, forming a sharp profile between region 910 and regions 906 / 908.Thus, in some embodiments, the width of region 910 is controlled by the width of oxide mandrel 610 and implantation parameters that affect the lateral ion straggle and the extent of crystal damage under mandrel 610, i.e., the implantation energy, and annealing parameters such as the incident laser energy density that affect the extent of crystal melting under oxide mandrel 610. Due to the first requirement of minimizing the residual doping in the region under oxide mandrel 610 and the second requirement of controlling the extent of lateral and vertical crystal damage to set the boundaries of regions 906 and 908, conflicting implantation requirements can exist for the dopant implantation process. Such conflicting requirements can be resolved by introducing additional PAI implantation of regions 806 / 808 using native ions of regions 806 / 808, i.e., by implanting Si+ into the silicon substrate or Ge+ into the germanium substrate. In this case, the PAI implantation parameters for the native ions are selected to control the desired extent of crystal damage, and the implantation parameters for the dopant ions are selected to minimize the residual doping in regions 810 / 910. In some embodiments, the dopant ion implantation energy is selected to be less than 1 keV, preferably less than 500 eV, while the native ion implantation energy is selected to be greater than 1 keV, preferably greater than 10 keV. However, by implanting the dopant into regions 906 / 908, region 910 can become a conductive region at room temperature due to lateral implantation straggle. The first superconducting region 906, the second superconducting region 908, and the conductive region can form a Josephson junction with a higher critical current than a Josephson junction having a dielectric gate at low temperature.

[0037] The process may include removing the oxide layer, for example using DHF. FIGS. 1A and 1B are a schematic plan view and a cross-sectional view of the quantum mechanical device of FIGS. 9A and 9B after removal of the oxide layer. The first superconducting region 104, the second superconducting region 106, and the undoped crystal region 108 form a Josephson junction at low temperature. The lateral dopant profile across regions 104, 106, and 108 is shown in FIG. 1C. The undoped region or the region 108 doped at a low concentration may be conductive at room temperature due to its residual doping, but its conductivity becomes zero at low temperature. The dopant profile transition region between regions 104 / 106 and region 108 is minimized by controlling the implant lateral spread and selecting an annealing process with little dopant diffusion in the solid phase.

[0038] According to some embodiments of the present invention, the Josephson junction may be coupled to other structures using wires. FIGS. 10A-12B are schematic diagrams of a process for forming a wire connected to a Josephson junction. The process may include patterning a lift-off resist for the wire. FIGS. 10A and 10B are a schematic plan view and a cross-sectional view of a substrate 1000 on which a first layer 1002 and a second layer 1004 of lift-off resist are formed thereon. The first layer 1002 covers a part of the first superconducting region 1006 and the second superconducting region 1008, and a region 1010 that separates the first superconducting region 1006 from the second superconducting region 1008. The first layer 1002 may be undercut to allow lift-off of the resist after the wire material is deposited.

[0039] The process may include depositing a superconducting material. FIGS. 11A and 11B are a schematic plan view and a cross-sectional view of a substrate 1100 on which a superconducting material 1112 is deposited thereon. The superconducting material 1112 is in lateral contact with the portions of the substrate 1100 exposed by the first layer 1102 and the second layer 1104 of the resist.

[0040] The process may include lift-off of the resist and the superconducting material deposited thereon. FIGS. 12A and 12B are schematic top and cross-sectional views of a substrate 1200 having a first superconducting wire 1202 in contact with a first superconducting region 1206 of the substrate 1200 and a second superconducting wire 1204 in contact with a second superconducting region 1208 of the substrate 1200. The first superconducting wire 1202 and the second superconducting wire 1204 may connect Josephson junctions to other structures such as capacitors or resonators. A capacitor or resonator may be formed during the formation of the superconducting wires 1202, 1204 or in a separate process. FIG. 2 is a schematic diagram of a quantum mechanical device 200 including capacitors 218, 220 connected to superconducting wires 214, 216 to form Josephson junction qubits.

[0041] According to some embodiments of the present invention, the crystalline region between the two superconducting regions is a conductive crystalline region at room temperature rather than an undoped crystalline region. According to some embodiments of the present invention, a quantum mechanical device includes a monolithic crystal structure including a first region doped to provide a first superconducting region at low temperature, a second region doped to provide a second superconducting region at low temperature, and a third region doped to provide a first conductive region at room temperature. The first conductive region separates the first superconducting region from the second superconducting region. The first and second superconducting regions and the first conductive region form Josephson junctions at low temperature.

[0042] FIG. 13 is a flowchart showing a method 1300 for manufacturing a quantum mechanical device according to an embodiment of the present invention. The method 1300 includes providing a crystalline substrate (1302) and implanting dopant and native elements into first and second regions of the crystalline substrate, the first and second regions being separated by undoped crystalline regions (1304). The method 1300 includes annealing the first and second regions to form first and second superconducting regions at a low temperature, the annealing including directing the dopants laterally into the undoped crystalline regions to form conductive regions at room temperature, the first and second superconducting regions and the conductive regions forming Josephson junctions at a low temperature (1306).

[0043] Embodiments of the present invention include Josephson junction devices having crystalline Josephson junction barriers instead of SiO2 or other oxide dielectrics. The barrier may include, for example, single crystal undoped or lightly doped Si or Ge. The crystalline material may have fewer defects and thus improved quantum coherence. Device fabrication may be compatible with conventional CMOS processing and may have a short process flow. The device frequency may be lithographically tuned.

[0044] According to some embodiments of the present invention, a Josephson junction qubit device uses superconducting Si or Ge as the source and drain of the Josephson junction and uses undoped or lightly doped crystalline Si or Ge as the device junction. According to some embodiments of the present invention, a method for manufacturing a quantum mechanical device includes patterning an oxide mandrel having a width of 6 to 15 nm on undoped Si. The method includes forming p-type epitaxial layers (P+ epi) at both ends of the oxide mandrel and subsequent ion implantation and laser annealing to crystallize the implanted semiconductor. The method includes removing the oxide mandrel with DHF. The method may also include forming capacitors and resonator wires by a lift-off process.

[0045] According to some embodiments of the present invention, a Josephson junction (JJ) qubit device includes a superconducting semiconductor region forming source and drain regions of the JJ, and an undoped or lightly doped crystalline semiconductor region forming a JJ gate region disposed between the source region and the drain region.

[0046] According to some embodiments of the present invention, a method of forming a JJ qubit device includes patterning an oxide mandrel on an undoped Si substrate, forming P+ epi regions at both ends of the oxide mandrel, and subsequent implantation and annealing. This method includes annealing the P+ epi regions to form a crystallized implanted Si region, removing the oxide mandrel to form an undoped crystalline Si region, and forming a JJ gate region disposed between the P+ epi regions. The method according to some embodiments further includes forming capacitors and resonator wires by a lift-off process.

[0047] The descriptions of various embodiments of the present invention are presented for purposes of illustration but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein are chosen to best explain the principles of the embodiments, actual applications or technical improvements over technologies found in the marketplace, or to enable those skilled in the art to understand the embodiments disclosed herein. The present invention is also disclosed below. <Appendix 1> A quantum mechanical device, comprising a monolithic crystal structure, the monolithic crystal structure comprising a first region doped to provide a first superconducting region, and a second region doped to provide a second superconducting region, the second superconducting region being separated from the first superconducting region by an undoped crystal region, the second region and A quantum mechanical device in which the first and second superconducting regions and the undoped crystal region form a Josephson junction. <Appendix 2> The quantum mechanical device according to Appendix 1, wherein the monolithic crystal structure includes undoped crystalline Si, and the first and second superconducting regions include superconducting Si. <Appendix 3> The quantum mechanical device according to Appendix 1 or 2, wherein the first and second superconducting regions include B-doped Si. <Appendix 4> The quantum mechanical device according to any one of Appendices 1 to 3, wherein the first and second superconducting regions include Ga-doped Si. <Appendix 5> The quantum mechanical device according to any one of Appendices 1 to 4, wherein the monolithic crystal structure includes undoped crystalline Ge, and the first and second superconducting regions include superconducting Ge. <Appendix 6> The quantum mechanical device according to any one of Appendices 1 to 5, wherein the first and second superconducting regions include Ga-doped Ge. <Appendix 7> The quantum mechanical device according to any one of Appendices 1 to 6, wherein the first and second superconducting regions include Al-doped Ge. <Appendix 8> The monolithic crystal structure includes an upper surface and a lower surface opposite to the upper surface. The quantum mechanical device according to any one of Appendices 1 to 7, wherein the first and second superconducting regions and the undoped crystal region each include an upper surface that is coplanar with the upper surface of the monolithic crystal structure. <Appendix 9> The quantum mechanical device according to any one of Appendices 1 to 8, further comprising a superconducting wire disposed on the surface of the monolithic crystal structure and in contact with the first superconducting region, the superconducting wire including a superconducting material different from that of the first superconducting region. <Appendix 10> A second superconducting wire disposed on the surface of the monolithic crystal structure and in contact with the second superconducting region, A first capacitor in contact with the superconducting wire described first, A second capacitor in contact with the second superconducting wire Further comprising, The quantum mechanical device according to appendix 9, wherein the quantum mechanical device is a Josephson junction quantum bit. <Appendix 11> The quantum mechanical device according to any one of appendices 1 to 10, wherein the undoped crystal region separates the first and second superconducting regions by less than 5 nm. <Appendix 12> The quantum mechanical device according to any one of appendices 1 to 11, wherein the first superconducting region and the second superconducting region are crystalline. <Appendix 13> A quantum mechanical device, Comprising a monolithic crystal structure, the monolithic crystal structure being, A first region doped to provide a first superconducting region, A second region doped to provide a second superconducting region, A third region doped to provide a metal region, wherein the second superconducting region is separated from the first superconducting region by the metal region, the third region Comprising, A quantum mechanical device in which the first and second superconducting regions and the metal region form a Josephson junction. <Appendix 14> A method for manufacturing a quantum mechanical device, Providing a crystalline substrate, Doping the first and second regions of the crystalline substrate to form first and second superconducting regions and securing a region between the first superconducting region and the second superconducting region as an undoped crystal region, A method in which the first and second superconducting regions and the undoped crystal region form a Josephson junction. <Supplementary Note 15> A method for manufacturing the quantum mechanical device according to Supplementary Note 14, wherein doping the first and second regions of the crystalline substrate with a dopant includes absorbing the dopant on the first and second regions of the crystalline substrate and annealing the first and second regions of the crystalline substrate. <Supplementary Note 16> A method for manufacturing the quantum mechanical device according to Supplementary Note 14 or 15, wherein the crystalline substrate contains undoped crystalline Si, and the first and second regions of the crystalline substrate are doped with B or Ga. <Supplementary Note 17> Doping the first and second regions of the crystalline substrate includes injecting a dopant into the first and second regions of the crystalline substrate, and annealing the first and second regions to form the first and second superconducting regions A method for manufacturing the quantum mechanical device according to any one of Supplementary Notes 14 to 16. <Supplementary Note 18> A method for manufacturing the quantum mechanical device according to Supplementary Note 17, wherein annealing the first and second regions to form the first and second superconducting regions includes laser-annealing the first and second regions to form the first and second superconducting regions. <Supplementary Note 19> A method for manufacturing the quantum mechanical device according to any one of Supplementary Notes 14 to 18, wherein the undoped crystalline region separates the first and second superconducting regions by less than 5 nm. <Supplementary Note 20> A method for manufacturing the quantum mechanical device according to any one of Supplementary Notes 14 to 19, further including forming a first superconducting wire in contact with the first superconducting region and a second superconducting wire in contact with the second superconducting region.

Claims

1. 1. A method of manufacturing a quantum device, comprising: providing a crystalline substrate; forming a capping layer on the crystalline substrate; Etching the capping layer to expose a first region and a second region of the crystalline substrate; doping the first and second regions of the crystalline substrate with a dopant to form first and second superconducting regions in an upper surface of the crystalline substrate and a crystalline region between the first and second superconducting regions in the upper surface of the crystalline substrate; wherein the first superconducting region, the second superconducting region, and a crystalline region between the first superconducting region and the second superconducting region form a Josephson junction.

2. 2. The method of claim 1, wherein forming the crystalline region comprises forming a conductive crystalline region as the crystalline region separating the first superconducting region and the second superconducting region.

3. 2. The method of claim 1, wherein forming the crystalline region comprises reserving as the crystalline region an undoped crystalline region separating the first superconducting region and the second superconducting region.

4. The method comprises: depositing a resist on the capping layer; patterning the resist; and wherein the exposing includes etching the portion of the capping layer exposed from the resist to expose the first and second regions of the crystalline substrate and undercutting the portion of the capping layer underlying the resist between the first and second regions of the crystalline substrate.

5. 5. The method of claim 1, wherein doping the first and second regions of the crystalline substrate with a dopant comprises absorbing the dopant on the first and second regions of the crystalline substrate; and annealing the first and second regions of the crystalline substrate.

6. The method of manufacturing a quantum device according to any one of claims 1 to 5, wherein the crystalline substrate comprises undoped crystalline Si, and the first and second regions of the crystalline substrate are doped with B or Ga.

7. doping the first region and the second region of the crystalline substrate with a dopant; implanting a dopant into the first region and the second region of the crystalline substrate; annealing the first region and the second region to form the first superconducting region and the second superconducting region; 7. A method for manufacturing a quantum device according to claim 1, comprising:

8. 8. The method of fabricating a quantum device as recited in claim 7, wherein annealing the first and second regions to form the first and second superconducting regions comprises laser annealing the first and second regions to form the first and second superconducting regions.

9. 4. The method of fabricating a quantum device as recited in claim 3, wherein said undoped crystalline region separates said first and second superconducting regions by less than 5 nm.

10. doping the first region and the second region of the crystalline substrate with a dopant; implanting a dopant into the first region and the second region of the crystalline substrate; 3. A method of fabricating a quantum device as defined in claim 2, comprising annealing the first and second regions to form the first and second superconducting regions and to direct dopants laterally into the crystalline regions to form the conductive crystalline regions.

11. 11. A method of fabricating a quantum device as claimed in any one of claims 1 to 10, further comprising forming a first superconducting wire in contact with the first superconducting region and a second superconducting wire in contact with the second superconducting region.

12. Forming the first superconducting wire and the second superconducting wire includes: forming a lift-off resist over a portion of the first superconducting region, a portion of the second superconducting region and the crystalline region; depositing a superconducting material; lifting off the lift-off resist and the superconducting material deposited on the lift-off resist; 12. A method for fabricating the quantum device of claim 11, comprising:

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