Display device

Abstract

To provide a display device including transistors in a pixel region and a driving circuit region, in which the variation in electric characteristics is suppressed and the reliability is improved.SOLUTION: A display device includes a first substrate 102 including a driving circuit region 140, which is externally adjacent to a pixel region 142, including at least one second transistor 103 that supplies a signal to a first transistor 101 included in each pixel of the pixel region, a second substrate 152 provided so as to face the first substrate, a liquid crystal layer 162 held between the first and second substrates, a first interlayer insulating film 114 formed of an inorganic insulating material on the first transistor and the second transistor, a second interlayer insulating film 116 formed of an organic insulating material on the first interlayer insulating film, and a third interlayer insulating film 120 formed of an inorganic insulating material on the second interlayer insulating film. The third interlayer insulating film is provided on a part of the pixel region, and an end part of the third interlayer insulating film is formed on the inside relative to the driving circuit region.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a display device using a liquid crystal panel or an organic EL panel. Further it relates to an electronic device having the display device.

Background Art

[0002] In recent years, the development of display devices using liquid crystal panels and display devices using organic EL panels has been active There are. This display device is roughly classified into one in which only a transistor (pixel transistor) for pixel control is formed on a substrate and a scanning circuit (driving circuit) is performed by a peripheral IC, and one in which both a pixel transistor and a scanning circuit are formed on the same substrate.

[0003] For the purpose of reducing the bezel width of the display device or reducing the cost of the peripheral IC, the driving circuit integrated type display device is more advantageous. However, as a transistor used for the driving circuit, electrical characteristics (for example, field effect mobility (μFE) or threshold value, etc.) higher than those used for the pixel transistor are required.

[0004] As a semiconductor thin film applicable to a transistor, a silicon-based semiconductor material is widely known However, an oxide semiconductor is attracting attention as another material. For example, as a semiconductor thin film used for a transistor, the electron carrier concentration is 10 / cm 18 3 A transistor using an amorphous oxide containing indium (In), gallium (Ga), and zinc (Zn) less than has been disclosed (see, for example, Patent Document 1).

[0005] A transistor using an oxide semiconductor for the semiconductor layer is an amorphous Since the field-effect mobility is higher than that of a transistor using silicon for the semiconductor layer, the operating speed is high, making it suitable for a display device with an integrated driving circuit, and the manufacturing process is easier than that of a transistor using polycrystalline silicon for the semiconductor layer.

[0006] However, in a transistor using an oxide semiconductor for the semiconductor layer, when impurities such as hydrogen and moisture enter the oxide semiconductor, carriers are formed, and the electrical characteristics of the transistor change

[0007] To solve the above-mentioned problems, a transistor with improved reliability is disclosed by setting the concentration of hydrogen atoms in the oxide semiconductor film used as the channel formation region of the transistor to less than 1 × 10 16 cm -3 (For example, Patent Document 2).

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0009] As described in Patent Document 2, in a transistor using an oxide semiconductor film for the semiconductor layer, in order to sufficiently maintain its electrical characteristics, it is important to extremely exclude hydrogen, moisture, etc. from the oxide semiconductor film.

[0010] Also, when transistors are used in both the pixel region and the driving circuit region of a display device, the driving​​​​​​ Depending on the method, the transistors used in the drive circuit region have a greater electrical load than those in the pixel region, so the electrical characteristics of the transistors used in the drive circuit region are important.

[0011] In particular, in a display device using transistors with an oxide semiconductor film as the semiconductor layer in both the pixel region and the drive circuit region, during a reliability test in a high-temperature and high-humidity environment, deterioration of the transistors used in the drive circuit region has become a problem. The cause of the deterioration of these transistors is that moisture and the like enter from the organic insulating film formed on the transistors into the oxide semiconductor film used as the semiconductor layer, increasing the carrier density of the oxide semiconductor film.

[0012] Therefore, one aspect of the present invention is to suppress fluctuations in electrical characteristics and improve reliability in a display device having transistors in a pixel region and a drive circuit region. In particular, in a display device using an oxide semiconductor film in the channel formation region of a transistor, it is an object to suppress the ingress of hydrogen and moisture into the oxide semiconductor film, suppress fluctuations in electrical characteristics, and improve reliability at the same time.

Means for Solving the Problems

[0013] In view of the above problems, in one aspect of the present invention, in a display device having transistors used in a pixel region and a drive circuit region, a structure capable of suppressing fluctuations in the electrical characteristics of the transistors is provided. More specifically, an oxide semiconductor film is used in the channel formation region of the transistor, and the structure of the planarization film formed of an organic insulating material provided on the transistor is made to have a characteristic, so that hydrogen and moisture do not enter the oxide semiconductor film, particularly the oxide semiconductor film used in the drive circuit region. ​​​​​​The structure will be designed to make it difficult for worms to get into the building. More specifically, the structure is as follows:

[0014] One aspect of the present invention is a pixel electrode and at least one first transistor electrically connected to the pixel electrode. A pixel region in which multiple pixels including transistor 1 are arranged and an adjacent pixel region on the outside of the pixel region. At least one transistor that supplies a signal to a first transistor included in each pixel of the pixel region a first substrate on which a driving circuit region including the second transistor is formed; A second substrate disposed so as to face the first substrate, and a liquid crystal layer sandwiched between the first substrate and the second substrate. and a second transistor formed of an inorganic insulating material on the first transistor and the second transistor. a first interlayer insulating film; and a second interlayer insulating film formed on the first interlayer insulating film and made of an organic insulating material. and a third interlayer insulating film formed of an inorganic insulating material on the second interlayer insulating film, The third interlayer insulating film is provided on a part of the pixel region, and an end of the third interlayer insulating film is disposed on the driving circuit region. The display device is characterized in that the display device is formed inside the above-mentioned area.

[0015] In the above-mentioned configuration, a first alignment film is provided on the pixel electrode, and a liquid crystal display is formed on the first alignment film. a liquid crystal layer provided on the liquid crystal layer, a second alignment film provided on the liquid crystal layer, and a counter electrode provided on the second alignment film. An organic protective insulating film provided on the counter electrode; and a colored insulating film provided on the organic protective insulating film. The colored film may have a light-shielding film and a light-shielding film, and a second substrate provided on the colored film and the light-shielding film.

[0016] Another aspect of the present invention is a pixel electrode and at least one a pixel region in which a plurality of pixels each including a first transistor are arranged; A small number of transistors are provided adjacent to the outside of the pixel region and supply signals to the first transistors included in each pixel of the pixel region. A first substrate on which a drive circuit region including at least one second transistor is formed, and a second substrate provided so as to face the first substrate, and a light-emitting layer sandwiched between the first substrate and the second substrate, and has a first interlayer insulating film formed of an inorganic insulating material on the first transistor and the second transistor, a second interlayer insulating film formed of an organic insulating material on the first interlayer insulating film, and a third interlayer insulating film formed of an inorganic insulating material on the second interlayer insulating film, wherein the third interlayer insulating film is provided on a part of the pixel region, and an end portion of the third interlayer insulating film is formed inside the drive circuit region. A display device characterized by being formed. In the above configuration, it may have a light-emitting layer provided on the pixel electrode and an electrode provided on the light-emitting layer.

[0017] In the above configuration, it may have a light-emitting layer provided on the pixel electrode and an electrode provided on the light-emitting layer. It may have.

[0018] Also, in each of the above configurations, the third interlayer insulating film is preferably any one selected from a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film.

[0019] Also, in each of the above configurations, the first transistor and the second transistor preferably have a semiconductor material for forming a channel formation region that is an oxide semiconductor. Also, the first transistor and the second transistor preferably have a gate electrode, a semiconductor layer made of an oxide semiconductor formed on the gate electrode, and a source electrode and a drain electrode formed on the semiconductor layer. It is preferably a configuration having. Configuration.

[0020] Also, one aspect of the present invention includes an electronic device having the display device of each of the above configurations. It is.

Effects of the Invention

[0021] In a display device having transistors in a pixel region and a drive circuit region, fluctuations in electrical characteristics can be suppressed and reliability can be improved. In particular, in a display device using an oxide semiconductor film in a channel formation region of a transistor, entry of hydrogen and moisture into the oxide semiconductor film can be suppressed, fluctuations in electrical characteristics can be suppressed, and reliability can be improved.

Brief Description of the Drawings

[0022]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Modes for Carrying Out the Invention

[0023] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can make various changes to its form and details. ​This will be easily understood. Further, the present invention is not construed as being limited to the description of the embodiments shown below. It is not so construed.

[0024] In the embodiments described below, the same reference numerals are commonly used between different drawings to indicate the same components. Note that the components shown in the drawings, that is, the thickness widths of layers, regions, etc., and the relative positional relationships, etc., are exaggerated for clarity in the description of the embodiments. In the drawings, the components shown, that is, the thickness widths of layers, regions, etc., and the relative positional relationships, etc., are exaggerated for clarity in the description of the embodiments. relationships, etc., are exaggerated for clarity in the description of the embodiments.

[0025] Also, in this specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Further, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed. For example, an "electrode" may be used as part of a "wiring", and vice versa. Further, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed. For example, an "electrode" may be used as part of a "wiring", and vice versa. Further, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0026] Also, in this specification and the like, a silicon oxynitride film is a film containing nitrogen, oxygen, silicon, and having a nitrogen content higher than the oxygen content. A silicon nitride oxide film is a film containing oxygen, nitrogen, silicon, and having an oxygen content higher than the nitrogen content. Also, in this specification and the like, a silicon oxynitride film is a film containing nitrogen, oxygen, silicon, and having a nitrogen content higher than the oxygen content. A silicon nitride oxide film is a film containing oxygen, nitrogen, silicon, and having an oxygen content higher than the nitrogen content. A silicon nitride oxide film is a film containing oxygen, nitrogen, silicon, and having an oxygen content higher than the nitrogen content.

[0027] Also, the functions of "source" and "drain" may be interchanged when different polarities of transistors are employed or when the direction of current changes in circuit operation. Therefore, in this specification and the like, the terms "source" and "drain" are assumed to be interchangeable. Also, the functions of "source" and "drain" may be interchanged when different polarities of transistors are employed or when the direction of current changes in circuit operation. Therefore, in this specification and the like, the terms "source" and "drain" are assumed to be interchangeable. Therefore, in this specification and the like, the terms "source" and "drain" are assumed to be interchangeable.

[0028] (Embodiment 1) In this embodiment, as one form of a display device, a display device using a liquid crystal panel will be described with reference to the drawings. This will be described with reference to FIGS. 1 and 2.

[0029] FIGS. 1(A), (B), and (C) show a top view of a display device as one form of the display device. FIG. 1(A) shows the entire display device, FIG. 1(B) shows a part of the drive circuit portion of the display device, and FIG. 1(C) shows a top view of a part of the pixel region, respectively. FIG. 2 corresponds to the cross-sectional view of X1 - Y1 in FIG. 1(A).

[0030] In the display device shown in FIG. 1(A), a pixel region 142 provided on a first substrate 102 and a gate driver circuit portion 140 and a source driver circuit portion 144 that are adjacent to the outside of the pixel region 142 and supply signals to the pixel region 142 are surrounded by a sealing material 166 and sealed by a second substrate 152. Also, the second substrate 152 is provided so as to face the first substrate 102 on which the pixel region 142, the gate driver circuit portion 140, and the source driver circuit portion 144 are provided. Therefore, the pixel region 14 2, the gate driver circuit portion 140, and the source driver circuit portion 144 are sealed together with the display elements by the first substrate 1 02, the sealing material 166, and the second substrate 152.

[0031] Also, in FIG. 1(A), in a region different from the region surrounded by the sealing material 166 on the first substrate 102, an FPC terminal portion 146 (FPC: Flexible printed circuit) that is electrically connected to the pixel region 142, the gate driver circuit portion 140, and the source driver circuit portion 144 is provided. An FPC 148 is connected to the FPC terminal portion 146, and the pixel region 142, the gate driver circuit portion 140, and the source driver circuit portion 144 are electrically connected to the FPC 148. The various signals and potentials supplied to the driver circuit section 144 are supplied by the FPC 148. There.

[0032] Also, in FIG. 1(A), an example is shown in which the gate driver circuit section 140 and the source driver circuit section 144 are formed on the same first substrate 102 as the pixel region 142, but the present invention is not limited to this configuration. For example, only the gate driver circuit section 140 may be formed on the first substrate 102, and a separately prepared substrate on which a source driver circuit is formed (for example, a driving circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the first substrate 102. formed, and a separately prepared substrate on which a source driver circuit is formed (for example, a driving circuit substrate formed of a single crystal semiconductor film, a polycrystalline semiconductor film) may be mounted on the first substrate 102. is also acceptable.

[0033] Also, in FIG. 1(A), an example is shown in which two gate driver circuit sections 140 are arranged on both sides of the pixel region 142, but the present invention is not limited to this configuration. For example, the gate driver circuit section 140 may be arranged on only one side of the pixel region 142. 142.

[0034] Note that the connection method of the separately formed driving circuit substrate is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or a TAB (Tap e Automated Bonding) method or the like can be used. Also, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller and the like is mounted on the panel.

[0035] In this way, part or all of the driving circuit including transistors can be integrally formed on the same first substrate 102 as the pixel region 142 to form a system-on-panel.

[0036] In addition, in FIG. 1(C), a first transistor 101 and a capacitor element 107 are formed in the pixel region 142. The first transistor 101 has a gate electrode 104, a source electrode 110, and a drain electrode 112 electrically connected to the semiconductor layer 108, respectively. Also, in the plan view shown in FIG. 1(C), although not shown, a first interlayer insulating film formed of an inorganic insulating material, a second interlayer insulating film formed of an organic insulating material on the first interlayer insulating film, and a third interlayer insulating film formed of an inorganic insulating material on the second interlayer insulating film are formed on the first transistor 101. The capacitor element 107 is composed of a capacitor electrode 118, a third interlayer insulating film formed on the capacitor electrode 118, and a pixel electrode 122 formed on the third interlayer insulating film. In FIG. 1(B), a second transistor 103 and a third transistor 105 are formed in the gate driver circuit section 140 which is a drive circuit region. Each transistor in the gate driver circuit section 140 has a gate electrode 104, a source electrode 110, and a drain electrode 112 electrically connected to the semiconductor layer 108, respectively. In the gate driver circuit section 140, a gate line including the gate electrode 104 extends in the left - right direction, a source line including the source electrode 110 extends in the up - down direction, and a drain line including the drain electrode 112 extends in the up - down direction spaced apart from the source electrode. The gate driver circuit section 140 including the second transistor 103 and the third transistor 105 can supply a signal to the first transistor 101 included in each pixel of the pixel region 142.

[0037]

[0038]

[0039] In addition, the second transistor 103 and the third transistor 105 in the gate driver circuit section 140 require a relatively high voltage for controlling various signals and performing functions such as boosting. Specifically, a voltage of about 10V to 30V is required. On the other hand, the first transistor 101 in the pixel region 142 is only used for pixel switching, so it can be driven with a voltage of several volts to about 20V. Therefore, the second transistor 103 and the third transistor 105 in the gate driver circuit section 140 are configured to have a much greater stress applied compared to the first transistor 101 in the pixel region 142. To more specifically describe the configuration of the display device shown in FIGS. 1(A), (B), and (C), FIG. 2, which corresponds to the cross-sectional view of X1 - Y1 in FIGS. 1(A), (B), and (C), will be used to explain the configurations of the gate driver circuit section 140 and the pixel region 142 as follows.

[0040] In the pixel region 142, the first transistor 101 is formed by the first substrate 102, the gate electrode 104 formed on the first substrate 102, the gate insulating film 106 formed on the gate electrode 104, the semiconductor layer 108 provided in contact with the gate insulating film 106 and overlapping the gate electrode 104, and the source electrode 110 and the drain electrode 112 formed on the gate insulating film 106 and the semiconductor layer 108.

[0041] Also, in the pixel region 142, an inorganic insulating film is formed on the first transistor 101, more specifically, on the gate insulating film 106, the semiconductor layer 108, the source electrode 110, and the drain electrode 112.

[0042] A first interlayer insulating film 114 formed of an organic insulating material is provided on the first interlayer insulating film 114. A second interlayer insulating film 116 formed by the above method and a capacitive capacitor formed on the second interlayer insulating film 116 are The electrode 118, the second interlayer insulating film 116 and the capacitance electrode 118 are formed of an inorganic insulating material. a third interlayer insulating film 120, a pixel electrode 122 formed on the third interlayer insulating film 120; It has.

[0043] The capacitance electrode 118, the third interlayer insulating film 120, and the pixel electrode 122 form a capacitance. The element 107 is formed. A capacitance electrode 118, a third interlayer insulating film 120, and a pixel electrode 122 are formed from a material that is transparent to visible light, This is preferable because it is possible to ensure a large capacity without impairing the aperture ratio of the region.

[0044] In addition, a first alignment film 124 is provided on the pixel electrode 122, and a liquid crystal display (LCD) is provided on the first alignment film 124. A liquid crystal layer 162 is formed on the liquid crystal layer 162, a second alignment film 164 is formed on the liquid crystal layer 162, and the second alignment film A counter electrode 158 provided on the substrate 164 and an organic protective insulating film provided on the counter electrode 158 156, a colored film 153 and a light-shielding film 154 provided on the organic protective insulating film 156, and a colored and a second substrate 152 provided on the film 153 and the light-shielding film 154.

[0045] The pixel electrode 122, the first alignment film 124, the liquid crystal layer 162, and the second alignment film 16 4 and a counter electrode 158 form a liquid crystal element 150 which is a display element.

[0046] In the gate driver circuit section 140, a first substrate 102 and a a gate electrode 104 formed on the gate electrode 104; and a gate insulating film 106 formed on the gate electrode 104. A semiconductor layer 108 that is in contact with the gate insulating film 106 and is provided at a position overlapping with the gate electrode 104 8, and a source electrode 110 and a drain electrode 112 formed on the gate insulating film 106 and the semiconductor layer 108, form the second transistor 103 and the third transistor 10 5. is formed.

[0047] Also, in the gate driver circuit section 140, on the second transistor 103 and the third transistor 10 5, more specifically, a first interlayer insulating film 114 formed on the gate insulating film 106, the semiconductor layer 108, the source electrode 110, and the drain electrode 112, and a second interlayer insulating film 116 formed on the first interlayer insulating film 114 are formed. That is, the third interlayer insulating film 120 is provided on a part of the pixel region 142, and the end of the third interlayer insulating film 120 is formed inside the gate driver circuit section 140 which is the driving circuit region. is formed.

[0048] That is, the third interlayer insulating film 120 is provided on a part of the pixel region 142, and the end of the third interlayer insulating film 120 is formed inside the gate driver circuit section 140 which is the driving circuit region. is formed. By adopting such a configuration, moisture taken in from the outside or moisture, gases such as hydrogen generated inside the display device can be released upward from the second interlayer insulating film 116 of the gate driver circuit section 140. Therefore, it is possible to suppress gases such as moisture and hydrogen from being taken into the first transistor 101, the second transistor 103, and the third transistor 105.

[0049] By adopting such a configuration, moisture taken in from the outside or moisture, gases such as hydrogen generated inside the display device can be released upward from the second interlayer insulating film 116 of the gate driver circuit section 140. Therefore, it is possible to suppress gases such as moisture and hydrogen from being taken into the first transistor 101, the second transistor 103, and the third transistor 105. is formed. From the second interlayer insulating film 116 of the gate driver circuit section 140. is formed. is formed.

[0050] Note that the second interlayer insulating film 116 formed of an organic insulating material requires an organic insulating material with high flatness in order to reduce the unevenness of the transistors constituting the display device. is formed. This is because the image quality of the display device can be improved by reducing the unevenness of the transistor and the like. However, the organic insulating material releases hydrogen, moisture, or organic components as gas by heating or the like.

[0051] However, in a transistor using, for example, a silicon film which is a silicon-based semiconductor material for the semiconductor layer 108, the above-mentioned gas of hydrogen, moisture, or organic components is less likely to become a major problem. However, in one aspect of the present invention, since an oxide semiconductor film is used for the semiconductor layer 108, it is necessary to preferably release the gas from the second interlayer insulating film 116 formed of the organic insulating material to the outside. Note that the configuration in which the end portion of the third interlayer insulating film 120 is formed inside the gate driver circuit portion 140 which is a driving circuit region exhibits excellent effects when the semiconductor layer 108 is formed of an oxide semiconductor film. However, the same effects can also be obtained in a transistor formed of a material other than an oxide semiconductor (for example, amorphous silicon which is a silicon-based semiconductor material, crystalline silicon, etc.) for the semiconductor layer 108. In addition, the third interlayer insulating film 120 formed of an inorganic insulating material formed on the second interlayer insulating film 116 formed of an organic insulating material is used as a dielectric of the capacitor element 107 in the present embodiment. Further, the third interlayer insulating film 120 formed of an inorganic insulating material can suppress hydrogen, moisture, etc. entering from the outside into the second interlayer insulating film 116.

[0052]

[0053] However, the third interlayer insulating film 120 is formed on the second interlayer insulating film 116 on the second transistor 103 and the third transistor 105 used for the gate driver circuit portion 140. Then, the gas released from the organic insulating material used for the second interlayer insulating film 116 cannot diffuse to the outside and enters the second transistor 103 and the third transistor 105.

[0054] When the gas released from the above-described organic insulating material enters the oxide semiconductor used for the semiconductor layer 108 of the transistor, it is taken in as an impurity in the oxide semiconductor film, and the characteristics of the transistor using the semiconductor layer 108 fluctuate.

[0055] However, as shown in FIG. 2, the second transistor 103 used for the gate driver circuit portion 140 and the third interlayer insulating film 120 on the third transistor 105 are opened, that is, the third interlayer insulating film 120 is provided in a part of the pixel region 142, and the end portion of the third interlayer insulating film 120 is formed inside the gate driver circuit portion 140, so that the gas released from the second interlayer insulating film 116 can be diffused to the outside.

[0056] In addition, as shown in FIG. 2, in the first transistor 101 used for the pixel region 142, it is preferable that the third interlayer insulating film 120 formed of the inorganic insulating material at the overlapping position of the semiconductor layer 108 is removed. By adopting such a configuration, it is possible to suppress the gas released from the second interlayer insulating film 116 formed of the organic insulating material from entering the first transistor 101.

[0057] Here, other components of the display device shown in FIGS. 1 and 2 will be described in detail below.

[0058] As the first substrate 102 and the second substrate 152, glass materials such as aluminosilicate glass, aluminum borosilicate glass, and barium borosilicate glass are used. In mass production, the first substrate 102 and the second substrate 152 are preferably made of mother glass of the 8th generation (2160 mm × 2460 m m), the 9th generation (2400 mm × 2800 mm, or 2450 mm × 3050 mm), the 10th generation (2950 mm × 3400 mm), etc. Since the mother glass shrinks significantly when the processing temperature is high and the processing time is long, when mass-producing using the mother glass, the heat treatment in the manufacturing process is preferably 600°C or lower, more preferably 450°C or lower, and even more preferably 350°C or lower.

[0059] An underlying insulating film may be provided between the first substrate 102 and the gate electrode 104. As the underlying insulating film, there are a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, a gallium oxide film, a hafnium oxide film, a yttrium oxide film, an aluminum oxide film, an aluminum oxynitride film, etc. In addition, as the underlying insulating film, a silicon nitride film, a gallium oxide film, a hafnium oxide film, a yttrium oxide film, an aluminum oxide film, etc. are used, and impurities, typically alkali metals, water, hydrogen, etc. can be prevented from entering the semiconductor layer 10 8 from the first substrate 102.

[0060] The gate electrode 104 can be formed using a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or an alloy containing the above-described metal elements as components, an alloy combining the above-described metal elements, etc. Also, manganese , a metal element selected from any one or more of zirconium may be used. Also, The gate electrode 104 may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on the aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a titanium nitride film a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a three-layer structure in which a titanium film, an aluminum film is laminated on the titanium film, and a titanium film is further formed thereon, etc. Also, on aluminum, a film of an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium, or a combined alloy film or a nitride film may be used. a combined alloy film or a nitride film may be used. a combined alloy film or a nitride film may be used.

[0061] Also, the gate electrode 104 can be applied with a conductive material having translucency such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. Also, a laminated structure of the above-mentioned conductive material having translucency and the above-mentioned metal element can also be used. a laminated structure of the above-mentioned conductive material having translucency and the above-mentioned metal element can also be used. a laminated structure of the above-mentioned conductive material having translucency and the above-mentioned metal element can also be used. a laminated structure of the above-mentioned conductive material having translucency and the above-mentioned metal element can also be used.

[0062] Also, an In-Ga-Zn-based oxynitride semiconductor film, an In-Sn-based oxynitride semiconductor film, an In-Ga-based oxynitride semiconductor film, an In-Zn-based oxynitride semiconductor film, an Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, a metal nitride film ( InN, ZnN, etc.) etc. may be provided between the gate electrode 104 and the gate insulating film 106. These films are 5 eV or more, preferably 5.5 eV InN, ZnN, etc.) etc. may be provided between the gate electrode 104 and the gate insulating film 106. These films are 5 eV or more, preferably 5.5 eV InN, ZnN, etc.) etc. may be provided between the gate electrode 104 and the gate insulating film 106. These films are 5 eV or more, preferably 5.5 eV Since the work function is larger than the electron affinity of the oxide semiconductor, The threshold voltage of the transistor using the conductor can be shifted to the positive side, so that the so-called normal For example, an In-Ga-Zn oxynitride semiconductor When a conductive film is used, the nitrogen concentration is at least higher than that of the semiconductor layer 108, specifically, 7 atomic %. The above-mentioned In-Ga-Zn-based oxynitride semiconductor film is used.

[0063] The gate insulating film 106 may be, for example, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. Silicon film, silicon nitride film, aluminum oxide film, hafnium oxide film, gallium oxide film Alternatively, a Ga-Zn-based metal oxide film or the like may be used, and may be provided as a laminated layer or a single layer. In order to improve the interface characteristics with the semiconductor layer 108, at least the gate insulating film 106 is In addition, a region in contact with the semiconductor layer 108 is preferably formed using an oxide insulating film.

[0064] In addition, the gate insulating film 106 is provided with an insulating film having a blocking effect against oxygen, hydrogen, water, etc. By providing the insulating layer 104, the diffusion of oxygen from the semiconductor layer 108 to the outside and the diffusion of oxygen from the outside to the semiconductor layer 108 can be prevented. It can prevent hydrogen, water, etc. from entering. It has a blocking effect on oxygen, hydrogen, water, etc. Examples of insulating films that can be used include aluminum oxide, aluminum oxynitride, gallium oxide, and nitridium oxide. Gallium oxide, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride Nium, etc.

[0065] In addition, the gate insulating film 106 has a laminated structure, and is formed as a first silicon nitride film, so that the gate insulating film 106 has few defects. A silicon nitride film having a thickness of 100 nm was formed on the first silicon nitride film. A second silicon nitride film having a thickness of 100 nm was formed on the first silicon nitride film. A silicon nitride film with a small amount of hydrogen and ammonia release is provided, and on the second silicon nitride film By providing an insulating oxide film, as the gate insulating film 106, a gate insulating film 106 with few defects and a small amount of hydrogen and ammonia release can be formed. As a result, it is possible to suppress the movement of hydrogen and nitrogen contained in the gate insulating film 106 into the semiconductor layer 108.

[0066] In addition, by using a silicon nitride film for the gate insulating film 106, the following effects can be obtained. The silicon nitride film has a higher relative dielectric constant than the silicon oxide film, and since the film thickness required to obtain the same capacitance is large, the gate insulating film can be physically thickened. Therefore, a decrease in the breakdown voltage of the first transistor 101, the second transistor 103, and the third transistor 105 can be suppressed, and further, the breakdown voltage can be improved, suppressing the electrostatic breakdown of the transistors used in the display device.

[0067] When copper is used for the gate electrode 104 and a silicon nitride film is used for the gate insulating film 10 6 in contact with the gate electrode 104, in order to suppress the reaction between copper and ammonia molecules, it is preferable that the silicon nitride film reduces the ammonia molecule release amount due to heating as much as possible.

[0068] In a transistor using an oxide semiconductor film for the semiconductor layer 108, if there are trap levels (also referred to as interface levels) at the interface between the oxide semiconductor film and the gate insulating film or in the gate insulating film, fluctuations in the threshold voltage of the transistor, typically a negative shift in the threshold voltage, and the gate voltage required for the drain current to change by one digit when the transistor is in the on state ​​​​This causes an increase in the sub-threshold coefficient (S value) shown. As a result, there is a problem that the electrical characteristics vary for each transistor. Therefore, by using a silicon nitride film with few defects as the gate insulating film, a negative shift in the threshold voltage and variations in the electrical characteristics of the transistor can be reduced.

[0069] Also, as the gate insulating film 106, hafnium silicate (HfSiO x ), hafnium silicate with nitrogen added (HfSi O x y N z ), hafnium aluminate with nitrogen added (HfAl O x y N z ), high-k materials such as hafnium oxide and yttrium oxide can be used to reduce the gate leakage of the transistor.

[0070] The thickness of the gate insulating film 106 is preferably 5 nm or more and 400 nm or less, more preferably 10 nm or more and 300 nm or less, and even more preferably 50 nm or more and 250 nm or less.

[0071] The semiconductor layer 108 preferably uses an oxide semiconductor and contains at least indium (In) or zinc (Zn). Or it preferably contains both In and Zn. Also, in order to reduce variations in the electrical characteristics of the transistor using the oxide semiconductor, it preferably has one or more stabilizers in combination with them.

[0072] Examples of the stabilizer include gallium (Ga), tin (Sn), hafnium (Hf), al uminum (Al), or zirconium (Zr), etc. Also, other stabilizers ​​​​​​​Examples include lanthanoids such as lanthanum (La), cerium (Ce), praseodymium ( Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), and the like.

[0073] For example, as oxide semiconductors, indium oxide, tin oxide, zinc oxide, In-Zn-based metal oxides, Sn-Zn-based metal oxides, Al-Zn-based metal oxides, Zn-Mg-based metal oxides , Sn-Mg-based metal oxides, In-Mg-based metal oxides, In-Ga-based metal oxides, In- W-based metal oxides, In-Ga-Zn-based metal oxides (also denoted as IGZO), In-Al -Zn-based metal oxides, In-Sn-Zn-based metal oxides, Sn-Ga-Zn-based metal oxides, Al-Ga-Zn-based metal oxides, Sn-Al-Zn-based metal oxides, In-Hf-Zn-based metal oxides, In-La-Zn-based metal oxides, In-Ce-Zn-based metal oxides, In-Pr -Zn-based metal oxides, In-Nd-Zn-based metal oxides, In-Sm-Zn-based metal oxides, In-Eu-Zn-based metal oxides, In-Gd-Zn-based metal oxides, In-Tb-Zn-based metal oxides, In-Dy-Zn-based metal oxides, In-Ho-Zn-based metal oxides, In-Er -Zn-based metal oxides, In-Tm-Zn-based metal oxides, In-Yb-Zn-based metal oxides, In-Lu-Zn-based metal oxides, In-Sn-Ga-Zn-based metal oxides, In-Hf-G a-Zn-based metal oxides, In-Al-Ga-Zn-based metal oxides, In-Sn-Al-Zn -based metal oxides, In-Sn-Hf-Zn-based metal oxides, In-Hf-Al-Zn-based metal oxides ​Compounds can be used.

[0074] Here, for example, the In-Ga-Zn-based metal oxide means an oxide containing In, Ga, and Zn as main components, and the ratio of In, Ga, and Zn is not limited. Also, other metal elements may be contained in addition to In, Ga, and Zn.

[0075] Also, as the oxide semiconductor, a material represented by InMO3(ZnO) m (m > 0, and m is not an integer) may be used. Here, M represents one or more metal elements selected from Ga, Fe, Mn, and Co. Also, as the oxide semiconductor, a material represented by In2SnO 5(ZnO) n (n > 0, and n is an integer) may be used.

[0076] For example, In-Ga-Zn-based metal oxides with an atomic ratio of In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3), In:Ga: Zn = 2:2:1 (= 2 / 5:2 / 5:1 / 5), or In:Ga:Zn = 3:1: 2 (= 1 / 2:1 / 6:1 / 3) and oxides in the vicinity of their compositions can be used. Alternatively, In:Sn:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3), In:Sn:Zn = 2:1:3 (= 1 / 3:1 / 6:1 / 2) or In:Sn:Zn = 2:1:5 (= 1 / 4:1 / 8:5 / 8) atomic ratio of In -Sn-Zn-based metal oxides may be used. The atomic ratio of the metal oxide includes fluctuations of plus or minus 20% of the above atomic ratio as an error.

[0077] However, it is not limited to these, and depending on the required semiconductor characteristics and electrical characteristics (field-effect mobility, etc.). An appropriate composition may be used according to the threshold voltage, variation, etc. Also, in order to obtain the required semiconductor characteristics, it is preferable to make the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, etc. appropriate.

[0078] For example, in an In-Sn-Zn-based metal oxide, relatively high mobility can be obtained easily. However, even in an In-Ga-Zn-based metal oxide, the field-effect mobility can be increased by reducing the defect density in the bulk.

[0079] In addition, as the oxide semiconductor film that can be used as the semiconductor layer 108, the energy gap is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. In this way, by using an oxide semiconductor film with a wide energy gap, the off-current of the transistor can be reduced.

[0080] Next, the structure of the oxide semiconductor film that can be used as the semiconductor layer 108 will be described. Here.

[0081] The oxide semiconductor film is roughly classified into a non-single crystal oxide semiconductor film and a single crystal oxide semiconductor film. The non-single crystal oxide semiconductor film refers to a CAAC-OS (C Axis Aligned Cry stalline Oxide Semiconductor) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, etc.

[0082] Here, the CAAC-OS film will be described.

[0083] The CAAC-OS film is one of the oxide semiconductor films having a plurality of crystal parts, and most of the The crystal part has a size that fits within a cube with a side length of less than 100 nm. Therefore, CAAC- The crystal parts included in the CAAC- OS film also include cases where the size fits within a cube with a side length of less than 10 nm, less than 5 nm, or less than 3 nm.

[0084] When the CAAC-OS film is observed with a transmission electron microscope (TEM: Transmission Elec tron Microscope), the boundaries between distinct crystal parts, that is, crystal grain boundaries (also referred to as grain boundaries) cannot be confirmed. Therefore, it can be said that in the C AAC-OS film, a decrease in electron mobility due to crystal grain boundaries is unlikely to occur.

[0085] When the CAAC-OS film is observed by TEM from a direction approximately parallel to the sample surface (cross-sectional TEM observation), it can be confirmed that in the crystal part, metal atoms are arranged in layers. Each layer of the metal atoms has a shape that reflects the concavities and convexities of the surface (also referred to as the formed surface) or the upper surface of the CAAC-OS film, and is arranged parallel to the formed surface or the upper surface of the CAAC-OS film. On the other hand, when the CAAC-OS film is observed by TEM from a direction approximately perpendicular to the sample surface (planar TEM observation), it can be confirmed that in the crystal part, metal atoms are arranged in a triangular or hexagonal shape. However, no regularity is seen in the arrangement of metal atoms between different crystal parts.

[0086] In this specification, "parallel" refers to a state where two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, cases of -5° or more and 5° or less are also included. Also, " perpendicular" refers to a state where two straight lines are arranged at an angle of 80° or more and 100° or less. In the crystal part, it can be confirmed that metal atoms are arranged in a triangular or hexagonal shape. However, no regularity is seen in the arrangement of metal atoms between different crystal parts.

[0087] In this specification, "parallel" means a state where two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, cases of -5° or more and 5° or less are also included. Also, " perpendicular" means a state where two straight lines are arranged at an angle of 80° or more and 100° or less. ​​Therefore, it also includes the case where the angle is 85° or more and 95° or less.

[0088] From cross-sectional TEM observation and planar TEM observation, it can be seen that the crystal part of the CAAC-OS film has orientation. and.

[0089] For the CAAC-OS film, when structural analysis is performed using an X-ray diffraction (XRD: X-Ray Diffraction) device, for example, in the analysis of the CAAC-OS film having InGaZnO4 crystals by the out-of-plane method, a peak may appear at around a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystal of the CAAC-OS film has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface.

[0090] On the other hand, for the CAAC-OS film, in the analysis by the in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak may appear at around 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. If it is a single-crystalline oxide semiconductor film of InGaZnO4, when analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed at around 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. In contrast, in the case of the CAAC-OS film, no distinct peak appears even when φ scan is performed with 2θ fixed at around 56°. From the above, in the CAAC-OS film, the orientations of the a-axis and b-axis are irregular between different crystal parts, but it has c-axis orientation, and the c-axis is parallel to the normal vector of the formed surface or the upper surface.

[0091] irregular, but has c-axis orientation, and the c-axis is parallel to the normal vector of the formed surface or the upper surface. It can be seen that it is facing the traveling direction. Therefore, each layer of the metal atoms arranged in a layered manner confirmed by the above-described cross-sectional TEM observation is a plane parallel to the ab plane of the crystal. Each layer of the metal atoms arranged in a layered manner confirmed by the above-described cross-sectional TEM observation is a plane parallel to the ab plane of the crystal.

[0092] Note that the crystal part is formed when the CAAC-OS film is formed or when a crystallization process such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the surface to be formed or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the surface to be formed or the upper surface of the CAAC-OS film. Note that the crystal part is formed when the CAAC-OS film is formed or when a crystallization process such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the surface to be formed or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the surface to be formed or the upper surface of the CAAC-OS film. Note that the crystal part is formed when the CAAC-OS film is formed or when a crystallization process such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the surface to be formed or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the surface to be formed or the upper surface of the CAAC-OS film. Note that the crystal part is formed when the CAAC-OS film is formed or when a crystallization process such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the surface to be formed or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the surface to be formed or the upper surface of the CAAC-OS film. Note that the crystal part is formed when the CAAC-OS film is formed or when a crystallization process such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the surface to be formed or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the surface to be formed or the upper surface of the CAAC-OS film.

[0093] Also, the crystallinity in the CAAC-OS film may not be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the upper surface of the CAAC-OS film, the crystallinity in the region near the upper surface may be higher than that in the region near the surface to be formed. Also, when impurities are added to the CAAC-OS film, the crystallinity in the region where the impurities are added changes, and regions with different crystallinities may be formed partially. Also, the crystallinity in the CAAC-OS film may not be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the upper surface of the CAAC-OS film, the crystallinity in the region near the upper surface may be higher than that in the region near the surface to be formed. Also, when impurities are added to the CAAC-OS film, the crystallinity in the region where the impurities are added changes, and regions with different crystallinities may be formed partially. Also, the crystallinity in the CAAC-OS film may not be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the upper surface of the CAAC-OS film, the crystallinity in the region near the upper surface may be higher than that in the region near the surface to be formed. Also, when impurities are added to the CAAC-OS film, the crystallinity in the region where the impurities are added changes, and regions with different crystallinities may be formed partially. Also, the crystallinity in the CAAC-OS film may not be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the upper surface of the CAAC-OS film, the crystallinity in the region near the upper surface may be higher than that in the region near the surface to be formed. Also, when impurities are added to the CAAC-OS film, the crystallinity in the region where the impurities are added changes, and regions with different crystallinities may be formed partially. Also, the crystallinity in the CAAC-OS film may not be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the upper surface of the CAAC-OS film, the crystallinity in the region near the upper surface may be higher than that in the region near the surface to be formed. Also, when impurities are added to the CAAC-OS film, the crystallinity in the region where the impurities are added changes, and regions with different crystallinities may be formed partially.

[0094] Note that in the out-of-plane method analysis of the CAAC-OS film having InGaZnO4 crystals, in addition to the peak at around 2θ = 31°, a peak may also appear at around 2θ = 36°. Since the peak at around 2θ = 36° is attributed to the (311) plane of the ZnGa2O4 crystal, it indicates that a part of the CAAC-OS film having InGaZnO4 crystals contains ZnGa2O4 crystals. The CAAC-OS film preferably shows a peak at around 2θ = 31° and does not show a peak at around 2θ = 36°. Note that in the out-of-plane method analysis of the CAAC-OS film having InGaZnO4 crystals, in addition to the peak at around 2θ = 31°, a peak may also appear at around 2θ = 36°. Since the peak at around 2θ = 36° is attributed to the (311) plane of the ZnGa2O4 crystal, it indicates that a part of the CAAC-OS film having InGaZnO4 crystals contains ZnGa2O4 crystals. The CAAC-OS film preferably shows a peak at around 2θ = 31° and does not show a peak at around 2θ = 36°. Note that in the out-of-plane method analysis of the CAAC-OS film having InGaZnO4 crystals, in addition to the peak at around 2θ = 31°, a peak may also appear at around 2θ = 36°. Since the peak at around 2θ = 36° is attributed to the (311) plane of the ZnGa2O4 crystal, it indicates that a part of the CAAC-OS film having InGaZnO4 crystals contains ZnGa2O4 crystals. The CAAC-OS film preferably shows a peak at around 2θ = 31° and does not show a peak at around 2θ = 36°. Note that in the out-of-plane method analysis of the CAAC-OS film having InGaZnO4 crystals, in addition to the peak at around 2θ = 31°, a peak may also appear at around 2θ = 36°. Since the peak at around 2θ = 36° is attributed to the (311) plane of the ZnGa2O4 crystal, it indicates that a part of the CAAC-OS film having InGaZnO4 crystals contains ZnGa2O4 crystals. The CAAC-OS film preferably shows a peak at around 2θ = 31° and does not show a peak at around 2θ = 36°. Note that in the out-of-plane method analysis of the CAAC-OS film having InGaZnO4 crystals, in addition to the peak at around 2θ = 31°, a peak may also appear at around 2θ = 36°. Since the peak at around 2θ = 36° is attributed to the (311) plane of the ZnGa2O4 crystal, it indicates that a part of the CAAC-OS film having InGaZnO4 crystals contains ZnGa2O4 crystals. The CAAC-OS film preferably shows a peak at around 2θ = 31° and does not show a peak at around 2θ = 36°. Note that in the out-of-plane method analysis of the CAAC-OS film having InGaZnO4 crystals, in addition to the peak at around 2θ = 31°, a peak may also appear at around 2θ = 36°. Since the peak at around 2θ = 36° is attributed to the (311) plane of the ZnGa2O4 crystal, it indicates that a part of the CAAC-OS film having InGaZnO4 crystals contains ZnGa2O4 crystals. The CAAC-OS film preferably shows a peak at around 2θ = 31° and does not show a peak at around 2θ = 36°.

[0095] The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. Impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon , silicon, and transition metal elements. In particular, elements with a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor film, such as silicon , will disrupt the atomic arrangement of the oxide semiconductor film by depriving it of oxygen, leading to a decrease in crystallinity . Also, heavy metals such as iron and nickel, argon, carbon dioxide, etc., have a large atomic radius (or molecular radius), so when contained inside the oxide semiconductor film, they will disrupt the atomic arrangement of the oxide semiconductor film and become a factor in reducing crystallinity. Note that impurities contained in the oxide semiconductor film may become carrier traps or carrier generation sources. . Also, the CAAC-OS film is an oxide semiconductor film with a low defect level density. For example, oxygen deficiencies in the oxide semiconductor film may become carrier traps or may become carrier generation sources by capturing hydrogen.

[0096] When the impurity concentration is low and the defect level density is low (with few oxygen deficiencies), it is called high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor using such an oxide semiconductor film is less likely to have an electrical characteristic (also called n-channel) where the threshold voltage becomes negative. Also, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor.

[0097] Note that it takes a certain time for charges trapped in the carrier traps in the oxide semiconductor film to be released. The time is long and the charge may behave as if it were a fixed charge. In addition, a transistor using an oxide semiconductor film having a high density of defect states has unstable electrical characteristics. There may be cases where this occurs.

[0098] In addition, the electrical characteristics of transistors using CAAC-OS films are improved by irradiation with visible light or ultraviolet light. Gender variation is small.

[0099] In addition, the CAAC-OS film can be used as a sputtering target for a polycrystalline oxide semiconductor. The sputtering method is used to form a film using the sputtering target. When ions collide, the crystalline regions in the sputtering target are cleaved from the ab plane. The particles are sputtered as flat or pellet-shaped particles with faces parallel to the ab plane. In this case, the plate-like sputtered particles may peel off while maintaining their crystalline state. By reaching the substrate in this state, a CAAC-OS film can be formed.

[0100] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0101] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the deposition chamber can be In addition, the impurity concentration in the deposition gas may be reduced. A deposition gas having a temperature of −80° C. or lower, preferably −100° C. or lower is used.

[0102] In addition, by increasing the substrate heating temperature during film formation, the microstructure of sputtered particles is improved after they reach the substrate. Gradation occurs. Specifically, film formation is performed with the substrate heating temperature being 100°C or higher and 740°C or lower, preferably 150°C or higher and 500°C or lower. By increasing the substrate heating temperature during film formation, when flat sputtering particles reach the substrate, migration occurs on the substrate and the flat surface of the sputtering particles adheres to the substrate.

[0103] Also, it is preferable to reduce the plasma damage during film formation by increasing the oxygen ratio in the film-forming gas and optimizing the power. The oxygen ratio in the film-forming gas is 30% by volume or higher, preferably 100 % by volume.

[0104] Also, the oxide semiconductor film used as the semiconductor layer 108 may have a structure in which a plurality of oxide semiconductor films are stacked. For example, the oxide semiconductor film may be a stack of a first oxide semiconductor film and a second oxide semiconductor film, and different composition metal oxides may be used for the first oxide semiconductor film and the second oxide semiconductor film. For example, a binary metal oxide to a quaternary metal oxide may be used for the first oxide semiconductor film, and a binary metal oxide to a quaternary metal oxide different from the first oxide semiconductor film may be used for the second oxide semiconductor film.

[0105] Also, the constituent elements of the first oxide semiconductor film and the second oxide semiconductor film may be the same, and their compositions may be different. For example, the atomic ratio of the first oxide semiconductor film may be In:Ga:Zn = 1:1:1, and the atomic ratio of the second oxide semiconductor film may be In:Ga:Zn = 3:1:2 Also, the atomic ratio of the first oxide semiconductor film may be In:Ga:Zn = 1:3:2, and the atomic ratio of the second oxide semiconductor film may be In:Ga:Zn = 2:1:3. Note that ​​​​​​​, the atomic ratio of each oxide semiconductor film includes fluctuations of plus or minus 20% of the above atomic ratio as an error. including fluctuations.

[0106] At this time, among the first oxide semiconductor film and the second oxide semiconductor film, it is preferable that the content ratio of In and Ga in the oxide semiconductor film on the side closer to the gate electrode ( channel side) is In > Ga. Also, the content ratio of In and Ga in the oxide semiconductor film on the side farther from the gate electrode (back channel side) is preferably In ≦Ga.

[0107] In addition, the oxide semiconductor film may have a three-layer structure, and the constituent elements of the first oxide semiconductor film to the third oxide semiconductor film may be the same, and their respective compositions may be different. For example, the atomic ratio of the first oxide semiconductor film is In:Ga:Zn = 1:3:2, the atomic ratio of the second oxide semiconductor film is In:Ga:Zn = 3:1:2, and the atomic ratio of the third oxide semiconductor film may be In:G a:Zn = 1:1:1.

[0108] An oxide semiconductor film in which the atomic ratio of In is smaller than that of Ga and Zn, typically the first oxide semiconductor film with an atomic ratio of In :Ga:Zn = 1:3:2, compared with an oxide semiconductor film in which the atomic ratio of In is larger than that of Ga and Zn, typically the second oxide semiconductor film, and an oxide semiconductor film in which the atomic ratios of Ga, Zn, and In are the same, typically the third oxide semiconductor film, is less likely to generate oxygen deficiency, so an increase in carrier density can be suppressed. Also when the first oxide semiconductor film with an atomic ratio of In:Ga:Zn = 1:3:2 has an amorphous structure the second oxide semiconductor film is likely to be a CAAC-OS film.

[0109] In addition, since the constituent elements of the first oxide semiconductor film to the third oxide semiconductor film are the same, the first​​​ The oxide semiconductor film of 1 has few trap levels at the interface with the second oxide semiconductor film. Therefore, by forming the oxide semiconductor film into the above structure, the variation amount of the threshold voltage due to the temporal change and photo-degradation of the transistor can be reduced.

[0110] In an oxide semiconductor, the s orbitals of heavy metals mainly contribute to carrier conduction. By increasing the In content rate, more s orbitals overlap. Therefore, an oxide with an In>Ga composition has a higher carrier mobility compared to an oxide with an In≦Ga composition. Also, since Ga has a larger oxygen deficiency formation energy compared to In and is less likely to form oxygen deficiencies, an oxide with an In≦Ga composition has more stable characteristics compared to an oxide with an In>Ga composition.

[0111] By applying an oxide semiconductor with an In>Ga composition to the channel side and an oxide semiconductor with an In≦Ga composition to the back channel side, the field-effect mobility and reliability of the transistor can be further improved.

[0112] Moreover, oxide semiconductors with different crystallinities may be applied to the first to third oxide semiconductor films. That is, a structure in which a single crystal oxide semiconductor, a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, an amorphous oxide semiconductor, or CAAC-OS is appropriately combined may also be used. Also, if an amorphous oxide semiconductor is applied to any one of the first to second oxide semiconductor films, the internal stress and external stress of the oxide semiconductor film are relaxed, the variation in the characteristics of the transistor is reduced, and the reliability of the transistor can be further improved.

[0113] The thickness of the oxide semiconductor film is 1 nm or more and 100 nm or less, more preferably 1 nm or more and 30 nm or less, more preferably 1 nm or more and 50 nm or less, and still more preferably 3 nm or more and 20 nm or less, which is preferable.

[0114] In the oxide semiconductor film used for the semiconductor layer 108, the concentration of alkali metal or alkaline earth metal obtained by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) is 1×10 18 atoms / cm 3 or less, more preferably 2×10 or less, which is desirable. Alkali metals 16 and alkaline earth metals may generate carriers when combined with the oxide semiconductor, 3 which is the cause of the increase in the off-current of the transistor.

[0115] Also, in the oxide semiconductor film used for the semiconductor layer 108, the hydrogen concentration obtained by secondary ion mass spectrometry is less than 5×10 18 atoms / cm 3 , preferably 1×10 18 a toms / cm 3 or less, more preferably 5×10 17 atoms / cm 3 or less, still more preferably 1×10 or less, which is preferable. 16 atoms / cm 3

[0116] The hydrogen contained in the oxide semiconductor film reacts with the oxygen bonded to the metal atoms to form water, and at the same time , defects are formed in the lattice from which oxygen has desorbed (or the part from which oxygen has desorbed). Also ​​​In addition, when some of the hydrogen bonds with oxygen, electrons that act as carriers are generated. Therefore, by drastically reducing impurities including hydrogen in the film formation process of the oxide semiconductor film, Therefore, the hydrogen concentration in the oxide semiconductor film can be reduced. By using the removed oxide semiconductor film as a channel region, the threshold voltage is reduced. It is possible to suppress the fluctuation of the electrical characteristics. The leakage current at the source and drain of the transistor is typically reduced by reducing the off-current. It is possible to reduce

[0117] In addition, the nitrogen concentration of the oxide semiconductor film used for the semiconductor layer 108 is set to 5×10 18 atoms / cm 3 By setting the threshold voltage of the transistor to the negative shift, This makes it possible to reduce the variation in electrical characteristics.

[0118] Note that the oxide semiconductor film is purified by removing hydrogen as much as possible, and is used as the channel region. The low off-state current of the transistors used in the For example, the channel width is 1×10 6 Even if the transistor has a channel length of 10 μm, When the voltage between the source and drain electrodes (drain voltage) is in the range of 1V to 10V, The current is below the measurement limit of the semiconductor parameter analyzer, i.e., 1×10 -13 Below A In this case, the off-state current is divided by the channel width of the transistor. The off-current corresponding to the value is 100zA / μm or less. The capacitor and the transistor are connected to each other to transfer the charge flowing into or out of the capacitor. Using a circuit controlled by a transistor, the off-current was measured. In this measurement, an oxide semiconductor film with high purity was used in the channel region of the transistor, and the off-current of the transistor was measured from the change in the charge amount per unit time of the capacitor element. As a result, when the voltage between the source electrode and the drain electrode of the transistor was 3 V, an extremely low off-current of several tens of yA / μm was obtained. Therefore, a transistor using an oxide semiconductor film with high purity in the channel region has an extremely small off-current. For the source electrode 110 and the drain electrode 112, as the conductive material, a single metal made of aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy having this as a main component is used in a single layer structure or a laminated structure. For example, a single layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a titanium film or a titanium nitride film, and an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is further formed thereon, a three-layer structure, a molybdenum film or a molybdenum nitride film, and an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is further formed thereon, and there are three-layer structures and the like. In addition, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0119]

[0120] In this embodiment, the source electrode 110 and the drain electrode 112 are formed on the semiconductor layer 108. However, it may be provided between the gate insulating film 106 and the semiconductor layer 108 .

[0121] The first interlayer insulating film 114 is a thin film having a thickness of 100 nm to 100 nm. In order to improve surface characteristics, it is preferable to use an oxide insulating film. 4 is a silicon oxide film or a silicon oxynitride film having a thickness of 150 nm or more and 400 nm or less. , aluminum oxide film, hafnium oxide film, gallium oxide film, or Ga-Zn-based metal oxide The first interlayer insulating film 114 may be an oxide insulating film. For example, the first interlayer insulating film 114 may have a stacked structure of an oxide insulating film and a nitride insulating film. The silicon nitride film may have a laminated structure of a silicon oxynitride film and a silicon nitride film.

[0122] The second interlayer insulating film 116 may be made of an acrylic resin, a polyimide resin, a benzocyclopentadiene resin, or the like. Heat-resistant organic insulating materials such as butene resins, polyamide resins, and epoxy resins are used. In addition, by stacking a plurality of insulating films made of these materials, A second interlayer insulating film 116 may be formed. By using the second interlayer insulating film 116, Therefore, it is possible to flatten the unevenness of the first transistor 101 and the like.

[0123] The capacitance electrode 118 may be formed of indium oxide containing tungsten oxide, tungsten oxide, or the like. Indium zinc oxide containing titanium oxide, Indium oxide containing titanium oxide Indium tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide The material used is a conductive material with transparency, such as indium tin oxide doped with silicon oxide or indium tin oxide doped with silicon oxide. can be achieved.

[0124] As the third interlayer insulating film 120, an inorganic insulating material such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, or an aluminum oxide film can be used. In particular, as the third interlayer insulating film 120, it is preferably any one selected from a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. By using any one selected from a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film as the third interlayer insulating film 120, the release of hydrogen and moisture from the second interlayer insulating film 116 can be suppressed.

[0125] As the pixel electrode 122, a material similar to the material shown for the capacitive electrode 118 can be used. As the materials used for the capacitive electrode 118 and the pixel electrode 122, the same material or different materials may be used, but the same material is preferable because the manufacturing cost can be reduced.

[0126] As the first alignment film 124 and the second alignment film 164, an organic material having heat resistance such as an acrylic resin, a polyimide resin, a benzocyclobutene resin, a polyamide resin, or an epoxy resin can be used.

[0127] As the liquid crystal layer 162, a liquid crystal material such as a thermotropic liquid crystal, a low molecular liquid crystal, a high molecular liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, or an antiferroelectric liquid crystal can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on conditions.

[0128] ​​​​​​​​​​​​In addition, when adopting the horizontal electric field method, a liquid crystal showing a blue phase without using an alignment film (the first alignment film 124 and the second alignment film 16 4) may be used. The blue phase is one of the liquid crystal phases, and when a cholesteric liquid crystal is heated up, it appears immediately before the transition from the cholesteric phase to the isotropic phase . Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with a chiral agent of several weight% or more is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed and optical isotropy, so alignment treatment is not required and the viewing angle dependence is small. Also, since an alignment film does not need to be provided, rubbing treatment is not required either, so electrostatic breakdown caused by rubbing treatment can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. Therefore, it is possible to improve the productivity of the liquid crystal display device. A transistor using an oxide semiconductor film may have its electrical characteristics significantly fluctuated by the influence of static electricity and deviate from the design range . Therefore, it is more effective to use a liquid crystal material with a blue phase in a liquid crystal display device having a transistor using an oxide semiconductor film . . . . . . . . .

[0129] Also, the intrinsic resistance of the liquid crystal material is 1×10 9 Ω·cm or more, preferably 1×10 1 1 Ω·cm or more, and more preferably 1×10 12 Ω·cm or more. The value of the intrinsic resistance in this specification is the value measured at 20°C .

[0130] . The size of the holding capacitance provided in the display device is the lead of the transistor arranged in the pixel region It is set so as to be able to hold charges for a predetermined period in consideration of leakage current and the like. The size of the holding capacitance may be set in consideration of the off-current of the transistor and the like. By using a transistor having an oxide semiconductor layer with high purity and suppressed formation of oxygen deficiency, for example, as a display element when a liquid crystal element is used, a holding capacitance having a size of 1 / 3 or less, preferably 1 / 5 or less, of the liquid crystal capacitance in each pixel is sufficient.

[0131] In addition, the transistor using the oxide semiconductor with high purity and suppressed formation of oxygen deficiency used in this embodiment for the semiconductor layer can reduce the current value (off-current value) in the off state. Therefore, the holding time of an electric signal such as an image signal can be lengthened, and the writing interval can also be set long in the power-on state. Therefore, the frequency of the refresh operation can be reduced, and thus the effect of suppressing power consumption is achieved.

[0132] In addition, in the display device shown in FIGS. 1 and 2, as the driving mode of the liquid crystal element 150, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode , ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode , AFLC (AntiFerroelectric Liquid Crystal) mode, etc. can be used. In particular, it is preferable to use the FFS mode to obtain a wide viewing angle. ​​​​​​​​

[0133] Further, a normally black type liquid crystal display device, for example, one adopting a vertical alignment (VA) mode may be a transmissive liquid crystal display device. Examples of the vertical alignment mode include, but are not limited to for example, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode and the like can be used. Also, the pixel can be divided into several regions (sub-pixels), and a multi-domain or multi-domain design method in which molecules are tilted in different directions can be used respectively.

[0134] Also, in FIGS. 1 and 2, although not shown, optical members (optical substrates) such as polarizing members, retardation members, and anti-reflection members may be appropriately provided. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. Also, a backlight, a side light, etc. may be used as the light source

[0135] Also, the display method in the pixel region 142 can use a progressive method, an interlace method, etc. Also, when performing color display, the color elements controlled by the pixel are not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, RGBW (W represents white), or one or more colors such as yellow, cyan, and magenta are added to RGB There is. Note that the size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to a color display device, and can also be applied to a monochrome display device

[0136] ​​​​​​​​​Also, a spacer 160 is formed below the second substrate 152 and is provided to control the distance (also referred to as the cell gap) between the first substrate 1 02 and the second substrate 152. Note that the film thickness of the liquid crystal layer 162 is determined by the cell gap. As the spacer 1 60, a spacer of any shape such as a columnar spacer or a spherical spacer obtained by selectively etching an insulating film may be used.

[0137] Also, the colored film 153 functions as a so-called color filter. As the colored film 153, a material that exhibits transparency to light in a specific wavelength band may be used, and an organic resin film containing a dye or a pigment can be used.

[0138] Also, the light-shielding film 154 functions as a so-called black matrix. As the light-shielding film 154, it is sufficient if it can block the emitted light between adjacent pixels, and a metal film, an organic resin film containing a black dye or a black pigment, etc. can be used. In this embodiment, a light-shielding film 154 made of an organic resin film containing a black pigment is exemplified.

[0139] Also, the organic protective insulating film 156 is provided so that the ionic substances contained in the colored film 153 do not diffuse into the liquid crystal layer 162. However, the organic protective insulating film 156 is not limited to this configuration and may not be provided.

[0140] Also, as the sealing material 166, a thermosetting resin, an ultraviolet-curing resin, or the like can be used. In the sealing region of the sealing material 166 shown in FIG. 2, between the first substrate 10 2 and the second substrate 152, a gate insulating film 106, a source electrode 110, and a drain electrode 1 ​​​​​​The electrode 113, the first interlayer insulating film 114, and the second interlayer insulating film formed in the same process as 12 are exemplified, but the present invention is not limited thereto. For example, it may be configured with only the gate insulating film 106 and the first interlayer insulating film 114. In addition, since there is no entry of moisture or the like from the outside when the second interlayer insulating film 116 is removed, as shown in FIG. 2, a structure in which a part of the second interlayer insulating film 116 is removed or a part thereof is retracted is preferable. Although the configuration in which the gate insulating film 106 and the first interlayer insulating film 114 are provided is exemplified, the present invention is not limited thereto. For example, it may be configured with only the first interlayer insulating film 114. In addition, since there is no entry of moisture or the like from the outside when the second interlayer insulating film 116 is removed, as shown in FIG. 2, a structure in which a part of the second interlayer insulating film 116 is removed or a part thereof is retracted is preferable. Except for the second interlayer insulating film 116, since there is no entry of moisture or the like from the outside, as shown in FIG. 2, a structure in which a part of the second interlayer insulating film 116 is removed or a part thereof is retracted is preferable. Except for the second interlayer insulating film 116, since there is no entry of moisture or the like from the outside, as shown in FIG. 2, a structure in which a part of the second interlayer insulating film 116 is removed or a part thereof is retracted is preferable. Except for the second interlayer insulating film 116, since there is no entry of moisture or the like from the outside, as shown in FIG. 2, a structure in which a part of the second interlayer insulating film 116 is removed or a part thereof is retracted is preferable.

[0141] As described above, the display device according to the present embodiment has transistors formed in each of the pixel region and the drive circuit region, a first interlayer insulating film formed on the transistors, a second interlayer insulating film formed on the first interlayer insulating film, and a third interlayer insulating film formed on the second interlayer insulating film. The third interlayer insulating film is provided in a part on the pixel region, and an end portion of the third interlayer insulating film is formed inside the drive circuit region. With such a configuration, outgassing from the second interlayer insulating film can be suppressed from entering the transistor side, and a highly reliable display device can be obtained. Further, the first interlayer insulating film can suppress outgassing from the second interlayer insulating film from entering the transistor side. As described above, the display device according to the present embodiment has transistors formed in each of the pixel region and the drive circuit region, a first interlayer insulating film formed on the transistors, a second interlayer insulating film formed on the first interlayer insulating film, and a third interlayer insulating film formed on the second interlayer insulating film. The third interlayer insulating film is provided in a part on the pixel region, and an end portion of the third interlayer insulating film is formed inside the drive circuit region. With such a configuration, outgassing from the second interlayer insulating film can be suppressed from entering the transistor side, and a highly reliable display device can be obtained. Further, the first interlayer insulating film can suppress outgassing from the second interlayer insulating film from entering the transistor side. As described above, the display device according to the present embodiment has transistors formed in each of the pixel region and the drive circuit region, a first interlayer insulating film formed on the transistors, a second interlayer insulating film formed on the first interlayer insulating film, and a third interlayer insulating film formed on the second interlayer insulating film. The third interlayer insulating film is provided in a part on the pixel region, and an end portion of the third interlayer insulating film is formed inside the drive circuit region. With such a configuration, outgassing from the second interlayer insulating film can be suppressed from entering the transistor side, and a highly reliable display device can be obtained. Further, the first interlayer insulating film can suppress outgassing from the second interlayer insulating film from entering the transistor side. As described above, the display device according to the present embodiment has transistors formed in each of the pixel region and the drive circuit region, a first interlayer insulating film formed on the transistors, a second interlayer insulating film formed on the first interlayer insulating film, and a third interlayer insulating film formed on the second interlayer insulating film. The third interlayer insulating film is provided in a part on the pixel region, and an end portion of the third interlayer insulating film is formed inside the drive circuit region. With such a configuration, outgassing from the second interlayer insulating film can be suppressed from entering the transistor side, and a highly reliable display device can be obtained. Further, the first interlayer insulating film can suppress outgassing from the second interlayer insulating film from entering the transistor side. As described above, the display device according to the present embodiment has transistors formed in each of the pixel region and the drive circuit region, a first interlayer insulating film formed on the transistors, a second interlayer insulating film formed on the first interlayer insulating film, and a third interlayer insulating film formed on the second interlayer insulating film. The third interlayer insulating film is provided in a part on the pixel region, and an end portion of the third interlayer insulating film is formed inside the drive circuit region. With such a configuration, outgassing from the second interlayer insulating film can be suppressed from entering the transistor side, and a highly reliable display device can be obtained. Further, the first interlayer insulating film can suppress outgassing from the second interlayer insulating film from entering the transistor side. As described above, the display device according to the present embodiment has transistors formed in each of the pixel region and the drive circuit region, a first interlayer insulating film formed on the transistors, a second interlayer insulating film formed on the first interlayer insulating film, and a third interlayer insulating film formed on the second interlayer insulating film. The third interlayer insulating film is provided in a part on the pixel region, and an end portion of the third interlayer insulating film is formed inside the drive circuit region. With such a configuration, outgassing from the second interlayer insulating film can be suppressed from entering the transistor side, and a highly reliable display device can be obtained. Further, the first interlayer insulating film can suppress outgassing from the second interlayer insulating film from entering the transistor side. As described above, the display device according to the present embodiment has transistors formed in each of the pixel region and the drive circuit region, a first interlayer insulating film formed on the transistors, a second interlayer insulating film formed on the first interlayer insulating film, and a third interlayer insulating film formed on the second interlayer insulating film. The third interlayer insulating film is provided in a part on the pixel region, and an end portion of the third interlayer insulating film is formed inside the drive circuit region. With such a configuration, outgassing from the second interlayer insulating film can be suppressed from entering the transistor side, and a highly reliable display device can be obtained. Further, the first interlayer insulating film can suppress outgassing from the second interlayer insulating film from entering the transistor side. As described above, the display device according to the present embodiment has transistors formed in each of the pixel region and the drive circuit region, a first interlayer insulating film formed on the transistors, a second interlayer insulating film formed on the first interlayer insulating film, and a third interlayer insulating film formed on the second interlayer insulating film. The third interlayer insulating film is provided in a part on the pixel region, and an end portion of the third interlayer insulating film is formed inside the drive circuit region. With such a configuration, outgassing from the second interlayer insulating film can be suppressed from entering the transistor side, and a highly reliable display device can be obtained. Further, the first interlayer insulating film can suppress outgassing from the second interlayer insulating film from entering the transistor side.

[0142] The configuration shown in the present embodiment can be appropriately combined with the configurations shown in other embodiments or examples and used. The configuration shown in the present embodiment can be appropriately combined with the configurations shown in other embodiments or examples and used.

[0143] (Embodiment 2) In the present embodiment, as one form of the display device, a display device using an organic EL panel will be described with reference to FIGS. 3 and 4. The same reference numerals are given to the same parts as those shown in the first embodiment, and the detailed description thereof will be omitted. In the present embodiment, as one form of the display device, a display device using an organic EL panel will be described with reference to FIGS. 3 and 4. The same reference numerals are given to the same parts as those shown in the first embodiment, and the detailed description thereof will be omitted. In the present embodiment, as one form of the display device, a display device using an organic EL panel will be described with reference to FIGS. 3 and 4. The same reference numerals are given to the same parts as those shown in the first embodiment, and the detailed description thereof will be omitted.

[0144] As one form of the display device, a top view of the display device is shown in FIG. 3, and a cross-sectional view of the display device is shown in FIG. 4. Note that FIG. 4 corresponds to a cross-sectional view taken along X2 - Y2 in FIG. 3.

[0145] In the display device shown in FIG. 3, a pixel region 142 provided on the first substrate 102, and a gate driver circuit portion 140 and a source driver circuit portion 144 that are adjacent to the outside of the pixel region 142 and supply signals to the pixel region 142 are surrounded by a sealing material 166 and sealed by a second substrate 152. Also, the second substrate 152 is provided so as to face the first substrate 102 on which the pixel region 142, the gate driver circuit portion 140, and the source driver circuit portion 144 are provided. Thus, the pixel region 142, the gate driver circuit portion 140, and the source driver circuit portion 144 are sealed together with the display element by the first substrate 102, the sealing material 166, and the second substrate 152.

[0146] In this way, a part or all of the drive circuit including the transistor can be integrally formed on the same first substrate 102 as the pixel region 142 to form a system - on - panel.

[0147] Next, with reference to FIG. 4, which corresponds to a cross - sectional view taken along X2 - Y2 in FIG. 3, the configuration of the pixel region 142 and the gate driver circuit portion 140 will be described in detail below.

[0148] In the pixel region 142, the first substrate 102, a gate electrode 104 formed on the first substrate 102, a gate insulating film 106 formed on the gate electrode 104, a semiconductor layer 108 that is in contact with the gate insulating film 106 and is provided at a position overlapping the gate electrode 104, and a gate The source electrode 110 and the drain electrode 1 formed on the insulating film 106 and the semiconductor layer 108 12 form the first transistor 101 therewith.

[0149] Also, in the pixel region 142, on the first transistor 101, more specifically, on the gate insulation film 106, the semiconductor layer 108, the source electrode 110, and the drain electrode 112, an inorganic first interlayer insulating film 114 formed of an insulating material, and an organic insulating second interlayer insulating film 116 formed of an insulating material on the first interlayer insulating film 114, and an inorganic insulating material third interlayer insulating film 120 formed of an insulating material on the second interlayer insulating film 116, and a partition wall 126 formed on the second interlayer insulating film 116 and the third interlayer insulating film 120, and a pixel electrode 122 formed on the third interlayer insulating film 120 and the partition wall 126, and a light-emitting layer 128 formed on the pixel electrode 122, and an electrode 130 formed on the light-emitting layer 12 8 are formed. 8.

[0150] Note that the pixel electrode 122, the light-emitting layer 128, and the electrode 130 form the light-emitting element 170 therewith.

[0151] Also, a filling material 172 is provided on the light-emitting element 170, more specifically, on the electrode 130, and a second substrate 152 is provided on the filling material 172. That is, the first substrate 102 and the second substrate 152 sandwich the light-emitting element 170 and the filling material 172 therebetween.

[0152] Also, in the gate driver circuit section 140, the first substrate 102, and the gate electrode 104 formed on the first substrate 102 and the gate insulating film 10 6 formed on the gate electrode 104, and the semiconductor provided in contact with the gate insulating film 106 and overlapping the gate electrode 104​​ Layer 108, gate insulating film 106, and source electrode 110 formed on semiconductor layer 108 And drain electrode 112 form the second transistor 103 and the third transistor 105.

[0153] Also, in gate driver circuit section 140, on the second transistor 103 and the third transistor 105, more specifically, on gate insulating film 106, semiconductor layer 108, source electrode 110, and drain electrode 112, first interlayer insulating film 11 4 formed of an inorganic insulating material, and second interlayer insulating film 116 formed of an organic insulating material on first interlayer insulating film 114 is formed.

[0154] That is, third interlayer insulating film 120 is provided on a part of pixel region 142, and the end of third interlayer insulating film 120 is formed inside gate driver circuit section 140 which is a driving circuit region than. formed.

[0155] By adopting such a configuration, moisture taken in from the outside or moisture, gas such as hydrogen generated inside the display device can be discharged upward from second interlayer insulating film 116 of gate driver circuit section 140. Therefore, it is possible to suppress the intake of gas such as moisture and hydrogen into the first transistor 101, the second transistor 103, and the third transistor 105. 103, and the third transistor 105. 103, and the third transistor 105. inside.

[0156] Note that second interlayer insulating film 116 formed of an organic insulating material requires an organic insulating material with high flatness in order to reduce the unevenness of the transistors constituting the display device. However, the organic insulating material releases hydrogen, moisture, or organic components as gas by heating or the like or the like. However, the organic insulating material releases hydrogen, moisture, or organic components as gas by heating or the like It will be released.

[0157] However, in a transistor using, for example, a silicon film which is a silicon-based semiconductor material for the semiconductor layer 108 the above-mentioned gases of hydrogen, moisture, or organic components do not pose a major problem and the probability is low. However, in one aspect of the present invention, since an oxide semiconductor film is used for the semiconductor layer 108 it is necessary to suitably release the gas from the second interlayer insulating film 116 formed of an organic insulating material to the outside. Note that the configuration in which the end of the third interlayer insulating film 120 is formed inside the gate driver circuit portion 140 which is the drive circuit region exhibits excellent effects when the semiconductor layer 108 is formed of an oxide semiconductor film. However, in a transistor formed of a material other than an oxide semiconductor (for example, amorphous silicon which is a silicon-based semiconductor material, crystalline silicon, etc.) for the semiconductor layer 108, the same effects can be obtained. silicon, etc.) for the semiconductor layer 108, the same effects can be obtained.

[0158] Further, the third interlayer insulating film 120 formed on the second interlayer insulating film 116 is formed in the present embodiment in order to suppress the gas released from the second interlayer insulating film 116 from entering the light emitting element 170 side and / or to improve the adhesion between the pixel electrode 122 and the second interlayer insulating film 116. With such a configuration, it is possible to suppress the entry of gases such as hydrogen and moisture from the second interlayer insulating film 116 into the light emitting element 170 side.

[0159] However, when the third interlayer insulating film 120 is formed on the second interlayer insulating film 116 on the second transistor 103 and the third transistor 105 used for the gate driver circuit portion 140 the gas released from the organic insulating material used for the second interlayer insulating film 116 diffuses to the outside It cannot be dissipated and will penetrate into the second transistor 103 and the third transistor 105. Penetrate.

[0160] When the above-described gas penetrates into the oxide semiconductor used for the semiconductor layer 108 of the transistor, it is incorporated as an impurity in the oxide semiconductor film, and the characteristics of the transistor using the semiconductor layer 108 will fluctuate. Incorporated as an impurity in the oxide semiconductor film, and the characteristics of the transistor using the semiconductor layer 108 will fluctuate. The characteristics will fluctuate.

[0161] However, as shown in FIG. 4, the second transistor 103 used for the gate driver circuit section 140 and the third interlayer insulating film 120 on the third transistor 105 are opened, that is, the third interlayer insulating film 120 is provided in a part of the pixel region 142, and the end of the third interlayer insulating film 120 is formed inside the gate driver circuit section 140. By doing so, the gas released from the second interlayer insulating film 116 can be diffused to the outside. That is, the third interlayer insulating film 120 is provided in a part of the pixel region 142, and the end of the third interlayer insulating film 120 is formed inside the gate driver circuit section 140. By doing so, the gas released from the second interlayer insulating film 116 can be diffused to the outside. That is, the third interlayer insulating film 120 is provided in a part of the pixel region 142, and the end of the third interlayer insulating film 120 is formed inside the gate driver circuit section 140. By doing so, the gas released from the second interlayer insulating film 116 can be diffused to the outside. That is, the third interlayer insulating film 120 is provided in a part of the pixel region 142, and the end of the third interlayer insulating film 120 is formed inside the gate driver circuit section 140. By doing so, the gas released from the second interlayer insulating film 116 can be diffused to the outside. That is, the third interlayer insulating film 120 is provided in a part of the pixel region 142, and the end of the third interlayer insulating film 120 is formed inside the gate driver circuit section 140. By doing so, the gas released from the second interlayer insulating film 116 can be diffused to the outside. It can be made.

[0162] In addition, as shown in FIG. 4, in the first transistor 101 used for the pixel region 142, it is also preferable that the third interlayer insulating film 120 formed of an inorganic insulating material at the position where the semiconductor layer 108 overlaps is removed. By adopting such a configuration, the gas released from the second interlayer insulating film 116 formed of an organic insulating material can be suppressed from entering the first transistor 101. In addition, as shown in FIG. 4, in the first transistor 101 used for the pixel region 142, it is also preferable that the third interlayer insulating film 120 formed of an inorganic insulating material at the position where the semiconductor layer 108 overlaps is removed. By adopting such a configuration, the gas released from the second interlayer insulating film 116 formed of an organic insulating material can be suppressed from entering the first transistor 101. In addition, as shown in FIG. 4, in the first transistor 101 used for the pixel region 142, it is also preferable that the third interlayer insulating film 120 formed of an inorganic insulating material at the position where the semiconductor layer 108 overlaps is removed. By adopting such a configuration, the gas released from the second interlayer insulating film 116 formed of an organic insulating material can be suppressed from entering the first transistor 101. In addition, as shown in FIG. 4, in the first transistor 101 used for the pixel region 142, it is also preferable that the third interlayer insulating film 120 formed of an inorganic insulating material at the position where the semiconductor layer 108 overlaps is removed. By adopting such a configuration, the gas released from the second interlayer insulating film 116 formed of an organic insulating material can be suppressed from entering the first transistor 101. In addition, as shown in FIG. 4, in the first transistor 101 used for the pixel region 142, it is also preferable that the third interlayer insulating film 120 formed of an inorganic insulating material at the position where the semiconductor layer 108 overlaps is removed. By adopting such a configuration, the gas released from the second interlayer insulating film 116 formed of an organic insulating material can be suppressed from entering the first transistor 101.

[0163] Here, regarding the other components of the display device shown in FIGS. 3 and 4, the configurations different from those of the display device shown in the first embodiment will be described in detail below. The configurations different from those of the display device shown in the first embodiment will be described in detail below.

[0164] The partition wall 126 is formed using an organic insulating material or an inorganic insulating material. In particular, a photosensitive Using the resin material, an opening is formed on the pixel electrode 122, and it is preferable that the side wall of the opening is formed as an inclined surface having a continuous curvature. It is preferably formed so as to be an inclined surface formed with a continuous curvature.

[0165] As the filling material 172, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), an acrylic resin, a polyimide resin, an epoxy resin, a silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. For example, nitrogen may be used as the filling material 17 2. For example, nitrogen may be used as the filling material 172.

[0166] As the light emitting element 170, a light emitting element utilizing electroluminescence can be applied. The light emitting element utilizing electroluminescence is distinguished depending on whether the light emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element. Here, an organic EL element will be described.

[0167] In the organic EL element, when a voltage is applied to the light emitting element, electrons and holes are respectively injected from a pair of electrodes (the pixel electrode 122 and the electrode 130) into the layer containing the light emitting organic compound, and a current flows. Then, when these carriers (electrons and holes) recombine, the light emitting organic compound forms an excited state, and light is emitted when the excited state returns to the ground state. Due to such a mechanism, such a light emitting element is called a current excitation type light emitting element.

[0168] At least one of the pair of electrodes (the pixel electrode 122 or the electrode 130) of the light emitting element 170 may be translucent in order to extract light. And from the surface on the side opposite to the first substrate 102​​​ There are top emission for extracting light emission, bottom emission for extracting light emission from the surface on the side of the first substrate 102, and double-sided emission structures for extracting light emission from the surfaces on the side of the first substrate 102 and the side opposite to the first substrate 102, and light-emitting elements of any emission structure can be applied. There are top emission for extracting light emission, bottom emission for extracting light emission from the surface on the side of the first substrate 102, and double-sided emission structures for extracting light emission from the surfaces on the side of the first substrate 102 and the side opposite to the first substrate 102, and light-emitting elements of any emission structure can be applied. There are top emission for extracting light emission, bottom emission for extracting light emission from the surface on the side of the first substrate 102, and double-sided emission structures for extracting light emission from the surfaces on the side of the first substrate 102 and the side opposite to the first substrate 102, and light-emitting elements of any emission structure can be applied.

[0169] Also, a protective film may be formed on the electrode 130 and the partition wall 126 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light-emitting element 170. As the protective film, a silicon nitride film, a silicon oxynitride film, etc. can be formed. Further, a filling material 172 is provided and sealed in the space sealed by the first substrate 102, the second substrate 152, and the sealing material 166. In this way, it has high airtightness so as not to be exposed to the outside air and is preferably packaged (encapsulated) with a protective film (laminating film, ultraviolet curable resin film, etc.) or a cover material with little outgassing. 152, and the sealing material 166. In this way, it has high airtightness so as not to be exposed to the outside air and is preferably packaged (encapsulated) with a protective film (laminating film, ultraviolet curable resin film, etc.) or a cover material with little outgassing. 152, and the sealing material 166. In this way, it has high airtightness so as not to be exposed to the outside air and is preferably packaged (encapsulated) with a protective film (laminating film, ultraviolet curable resin film, etc.) or a cover material with little outgassing. 152, and the sealing material 166. In this way, it has high airtightness so as not to be exposed to the outside air and is preferably packaged (encapsulated) with a protective film (laminating film, ultraviolet curable resin film, etc.) or a cover material with little outgassing. 152, and the sealing material 166. In this way, it has high airtightness so as not to be exposed to the outside air and is preferably packaged (encapsulated) with a protective film (laminating film, ultraviolet curable resin film, etc.) or a cover material with little outgassing.

[0170] Also, if necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter may be appropriately provided on the light-emitting surface of the light-emitting element 170. Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment that diffuses reflected light due to surface unevenness and reduces reflection can be performed. Also, if necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter may be appropriately provided on the light-emitting surface of the light-emitting element 170. Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment that diffuses reflected light due to surface unevenness and reduces reflection can be performed. Also, if necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter may be appropriately provided on the light-emitting surface of the light-emitting element 170. Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment that diffuses reflected light due to surface unevenness and reduces reflection can be performed. Also, if necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter may be appropriately provided on the light-emitting surface of the light-emitting element 170. Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment that diffuses reflected light due to surface unevenness and reduces reflection can be performed.

[0171] Also, as the light-emitting layer 128, it is preferable to use an organic compound containing a guest material that is a light-emitting material that converts triplet excitation energy into light emission and a host material having a higher triplet excitation energy level (T1 level) than the guest material. Note that the light-emitting layer 128 has a structure in which a plurality of light-emitting layers are laminated (so-called tandem structure), or a functional layer other than the light-emitting layer (hole injection layer, hole transport Also, as the light-emitting layer 128, it is preferable to use an organic compound containing a guest material that is a light-emitting material that converts triplet excitation energy into light emission and a host material having a higher triplet excitation energy level (T1 level) than the guest material. Note that the light-emitting layer 128 has a structure in which a plurality of light-emitting layers are laminated (so-called tandem structure), or a functional layer other than the light-emitting layer (hole injection layer, hole transport Also, as the light-emitting layer 128, it is preferable to use an organic compound containing a guest material that is a light-emitting material that converts triplet excitation energy into light emission and a host material having a higher triplet excitation energy level (T1 level) than the guest material. Note that the light-emitting layer 128 has a structure in which a plurality of light-emitting layers are laminated (so-called tandem structure), or a functional layer other than the light-emitting layer (hole injection layer, hole transport layer, etc.) It may be configured to include a layer, an electron transport layer, an electron injection layer, a charge generation layer, etc.

[0172] In addition, as the sealing material 166, in addition to the materials shown in Embodiment 1, a material including a glass material such as a glass body formed by melting and solidifying powdered glass (also called frit glass) may be used. Such a material can effectively suppress the permeation of moisture and gas. Therefore, when the light-emitting element 170 is used as the display element, the deterioration of the light-emitting element 170 can be suppressed, and a highly reliable display device can be realized. In addition, in the sealing region of the sealing material 166 shown in FIG. 4, a configuration in which only the gate insulating film 106 is provided between the first substrate 102 and the second substrate 152 is illustrated, but it is not limited to this. For example, a configuration in which the gate insulating film 106 and the first interlayer insulating film 114 are laminated may also be used. However, as shown in FIG. 4, in the region where the second interlayer insulating film 116 is removed, a configuration in which the sealing material 166 is disposed is preferable.

[0173] As described above, the display device shown in this embodiment has transistors formed in the pixel region and the drive circuit region, respectively, a first interlayer insulating film formed on the transistors, a second interlayer insulating film formed on the first interlayer insulating film, and a third interlayer insulating film formed on the second interlayer insulating film. The third interlayer insulating film is provided in a part of the pixel region, and the end of the third interlayer insulating film is formed inside the drive circuit region. With such a configuration, the outgassing from the second interlayer insulating film can be suppressed from entering the transistor side, and a highly reliable display device can be obtained. Further, the first interlayer insulating film can also prevent the outgassing from the second interlayer insulating film from entering the transistor side. For example, a configuration in which the gate insulating film 106 and the first interlayer insulating film 114 are laminated may also be used. However, as shown in FIG. 4, in the region where the second interlayer insulating film 116 is removed, a configuration in which the sealing material 166 is disposed is preferable. However, as shown in FIG. 4, in the region where the second interlayer insulating film 116 is removed, a configuration in which the sealing material 166 is disposed is preferable. As described above, the display device shown in this embodiment has transistors formed in the pixel region and the drive circuit region, respectively, a first interlayer insulating film formed on the transistors, a second interlayer insulating film formed on the first interlayer insulating film, and a third interlayer insulating film formed on the second interlayer insulating film. The third interlayer insulating film is provided in a part of the pixel region, and the end of the third interlayer insulating film is formed inside the drive circuit region.

[0174] As described above, the display device shown in this embodiment has transistors formed in the pixel region and the drive circuit region, respectively, a first interlayer insulating film formed on the transistors, a second interlayer insulating film formed on the first interlayer insulating film, and a third interlayer insulating film formed on the second interlayer insulating film. The third interlayer insulating film is provided in a part of the pixel region, and the end of the third interlayer insulating film is formed inside the drive circuit region. With such a configuration, the outgassing from the second interlayer insulating film can be suppressed from entering the transistor side, and a highly reliable display device can be obtained. As described above, the display device shown in this embodiment has transistors formed in the pixel region and the drive circuit region, respectively, a first interlayer insulating film formed on the transistors, a second interlayer insulating film formed on the first interlayer insulating film, and a third interlayer insulating film formed on the second interlayer insulating film. The third interlayer insulating film is provided in a part of the pixel region, and the end of the third interlayer insulating film is formed inside the drive circuit region. With such a configuration, the outgassing from the second interlayer insulating film can be suppressed from entering the transistor side, and a highly reliable display device can be obtained. With such a configuration, the outgassing from the second interlayer insulating film can be suppressed from entering the transistor side, and a highly reliable display device can be obtained. With such a configuration, the outgassing from the second interlayer insulating film can be suppressed from entering the transistor side, and a highly reliable display device can be obtained. In addition, the first interlayer insulating film can also prevent the outgassing from the second interlayer insulating film from entering the transistor side. It is possible to suppress the degassing from the film from entering the transistor side.

[0175] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments or examples. and can be used.

[0176] (Embodiment 3) In this embodiment, an image sensor that can be combined with the display device shown in the previous embodiment will be described.

[0177] FIG. 5(A) shows an example of a display device with an image sensor. FIG. 5(A) is an equivalent circuit showing one pixel of the display device with an image sensor.

[0178] One electrode of the photodiode element 4002 is electrically connected to the reset signal line 4058, and the other electrode is electrically connected to the gate electrode of the transistor 4040. One of the source electrode or drain electrode of the transistor 4040 is at the power supply potential (VDD), and the other of the source electrode or drain electrode is electrically connected to one of the source electrode or drain electrode of the transistor 4056. The gate electrode of the transistor 4056 is connected to the gate selection line 4057, and the other of the source electrode or drain electrode is electrically connected to the output signal line 4071.

[0179] Also, the first transistor 4030 is a transistor for pixel switching, and one of the source electrode or drain electrode is connected to the video signal line 4059, and the other of the source electrode or drain electrode is electrically connected to the capacitor element 4032 and the liquid crystal element 4034. Also, the gate electrode of the first transistor 4030 is electrically connected to the gate line 4036.

[0180] Note that the first transistor 4030, the capacitive element 4032, and the liquid crystal element 4034 may have the same structure as the display device shown in Embodiment Form 1.

[0181] FIG. 5(B) is a cross-sectional view showing a part of one pixel of the display device with an image sensor and a cross-sectional view of the drive circuit section. In the pixel region 5042, a photodiode element 4002 and a first transistor 4030 are provided on the first substrate 4001. Also, in the gate driver circuit section 5040 which is a drive circuit on the first substrate 4001, a second transistor 4060 and a third transistor 4062 are provided.

[0182] Note that on the photodiode element 4002 and the first transistor 4030 in the pixel region 5042, a first interlayer insulating film 4014, a second interlayer insulating film 4016, and a third interlayer insulating film 4020 are formed. Also, a capacitive element 4032 using the third interlayer insulating film 4020 as a dielectric is formed on the second interlayer insulating film 4016.

[0183] That is, the third interlayer insulating film 4020 is provided in a part of the pixel region 5042, and the end of the third interlayer insulating film 4020 is formed inside the gate driver circuit section 5040. With such a configuration, the gas released from the second interlayer insulating film 4016 can be diffused to the outside. Therefore, it is possible to suppress the outgassing from the second interlayer insulating film 40 16 from entering the transistor side, and a highly reliable display device can be obtained.

[0184] Note that the photodiode element 4002 is connected to the source electrode of the first transistor 4030 and A lower electrode formed in the same process as the drain electrode and an upper electrode formed in the same process as the pixel electrode of the liquid crystal element 4034 are used as a pair of electrodes, and a diode is provided between the pair of electrodes. This is the configuration.

[0185] As the diode that can be used for the photodiode element 4002, a pn diode including a stack of a p-type semiconductor film and an n-type semiconductor film, a pin diode including a stack of a p-type semiconductor film, an i-type semiconductor film, and an n-type semiconductor film, a Schottky diode, etc. may be used.

[0186] Further, on the photodiode element 4002, a first alignment film 4024, a liquid crystal layer 4096, a second alignment film 4084, a counter electrode 4088, an organic insulating film 4086, a colored film 4085, a second substrate 4052, etc. are provided.

[0187] Note that the pin diode exhibits higher photoelectric conversion characteristics when the p-type semiconductor film side is used as the light-receiving surface. This is because the hole mobility is smaller than the electron mobility. In the present embodiment, an example of a configuration for converting light incident on the photodiode element 4002 from the surface of the second substrate 4052 into an electrical signal through the colored film 4085, the liquid crystal layer 4096, etc. is shown, but it is not limited to this. For example, a configuration without the colored film 4085 may be used.

[0188] The photodiode element 4002 shown in the present embodiment utilizes the fact that when light is incident on the photodiode element 4002, a current flows between the pair of electrodes. By detecting light with the photodiode element 4002, information on the object to be detected can be read.

[0189] ​​​​​​​​​​​​The display device with an image sensor shown in this embodiment can improve productivity by sharing processes such as the fabrication of transistors for the display device and the image sensor. However, the display device shown in the previous embodiment and the image sensor shown in this embodiment may be fabricated on different substrates. Specifically, in the display device shown in the previous embodiment, an image sensor may be fabricated on the second substrate.

[0190] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments or other examples.

[0191] (Embodiment 4) In this embodiment, an example of a tablet-type terminal using the display device according to one aspect of the present invention will be described.

[0192] FIGS. 6(A) and 6(B) show a foldable tablet-type terminal. FIG. 6(A) shows the tablet-type terminal in an open state. The tablet-type terminal includes a housing 8630, and provided in the housing 86 30 are a display unit 8631a, a display unit 8631b, a display mode changeover switch 8034, a power switch 8035, a power saving mode changeover switch 8036, a fastener 80 33, and an operation switch 8038.

[0193] The display device according to one aspect of the present invention can be applied to the display unit 8631a and the display unit 8631b.

[0194] The display unit 8631a can function as a touch panel partially or entirely, and input can be performed by touching the displayed operation keys. For example, all of the display unit 8631a can be made to function as a touch panel, and input can be performed by touching the displayed operation keys. For example, all of the display unit 8631a Display keyboard buttons on the surface, function as a touch panel, and display the display unit 8631b It may be used as a screen.

[0195] Also, similar to the display unit 8631a, part or all of the display unit 8631b can be made to function as a touch panel and can function as such.

[0196] Moreover, it is also possible to perform touch input simultaneously on the touch panel area of the display unit 8631a and the touch panel area of the display unit 8631b

[0197] Also, the display mode switching switch 8034 can select switching of the display orientation such as vertical display or horizontal display, switching between black-and-white display and color display, etc. The power-saving mode switching switch 8036 can optimize the display brightness according to the external light detected by the optical sensor built into the tablet terminal . Note that the tablet terminal may have other detection devices such as a gyroscope and an acceleration sensor that can detect inclination in addition to the optical sensor .

[0198] Also, in Fig. 6(A), an example where the areas of the display unit 8631b and the display unit 8631a are the same is shown but it is not particularly limited. Even if the areas of the display unit 8631b and the display unit 8631a are different it is fine, and even if the display qualities are different. For example, one may be a display panel that can perform higher-definition display than the other

[0199] Fig. 6(B) shows a state where the tablet terminal is closed. The tablet terminal includes a housing 86 30 and a solar cell 8633 and a charge / discharge control circuit 8634 provided in the housing 8630 and. Note that in Fig. 6(B), as an example of the charge / discharge control circuit 8634, a battery 86 ​​​​35. A configuration having a DCDC converter 8636 is shown.

[0200] Since the tablet terminal is foldable in two, the housing 8630 can be closed when not in use. Therefore, the display units 8631a and 8631b can be protected, so it is excellent in durability and reliability from the viewpoint of long-term use.

[0201] In addition, the tablet terminal shown in FIGS. 6(A) and 6(B) can also have various functions, such as the function of displaying various information (such as still images, moving images, text images, etc.), the function of displaying a calendar, date or time, etc. on the display unit, the touch input function of touch input operation or editing the information displayed on the display unit, the function of controlling the processing by various software (programs), etc. can be provided. The tablet terminal can use the power obtained by the solar cell 8633 for the operation of the tablet terminal.

[0202] Or the power can be stored in the battery 8635. The solar cell 8633 can also be configured to be provided on two sides of the housing 8630. When a lithium-ion battery is used as the battery 8635, there are advantages in terms of miniaturization.

[0203] In addition, the configuration and operation of the charge / discharge control circuit 8634 shown in FIG. 6(B) are illustrated and explained in FIG. 6(C) by a block diagram. FIG. 6(C) shows the solar cell 8633, the battery 863 5, the DCDC converter 8636, the converter 8637, the switch SW1, the sw itch SW2, the switch SW3, and the display unit 8631. Then, the battery 8635, the DCDC converter 8636, the converter 8637, the switches SW1, switch SW2, and switch SW3 correspond to the charge / discharge control circuit 86 shown in FIG. 6(B).

[0204] When power is generated by the solar cell 8633, the power generated by the solar cell is stepped up or down by the DCDC converter 8636 to a voltage for charging the battery 8 635. Next, switch SW1 is turned on, and the converter 8637 steps up or down the voltage to an optimal voltage for the display unit 8631. When the display on the display unit 8631 is not performed, switch S W1 is turned off, and switch SW2 is turned on to charge the battery 8635.

[0205] Although the solar cell 8633 is shown as an example of the power generation means, it is not particularly limited, and other power generation means such as piezoelectric elements (piezoelectric elements) and thermoelectric conversion elements (Peltier elements) can be used instead. For example, a configuration in which other charging means such as a contactless power transmission module that wirelessly (non - contact) transmits and receives power for charging is combined may be used.

[0206]

[0207] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments or other examples.

[0207] (Embodiment 5) In this embodiment, an example of an electronic device equipped with the display device and the like shown in the previous embodiment will be described.

[0208] FIG. 7(A) shows a portable information terminal. The portable information terminal shown in FIG. 7(A) includes a housing 930 0, a button 9301, a microphone 9302, a display unit 9303, a speaker 93 04 and a camera 9305, and has a function as a mobile phone. A display unit 93 The display device shown in the previous embodiment or / and the display device with an image sensor can be applied to 03.

[0209] FIG. 7(B) is a display. The display shown in FIG. 7(B) includes a housing 9310 and a display unit 9311. The display device shown in the previous embodiment or / and the display device with an image sensor can be applied to the display unit 9311.

[0210] FIG. 7(C) is a digital still camera. The digital still camera shown in FIG. 7(C) includes a housing 9320, buttons 9321, a microphone 9322, and a display unit 9323 . The display device shown in the previous embodiment or / and the display device with an image sensor can be applied to the display unit 9323.

[0211] By using one aspect of the present invention, the reliability of the electronic device can be improved.

[0212] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments or other examples.

Example

[0213] In this example, the emission gas of acrylic resin, which is a typical organic resin that can be used for the display device, was investigated.

[0214] The sample was prepared by coating acrylic resin on a glass substrate and performing heat treatment at 250°C for 1 hour in a nitrogen gas atmosphere. Note that the acrylic resin was formed to have a thickness of 1.5 μm after the heat treatment.

[0215] ​​​​​​​ For the prepared sample, measurement of the released gas was performed by TDS (Thermal Desorption Spectroscopy: temperature-programmed desorption gas spectroscopy).

[0216] Fig. 8 shows the ion intensity of the released gas at each mass-to-charge ratio (also referred to as M / z) when the substrate surface temperature is 250 °C. In Fig. 8, the horizontal axis represents the mass-to-charge ratio, and the vertical axis represents the intensity (in arbitrary units). respectively. From Fig. 8, it was found that gases with a mass-to-charge ratio of 18 (H2O) attributed to water and gases with mass-to-charge ratios of 28 (C2H4), 44 (C3H8), and 56 (C4H8) attributed to hydrocarbons were detected from the sample. Near each mass-to-charge ratio, the respective fragment ions were detected.

[0217] Similarly, Fig. 9 shows the ion intensity of each mass-to-charge ratio (18, 28, 44, and 56) with respect to the substrate surface temperature. In Fig. 9, the horizontal axis represents the substrate surface temperature (°C), and the vertical axis represents the intensity (in arbitrary units). When the substrate surface temperature range was from 55 °C to 270 °C, it was found that the ion intensity of the mass-to-charge ratio of 18 attributed to water had peaks at 55 °C or higher and 100 °C or lower and at 150 °C or higher and 270 °C or lower. On the other hand, the ion intensities of the mass-to-charge ratios of 28, 44, and 56 attributed to hydrocarbons had peaks at 150 °C or higher and 270 °C or lower.

[0218] As shown above, it was found that impurities such as water and hydrocarbons from the organic resin were released for the oxide semiconductor film. In particular, it was found that water was released even at a relatively low temperature of 55 °C or higher and 100 °C or lower. That is, impurities caused by the organic resin reached the oxide semiconductor film. ​​​​​​​​​​​​​It was suggested that the electrical characteristics of a transistor may be deteriorated if the

[0219] In addition, organic resins are treated with a film that does not transmit water, hydrocarbons, and other released gases (silicon nitride film, nitride When the material is covered with a film of silicon oxide or aluminum oxide, gas is released from the organic resin. This increases pressure on the membrane, which is impermeable to water, hydrocarbons, and other released gases, eventually causing the This can destroy the film that is impermeable to released gases such as hydrogen chloride, resulting in defective transistor shapes. was suggested. EXAMPLES

[0220] In this example, a transistor was fabricated, and its cross-sectional shape and electrical characteristics were evaluated.

[0221] Each sample has a bottom-gate, top-contact, channel-etched oxide semiconductor The transistor is provided on a glass substrate. A gate electrode formed on the gate electrode, a gate insulating film formed on the gate electrode, and a gate insulating film formed on the gate electrode. an oxide semiconductor film provided on the gate electrode; The gate electrode is a tungsten film, and the gate electrode is a pair of electrodes. The insulating film is a silicon nitride film and a silicon oxynitride film on the silicon nitride film, which are oxide semiconductors. The substrate is an In-Ga-Zn oxide film, the pair of electrodes are tungsten films, and the An aluminum film and a titanium film on an aluminum film were used, respectively.

[0222] A protective insulating film (a silicon oxynitride film with a thickness of 450 nm and a silicon oxynitride film) is formed on the pair of electrodes. A 50 nm thick silicon nitride film is provided on the silicon film.

[0223] Note that in the example sample, an acrylic resin is provided on the protective insulating film with a thickness of 2 μm, and a silicon nitride film with a thickness of 200 nm is provided on the acrylic resin so as to expose a part of the side surface of the acrylic resin. Also, in the comparative example sample, an acrylic resin is provided on the protective insulating film with a thickness of 1.5 μm, and a silicon nitride film with a thickness of 200 nm is provided on the acrylic resin so as to cover the acrylic resin.

[0224] Fig. 10 shows a transmission electron image (also referred to as a Transmitted Electron: TE image) cross-sectional shape of an enlarged region of a part of the comparative example sample by TEM. For the observation of the cross-sectional shape, "Hitachi Ultra-Thin Film Evaluation Device HD-2300" manufactured by Hitachi High-Technologies Corporation was used. In Fig. 10, only one of the pair of electrodes is shown. Focusing on the electrode shown in Fig. 10 and the protective insulating film provided so as to cover the electrode, it was found that cracks had occurred in the protective insulating film from the step difference portion formed by the electrode. Note that in the observation region, since the example sample and the comparative example sample have substantially the same structure, the cross-sectional shape of the example sample is omitted.

[0225] Therefore, the example sample has a structure in which the gas released from the acrylic resin escapes to the outside of the example sample, and the comparative example sample has a structure in which the gas released from the acrylic resin does not escape to the outside of the comparative example sample. That is, in the comparative example sample, it was found that the gas released from the acrylic resin does not escape to the outside and reaches the transistor through the cracks generated in the protective insulating film.

[0226] Next, the gate voltage (Vg)-drain current (I d) characteristics, which are the electrical characteristics of the transistors of each sample, were measured. The Vg-Id characteristics were measured for transistors with a channel length of 3 μm and a channel width of 3 μm. ​​​Measured using a transistor. In the measurement of the Vg-Id characteristics, the drain voltage ( Vd) was set to 1 V or 10 V, and the gate voltage (Vg) was swept from -20 V to 15 V.

[0227] Fig. 11 shows the Vg-Id characteristics of each sample. On a 600 mm × 720 mm glass substrate the Vg-Id characteristics of 20 transistors were measured as evenly as possible. Fig. 11(A) shows the Vg-Id characteristics and the field-effect mobility of the transistors of the example sample, and Fig. 11(B) shows the Vg-Id characteristics of the transistors of the comparative example sample. The field-effect mobility shown in Fig. 11(A) represents the value at a drain voltage (Vd) of 10 V. Also, in Fig. 11 (B), since it was difficult to calculate the field-effect mobility, it is omitted.

[0228] From Fig. 11(A), it was found that good switching characteristics were obtained for the transistors of the example sample. Also, from Fig. 11(B), it was found that switching characteristics were not obtained for the transistors of the comparative example sample, and they were always on. By comparison with the example sample, it was found that the poor switching characteristics of the comparative example sample were due to the release gas from the acrylic resin

[0229] affecting the transistors. Specifically, it is presumed that the carrier density of the oxide semiconductor film increased due to the influence of the release gas from the acrylic resin, and the transistors could not be turned off by the electric field from the gate electrode. From this example, when the organic resin is covered with a film that does not permeate release gases such as water and hydrocarbons (here, a silicon nitride film with a thickness of 200 nm), the release gas from the organic resin does not cause problems with the transistors

[0230] ​​It can be seen that the switching characteristics of the transistor are deteriorated. Further, a part of the film that covers the organic resin and does not permeate release gases such as water and hydrocarbons is provided with a path for the release gas to escape to the outside of the sample, whereby the deterioration of the switching characteristics of the transistor can be avoided, and it can be seen that good switching characteristics can be obtained.

Explanation of Signs

[0231] 101 First transistor 102 First substrate 103 Second transistor 104 Gate electrode 105 Third transistor 106 Gate insulating film 107 Capacitor element 108 Semiconductor layer 110 Source electrode 112 Drain electrode 113 Electrode 114 First interlayer insulating film 116 Second interlayer insulating film 118 Capacitor electrode 120 Third interlayer insulating film 122 Pixel electrode 124 First alignment film 126 Partition wall 128 Light emitting layer 130 Electrode 140 Gate driver circuit section 142 Pixel region 144 Source driver circuit section 146 FPC terminal section 148 FPC 150 Liquid crystal element 152 Second substrate 153 Color film 154 Light shielding film 156 Organic protective insulating film 158 Counter electrode 160 Spacer 162 Liquid crystal layer 164 Second alignment film ​166 Sealing material 170 Light-emitting element 172 Filling material 4001 First substrate 4002 Photodiode element 4014 First interlayer insulating film 4016 Second interlayer insulating film 4020 Third interlayer insulating film 4024 First alignment film 4030 First transistor 4032 Capacitor element 4034 Liquid crystal element 4036 Gate line 4040 Transistor 4052 Second substrate 4056 Transistor 4057 Gate selection line 4058 Reset signal line 4059 Video signal line 4060 Second transistor 4062 Third transistor 4071 Output signal line 4084 Second alignment film 4085 Colored film 4086 Organic insulating film 4088 Counter electrode 4096 Liquid crystal layer 5040 Gate driver circuit section 5042 Pixel region 8033 Fastener 8034 Switch 8035 Power switch 8036 Switch 8038 Operation switch 8630 Housing 8631 Display section 8631a Display section 8631b Display section 8633 Solar cell 8634 Charge and discharge control circuit 8635 Battery 8636 DCDC converter 8637 Converter 9300 Housing 9301 Button 9302 Microphone 9303 Display Unit 9304 Speaker 9305 Camera 9310 Housing 9311 Display Unit 9320 Housing 9321 Button 9322 Microphone 9323 Display Unit

Claims

1. A pixel region having a first transistor; a driving circuit region adjacent to the outside of the pixel region and having a second transistor, a first conductive film having a region in contact with an upper surface of a substrate and functioning as a gate electrode of the first transistor; a second conductive film having a region in contact with an upper surface of the substrate and functioning as a gate electrode of the second transistor; a first insulating film having a region in contact with an upper surface of the first conductive film and a region in contact with an upper surface of the second conductive film, and having a function as a gate insulating film of the first transistor and a function as a gate insulating film of the second transistor; a first oxide semiconductor layer having a region in contact with a top surface of the first insulating film and functioning as a channel formation region of the first transistor; a second oxide semiconductor layer having a region in contact with a top surface of the first insulating film and functioning as a channel formation region of the first transistor; a third conductive film having a region in contact with a top surface of the first oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the first transistor; a fourth conductive film having a region in contact with a top surface of the first oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the first transistor; a fifth conductive film having a region in contact with a top surface of the second oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the first transistor; a sixth conductive film having a region in contact with a top surface of the second oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the first transistor; a second insulating film having a region in contact with an upper surface of the third conductive film, a region in contact with an upper surface of the fourth conductive film, a region in contact with an upper surface of the fifth conductive film, and a region in contact with an upper surface of the sixth conductive film; a third insulating film having a region in contact with an upper surface of the second insulating film; a seventh conductive film having a region in contact with an upper surface of the third insulating film; a fourth insulating film having a region in contact with an upper surface of the third insulating film and a region in contact with an upper surface of the seventh conductive film; an eighth conductive film having a region in contact with an upper surface of the fourth insulating film and functioning as a pixel electrode; the eighth conductive film has a region in contact with an upper surface of the second conductive film or the third conductive film via a first opening formed in the third insulating film and a second opening formed in the fourth insulating film; the first and second openings do not have a region overlapping with the first oxide semiconductor layer; The diameter of the second opening is larger than the diameter of the first opening, an end portion of the fourth insulating film is located between the pixel region and the drive circuit region; the first conductive film and the second conductive film each have a stacked structure of a film containing nitrogen and tantalum and a tungsten film, the first insulating film has a stacked structure of an insulating film containing nitrogen and silicon and an insulating film containing oxygen and silicon, the first oxide semiconductor layer and the second oxide semiconductor layer each have a stacked structure of a first oxide semiconductor film and a second oxide semiconductor film; the third conductive film, the fourth conductive film, the fifth conductive film, and the sixth conductive film each have a stacked structure of a titanium film, an aluminum film, and a titanium film; the second insulating film has a stacked structure of an insulating film containing oxygen and silicon and an insulating film containing nitrogen and silicon, the third insulating film comprises an organic insulating material; the seventh conductive film and the eighth conductive film each contain indium, tin, and oxygen; The fourth insulating film includes nitrogen and silicon.

2. A pixel region having a first transistor; a driving circuit region adjacent to the outside of the pixel region and having a second transistor, a first conductive film having a region in contact with an upper surface of a substrate and functioning as a gate electrode of the first transistor; a second conductive film having a region in contact with an upper surface of the substrate and functioning as a gate electrode of the second transistor; a first insulating film having a region in contact with an upper surface of the first conductive film and a region in contact with an upper surface of the second conductive film, and having a function as a gate insulating film of the first transistor and a function as a gate insulating film of the second transistor; a first oxide semiconductor layer having a region in contact with a top surface of the first insulating film and functioning as a channel formation region of the first transistor; a second oxide semiconductor layer having a region in contact with a top surface of the first insulating film and functioning as a channel formation region of the first transistor; a third conductive film having a region in contact with a top surface of the first oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the first transistor; a fourth conductive film having a region in contact with a top surface of the first oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the first transistor; a fifth conductive film having a region in contact with a top surface of the second oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the first transistor; a sixth conductive film having a region in contact with a top surface of the second oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the first transistor; a second insulating film having a region in contact with an upper surface of the third conductive film, a region in contact with an upper surface of the fourth conductive film, a region in contact with an upper surface of the fifth conductive film, and a region in contact with an upper surface of the sixth conductive film; a third insulating film having a region in contact with an upper surface of the second insulating film; a seventh conductive film having a region in contact with an upper surface of the third insulating film; a fourth insulating film having a region in contact with an upper surface of the third insulating film and a region in contact with an upper surface of the seventh conductive film; an eighth conductive film having a region in contact with an upper surface of the fourth insulating film and functioning as a pixel electrode; the eighth conductive film has a region in contact with an upper surface of the second conductive film or the third conductive film via a first opening formed in the third insulating film and a second opening formed in the fourth insulating film; the first and second openings do not have a region overlapping with the first oxide semiconductor layer; The diameter of the second opening is larger than the diameter of the first opening, an end portion of the fourth insulating film does not overlap with the drive circuit region; the first conductive film and the second conductive film each have a stacked structure of a film containing nitrogen and tantalum and a tungsten film, the first insulating film has a stacked structure of an insulating film containing nitrogen and silicon and an insulating film containing oxygen and silicon, the first oxide semiconductor layer and the second oxide semiconductor layer each have a stacked structure of a first oxide semiconductor film and a second oxide semiconductor film; the third conductive film, the fourth conductive film, the fifth conductive film, and the sixth conductive film each have a stacked structure of a titanium film, an aluminum film, and a titanium film; the second insulating film has a stacked structure of an insulating film containing oxygen and silicon and an insulating film containing nitrogen and silicon, the third insulating film comprises an organic insulating material; the seventh conductive film and the eighth conductive film each contain indium, tin, and oxygen; The fourth insulating film includes nitrogen and silicon.

3. A pixel region having a first transistor; a driving circuit region adjacent to the outside of the pixel region and having a second transistor, a first conductive film having a region in contact with an upper surface of a substrate and functioning as a gate electrode of the first transistor; a second conductive film having a region in contact with an upper surface of the substrate and functioning as a gate electrode of the second transistor; a first insulating film having a region in contact with an upper surface of the first conductive film and a region in contact with an upper surface of the second conductive film, and having a function as a gate insulating film of the first transistor and a function as a gate insulating film of the second transistor; a first oxide semiconductor layer having a region in contact with a top surface of the first insulating film and functioning as a channel formation region of the first transistor; a second oxide semiconductor layer having a region in contact with a top surface of the first insulating film and functioning as a channel formation region of the first transistor; a third conductive film having a region in contact with a top surface of the first oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the first transistor; a fourth conductive film having a region in contact with a top surface of the first oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the first transistor; a fifth conductive film having a region in contact with a top surface of the second oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the first transistor; a sixth conductive film having a region in contact with a top surface of the second oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the first transistor; a second insulating film having a region in contact with an upper surface of the third conductive film, a region in contact with an upper surface of the fourth conductive film, a region in contact with an upper surface of the fifth conductive film, and a region in contact with an upper surface of the sixth conductive film; a third insulating film having a region in contact with an upper surface of the second insulating film; a seventh conductive film having a region in contact with an upper surface of the third insulating film; a fourth insulating film having a region in contact with an upper surface of the third insulating film and a region in contact with an upper surface of the seventh conductive film; an eighth conductive film having a region in contact with an upper surface of the fourth insulating film and functioning as a pixel electrode; the eighth conductive film has a region in contact with an upper surface of the second conductive film or the third conductive film via a first opening formed in the third insulating film and a second opening formed in the fourth insulating film; the first and second openings do not have a region overlapping with the first oxide semiconductor layer; The diameter of the second opening is larger than the diameter of the first opening, an end portion of the fourth insulating film does not overlap with a transistor included in the driver circuit region; the first conductive film and the second conductive film each have a stacked structure of a film containing nitrogen and tantalum and a tungsten film, the first insulating film has a stacked structure of an insulating film containing nitrogen and silicon and an insulating film containing oxygen and silicon, the first oxide semiconductor layer and the second oxide semiconductor layer each have a stacked structure of a first oxide semiconductor film and a second oxide semiconductor film; the third conductive film, the fourth conductive film, the fifth conductive film, and the sixth conductive film each have a stacked structure of a titanium film, an aluminum film, and a titanium film; the second insulating film has a stacked structure of an insulating film containing oxygen and silicon and an insulating film containing nitrogen and silicon, the third insulating film comprises an organic insulating material; the seventh conductive film and the eighth conductive film each contain indium, tin, and oxygen; The fourth insulating film includes nitrogen and silicon.

4. A pixel region having a first transistor; a driving circuit region adjacent to the outside of the pixel region and having a second transistor, a first conductive film having a region in contact with an upper surface of a substrate and functioning as a gate electrode of the first transistor; a second conductive film having a region in contact with an upper surface of the substrate and functioning as a gate electrode of the second transistor; a first insulating film having a region in contact with an upper surface of the first conductive film and a region in contact with an upper surface of the second conductive film, and having a function as a gate insulating film of the first transistor and a function as a gate insulating film of the second transistor; a first oxide semiconductor layer having a region in contact with a top surface of the first insulating film and functioning as a channel formation region of the first transistor; a second oxide semiconductor layer having a region in contact with a top surface of the first insulating film and functioning as a channel formation region of the first transistor; a third conductive film having a region in contact with a top surface of the first oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the first transistor; a fourth conductive film having a region in contact with a top surface of the first oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the first transistor; a fifth conductive film having a region in contact with a top surface of the second oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the first transistor; a sixth conductive film having a region in contact with a top surface of the second oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the first transistor; a second insulating film having a region in contact with an upper surface of the third conductive film, a region in contact with an upper surface of the fourth conductive film, a region in contact with an upper surface of the fifth conductive film, and a region in contact with an upper surface of the sixth conductive film; a third insulating film having a region in contact with an upper surface of the second insulating film; a seventh conductive film having a region in contact with an upper surface of the third insulating film; a fourth insulating film having a region in contact with an upper surface of the third insulating film and a region in contact with an upper surface of the seventh conductive film; an eighth conductive film having a region in contact with an upper surface of the fourth insulating film and functioning as a pixel electrode; the eighth conductive film has a region in contact with an upper surface of the second conductive film or the third conductive film via a first opening formed in the third insulating film and a second opening formed in the fourth insulating film; the first and second openings do not have a region overlapping with the first oxide semiconductor layer; The diameter of the second opening is larger than the diameter of the first opening, an end portion of the fourth insulating film does not overlap with the second conductive film, the fifth conductive film, the sixth conductive film, or the second oxide semiconductor layer; the first conductive film and the second conductive film each have a stacked structure of a film containing nitrogen and tantalum and a tungsten film, the first insulating film has a stacked structure of an insulating film containing nitrogen and silicon and an insulating film containing oxygen and silicon, the first oxide semiconductor layer and the second oxide semiconductor layer each have a stacked structure of a first oxide semiconductor film and a second oxide semiconductor film; the third conductive film, the fourth conductive film, the fifth conductive film, and the sixth conductive film each have a stacked structure of a titanium film, an aluminum film, and a titanium film; the second insulating film has a stacked structure of an insulating film containing oxygen and silicon and an insulating film containing nitrogen and silicon, the third insulating film comprises an organic insulating material; the seventh conductive film and the eighth conductive film each contain indium, tin, and oxygen; The fourth insulating film includes nitrogen and silicon.

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