Array substrate and display device

Abstract

To reduce parasitic capacitance and suppress signal delay.SOLUTION: An array substrate 21 comprises: gate wiring 26; source wiring 27 that intersects the gate wiring 26; a switching element 23 provided at an intersection of the gate wiring 26 and the source wiring 27; a semiconductor film 23A provided to the switching element 23; a first insulting film F2 interposed between the gate wiring 26 and the semiconductor film 23A; and a second insulating film F4 interposed between the semiconductor film 23A and the source wiring 27. The source wiring 27 is superimposed on the gate wiring 26 via the first insulating film F2 and the second insulting film F4.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The technology disclosed in this specification relates to an array substrate and a display device.

Background Art

[0002] The following Patent Document 1 discloses an array substrate of a liquid crystal display device. In the array substrate described in Patent Document 1, by increasing the thickness of the wiring, the cross-sectional area becomes larger and the resistance value decreases. When the resistance value decreases, the time constant becomes smaller, and signal delay can be suppressed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The time constant τ of a signal transmission circuit (RC circuit) is represented by τ = RC and depends not only on the resistance value R but also on the capacitance (parasitic capacitance) C. Depending on the drive voltage of the transistor to which the signal is input and the resistance value of the peripheral circuit, reducing the parasitic capacitance of the transmission circuit may be more effective in suppressing signal delay than reducing the resistance value of the transmission circuit.

[0005] The technology disclosed in this specification has been completed based on the above circumstances, and an object thereof is to reduce the parasitic capacitance of wiring and suppress signal delay.

Means for Solving the Problems

[0006] (1) The array substrate described in this specification includes a gate wiring, a source wiring that intersects with the gate wiring, a switching element provided at an intersection of the gate wiring and the source wiring, a semiconductor film provided on the switching element, a first insulating film disposed in a layer between the gate wiring and the semiconductor film, and a second insulating film disposed in a layer between the semiconductor film and the source wiring. The source wiring overlaps with the gate wiring via the first insulating film and the second insulating film.

[0007] (2) In the array substrate described in (1) above, the switching element has a source electrode connected to the semiconductor film. The source wiring is connected to the source electrode, thereby being connected to the semiconductor film via the source electrode. The source electrode may be provided between the first insulating film and the second insulating film.

[0008] (3) In the array substrate described in (1) or (2) above, the source electrode may not overlap with the gate wiring.

[0009] (4) The array substrate described in any one of (1) to (3) above includes a relay electrode. The switching element has a drain electrode connected to the semiconductor film. The relay electrode is connected to the drain electrode, thereby being connected to the semiconductor film via the drain electrode. The drain electrode may be provided between the first insulating film and the second insulating film.

[0010] (5) A display device according to the technology described in this specification may include the array substrate described in any one of (1) to (4) above and a counter substrate facing the array substrate.

Advantages of the Invention

[0011] According to the technology described in this specification, it is possible to reduce the parasitic capacitance of the wiring and suppress the delay of the signal.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Embodiments for Carrying Out the Invention

[0013] <Embodiment> Embodiments of the present invention will be described with reference to FIGS. 1 to 6. In this embodiment, a liquid crystal panel 11 (an example of a “display panel”) provided in a liquid crystal display device 10 (an example of a “display device”) will be exemplified and described. In some of the drawings, the X-axis, Y-axis, and Z-axis are shown, and the axial directions are drawn so as to be common in each drawing. Also, regarding the vertical direction, with reference to FIG. 2, the upper side of the figure is the front side, and the lower side of the figure is the back side.

[0014] 1. Outline of the liquid crystal panel FIG. 1 is a plan view of the liquid crystal panel 11. As shown in FIG. 1, the liquid crystal panel 11 according to this embodiment has a substantially rectangular planar shape that is horizontally long as a whole. In this liquid crystal panel 11, the long side direction coincides with the X-axis direction, the short side direction coincides with the Y-axis direction, and the plate thickness direction coincides with the Z-axis direction, respectively.

[0015] The liquid crystal panel 11 can display an image using illumination light irradiated from a backlight device (lighting device). The central side portion of the screen in the liquid crystal panel 11 is a display area (pixel area) AA where an image is displayed. On the other hand, the frame-shaped outer peripheral side portion surrounding the display area AA on the screen is a non-display area (frame area) NAA where no image is displayed. The range surrounded by the dashed-dotted line in FIG. 1 is the display area AA.

[0016] As shown in FIG. 1, the liquid crystal panel 11 has a pair of substrates 20 and 21 made of glass that are substantially transparent and have excellent light transmittance. Among the pair of substrates 20 and 21, the substrate arranged on the front side is the counter substrate 20 (CF substrate), and the substrate arranged on the back side is the array substrate 21 (active matrix substrate, element substrate). Various films are laminated and formed on the inner surface side of both the counter substrate 20 and the array substrate 21.

[0017] The array substrate 21 has a short side dimension larger than that of the counter substrate 20, and one end in the long side direction does not overlap with the counter substrate 20. A driver (signal supply unit, mounted component) 12 and a flexible substrate (mounted component) 13 are mounted at the non-overlapping portion. The driver 12 is composed of an LSI chip having a drive circuit inside, and is COG (Chip On Glass) mounted on the mounting area of the array substrate 21. The driver 12 processes various signals transmitted via the flexible substrate 13.

[0018] The flexible substrate 13 has the driver 12 mounted thereon. The driver 12 is composed of an LSI chip having a drive circuit inside. The driver 12 is mounted on the flexible substrate 13 and processes various signals supplied from an external control substrate.

[0019] In the non-display area NAA of the array substrate 21, a pair of gate circuit portions 14 are provided at positions adjacent to both sides (the left side and the right side in FIG. 1) of the display area AA in the X-axis direction. The gate circuit portion 14 supplies a scanning signal to the gate wiring 26 described later. The gate circuit portion 14 is monolithically provided on the array substrate 21 using a metal film or the like that constitutes the gate wiring 26 and the source wiring 27. The gate circuit portion 14 has a shift register circuit or the like for sequentially supplying a scanning signal to a plurality of gate wirings 26.

[0020] The flexible substrate 13 is configured such that a number of wiring patterns (not shown) are formed on a base material made of a synthetic resin material (such as a polyimide resin) having insulation and flexibility. One end side of the flexible substrate 13 is connected to the array substrate 21, and the other end side is connected to an external control substrate (signal supply source). Various signals supplied from the control substrate are transmitted to the liquid crystal panel 11 via the flexible substrate 13.

[0021] FIG. 2 is a schematic cross-sectional view of the display area AA of the liquid crystal panel 11. As shown in FIG. 2, the liquid crystal panel 11 sandwiches a liquid crystal layer 29 containing liquid crystal molecules whose optical properties change with the application of voltage between a pair of substrates 20 and 21.

[0022] On the inner surface side of the counter substrate 20 in the display area AA, three-color color filters 30 presenting red (R), green (G), and blue (B) are provided. These color filters 30 are arranged so as to overlap with the respective pixel electrodes 24 of the array substrate 21 in a planar view. A light-shielding portion 31 is provided between adjacent color filters 30. The light-shielding portion 31 functions as a partition between the color filters 30. In the liquid crystal panel 11, the RGB color filters 30 arranged along the X-axis direction and the three pixel electrodes 24 facing each color filter 30 constitute three-color pixels PX.

[0023] The counter substrate 20 is provided with a solid counter electrode 22 extending over the entire display area AA. The counter electrode 22 is made of the same transparent electrode material as the pixel electrode 24, and is arranged to face all the pixel electrodes 24 arranged in the display area AA with the liquid crystal layer 29 interposed therebetween.

[0024] Alignment films 32 are respectively provided on the innermost surfaces of the pair of substrates 20 and 21. Polarizing plates 33 are respectively provided on the outermost surfaces of the pair of substrates 20 and 21.

[0025] 2. Wiring and TFT FIG. 3 is an enlarged view of the display area AA of the array substrate 21. As shown in FIG. 3, a plurality of gate wirings 26 (wiring, scanning wiring) and source wirings 27 (wiring, image wiring) in a lattice pattern are provided on the inner surface side of the display area AA of the array substrate 21.

[0026] The gate wiring 26 extends along the X-axis direction across the display area AA. The source wiring 27 extends along the Y-axis direction longitudinally across the display area AA. The plurality of gate wirings 26 are arranged at intervals in the Y-axis direction. The plurality of source wirings 27 are arranged at intervals along the X-axis direction. The gate wiring 26 and the source wiring 27 are each composed of two metal films arranged in different layers via at least a gate insulating film F2 (described later).

[0027] The gate wiring 26 and the source wiring 27 intersect as viewed from the Z-axis direction, and a TFT 23 (an example of a “switching element”) is formed in the vicinity of each intersection. The rectangular area surrounded by the gate wiring 26 and the source wiring 27 corresponds to the pixel PX described above. Inside the pixel PX, a pixel electrode 24 (transparent electrode) is formed. Each metal film constituting the gate wiring 26 and the source wiring 27 has conductivity.

[0028] The configuration of the TFT 23 and the wirings 26 and 27 will be described with reference to FIG. 4. FIG. 4 is a plan view of an enlarged view of the vicinity of the TFT 23. As shown in FIG. 4, the TFT 23 has a semiconductor film 23A, a gate electrode 23G, a source electrode 23S, and a drain electrode 23D.

[0029] A gate electrode 23G protruding in the Y-axis direction is connected to the gate wiring 26 extending along the X-axis direction. The gate electrode 23G is arranged so as to overlap at least a part of the semiconductor film 23A.

[0030] A part of the source wiring 27 extending along the Y-axis direction has a source convex portion 27A protruding in the X-axis direction. The source convex portion 27A is provided at a position that does not overlap with the gate wiring 26. Thereby, the capacitance component generated between the source convex portion 27A and the gate wiring 26 is suppressed.

[0031] The source electrode 23S is provided at the protruding end of the source convex portion 27A so as to at least partially overlap with the source convex portion 27A. The source convex portion 27A and the source electrode 23S are electrically connected in the Z-axis direction at the overlapping portion and have the same potential. The source electrode 23S is provided at a position that does not overlap with the gate wiring 26, and the capacitance component generated between the source electrode 23S and the gate wiring 26 is suppressed.

[0032] The pixel electrode 24 is connected to the drain electrode 23D of the TFT 23 via a contact electrode 34 (an example of a "relay electrode", see FIG. 5).

[0033] The TFT 23 has a semiconductor film 23A made of a semiconductor material. One end side of the semiconductor film 23A is connected to the source electrode 23S, and the other end side is connected to the drain electrode 23D, respectively. The semiconductor film 23A is disposed to overlap with the gate electrode 23G provided on the back side via a gate insulating film F2.

[0034] 2.1 About various films Next, various films that are laminated on the glass substrate of the array substrate 21 and constitute the wirings 26 and 27 and the TFT 23 will be described with reference to FIG. 5. FIG. 5 is a cross-sectional view taken along line A-A in FIG. 4. The line A-A in FIG. 4 is a line that crosses the TFT 23 in the X-axis direction, then bends in the Y-axis direction at a point 27B on the source wiring 27, and longitudinally cuts the intersection of the source wiring 27 and the gate wiring 26 in the Y-axis direction.

[0035] On the glass substrate of the array substrate 21, a first metal film F1, a gate insulating film F2 (an example of a "first insulating film"), a semiconductor film 23A, a second metal film F3, a second insulating film F4, a third metal film F5, a protective film F6, a planarizing film F7, and a transparent electrode film F8 are laminated in order from the lower layer side (glass substrate side).

[0036] The first metal film F1, the second metal film F3, and the third metal film F5 are each made of a metal such as copper or aluminum and have conductivity. The first metal film F1 constitutes a gate wiring 26, a gate electrode 23G of the TFT 23, etc.

[0037] The second metal film F3 constitutes a source electrode 23S and a drain electrode 23D of the TFT 23, etc. The third metal film F5 constitutes a source wiring 27, a contact electrode 34, etc.

[0038] A part of the source wiring 27 extends convexly along the X-axis direction and overlaps with the source electrode 23S at the end in the X-axis direction. At the portion of the source wiring 27 that overlaps with the source electrode 23S, a contact portion 27C that protrudes in the Z-axis direction and contacts the source electrode 23S is formed.

[0039] The source wiring 27 is electrically connected to the source electrode 23S at the contact portion 27C. Similarly, the contact electrode 34 has a contact portion 34A formed at the end of the contact electrode 34 and is connected to the drain electrode 23D at the contact portion 34A.

[0040] The semiconductor film 23A is made of a thin film using a semiconductor material such as an oxide semiconductor or amorphous silicon, and constitutes the channel of the TFT 23. The gate insulating film F2, the second insulating film F4, and the protective film F6 are silicon nitride (SiN x) It is made of an inorganic material such as silicon oxide (SiO2). The gate insulating film F2 is interposed between the first metal film F1 and the semiconductor film 23A to insulate them. More specifically, in the TFT23, the gate insulating film F2 is interposed between the gate electrode 23G and the semiconductor film 23A to generate an electric field and control the current flowing through the channel. Also, the gate insulating film F2 extends to the overlapping portion 36 where the gate wiring 26 and the source wiring 27 cross and overlap. In this overlapping portion, the gate insulating film F2 is interposed between the gate wiring 26 and the source wiring 27 to prevent a short circuit.

[0041] The second insulating film F4 is interposed between the second metal film F3 and the third metal film F5 to prevent a short circuit between the second metal film F3 and the third metal film F5. Specifically, except for the contact portion 27C provided at the location where the source electrode 23S and the source wiring 27 overlap, and the contact portion 34A provided at the location where the drain electrode 23D and the contact electrode 34 overlap, it prevents a short circuit at unintended locations. Also, the second insulating film F4 extends to the overlapping portion 36 of the gate wiring 26 and the source wiring 27, and is interposed between the gate wiring 26 and the source wiring 27 to prevent a short circuit.

[0042] The protective film F6 is formed in a solid shape over substantially the entire area of the array substrate 21 in order to protect various films laminated on the back side of the protective film F6. Contact holes 35 that penetrate the protective film F6 and the planarization film F7 in the film thickness direction (Z-axis direction) are formed in the portions of the protective film F6 and the planarization film F7 that overlap the contact electrode 34.

[0043] The planarization film F7 is made of an organic material such as PMMA (acrylic resin). The film thickness of the planarization film F7 is much larger than that of other films laminated on the glass substrate, and the inner surface (the surface on the liquid crystal layer 29 side) of the array substrate 21 is planarized by this planarization film F7.

[0044] The transparent electrode film F8 is continuously formed across the inner peripheral surface and the bottom surface of the contact hole 35 and the surface of the planarization film F7. Among the transparent electrode film F8, the portion formed on the inner surface side of the array substrate 21 is the pixel electrode 24. The transparent electrode film F8 is in contact with the contact electrode 34 at the bottom of the contact hole 35, and the pixel electrode 24 is electrically connected to the contact electrode 34 and the drain electrode 23D connected to the contact electrode 34.

[0045] When the TFT 23 is turned on based on the scanning signal transmitted by the gate wiring 26, the gradation signal (image signal) transmitted by the source wiring 27 is supplied to the pixel electrode 24 via the source electrode 23S, the semiconductor film 23A, the drain electrode 23D, and the contact electrode 34. At this time, the pixel electrode 24 is charged to the potential based on the gradation signal.

[0046] The liquid crystal panel 11 can apply a predetermined electric field to the liquid crystal layer 29 based on the potential difference generated between the counter electrode 22 and each pixel electrode 24, thereby causing each pixel PX to perform a predetermined gradation display.

[0047] 2.2 About Parasitic Capacitance and Signal Delay The gradation signal input to the TFT 23 through the source wiring 27 is delayed due to the influence of the time constant τs of the source wiring. The time constant τs is represented by τs = RsCs. Rs is the resistance value [Ω] of the source wiring 27, and Cs is the parasitic capacitance [F] of the source wiring 27.

[0048] As shown in FIG. 5, the gate wiring 26 and the source wiring 27 overlap via an insulator (gate insulating film F2 and second insulating film F4) in the overlapping portion 36. The parasitic capacitance Cs2 is a capacitance component caused by the physical structure of the wirings 26 and 27. If the parasitic capacitance Cs2 is large, the time constant τs of the source wiring 27 also becomes large, and the delay of the gradation signal input to the TFT 23 through the source wiring 27 becomes large.

[0049] For comparison purposes here, the conventional array substrate 121 will be described with reference to FIG. 7. FIG. 7 is a cross-sectional view of a portion of the array substrate 121 corresponding to the line A-A in FIG. 4 (a broken line that crosses the TFT23 and longitudinally cuts through the overlapping portion 36 of the gate wiring 26 and the source wiring 27). The array substrate 121 includes a first metal film F11, a gate insulating film F12 (first insulating film), a semiconductor film 123A, a second metal film F13, a protective film F14, a planarizing film F15, a transparent conductive film F16, etc. on a glass substrate.

[0050] The first metal film F11 and the second metal film F13 are each made of a metal such as copper or aluminum and have conductivity. The first metal film F11 forms the gate wiring 126, the gate electrode 123G, etc., similar to the first metal film F1 of the array substrate 21. The second metal film F13 forms the source electrode 123S and the source wiring 127 formed continuously, and the drain electrode 123D, etc. For convenience, among the source electrode 123S and the source wiring 127 formed continuously, the portion extending in the Y-axis direction is defined as the source wiring 127, and the portion protruding from the source wiring 27 in the X-axis direction and extending to be connected to the semiconductor film 123A is defined as the source electrode 123S.

[0051] Both the source electrode 123S and the source wiring 127 of the array substrate 121 are made of the second metal film F13. This is a configuration different from the array substrate 21 of the present invention, in which the source electrode 23S and the source wiring 27 are made of separate metal films (the first metal film F1 and the third metal film F5), and the two are separated by an insulator (the second insulating film F4).

[0052] Also, in the array substrate 21, a portion corresponding to the contact electrode 34 that is interposed between the drain electrode 23D and the transparent conductive film F16 and connected to both is not provided on the array substrate 121. The drain electrode 123D of the array substrate 121 is directly connected to the contact portion 134A made of the transparent conductive film F16.

[0053] The semiconductor film 123A, the protective film F14, the planarization film F15, and the transparent conductive film F16 each have the same configuration as the semiconductor film 23A, the protective film F6, the planarization film F7, and the transparent electrode film F8 of the array substrate 21, respectively.

[0054] The gate insulating film F12 is interposed between the semiconductor film 123A and the gate electrode 123G to insulate between them. Further, the gate insulating film F12 is interposed between the gate wiring 126 and the source wiring 127 at the overlapping portion 136 where the gate wiring 126 and the source wiring 127 overlap to insulate between them.

[0055] In the conventional array substrate 121, the insulator interposed between the gate wiring 126 and the source wiring 127 is only the gate insulating film F12. In the array substrate 121, the distance L1 between the gate wiring 126 and the source wiring 127 depends on the thickness of the gate insulating film F12.

[0056] As a method for reducing the parasitic capacitance Cs1 of the overlapping portion 136, it is conceivable to increase the thickness of the gate insulating film F12. However, changing the thickness of the gate insulating film F12 is feared to affect the characteristics of the TFT123.

[0057] 3. Explanation of Effects In the array substrate 21 of the present embodiment, in order to reduce the parasitic capacitance Cs2 of the overlapping portion 36, it is conceivable to increase the distance L2 between the gate wiring 26 and the source wiring 27. The array substrate 21 of the present embodiment includes a gate wiring 26, a source wiring 27 that intersects the gate wiring 26, a TFT23 provided at the intersection of the gate wiring 26 and the source wiring 27, a semiconductor film 23A provided in the TFT23, a gate insulating film F2 disposed in a layer between the gate wiring 26 and the semiconductor film 23A, and a second insulating film F4 disposed in a layer between the semiconductor film 23A and the source wiring 27. The source wiring 27 overlaps the gate wiring 26 via the gate insulating film F2 and the second insulating film F4.

[0058] In such a configuration, as shown in FIG. 5, in addition to the gate insulating film F2 which is an insulator, a second insulating film F4 is interposed between the gate wiring 26 and the source wiring 27. Even if the thickness of the gate insulating film F2 is the same as the thickness of the gate insulating film F12 (see FIG. 7), the distance L2 between the gate wiring 26 and the source wiring 27 is larger than the distance L1 (see FIG. 7) by the thickness of the second insulating film F4. The parasitic capacitance Cs2 in the overlapping portion 36 is reduced compared to the parasitic capacitance Cs1 at the time of the distance L1. As the parasitic capacitance is reduced, the time constant τs becomes smaller, and the delay of the signal input from the source wiring 27 to the TFT23 can be suppressed.

[0059] Regarding the suppression of the delay, it will be described with reference to the graph 50 shown in FIG. 6. The graph 50 is a graph schematically showing the signal waveforms applied to the source electrodes 23S and 123S when a gradation signal of a rectangular wave (voltage value V0) is input to the source wirings 27 and 127. In the graph 50, the horizontal axis is time and the vertical axis is voltage. The voltage waveform 51 in the graph 50 is the voltage waveform of the gradation signal input to the source wiring 27. The voltage waveforms 52 and 53 are the waveforms of the source voltages transmitted through the source wirings 27 and 127 and applied to the source electrodes 23S and 123S.

[0060] The voltage waveform 51 starts to be applied at the time t0, and the voltage rises from 0 to V0 at the time t0. Further, the voltage V0 is maintained from the time t0 to the time t3, and the voltage drops from V0 to 0 at the time t3. For the sake of convenience, it is assumed that the voltage of the gradation signal rises instantaneously and also drops instantaneously.

[0061] The voltage waveform 52 is the waveform that appears at the source electrode 123S when the gradation signal of the voltage waveform 51 is applied to the source wiring 127 of the array substrate 121 having the conventional configuration shown in FIG. 7. The time constant τ1 calculated by using the electrostatic capacitance C of the source wiring 127 as the parasitic capacitance Cs1 is applied to the voltage waveform 52.

[0062] As shown in FIG. 6, the voltage waveform 52 rises with the passage of time from time t0 and reaches the voltage V0 at time t2. In the array substrate 121 of the conventional configuration, after the application of the gradation signal (voltage waveform 51), it takes a time of t2 - t0 until the voltage reaches the voltage V0.

[0063] If the delay time is defined as the time (time t2) from the start of application of the gradation signal (time t0) until the voltage V0 is reached, the delay time of the array substrate 121 is t2 - t0.

[0064] The voltage waveform 53 shows the voltage of the source electrode 23S when the gradation signal of the voltage waveform 51 is input to the source wiring 27 of the array substrate 21 of the present embodiment shown in FIG. 5. A time constant τ2 calculated by using the capacitance C of the source wiring 27 as the parasitic capacitance Cs2 is applied to the voltage waveform 53. As described above, since the distance L2 between the gate wiring 26 and the source wiring 27 is in the relation of L1 < L2, the parasitic capacitance Cs2 is smaller than Cs1 (Cs1 > Cs2), and the time constant τ2 is smaller than τ1 (τ1 > τ2).

[0065] As shown in FIG. 6, the voltage of the voltage waveform 53 rises with the passage of time from time t0 and reaches the voltage V0 at time t1. The delay time of the array substrate 21 of the present embodiment is t1 - t0. Since the time constant τ1 > τ2, the delay time t1 - t0 of the array substrate 21 is shorter than the delay time t2 - t0 of the array substrate 121. The array substrate 21 of the present embodiment reaches the voltage V0 with a shorter delay time than the array substrate 121, and the signal delay of the source wiring 27 is suppressed as compared with the array substrate 121.

[0066] The shortening of the delay time means that the time from the application of the gradation signal until the pixel performs a predetermined gradation display is shortened. Thereby, the refresh rate of the liquid crystal panel 11 can be increased to a higher frequency, or the number of pixels in the display area AA can be increased to increase the resolution of the liquid crystal panel 11.

[0067] In the array substrate 21 of the present embodiment, the TFT 23 has a source electrode 23S connected to the semiconductor film 23A. The source wiring 27 is connected to the source electrode 23S, and thus is connected to the semiconductor film 23A via the source electrode 23S. The source electrode 23S is provided between the gate insulating film F2 and the second insulating film F4.

[0068] As shown in FIG. 5, the source wiring 27 is connected to the semiconductor film 23A via the source electrode 23S, and the source wiring 27 and the semiconductor film 23A do not directly contact each other. By not directly contacting, it is not necessary to match the material of the source wiring 27 and the formation process (chemical resistance, annealing temperature, etc.) to the material characteristics of the semiconductor film 23A.

[0069] For example, as the material of the source wiring 27, a material that can be well connected to the source electrode 23S but has low connection reliability with the semiconductor film 23A can be applied, or in the formation process of the source wiring 27, a chemical solution with high aggressiveness to the semiconductor film 23A can be used. Thereby, the degree of freedom in the material and process of the source wiring 27 with respect to the semiconductor film 23A is improved.

[0070] In addition, since the source electrode 23S and the source wiring 27 are formed in different layers via the second insulating film F4, the materials and formation processes do not have to be the same. Thereby, the degree of freedom in the material and formation process between the source electrode 23S and the source wiring 27 is improved.

[0071] Since the source wiring 27 is connected to the semiconductor film 23A via the source electrode 23S, the degree of freedom in the arrangement of the source wiring 27 with respect to the semiconductor film 23A is improved. For example, even when the semiconductor film 23A is located at a position where it does not overlap with the source wiring 27, electrical connection between the semiconductor film 23A and the source wiring 27 is possible via the source electrode 23S.

[0072] In the array substrate 21 of the present embodiment, the source electrode 23S does not overlap with the gate wiring 26. When the source electrode 23S and the gate wiring 26 do not overlap, the capacitance component between the two is smaller than when they overlap. In the path of the gradation signal input from the source wiring 27 to the semiconductor film 23A via the source electrode 23S, the total capacitance value between the source wiring 27 and the source electrode 23S, which are connected to each other and have the same potential, and the gate wiring 26 decreases, and the time constant τ becomes smaller, suppressing signal delay.

[0073] In the array substrate 21 of the present embodiment, the TFT 23 has a drain electrode 23D connected to the semiconductor film 23A, and the drain electrode 23D is provided between the gate insulating film F2 and the second insulating film F4.

[0074] By doing so, similar to the relationship between the source wiring 27 and the semiconductor film 23A described above, the degree of freedom in the material and formation process of the drain electrode 23D can be increased.

[0075] Further, the liquid crystal display device 10 according to the present embodiment includes the array substrate 21 described above and a counter substrate 20 disposed opposite to the array substrate 21. According to such a liquid crystal display device 10, since the parasitic capacitance Cs2 of the source wiring 27 is reduced, the signal (gradation signal) transmitted by the source wiring 27 is less likely to be dulled. Thereby, the display quality is improved.

[0076] <Other Embodiments> (1) In the above embodiment, the TFT 23 (switching element) having the semiconductor film 23A, the source electrode 23S, and the drain electrode 23D is exemplified. The switching element may not have one or both of the source electrode and the drain electrode. In this case, a part of the semiconductor film is made conductive by a conductor formation process, and the source wiring or the contact electrode is brought into contact with the conductive portion, thereby electrically connecting the source wiring or the contact electrode and the switching element.

[0077] (2) In the above embodiment, the case where the source electrode 23S does not overlap with the gate wiring 26 has been exemplified and described. Part or all of the source electrode 23S may overlap with the gate wiring 26.

[0078] (3) In the above embodiment, the TFT 23 has been exemplified and described as a bottom gate type TFT having a gate electrode 23G on the back side with a gate insulating film F2 interposed between the semiconductor film 23A. The TFT is not limited to the bottom gate type, and may be a top gate type having a gate electrode on the front side with respect to the semiconductor film. Also, it may be a double gate type having gate electrodes on the front side and the back side with respect to the semiconductor film, respectively.

[0079] (4) In the above embodiment, the TFT has been exemplified and described as a switching element. The switching element is not limited to the TFT, and may be other types of transistors (such as MOSFET, IGBT, etc.).

[0080] (5) As a driving method of the liquid crystal panel, the SSD method (SSD (Source Shared Driving)) in which the display area AA is divided into a plurality of parts and a source signal is distributed from one TFT for each divided area may be applied. Since the delay time of the TFT can be shortened in the array substrate of the present invention, high-speed switching is possible. By using a TFT capable of high-speed switching for the liquid crystal panel of the SSD method, the number of divisions of the display area can be increased.

[0081] (6) In the above embodiment, the case (vertical electric field liquid crystal mode) where the counter electrode 22 is provided on the counter substrate 20 and the alignment state of the liquid crystal molecules contained in the liquid crystal layer 29 is controlled by using the vertical electric field generated between the pixel electrode 24 and the counter electrode 22 has been shown. However, a horizontal electric field may be generated in the liquid crystal layer 29, and the alignment state of the liquid crystal molecules contained in the liquid crystal layer 29 may be controlled by using the horizontal electric field (horizontal electric field liquid crystal mode). To achieve the horizontal electric field liquid crystal mode, instead of the configuration in which the counter electrode 22 is provided on the counter substrate 20, for example, a configuration in which a common electrode overlapping the pixel electrode 24 via an insulating film is provided on the array substrate 21 may be adopted, and a horizontal electric field may be generated between the pixel electrode 24 and the common electrode.

Description of Symbols

[0082] 11: Liquid crystal panel, 21: Array substrate, 22: Counter electrode, 23: TFT (an example of a switching element), 23A: Semiconductor film, 23D: Drain electrode, 23G: Gate electrode, 23S: Source electrode, 26: Gate wiring, 27: Source wiring, 36: Overlapping portion, F1: First metal film, F2: Gate insulating film (an example of a first insulating film), F4: Second insulating film

Claims

1. An array substrate, comprising: a gate wiring; a source wiring intersecting with the gate wiring; a switching element provided at an intersection of the gate wiring and the source wiring; a semiconductor film provided on the switching element; a first insulating film disposed in a layer between the gate wiring and the semiconductor film; a second insulating film disposed in a layer between the semiconductor film and the source wiring, wherein the source wiring overlaps the gate wiring with the first insulating film and the second insulating film therebetween.

2. The array substrate according to Claim 1, wherein the switching element has a source electrode connected to the semiconductor film, the source wiring is connected to the source electrode, and thereby connected to the semiconductor film via the source electrode, and the source electrode is provided between the first insulating film and the second insulating film.

3. The array substrate according to Claim 2, wherein the source electrode does not overlap the gate wiring.

4. The array substrate according to Claim 2, comprising a relay electrode, wherein the switching element has a drain electrode connected to the semiconductor film, the relay electrode is connected to the drain electrode, and thereby connected to the semiconductor film via the drain electrode, and the drain electrode is provided between the first insulating film and the second insulating film.

5. A display device comprising the array substrate according to any one of Claims 1 to 4, and a counter substrate facing the array substrate.

Images