Light-emitting chip, light-emitting device and measuring device

Abstract

To suppress erroneous lighting, compared to such a structure that current leaked from a light-emitting element can flow to a terminal for supplying a reference potential of a driving part.SOLUTION: A light-emitting device includes: a substrate; a plurality of light-emitting elements provided on the substrate; a plurality of thyristors which, when turned on, cause each of the plurality of light emitting elements to emit light or increase the amount of light to be emitted by each of the plurality of light emitting elements; a driving part which is provided on the substrate, individually drives the plurality of thyristors and brings the thyristors into the ON state; and a reference potential terminal for supplying the predetermined reference potential to the driving part, where the region of the driving part connected to the reference potential terminal is electrically separated from the side face of the substrate.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a light-emitting chip, a light-emitting device, and a measuring device. [Background technology]

[0002] Patent document 1 describes a light-emitting device having a semiconductor substrate, a light-emitting element section formed on the semiconductor substrate and having a plurality of light-emitting elements that emit light, a signal line formed on the semiconductor substrate and that transmits a signal to the light-emitting element, and an oxide film formed along the signal line between the signal line and the semiconductor substrate. Patent Document 2 describes a light emitting section that uses transistor coupling. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-42123 [Patent Document 2] Japanese Patent Application Publication No. 2023-112937 Summary of the Invention [Problem to be solved by the invention]

[0004] In a light-emitting chip in which a light-emitting element and a driver that transmits signals to the light-emitting element are configured on a semiconductor substrate, leakage current from the light-emitting element may flow from the substrate, particularly through the dicing surface on the outer periphery of the substrate, to a terminal that supplies a reference potential to the driver. In this case, the light-emitting element that has once emitted light remains on, causing erroneous lighting. An object of the present invention is to suppress erroneous lighting compared to a configuration in which leakage current from a light emitting element can flow to a terminal that supplies a reference potential of a driving unit. [Means for solving the problem]

[0005] The invention described in claim 1 is a light-emitting device comprising: a substrate; a plurality of light-emitting elements provided on the substrate; a plurality of thyristors that, when turned on, cause each of the light-emitting elements to emit light or increase the amount of light emitted by the light-emitting elements; a driving unit provided on the substrate that individually drives the plurality of thyristors to transition them to the on state; and a reference potential terminal that supplies a predetermined reference potential to the driving unit, wherein the region of the driving unit connected to the reference potential terminal is electrically isolated from the side of the substrate. The invention described in claim 2 is a light-emitting chip comprising a semiconductor substrate, a plurality of light-emitting elements provided on the surface side of the substrate, and a plurality of thyristors that cause the light-emitting elements to emit light or increase the amount of light emitted by the light-emitting elements when turned on, a drive unit provided on the surface side of the substrate that individually drives the plurality of thyristors to transition them to the on state, a reference potential terminal that supplies a predetermined reference potential to the drive unit, and a separation unit that suppresses the flow of current between the reference potential terminal and the substrate. A third aspect of the present invention is the light-emitting chip according to the second aspect, wherein the separating portion prevents the driving portion from being formed to extend to the outer periphery of the substrate. The invention described in claim 4 is a light-emitting chip described in claim 2, in which the separation portion prevents a current path from being formed between the light-emitting element and the reference potential terminal through the side of the substrate. The invention described in claim 5 is a light-emitting chip described in claim 2, in which the thyristor is stacked on the light-emitting element provided on the substrate, and the driving unit is stacked on a structure equivalent to the light-emitting element provided on the substrate. The invention described in claim 6 is a light-emitting chip described in claim 5, in which the light-emitting element, the thyristor, and the driving unit are composed of a semiconductor laminate in which multiple semiconductor layers of different conductivity types are stacked, and the separation unit is a groove provided in the semiconductor laminate or and a region in which insulating ions are injected into the semiconductor laminate. The invention described in claim 7 is a light-emitting chip described in claim 6, in which the light-emitting element and the structure have a diode structure in which a p-type semiconductor layer serving as an anode and an n-type semiconductor layer serving as a cathode are stacked, and the groove or the region into which the insulating ions are injected extends from the surface side of the substrate to at least the side of the p-type semiconductor layer and n-type semiconductor layer that constitute the diode structure that is farthest from the substrate side. The invention described in claim 8 is a light-emitting chip described in claim 6, in which the light-emitting element has a current confinement layer, which is a region that is oxidized and makes it difficult for current to flow, and the depth of the groove is deep enough to reach the current confinement layer. The invention described in claim 9 is a light-emitting chip described in claim 5, in which the reference potential is applied to the side of a diode structure farther from the substrate, in which a p-type semiconductor layer that serves as the anode of the structure and an n-type semiconductor layer that serves as the cathode are stacked. A tenth aspect of the present invention is the light-emitting chip according to the sixth aspect, wherein the groove and / or the region into which insulating ions are implanted is provided so as to surround the driving section. An eleventh aspect of the present invention is the light-emitting chip according to the second aspect, wherein the driving section sequentially shifts the on-states of the plurality of thyristors. The invention described in claim 12 is a light-emitting chip comprising a semiconductor substrate, a plurality of light-emitting elements provided on the surface side of the substrate, a plurality of thyristors stacked on the light-emitting elements and turning on to cause the light-emitting elements to emit light or increase the amount of light emitted by the light-emitting elements, a reference potential terminal provided on a structure equivalent to the light-emitting elements and to which a predetermined reference potential is supplied, and a separation portion that prevents a current path from being formed between the reference potential terminal and the light-emitting elements that passes through the side side of the substrate. The invention described in claim 13 is a light-emitting device comprising a light-emitting chip described in any one of claims 2 to 12, and a driver having one end set to ground potential and the other end connected to the substrate of the light-emitting chip, and transitioning to an on state at a predetermined timing to pass a current to the light-emitting element for light emission. The invention described in claim 14 is a measuring device comprising the light-emitting device described in claim 13 and an acquisition unit that acquires information about an object based on reflected light from the object that is light from the light-emitting device. [Effects of the Invention]

[0006] According to the inventions of claims 1, 2 and 12, erroneous lighting can be suppressed compared to a configuration in which leakage current from the light emitting element can flow to the reference potential terminal of the drive section. According to the invention of claim 3, the side surfaces of the light emitting chips are less susceptible to damage caused by dicing, compared to when the drive section is configured to extend to the outer periphery of the substrate. According to the invention of claim 4, damage caused by dicing is allowed. According to the invention of claim 5, the light emitting elements of the light emitting chip can be arranged at a higher density than when no thyristor is stacked on the light emitting elements. According to the sixth aspect of the present invention, the driving section and the dicing surface can be electrically isolated from each other. According to the seventh aspect of the present invention, the effect of electrically isolating the driving section and the dicing surface can be enhanced. According to the eighth aspect of the present invention, the isolation portion can be formed in the same process as that for forming the current blocking portion. According to the invention of claim 9, electrical isolation can be achieved by the pn junction. According to the tenth aspect of the present invention, the reference potential and the substrate potential can be separated more reliably than when the driving section is not enclosed. According to the invention of claim 11, lighting control of the light emitting elements becomes easier compared to when the ON states are not shifted in sequence. According to the invention of claim 13, the light emitting element can be operated at a higher speed than in high side driving. According to the invention of claim 14, there is provided a measuring device capable of performing three-dimensional measurement. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating an example of a measurement device to which the first embodiment is applied. [Figure 2]1 is an equivalent circuit diagram illustrating a light source device to which the first embodiment is applied. [Figure 3] 1(a) and 1(b) are an example of a planar layout diagram and a cross-sectional view of a light-emitting chip to which embodiment 1 is applied. 1(a) is an example of a planar layout diagram of the light-emitting chip, and 1(b) is an example of a cross-sectional view taken along line IIIB-IIIB in 1(a). [Figure 4] 1 is an example of an enlarged cross-sectional view of an island in which a VCSEL and a setting thyristor are stacked. [Figure 5] 1(a) and 1(b) are diagrams illustrating leakage current in a light source device to which embodiment 1 is applied, where 1(a) is a cross-sectional view when a light-emitting chip without a groove is used, and 1(b) is a cross-sectional view when a light-emitting chip with a groove is used. [Figure 6] 1(a) and 1(b) are an example of a planar layout diagram and a cross-sectional view of a light-emitting chip according to a modified example of embodiment 1. 1(a) is an example of a planar layout diagram of the light-emitting chip, and 1(b) is an example of a cross-sectional view taken along line VIB-VIB in 1(a). [Figure 7] FIG. 10 is an equivalent circuit diagram illustrating a light source device to which the second embodiment is applied. [Figure 8] FIG. 10 is an equivalent circuit diagram illustrating a light source device to which a third embodiment is applied. [Figure 9] 10(a) and 10(b) are diagrams illustrating the operation of the light-emitting chip to which Embodiment 3 is applied, where 10(a) is an equivalent circuit diagram and 10(b) is a cross-sectional view of a portion including a transfer thyristor and a coupling transistor. [Figure 10] 1(a) and 1(b) are an example of a planar layout diagram and a cross-sectional view of a light-emitting chip to which embodiment 3 is applied. 1(a) is an example of a planar layout diagram of the light-emitting chip, and 1(b) is an example of a cross-sectional view taken along line XB-XB of 1(a). [Figure 11] FIG. 10 is an equivalent circuit diagram illustrating a light source device to which a fourth embodiment is applied. [Figure 12] 10(a) and 10(b) are diagrams illustrating leakage current in a light source device to which embodiment 4 is applied, where 10(a) is a cross-sectional view when a light-emitting chip without a groove is used, and 10(b) is a cross-sectional view when a light-emitting chip with a groove is used. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Here, we will explain the case where a light source device 1 including a light emitting chip 10, which is an example of a light emitting device, is applied to a measurement device that measures the three-dimensional shape (hereinafter referred to as 3D shape) of an object to be measured.

[0009] [Embodiment 1] (Measuring device 100) FIG. 1 is a diagram showing an example of a measurement device 100 to which the first embodiment is applied. The measuring device 100 of the first embodiment measures the three-dimensional shape of an object to be measured. The measuring device 100 is a device that measures the 3D shape based on the so-called ToF (Time of Flight) method, which uses the time of flight of light. The measuring device 100 includes a light source device 1 including a light-emitting chip 10 and a control unit 110, and a three-dimensional sensor (hereinafter referred to as a 3D sensor) 5. The ToF method measures the time from when light is emitted from the light source device 1 to when the light is reflected by the object to be measured and received by the 3D sensor 5. Then, the distance to the object to be measured is calculated from the time acquired from the 3D sensor 5, and the 3D shape of the object to be measured is identified. Measuring a 3D shape may also be referred to as three-dimensional measurement, 3D measurement, or 3D sensing.

[0010] The light source device 1 emits light toward the object to be measured. The 3D sensor 5 acquires the light (reflected light) that is reflected by the object to be measured. The 3D sensor 5 outputs information (distance information) regarding the distance to the object to be measured based on the time from when the light is emitted to when the reflected light is received, measured using the ToF method. The measurement device 100 may also include a measurement control unit 200. The measurement control unit 200 is configured as a computer including a CPU, ROM, RAM, etc., and identifies the 3D shape of the object to be measured based on the distance information acquired from the 3D sensor 5. The measurement control unit 200 is an example of an acquisition unit.

[0011] Furthermore, the measurement device 100 can be applied to recognizing a measurement object from the identified 3D shape. For example, the measurement device 100 is installed in a portable information processing device and used to recognize the face of a user attempting to access the device. That is, the measurement device 100 acquires the 3D shape of the face of the accessing user, identifies whether or not the access is permitted, and permits use of the device (portable information processing device) only if it is recognized that the user is authorized to access the device. The measuring device 100 can also be applied to cases where the 3D shape of an object to be measured is continuously measured, such as in augmented reality (AR). The object to be measured is an example of an object, and the measurement device 100 is an example of a measurement device.

[0012] (Light source device 1) Fig. 2 is an equivalent circuit diagram illustrating the light source device 1 to which the embodiment 1 is applied. In Fig. 2, the right direction on the paper surface is the +x direction. The light source device 1 shown in FIG.

[0013] (control unit 110) The control unit 110 includes a transfer signal generating unit 120 , a lighting signal generating unit 140 , a reference potential supplying unit 160 , and a power supply potential supplying unit 170 . The transfer signal generating unit 120 generates a first transfer signal φ1 and a second transfer signal φ2 that sequentially switch the multiple transfer thyristors T in the transfer unit 12, which will be described later, to an ON state. The light-up signal generating unit 140 generates a light-up signal φI that supplies a current that lights up (emits light) multiple VCSELs, which will be described later. The reference potential supplying unit 160 supplies a reference potential Vst to the transfer unit 12. The power supply potential supplying unit 170 supplies a power supply potential Vga. The current that lights up (emits light) the VCSELs may be referred to as a light-up current.

[0014] (Light emitting chip 10) The light-emitting chip 10 includes a light-emitting unit 11 and a transfer unit 12. The light-emitting chip 10 includes a φ1 terminal, a φ2 terminal, a Vga terminal, a φI terminal, and a Vst terminal. The light-emitting chip 10 includes a Vsub terminal. The Vsub terminal is a back electrode 91 (see FIG. 3(b) described later) provided on the back surface of the substrate 80. In FIG. 2, the terminal of the element connected to the substrate 80 (which is the same as the Vsub terminal) is indicated by the symbol △.

[0015] The light-emitting unit 11 includes a vertical cavity surface-emitting laser (VCSEL). Hereinafter, the vertical cavity surface-emitting laser (VCSEL) will be referred to as VCSEL. In the example shown in FIG. 2, six VCSELs, VCSEL1 to VCSEL6, will be referred to as VCSELs when no distinction is made. The light-emitting unit 11 also includes six setting thyristors S1 to S6 (when no distinction is made, will be referred to as setting thyristor S). The anodes of the VCSELs and the cathodes of the setting thyristors S are connected. In other words, the setting thyristors S and VCSELs with the same number are connected in series. Additionally, as shown in FIG. 3(b) described later, the setting thyristors S are stacked on the VCSELs formed on the substrate 80. Hereinafter, the setting thyristors S may be referred to as thyristors. In the first embodiment, each VCSEL is an example of a light-emitting element, and each setting thyristor S is an example of a thyristor.

[0016] The transfer unit 12 includes six transfer thyristors T1 to T6 (referred to as transfer thyristors T when not distinguished), and six lower diodes UD1 to UD6 (referred to as lower diodes UD when not distinguished). The transfer thyristors T1 to T6 and the lower diodes UD1 to UD6 are connected in series with the transfer thyristor T and lower diode UD of the same number. Additionally, as shown in FIG. 3(b) to be described later, the transfer thyristor T is stacked on the lower diode UD formed on the substrate 80. As will be described later, the lower diodes UD1 to UD6 have an integrated structure without being separated. The lower diodes UD1 to UD6 do not operate. In FIG. 2, the lower diodes UD1 to UD6 are indicated by dashed lines.

[0017] The transfer unit 12 also pairs the transfer thyristors T1 to T6 in numerical order, and includes coupling diodes D1 to D5 (referred to as coupling diode D when no distinction is needed) between each pair. Furthermore, the transfer unit 12 includes power supply line resistors Rg1 to Rg6 (power supply line resistor Rg when no distinction is made).

[0018] The transfer unit 12 also includes one start diode SD. Furthermore, the transfer unit 12 includes current limiting resistors R1 and R2 that are provided to prevent excessive current from flowing through a first transfer signal line 72 to which a first transfer signal φ1 (described later) is supplied and a second transfer signal line 73 to which a second transfer signal φ2 (described later) is supplied.

[0019] The VCSEL1 to VCSEL6 and setting thyristors S1 to S6 of the light-emitting unit 11 and the transfer thyristors T1 to T6 of the transfer unit 12 are arranged in numerical order from one side (-x direction side, left side in FIG. 2) to the other side (+x direction side, right side in FIG. 2) in the light-emitting chip 10. Furthermore, the lower diodes UD1 to UD6, coupling diodes D1 to D5, and power supply line resistors Rg1 to Rg6 are arranged in numerical order from one side (-x direction side, left side in FIG. 2) to the other side (+x direction side, right side in FIG. 2) in the light-emitting chip 10.

[0020] In the first embodiment, the number of VCSELs and setting thyristors S in the light-emitting unit 11, the number of transfer thyristors T, lower diodes UD, and power line resistances Rg in the transfer unit 12 are six each. The number of coupling diodes D is five, which is one less than the number of transfer thyristors T. The numbers of VCSELs, setting thyristors S, transfer thyristors T, lower diodes UD, power line resistances Rg, and coupling diodes D are not limited to the above and may be any predetermined number. The number of transfer thyristors T may also be greater than the number of VCSELs.

[0021] The VCSEL, lower diode UD, coupling diode D, and start diode SD are two-terminal semiconductor elements with an anode terminal (anode) and a cathode terminal (cathode). The thyristors (setting thyristor S, transfer thyristor T) are three-terminal semiconductor elements with an anode terminal (anode), a gate terminal (gate), and a cathode terminal (cathode). Note that in the following, terminals may be abbreviated and written in parentheses.

[0022] The light-emitting chip 10 of the first embodiment is made of, for example, a III-V compound semiconductor such as GaAs, AlGaAs, or AlAs. The light-emitting chip 10 is a so-called monolithic integrated circuit made of a semiconductor laminate in which multiple semiconductor layers of different conductivity types are stacked by epitaxial growth on a semiconductor substrate 80. In addition, the light-emitting chip 10 is obtained by dicing a semiconductor wafer on which multiple light-emitting chips 10 are collectively manufactured.

[0023] Next, the electrical connections of the elements in the light-emitting chip 10 will be described. The cathodes of the VCSEL and the lower diode UD are connected (common cathode) to the substrate 80. A substrate potential Vsub is supplied to these cathodes via a back electrode 91 (see FIG. 3) which is a Vsub terminal provided on the back surface of the substrate 80. The anode of each of the VCSELs is connected to the cathode of a setting thyristor S.

[0024] The anodes of the lower diodes UD are connected to the cathodes of the transfer thyristors T. The cathodes of the transfer thyristors T (the same as the anodes of the lower diodes UD) are connected to a reference potential line 74. The reference potential line 74 is connected to a Vst terminal. A reference potential Vst is supplied to this Vst terminal from a reference potential supply unit 160. The Vst terminal may be a reference potential terminal 340 shown in FIGS. 3(a) and 3(b) to be described later. The reference potential terminal 340 is a terminal that supplies a reference potential to the transfer unit 12.

[0025] Along the arrangement of the transfer thyristors T, the anodes of the odd-numbered transfer thyristors T1, T3, and T5 are connected to a first transfer signal line 72. The first transfer signal line 72 is connected to a φ1 terminal via a current-limiting resistor R1. A first transfer signal φ1 is supplied to this φ1 terminal from the transfer signal generating unit 120 of the control unit 110. Meanwhile, along the arrangement of the transfer thyristors T, the anodes of the even-numbered transfer thyristors T2, T4, and T6 are connected to a second transfer signal line 73. The second transfer signal line 73 is connected to a φ2 terminal via a current-limiting resistor R2. A second transfer signal φ2 is supplied to this φ2 terminal from the transfer signal generating unit 120 of the control unit 110.

[0026] The anodes of the setting thyristors S are connected to a light-up signal line 75. The light-up signal line 75 is connected to a φI terminal. A light-up signal φI is supplied to the φI terminal from the light-up signal generating unit 140 of the control unit 110 via a current limiting resistor RI provided outside the light-emitting chip 10. The light-up signal φI supplies a current to the VCSEL for lighting.

[0027] The gates Gt1 to Gt6 (written as gate Gt when not distinguished) of the transfer thyristors T1 to T6 are connected one-to-one to the gates Gs1 to Gs6 (written as gate Gs when not distinguished) of the setting thyristors S1 to S6 having the same numbers. Therefore, the gates Gt1 to Gt6 and the gates Gs1 to Gs6 having the same numbers are electrically at the same potential. Therefore, for example, the gate is written as gate Gt1 (gate Gs1) to indicate that the potential is the same.

[0028] Coupling diodes D1 to D5 are connected between pairs of gates Gt1 to Gt6 of the transfer thyristors T1 to T6 in numerical order. That is, the coupling diodes D1 to D5 are directly connected so that they are sandwiched between the gates Gt1 to Gt6. The coupling diode D1 is connected in the direction in which current flows from the gate Gt2 to the gate Gt1. The same applies to the other coupling diodes D2 to D5.

[0029] The gates Gt (gates Gs) of the transfer thyristors T are connected to a power supply line 71 via power supply line resistors Rg provided corresponding to the respective transfer thyristors T. The power supply line 71 is connected to a Vga terminal. A power supply potential Vga is supplied to the Vga terminal from a power supply potential supply unit 170 of the control unit 110.

[0030] The gate Gt1 of the transfer thyristor T is connected to the anode of the start diode SD. On the other hand, the cathode of the start diode SD is connected to the second transfer signal line 73.

[0031] 3(a) and 3(b) are an example of a planar layout diagram and a cross-sectional view of the light-emitting chip 10 to which embodiment 1 is applied. Fig. 3(a) is an example of a planar layout diagram of the light-emitting chip 10, and Fig. 3(b) is an example of a cross-sectional view taken along line IIIB-IIIB in Fig. 3(a). 3(a) and 3(b), a protective layer (protective layer 90 in FIG. 4) and a light-shielding layer (light-shielding layer 95 in FIG. 4) are omitted. Also, in FIG. 3(b), the connection wirings shown in FIG. 3(a) are omitted. 3(a) shows VCSELs 1 to 4, setting thyristors S1 to S4, and transfer thyristors T1 to T4 for the VCSELs 1 to 6, setting thyristors S1 to S6, and transfer thyristors T1 to T6 shown in Fig. 2. Also, for the lower diodes UD1 to UD6, coupling diodes D1 to D5, and power line resistances Rg1 to Rg6, it shows lower diodes UD1 to UD4, coupling diodes D1 to D4, and power line resistances Rg1 to Rg4. FIG. 3(b) shows a cross section of the setting thyristor S1, VCSEL1, transfer thyristor T1, lower diode UD1, coupling diode D1, and power line resistance Rg1 shown in FIG.

[0032] First, the cross-sectional structure of the light-emitting chip 10 will be described with reference to FIG. The light emitting chip 10 includes an n-type cathode layer 81, a light emitting layer 82, and a p-type anode layer 83, which are sequentially provided on an n-type substrate 80 (substrate 80) and constitute the VCSEL and the lower diode UD. The n-type cathode layer 81 and the p-type anode layer 83 are configured by a distributed Bragg reflector (DBR) (hereinafter referred to as a DBR layer) in which multiple semiconductor layers having refractive index differences are stacked. Therefore, hereinafter, the n-type cathode layer 81 will be referred to as an n-cathode (DBR) layer 81. Similarly, the p-type anode layer 83 will be referred to as a p-anode (DBR) layer 83.

[0033] In the light emitting chip 10, a tunnel junction (tunnel diode) layer 84 (tunnel junction layer 84) is provided on the p anode (DBR) layer 83. Furthermore, the light-emitting chip 10 has an n-type cathode layer 85 (n-cathode layer 85), a p-type gate layer 86 (p-gate layer 86), an n-type gate layer 87 (n-gate layer 87), and a p-type anode layer 88 (p-anode layer 88) formed in this order on the tunnel junction layer 84, which constitute the setting thyristor S, the transfer thyristor T, the coupling diode D, and the power line resistance Rg. In the following, the notation in parentheses will be used. The same applies to other cases.

[0034] As shown in Figures 3(a) and 3(b), elements such as the VCSEL, lower diode UD, setting thyristor S, transfer thyristor T, and coupling diode D are composed of multiple islands separated by removing portions of each of the above layers through etching. Note that an island is sometimes referred to as a mesa, and the etching that forms the island (mesa) is sometimes referred to as mesa etching. In the light-emitting chip 10, these islands are connected to wiring such as a power supply line 71, a first transfer signal line 72, a second transfer signal line 73, a reference potential line 74, and a light-up signal line 75 via through-holes (indicated by ● in FIG. 3(a)) provided in a protective layer (protective layer 90 in FIG. 4, which will be described later). In the following explanation, the protective layer and the through-holes will not be described.

[0035] As shown in FIG. 3(b), a back surface electrode 91 that serves as a Vsub terminal is provided on the back surface of the substrate 80.

[0036] Here, the notation of the n-cathode (DBR) layer 81 and the p-anode (DBR) layer 83 corresponds to their functions when configuring the VCSEL and the lower diode UD. That is, the n-cathode (DBR) layer 81 functions as a cathode, and the p-anode (DBR) layer 83 functions as an anode.

[0037] The notations of the n-cathode layer 85, p-gate layer 86, n-gate layer 87, and p-anode layer 88 correspond to the functions (operations) when configuring the setting thyristor S and the transfer thyristor T. That is, the n-cathode layer 85 functions as a cathode, the p-gate layer 86 and n-gate layer 87 function as gates, and the p-anode layer 88 functions as an anode. When the above layers constitute the coupling diode D and the power supply line resistance Rg, they have different functions as will be described later.

[0038] As will be described below, the multiple islands included in the light-emitting chip 10 include those that do not include some of the n-cathode (DBR) layer 81, the light-emitting layer 82, the p-anode (DBR) layer 83, the tunnel junction layer 84, the n-cathode layer 85, the p-gate layer 86, the n-gate layer 87, and the p-anode layer 88. For example, islands 301 and 302, which will be described later, do not include part of the p-anode layer 88.

[0039] The substrate 80, the back electrode 91, and the n-cathode (DBR) layer 81 are at the same potential, and may be collectively referred to as the substrate 80. In this specification, the substrate 80 may include the back electrode 91 and the n-cathode (DBR) layer 81.

[0040] Next, an example of a planar layout of the light-emitting chip 10 will be described with reference to FIG. The island 301 is provided with a VCSEL1 and a setting thyristor S1. The island 302 is provided with a transfer thyristor T1 and a coupling diode D1. The island 303 is provided with a power line resistor Rg1. The island 304 is provided with a start diode SD. The island 305 is provided with a current limiting resistor R1, and the island 306 is provided with a current limiting resistor R2.

[0041] The light-emitting chip 10 has a plurality of islands formed in parallel, each of which is similar to the islands 301, 302, and 303. These islands are provided with VCSEL2 to VCSEL6, setting thyristors S2 to S6, lower diodes UD2 to UD6, transfer thyristors T2 to T6, coupling diodes D2 to D5, and the like, similar to the islands 301, 302, and 303. Islands 302 to 306, and islands similar to islands 302 and 303, are provided on island 300.

[0042] Here, the islands 300 to 306 will be described in detail with reference to FIGS. 3(a) and 3(b). 3(b), the island 301 is separated from other islands by removing the p anode layer 88, n gate layer 87, p gate layer 86, n cathode layer 85, tunnel junction layer 84, p anode (DBR) layer 83, and light-emitting layer 82 in the thickness direction by mesa etching. Note that it is sufficient that only a portion of the light-emitting layer 82 is removed in the thickness direction. Furthermore, the n cathode (DBR) layer 81 may be partially or entirely removed. The VCSEL1 provided in the island 301 is composed of an n-cathode (DBR) layer 81, a light-emitting layer 82, and a p-anode (DBR) layer 83. The setting thyristor S is composed of an n-cathode layer 85, a p-gate layer 86, an n-gate layer 87, and a p-anode layer 88 stacked via a tunnel junction layer 84 stacked on the p-anode (DBR) layer 83 of the VCSEL1.

[0043] As shown in black in Figure 3(b), the p anode (DBR) layer 83 of the VCSEL includes a current confinement layer (current confinement layer 83a in Figure 4, which will be described later) that confines the current. The current confinement layer forms a current blocking portion β through which current does not easily flow, as a result of part of the semiconductor layer that constitutes the p anode (DBR) layer 83 being exposed by mesa etching and oxidized from the exposed portion. On the other hand, the central portion of the semiconductor layer that constitutes the p anode (DBR) layer 83, where part of the semiconductor layer has not been oxidized, forms a current passing portion α through which current can easily flow. By providing the current blocking portion β, the power consumed by non-radiative recombination is reduced. By providing the current blocking portion β, it is possible to reduce power consumption and improve the light extraction efficiency. The light extraction efficiency is the amount of light that can be extracted per unit of power. In order to expose the current confinement layer, the depth of the mesa etching that separates the islands 301 is preferably such that a portion of the light emitting layer 82 in the thickness direction is removed. In the island 301, the setting thyristor S1 (the p-anode layer 88, the n-gate layer 87, the p-gate layer 86, the n-cathode layer 85, and the tunnel junction 84) in the light-emitting portion may be removed. In this case, the setting thyristor S1 has a cylindrical shape. This prevents the light emitted by the VCSEL 1 from being absorbed by the setting thyristor S1, resulting in a decrease in the amount of light.

[0044] 3(b), the island 301 will be described. The setting thyristor S1 has a p-type ohmic electrode 321 (p ohmic electrode 321) provided on a region 311 of the p anode layer 88 as its anode terminal. Also, an n-type ohmic electrode 331 (n ohmic electrode 331) provided on the n gate layer 87 exposed by removing the p anode layer 88 as its gate Gs1 terminal.

[0045] Island 300 is separated from island 301 and islands similar to island 301 by removing p anode layer 88, n gate layer 87, p gate layer 86, n cathode layer 85, tunnel junction layer 84, p anode (DBR) layer 83, and light emitting layer 82 by mesa etching in the thickness direction. Islands 302 to 306, and islands similar to islands 302 and 303, are provided in island 300. Islands 302 to 306 will be described below.

[0046] The islands 302 to 306 are separated from the island 300 by removing the p-anode layer 88, n-gate layer 87, p-gate layer 86, n-cathode layer 85, and tunnel junction layer 84 by mesa etching. In the island 300, the p-anode (DBR) layer 83, light-emitting layer 82, and n-cathode (DBR) layer 81 remain below the islands 302 to 306. The remaining p-anode (DBR) layer 83, light-emitting layer 82, and n-cathode (DBR) layer 81 of the island 300 constitute the lower diodes UD1 to UD6. In other words, the lower diodes UD1 to UD6 are not separated but integrated. The lower diodes UD1 to UD6 are composed of the n-cathode (DBR) layer 81, light-emitting layer 82, and p-anode (DBR) layer 83, similar to the VCSEL light-emitting element. Therefore, the lower diode UD is a structure in this embodiment and is equivalent to a light-emitting element. The VCSEL and the lower diode UD have a diode structure with a pn junction.

[0047] In the mesa etching of the islands 302 to 306, the n-cathode layer 85 and the tunnel junction layer 84 do not have to be removed. The p-anode (DBR) layer 83 and the n-cathode layer 85 are stacked with the tunnel junction layer 84 interposed therebetween. Therefore, the p-anode (DBR) layer 83 and the n-cathode layer 85 have the same potential, so the tunnel junction layer 84 and the n-cathode layer 85 do not have to be removed and can be left as they are. In the following description, it is assumed that the p-anode (DBR) layer 83 is exposed.

[0048] The transfer thyristor T1 provided in the island 302 is composed of an n-cathode layer 85, a p-gate layer 86, an n-gate layer 87, and a p-anode layer 88, similar to the setting thyristor S1. A p-ohmic electrode 323 provided on region 313 of p-anode layer 88 serves as an anode terminal. Furthermore, an n-ohmic electrode 332 provided on n-gate layer 87 exposed by removing p-anode layer 88 serves as a terminal of gate Gt1. Similarly, coupling diode D1 provided in island 302 is composed of an n-gate layer 87 and a p-anode layer 88. A p-ohmic electrode 324 provided on region 314 of p-anode layer 88 serves as the anode terminal. Furthermore, an n-ohmic electrode 332 provided on the n-gate layer 87 exposed by removing p-anode layer 88 serves as the cathode terminal. In this case, the cathode terminal of coupling diode D is the same as the terminal of gate Gt1.

[0049] The power supply line resistance Rg1 provided in the island 303 is composed of the p anode layer 88. That is, the power supply line resistance Rg1 is provided with the p anode layer 88 between the p ohmic electrode 333 and the p ohmic electrode 334 provided on the p anode layer 88 as a resistor.

[0050] Although not shown in FIG. 3(b), the start diode SD provided in the island 304 is composed of an n-gate layer 87 and a p-anode layer 88. That is, the start diode SD has a p-ohmic electrode 325 provided on a region 315 of the p-anode layer 88 as its anode terminal. Furthermore, the start diode SD has an n-ohmic electrode 335 provided on the n-gate layer 87 exposed by removing the p-anode layer 88 as its cathode terminal (see FIG. 3(a)). The current limiting resistor R1 provided in the island 305 and the current limiting resistor R2 provided in the island 306 are provided in the same manner as the power line resistor Rg1 provided in the island 303. Each resistor uses the p anode layer 88 between two p ohmic electrodes (no reference numeral) as a resistor (see FIG. 3(a)).

[0051] An island 302 provided with a transfer thyristor T1 and a coupling diode D1, an island 303 provided with a power line resistance Rg1, an island similar to the islands 302 and 303, an island 304 provided with a start diode SD, and islands 305 and 306 provided with current limiting resistors R1 and R2 constitute a transfer unit 12. The transfer unit 12 is provided in the island 300.

[0052] The island 300 has a groove 350 formed to surround the islands 302 to 306 and islands similar to the islands 302 and 303. The groove 350 is formed by removing the p-anode (DBR) layer 83 by mesa etching in a portion of the island 300 where the p-anode (DBR) layer 83 is exposed. The groove 350 may be formed by removing at least the p-anode (DBR) layer 83. However, the groove 350 may be formed so as to reach the light-emitting layer 82 below the p-anode (DBR) layer 83, or may be formed so as to reach the n-cathode (DBR) layer 81. In other words, the groove 350 may have the same depth as the mesa etching performed to separate the islands 301. Therefore, the groove 350 may be formed during the mesa etching performed to separate the islands 301. In other words, the mesa etching performed to separate the islands 301 and the mesa etching performed to form the groove 350 can be performed in the same process. This eliminates the need for a separate mesa etching process to form the groove 350. Additionally, the groove 350 extends from at least the surface side of the substrate 80 to the side (e.g., the p-anode (DBR) layer 83) of the p-type semiconductor layer (e.g., the p-anode (DBR) layer 83) and the n-type semiconductor layer (e.g., the n-cathode (DBR) layer 81) that constitute the diode structure, farther from the substrate 80. This allows electrical isolation by a pn junction between the p-type semiconductor layer and the n-type semiconductor layer that constitute the diode structure. The groove 350 will be described later.

[0053] Next, the connection relationships between the elements will be explained with reference to FIG. The light-on signal line 75 has a trunk 75a and multiple branch portions 75b. The trunk 75a is provided so as to extend in the column direction of the setting thyristors S / VCSEL. The branch portions 75b branch off from the trunk 75a and are connected to the p-ohmic electrode 321, which is the anode terminal of the setting thyristor S1 provided on the island 301. The anode terminals of the other setting thyristors S are connected in the same manner. The light-up signal line 75 is connected to the φI terminal.

[0054] The first transfer signal line 72 is connected to the p-ohmic electrode 323, which is the anode terminal of the transfer thyristor T1 provided in the island 302. The first transfer signal line 72 is connected to the anode terminals of other odd-numbered transfer thyristors T provided in islands similar to the island 302. The first transfer signal line 72 is connected to the φ1 terminal via a current limiting resistor R1 provided in the island 305. On the other hand, the second transfer signal line 73 is connected to a p-ohmic electrode (without reference numeral) which is the anode terminal of the even-numbered transfer thyristor T provided in the island without reference numeral. The second transfer signal line 73 is connected to the φ2 terminal via a current limiting resistor R2 provided in the island 306.

[0055] The power supply line 71 is connected to a p-ohmic electrode 334, which is one terminal of a power supply line resistor Rg1 provided on the island 303. One terminal of another power supply line resistor Rg is also connected to the power supply line 71. The power supply line 71 is connected to the Vga terminal.

[0056] The n-ohmic electrode 331 (gate terminal Gs1) of the setting thyristor S1 provided on the island 301 is connected to the n-ohmic electrode 332 (gate terminal Gt1) of the island 302 by a connection wire .

[0057] The n-ohmic electrode 332 (gate terminal Gt1) is connected to the p-ohmic electrode 333 (the other terminal of the power supply line resistance Rg1) of the island 303 by a connection wire 77. A p-ohmic electrode 324 (anode terminal of the coupling diode D1) provided on the island 302 is connected by a connection wiring 79 to an n-ohmic electrode (no reference numeral) which is the gate terminal Gt2 of the adjacent transfer thyristor T2. Although the explanation is omitted here, the same applies to other VCSELs, setting thyristors S, transfer thyristors T, coupling diodes D, etc.

[0058] The n-ohmic electrode 332 (gate terminal Gt1) of the island 302 is connected to the p-ohmic electrode 325 (cathode terminal of the start diode SD) provided on the island 304 by a connection wiring 78. The n-ohmic electrode 335 (cathode terminal of the start diode SD) is connected to a second transfer signal line 73.

[0059] In the island 300, a p-ohmic electrode 340 is provided on a p-anode (DBR) layer 83 surrounded by a groove 350. The p-ohmic electrode 340 is connected to a reference potential line 74. The reference potential line 74 is connected to a Vst terminal. A reference potential Vst is supplied to the Vst terminal. Note that the reference potential line 74 and the Vst terminal may be omitted, and the p-ohmic electrode 340 may serve as the Vst terminal or the reference potential terminal 340. Hereinafter, the Vst terminal will be referred to as the reference potential terminal 340. The reference potential terminal 340 is an example of a reference potential terminal. The p-anode (DBR) layer 83 provided with the reference potential terminal 340 is provided continuously below the transfer unit 12. The p-anode (DBR) layer 83 is set to a potential (reference potential Vst) that serves as a reference for the operation of the transfer unit 12 by the reference potential terminal 340. In other words, the transfer section 12 is provided in an area surrounded by the groove 350 and operates based on the reference potential Vst supplied to the reference potential terminal 340 . If the n-cathode layer 85 and the tunnel junction layer 84 are not removed during mesa etching of the islands 302 to 306, the p-ohmic electrode 340 may be used as an n-ohmic electrode.

[0060] (Stacked structure of setting thyristor S and VCSEL) FIG. 4 is an example of an enlarged cross-sectional view of an island 301 in which a setting thyristor S and a VCSEL are stacked, and is a cross-sectional view of the light-emitting chip 10 taken along line IV-IV in FIG. 3(a). Note that FIG. 4 corresponds to a cross-sectional view of the island in which a setting thyristor S and a VCSEL are stacked, viewed from the -y direction in FIG. 3(a). FIG. 4 also shows an island 301 in which a VCSEL1 and a setting thyristor S1 are stacked, and an island (without reference numerals) in which a VCSEL2 and a setting thyristor S2 are stacked. On the right side of FIG. 4, VCSEL1 and VCSEL2 are not distinguished from each other and are referred to as VCSEL. Similarly, the setting thyristor S1 and the setting thyristor S2 are not distinguished from each other and are referred to as setting thyristor S. As described above, the setting thyristor S is stacked on the VCSEL via the tunnel junction layer 84. That is, the setting thyristor S and the VCSEL are connected in series. Note that "on the VCSEL" does not only refer to a state in which the VCSEL is in direct contact with the VCSEL, but also includes a state in which the VCSEL is positioned above the VCSEL without being in direct contact with the VCSEL. The same applies to similar expressions such as "on the substrate."

[0061] As shown in FIG. 4, the VCSEL is composed of a semiconductor laminate in which an n-cathode (DBR) layer 81, a light-emitting layer 82, and a p-anode (DBR) layer 83 are epitaxially grown in this order on an n-type substrate 80. The n-cathode (DBR) layer 81 and the p-anode (DBR) layer 83 are DBR layers formed by alternately stacking multiple high-refractive-index layers and low-refractive-index layers, and are configured to reflect light emitted from the VCSEL.

[0062] The p anode (DBR) layer 83 also includes a current confinement layer 83a. In this example, the current confinement layer 83a is provided on the side of the p anode (DBR) layer 83 facing the light-emitting layer 82. The current confinement layer 83a is composed of a current passing portion α and a current blocking portion β. As shown in FIG. 4, the current passing portion α is provided in the center of the VCSEL, and the current blocking portion β is provided in the peripheral portion of the VCSEL. In other words, the portion of the current confinement layer 83a indicated by the thick solid line is the current blocking portion β, and the portion sandwiched between the two thick solid lines where the current confinement layer 83a is not provided is the current passing portion α. The current blocking portion β does not need to completely block the flow of current; it is sufficient if it can concentrate the current in the current passing portion α. In other words, it is sufficient if the current is less likely to flow through the current blocking portion β than through the current passing portion α. The current confinement layer 83a may be provided in the n-cathode (DBR) layer 81. The mesa etching for separating the islands 301 is performed to a depth that exposes the side surfaces of the current confinement layer 83 a. When the grooves 350 are formed simultaneously with the mesa etching for separating the islands 301, the grooves 350 are also formed to a depth that exposes the side surfaces of the current confinement layer 83 a.

[0063] The light-emitting layer 82 has a quantum well structure in which well layers and barrier layers are alternately stacked. The light-emitting layer 82 may be an intrinsic (i) type layer (i layer) to which no impurities are added. The light-emitting layer 82 may also have a structure other than a quantum well structure, such as a quantum wire or a quantum dot.

[0064] The tunnel junction layer 84 is an n-type layer doped with a high concentration of n-type impurities (dopants). ++ layer and p-type impurity-doped p ++ The tunnel junction layer 84 is a junction between the p-anode (DBR) layer 83 of the VCSEL and the setting thyristor S, and current flows due to the tunnel effect even when reverse bias is applied. The tunnel junction layer 84 prevents the p-anode (DBR) layer 83 of the VCSEL and the setting thyristor S from becoming reverse biased and making it difficult for current to flow. Current flows due to the tunnel effect even when reverse bias is applied.

[0065] The setting thyristor S is composed of an n-cathode layer 85, a p-gate layer 86, an n-gate layer 87, and a p-anode layer 88, which are stacked on a tunnel junction layer 84. That is, it has a four-layer pnpn structure.

[0066] These semiconductor layers are formed by stacking p-type semiconductor layers (p-gate layer 86, p-anode layer 88) and n-type semiconductor layers (n-cathode layer 85, n-gate layer 87) made of, for example, GaAs, AlGaAs, or AlAs on the substrate 80. The semiconductor layers are stacked by, for example, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or the like. Hereinafter, the stacked semiconductor layers will be referred to as a semiconductor stack. The structures of the substrate 80, the n-cathode (DBR) layer 81, the light-emitting layer 82, and the p-anode (DBR) layer 83 that constitute the VCSEL, and the n-cathode layer 85, the p-gate layer 86, the n-gate layer 87, and the p-anode layer 88 that constitute the setting thyristor S will be described in more detail later.

[0067] The p ohmic electrode 321 is made of Au containing Zn (AuZn), which can easily make ohmic contact with a p-type semiconductor layer such as the p anode layer 88, for example. The n-ohmic electrode 331 (see FIG. 3(b)) is made of Au containing Ge (AuGe), which can easily make ohmic contact with an n-type semiconductor layer such as the n-gate layer 87, for example. The rear electrode 91 is made of, for example, AuGe, similar to the n-ohmic electrode 331 .

[0068] In the above, the n-ohmic electrode 331 is provided on the n-gate layer 87 to serve as the gate Gs of the setting thyristor S, but the p-ohmic electrode may be provided on the p-gate layer 86 to serve as the gate Gs of the setting thyristor S.

[0069] Furthermore, a protective layer 90 made of a light-transmitting insulating material is provided so as to cover the surface and side surfaces of the island on the light-emitting chip 10. The protective layer 90 is made of, for example, SiO2, SiON, SiN, or the like. Furthermore, the light-emitting chip 10 is provided with a light-shielding layer 95 for preventing light emitted from the setting thyristor S from leaking out from between the islands onto the surface of the light-emitting chip 10. The light-shielding layer 95 may be the above-mentioned wiring.

[0070] (thyristor) Next, the basic operation of the thyristors (transfer thyristor T, setting thyristor S) will be explained. As mentioned above, the thyristor is a semiconductor element having a pnpn structure in which an n-cathode layer 85, a p-gate layer 86, an n-gate layer 87, and a p-anode layer 88 are stacked, and having three terminals: an anode terminal (anode), a cathode terminal (cathode), and a gate terminal (gate). Here, the forward voltage (built-in potential) Vd of the pn junction formed by a p-type semiconductor layer and an n-type semiconductor layer will be explained as 1.5 V as an example.

[0071] In the following, as an example, the substrate potential Vsub supplied to the rear electrode 91 (see FIG. 3) which is the Vsub terminal and the reference potential Vst supplied to the Vst terminal (reference potential terminal 340) will be described as a low-level potential (hereinafter referred to as "L") of 0V, and the power supply potential Vga supplied to the Vga terminal will be described as a high-level potential (hereinafter referred to as "H") of 5V. Therefore, "H" (5V) and "L" (0V) may be used. "L" (0V) is the ground potential GND. The ground potential GND will be described as the ground potential GND (0V).

[0072] First, we will explain the operation of a single thyristor. Here, we assume that the cathode of the thyristor is 0V. A thyristor in the off state, with no current flowing between the anode and cathode, transitions to the on state (turns on) when a potential higher than the threshold voltage is applied to the anode. Here, the threshold voltage of a thyristor is the gate potential plus the forward voltage Vd (1.5V) of the pn junction. If the gate potential is 1.5V, the thyristor will turn on when the anode potential exceeds 3V. When the thyristor is turned on, the gate of the thyristor will have a potential close to the potential of the cathode terminal. Here, the cathode is 0V, so the gate will be at 0V. Also, the anode of the thyristor in the on state will have a potential close to the potential of the cathode plus the forward voltage Vd (1.5V) of the pn junction. Here, the cathode is 0V, so the anode of the thyristor in the on state will have a potential close to 1.5V. The anode potential is set in relation to the power supply that supplies current to the thyristor in the on state.

[0073] A thyristor in the ON state transitions to the OFF state (turns off) when the anode potential becomes lower than the potential required to maintain the ON state (a potential close to the above 1.5 V). On the other hand, if a potential higher than the potential required to maintain the on state is continuously applied to the anode of a thyristor in the on state and a current (maintenance current) sufficient to maintain the on state is supplied, the thyristor will maintain the on state.

[0074] Next, we will explain the operation when the setting thyristor S and the VCSEL are stacked. Here, the substrate potential Vsub is set to "L" (0V), so the cathode of the VCSEL is 0V. As mentioned above, if the potential of the light-up signal φI is greater than the threshold voltage, the setting thyristor S turns on. At this time, because the VCSEL is connected in series, the anode of the setting thyristor S is higher by the forward voltage Vd (1.5 V) of the VCSEL, resulting in a potential close to 3.0 V. The difference between this anode potential and the potential of the light-up signal φI is applied to the current-limiting resistor RI (see Figure 2), and a current equivalent to the voltage drop across the current-limiting resistor RI flows through the turned-on setting thyristor S and the VCSEL, causing the VCSEL to light up. On the other hand, if the potential of the light-up signal φI is smaller than the threshold voltage, the setting thyristor S does not turn on and remains off. A thyristor in the on state can be maintained in the on state by supplying a current equal to or greater than the current required to maintain the on state (holding current).On the other hand, a thyristor will transition to the off state (turn off) by supplying a current equal to or less than the holding current.

[0075] The voltages shown above are just examples, and should be changed depending on the emission wavelength and light intensity of the VCSEL. In that case, the potential ("H") of the light-up signal φI should be adjusted. In the above, the setting thyristor S is described as controlling whether the VCSEL is turned on or off (lighting control), but the setting thyristor S may also be used as an element that increases the amount of light emitted by a VCSEL that is already turned on by turning on the setting thyristor S.

[0076] (Operation of light source device 1) Next, the operation of the light source device 1 will be described. The first transfer signal φ1 transmitted to the φ1 terminal (see FIGS. 2 and 3) and the second transfer signal φ2 transmitted to the φ2 terminal (see FIGS. 2 and 3) are signals having two potentials: "H" (5 V) and "L" (0 V). The waveforms of the first transfer signal φ1 and the second transfer signal φ2 are repeated every two consecutive periods T (for example, periods T(1) and T(2)). A set of transfer signals, the first transfer signal φ1 and the second transfer signal φ2, transitions the on-state of the transfer thyristor T in numerical order, thereby designating the VCSEL with the same number as the on-state transfer thyristor T as the target for lighting control. As described above, when the transfer thyristor T is turned on, the gate Gt of the transfer thyristor T becomes 0 V. Then, the gate Gs of the setting thyristor S, which is connected to the gate Gt of the transfer thyristor T, becomes 0 V. In other words, the threshold voltage of the setting thyristor S becomes 1.5 V. Note that the voltage of the gate Gt of the transfer thyristor T to the right of the on-state transfer thyristor T increases by the voltage drop across the coupling diode D and the parasitic resistance (not shown) connected in series with the coupling diode D, to 1.8 V. In other words, the threshold voltage of the setting thyristor S to the right becomes 3.3 V. The setting thyristor S to the right of that has a higher threshold voltage. Furthermore, the gate Gt on the left side of the on-state transfer thyristor T is 5 V, and the threshold voltage is 6.5 V. In this way, the threshold voltages of all setting thyristors S other than those with the same number as the on-state transfer thyristor T are 3.3 V or higher.

[0077] The light-up signal φI supplied to the φI terminal (see FIGS. 2 and 3) is a signal having two potentials: "H" (5V) and "L" (0V). When the light-up signal φI transitions from "L" to "H," the setting thyristor S corresponding to the VCSEL designated by the transfer signal as the target for lighting is turned on, and the VCSEL is lighted. When this setting thyristor S is turned on, the anode voltage becomes 3 V as described above, and the voltage of the light-up signal line 75 also becomes 3 V. Therefore, setting thyristors S other than the setting thyristor S corresponding to the designated VCSEL are not turned on.

[0078] That is, when the transfer thyristor T is turned on, it designates the VCSEL that is the target of lighting control, and the lighting signal φI of “H” (5 V) turns on the setting thyristor S connected in series to the VCSEL that is the target of lighting control, lighting the VCSEL. That is, in the light-emitting chip 10, the on state of the transfer thyristor T is transferred, causing the VCSELs to light up sequentially. When the transfer thyristor T is turned on, the gate Gt changes, and the potential of the gate Gs of the setting thyristor S connected to the gate Gt changes, turning on the setting thyristor S. Here, the signal that is sent from the gate Gt of the transfer thyristor T to the gate Gs of the setting thyristor S and turns on the setting thyristor S is referred to as an on signal. By shifting the on state sequentially, lighting control of the VCSELs becomes easier. The lighting signal φI at "L" (0V) maintains the setting thyristor S in the off state and also maintains the VCSEL in the non-lighted state. That is, the lighting signal φI sets the lighting / non-lighting of the VCSEL.

[0079] The light source device 1 of the first embodiment includes a plurality of elements (transfer thyristors T1 to T6, setting thyristors S1 to S6, and VCSEL1 to VCSEL6), and among the plurality of elements, elements that are turned on are successively switched to the on state. Specifically, in the light source device 1 of the first embodiment, the control unit 110 (see FIG. 2) controls the lighting of the plurality of transfer thyristors T1 to T6 in the transfer unit 12 of the light-emitting chip 10, and the plurality of transfer thyristors T1 to T6 are individually switched to the on state. When the transfer thyristors T1 to T6 are switched to the on state, a VCSEL that is the target of the lighting control is designated, and the plurality of setting thyristors S1 to S6 in the light-emitting unit 11 are individually switched to the on state. When each setting thyristor S is switched to the on state, the VCSEL corresponding to that setting thyristor S is individually lit. In the light source device 1 of the first embodiment, the transfer unit 12 of the light-emitting chip 10 is an example of a drive unit that individually drives the plurality of setting thyristors S to switch them to the on state. In the light-emitting chip 10 of the first embodiment, the portion of the light-emitting layer 82 of each VCSEL that actually emits light when supplied with current is the light-emitting region of each VCSEL.

[0080] In the light-emitting chip 10 of the first embodiment, when the setting thyristor S receives an ON signal, it is in a state where a current can be supplied to the corresponding VCSEL. Then, when the setting thyristor S is turned ON and a current of a magnitude necessary for the VCSEL to emit light is supplied, the VCSEL lights up. Depending on the configuration of the light-emitting chip 10 and the control by the control unit 110, after an ON signal is supplied to the setting thyristor S and a current is able to be supplied to the corresponding VCSEL, the ON signal to the setting thyristor S may be stopped while the VCSEL remains in a state where it can emit light, after which the setting thyristor S may be turned ON and a current of a magnitude necessary for the VCSEL to emit light may be supplied to the VCSEL, thereby causing the VCSEL to emit light. In the first embodiment, "a thyristor (setting thyristor S) turns on to cause a light-emitting element (VCSEL) to emit light" means that the setting thyristor S turns on to cause the corresponding VCSEL to emit light by supplying current. In other words, after an on signal is supplied to the setting thyristor S to make the VCSEL capable of emitting light by supplying current, when current is supplied to the VCSEL and the VCSEL actually emits light, the supply of the on signal to the setting thyristor S may be continued or stopped.

[0081] 5(a) and 5(b) are diagrams illustrating leakage current in the light source device 1 to which the first embodiment is applied. FIG. 5(a) is a cross-sectional view when a light-emitting chip 10′ without a groove 350 is used, and FIG. 5(b) is a cross-sectional view when a light-emitting chip 10 having a groove 350 is used. The horizontal direction of the drawings is the +y direction shown in FIG. 3(a). The cross-sectional view shown in FIG. 5(b) is the same as FIG. 3(b).

[0082] A case where a light emitting chip 10' shown in FIG. 5(a) is used will be described. When the setting thyristor S is turned on and a current flows through the series-connected setting thyristor S and VCSEL, the current flows from the p-ohmic electrode 321 to the substrate 80 and the back electrode 91 . The side surface of the light-emitting chip 10 is damaged when the semiconductor wafer is diced to separate it into chips. The side surface P of the light-emitting chip 10 (the rightmost portion in FIG. 5( a)) is an example of a dicing surface. When the n-cathode (DBR) layer 81 and the p-anode (DBR) layer 83 of the island 300 are exposed on the side surface P, which is the dicing surface, the p-n junction between the n-cathode (DBR) layer 81 and the p-anode (DBR) layer 83 is damaged by dicing. When the p-n junction is damaged, the p-n junction cannot be maintained, and a short circuit may occur. In other words, the n-cathode (DBR) layer 81 and the p-anode (DBR) layer 83 can no longer be electrically isolated by the p-n junction, and current may flow through a path via the side surface P, which is the damaged dicing surface. More specifically, the current flowing from the p-ohmic electrode 321 to the setting thyristor S and the VCSEL flows as leakage current through the inside of the substrate 80 to the side surface P of the light-emitting chip 10, as shown by the leakage current path 360 indicated by the arrow in FIG. 5( a). The leakage current then flows along the side surface P of the light-emitting chip 10 to the p-anode (DBR) layer 83. The leakage current that has flowed along the side surface P of the light-emitting chip 10 to the p-anode (DBR) layer 83 flows to the reference potential terminal 340 to which the reference potential Vst is supplied to the transfer unit 12. The region of the transfer unit 12 connected to the reference potential terminal 340 and the substrate potential Vsub supplied to the substrate 80 are no longer electrically separated. Note that the region of the transfer unit 12 connected to the reference potential terminal 340 is the region of the p-anode (DBR) layer 83 connected to the reference potential terminal 340 of the transfer unit 12, which is a continuous region in the island 300. If the current continues to flow to the reference potential terminal 340, there is a risk that the current will continue to flow from the p ohmic electrode 321 to the setting thyristor S and the VCSEL. If the setting thyristor S connected to the VCSEL that has emitted light remains on, the setting thyristor S may not turn off, resulting in erroneous lighting.

[0083] Next, a case where the light emitting chip 10 shown in FIG. 5(b) is used will be described. As shown in Figure 5(b), in the light-emitting chip 10 having a groove 350 to which embodiment 1 is applied, the area connected to the reference potential terminal 340 of the transfer section 12 and the side surface P of the light-emitting chip 10 are electrically separated by the groove 350. Even in a structure in which the n-cathode (DBR) layer 81 and p-anode (DBR) layer 83 of the island 300 are exposed in the light-emitting chip 10, the current flowing from the p-ohmic electrode 321 to the setting thyristor S and the VCSEL tends to flow as leakage current through the inside of the substrate 80, via the side surface P of the light-emitting chip 10, and from the p-anode (DBR) layer 83 to the reference potential terminal 340, as shown by the leakage current path 360 indicated by the dashed arrow in FIG. 5( b). However, the presence of the groove 350 separating the p-anode (DBR) layer 83 prevents the leakage current from flowing through the p-anode (DBR) layer 83 to the reference potential terminal 340. In other words, the formation of the leakage current path 360 via the side surface of the substrate 80 between the VCSEL, which is the light-emitting element, and the reference potential terminal 340 is prevented. The groove 350 prevents the transfer unit 12 from extending to the outer periphery of the substrate 80 of the light-emitting chip 10. To show that leakage current is suppressed, the leakage current path 360 is indicated by a dashed line. The groove 350 makes it difficult for the side surface P, which is the dicing surface of the light-emitting chip 10, to be damaged by dicing. Furthermore, damage by dicing to the side surface P, which is the dicing surface of the light-emitting chip 10, is tolerated. In order to provide the groove 350, it is preferable to make the light-emitting chip 10 slightly larger by the area thereof. Here, the transfer unit 12 is provided on the structure, and a p-n junction is formed between the p-anode (DBR) layer 83 and the n-cathode (DBR) layer 81 of the structure. This p-n junction also separates the substrate potential Vsub of the substrate 80 (including the back electrode 91 and the n-cathode (DBR) layer 81) from the reference potential terminal 340 that supplies the reference potential Vst to the transfer unit 12. Furthermore, since the function of the transfer unit 12 is completed on the structure, it is not necessary to make it an island in terms of its original function. However, because the side surface of the light-emitting chip 10 is damaged and the separation by the p-n junction is insufficient, the side surface is separated by the groove 350. The groove 350 is an example of a separating portion.

[0084] 6(a) and 6(b) are an example of a planar layout diagram and a cross-sectional view of a light-emitting chip 20 according to a modified example of the first embodiment. FIG. 6(a) is an example of a planar layout diagram of the light-emitting chip 20, and FIG. 6(b) is an example of a cross-sectional view taken along line VIB-VIB in FIG. 6(a). The light-emitting chip 20 is similar to the light-emitting chip 10 shown in FIGS. 3(a) and 3(b) except for the island 300. Therefore, the light-emitting chip 20 will be described with reference to the island 300, which is a different part from the light-emitting chip 10.

[0085] In the light-emitting chip 10 shown in FIG. 3(a), the groove 350 is provided in the island 300 so as to surround the transfer unit 12 (see FIG. 3). By providing the groove 350 so as to surround the transfer unit 12, the reference potential Vst and the substrate potential Vsub can be reliably separated. The groove 350 only needs to prevent leakage current that has flowed along the side surface of the light-emitting chip 10 to the p anode (DBR) layer 83 from flowing through the p anode (DBR) layer 83 to the reference potential terminal 340 of the transfer unit 12. 6(a) and 6(b), a groove 350 is provided along the outer periphery of the light emitting chip 20. In the light emitting chip 20, the portion along the outer periphery of the light emitting chip 20 is removed by mesa etching down to the p anode (DBR) layer 83 to form the groove 350. The periphery of the island 301 is also removed by mesa etching until the p anode (DBR) layer 83 is exposed. Therefore, the periphery of the island 301 can also be considered to be the groove 350.

[0086] Furthermore, the region of the transfer unit 12 connected to the reference potential terminal 340 and the side surface of the light-emitting chip 10 may be electrically isolated by a region in which insulating ions are implanted into the semiconductor layer constituting the transfer unit 12. The region of the transfer unit 12 connected to the reference potential terminal 340 and the side surface of the light-emitting chip 10 may be electrically isolated by both a groove and insulating ions. The region implanted with insulating ions becomes an insulating region, which can electrically isolate the region of the transfer unit 12 connected to the reference potential terminal 340 and the side surface of the substrate 80. The insulating ions are H for III-V group compound semiconductors such as GaAs, AlGaAs, and AlAs. +is. When the region of the transfer unit 12 connected to the reference potential terminal 340 and the side surface P of the light-emitting chip 10 are electrically separated by insulating ions, the insulating ions may be implanted to surround the transfer unit 12, as in the case where the groove 350 is formed in the light-emitting chip 10 shown in Fig. 3(a), or may be implanted along the periphery of the light-emitting chip 20, as in the case where the groove 350 is formed along the periphery of the light-emitting chip 20 shown in Fig. 6(a). The insulating ions are implanted to separate at least the p anode (DBR) layer 83, and may be implanted deeper. The region into which insulating ions are implanted is another example of a separation portion. Note that the separation portion may be formed partly as a groove and partly by implanting insulating ions. Alternatively, the separation portion may simply be formed to prevent the formation of a leakage current path 360 in an area where the leakage current path 360 is likely to form even without surrounding it.

[0087] As described above, it is sufficient that the separation portion such as the groove 350 prevents the p anode (DBR) layer 83 located below the transfer portion 12 connected to the reference potential terminal 340 from extending to the outer periphery of the light-emitting chip 10.

[0088] [Embodiment 2] In the first embodiment, a common-cathode light-emitting chip 10 is described. In the second embodiment, a common-anode light-emitting chip 30 is described. The measurement device 100 is the same as that in the first embodiment. Fig. 7 is an equivalent circuit diagram illustrating a light source device 2 to which the second embodiment is applied. In Fig. 7, the right direction on the paper surface is the +x direction. Note that parts having the same functions as those in the light source device 1 to which the first embodiment is applied are given the same reference numerals and their description will be omitted. The light source device 2 shown in FIG.

[0089] (control unit 110) The control unit 110 includes a transfer signal generating unit 120 , a lighting signal generating unit 140 , a reference potential supplying unit 160 , and a power supply potential supplying unit 170 . The transfer signal generating unit 120 generates a first transfer signal φ1 and a second transfer signal φ2 that sequentially transition the multiple transfer thyristors T in the transfer unit 12 to an ON state. The lighting signal generating unit 140 generates a lighting signal φI that supplies a current that lights up (emits light) the multiple VCSELs. The reference potential supplying unit 160 supplies a reference potential Vst to the transfer unit 12. The power supply potential supplying unit 170 supplies a power supply potential Vga. These have the same functions as those of the light source device 1, but the first transfer signal φ1, the second transfer signal φ2, the lighting signal φI, the reference potential Vst, and the power supply potential Vga have the same absolute values but opposite signs. In other words, they are negative potentials with respect to the ground potential GND (0 V).

[0090] (Light emitting chip 30) The light-emitting chip 30 includes a light-emitting unit 11 and a transfer unit 12. The light-emitting chip 30 includes a φ1 terminal, a φ2 terminal, a Vga terminal, a φI terminal, and a Vst terminal. The light-emitting chip 30 includes a Vsub terminal. The Vsub terminal is a back electrode 91 provided on the back surface of the substrate 80. In FIG. 7, the terminal of the element connected to the substrate 80 (which is also the Vsub terminal) is indicated by the symbol △.

[0091] The light emitting unit 11 includes vertical cavity surface emitting lasers (VCSELs). In the example shown in Fig. 7, six VCSELs, VCSEL1 to VCSEL6, are included. The light emitting unit 11 also includes six setting thyristors S1 to S6. The cathodes of the VCSELs and the anodes of the setting thyristors S are connected.

[0092] The transfer unit 12 includes six transfer thyristors T1 to T6 and six lower diodes UD1 to UD6. The transfer thyristors T1 to T6 and the lower diodes UD1 to UD6 are connected in series with the transfer thyristor T and lower diode UD of the same number. Additionally, similar to the light-emitting chip 10 shown in FIG. 3(b), the transfer thyristor T is stacked on the lower diode UD formed on the substrate 80. The lower diodes UD1 to UD6 are not separated but are integrated. The lower diodes UD1 to UD6 do not operate. In FIG. 7, the lower diodes UD1 to UD6 are indicated by dashed lines.

[0093] The transfer unit 12 pairs the transfer thyristors T1 to T6 in numerical order, and includes coupling diodes D1 to D5 between each pair. Furthermore, the transfer unit 12 includes power line resistors Rg1 to Rg6.

[0094] The transfer unit 12 also includes one start diode SD. Furthermore, the transfer unit 12 includes current limiting resistors R1 and R2 that are provided to prevent excessive current from flowing through a first transfer signal line 72 to which a first transfer signal φ1 (described later) is supplied and a second transfer signal line 73 to which a second transfer signal φ2 (described later) is supplied.

[0095] The VCSEL1 to VCSEL6 and setting thyristors S1 to S6 of the light-emitting unit 11, the transfer thyristors T1 to T6 of the transfer unit 12, the lower diodes UD1 to UD6, the coupling diodes D1 to D5, and the power line resistors Rg1 to Rg6 are arranged in numerical order in the light-emitting chip 30 from one side (-x direction side, left side in Figure 7) to the other side (+x direction side, right side in Figure 7).

[0096] In the second embodiment, similarly to the first embodiment, the number of VCSELs and setting thyristors S in the light-emitting unit 11, the number of transfer thyristors T in the transfer unit 12, the lower diodes UD, and the power line resistance Rg are six each. The number of coupling diodes D is five, which is one less than the number of transfer thyristors T. The numbers of VCSELs, setting thyristors S, transfer thyristors T, lower diodes UD, power line resistance Rg, and coupling diodes D are not limited to the above and may be any predetermined number. The number of transfer thyristors T may also be greater than the number of VCSELs.

[0097] Next, the electrical connections of the elements in the light-emitting chip 30 will be described.

[0098] The anodes of the VCSEL and the lower diode UD are connected (common anode) to the substrate 80. A substrate potential Vsub is supplied to these anodes via a back electrode 91 (see FIG. 3(b)), which is a Vsub terminal provided on the back surface of the substrate 80. The cathodes of the VCSELs are connected to the anodes of the setting thyristors S. The cathodes of the lower diodes UD are connected to the anodes of the transfer thyristors T. The anodes of the transfer thyristors T (the same as the cathodes of the lower diodes UD) are connected to a reference potential line 74. The reference potential line 74 is connected to a Vst terminal. A reference potential Vst is supplied to this Vst terminal from a reference potential supply unit 160. The Vst terminal may be the reference potential terminal 340 shown in FIGS. 3(a) to 3(b).

[0099] Along the arrangement of the transfer thyristors T, the anodes of the odd-numbered transfer thyristors T1, T3, and T5 are connected to a first transfer signal line 72. The first transfer signal line 72 is connected to a φ1 terminal via a current-limiting resistor R1. A first transfer signal φ1 is supplied to this φ1 terminal from the transfer signal generating unit 120 of the control unit 110. Meanwhile, along the arrangement of the transfer thyristors T, the anodes of the even-numbered transfer thyristors T2, T4, and T6 are connected to a second transfer signal line 73. The second transfer signal line 73 is connected to a φ2 terminal via a current-limiting resistor R2. A second transfer signal φ2 is supplied to this φ2 terminal from the transfer signal generating unit 120 of the control unit 110.

[0100] The cathodes of the setting thyristors S are connected to a light-up signal line 75. The light-up signal line 75 is connected to a φI terminal. A light-up signal φI is supplied to this φI terminal from the light-up signal generating unit 140 of the control unit 110 via a current-limiting resistor RI provided outside the light-emitting chip 30. The light-up signal φI supplies a current to the VCSEL for lighting.

[0101] The gates Gt1 to Gt6 of the transfer thyristors T1 to T6 are connected to the gates Gs1 to Gs6 of the setting thyristors S1 to S6 with the same numbers in a one-to-one relationship, so that the gates Gt1 to Gt6 and the gates Gs1 to Gs6 with the same numbers are electrically at the same potential.

[0102] Coupling diodes D1 to D5 are connected between pairs of gates Gt1 to Gt6 of the transfer thyristors T1 to T6 in numerical order. That is, the coupling diodes D1 to D5 are directly connected so that they are sandwiched between the gates Gt1 to Gt6. The coupling diode D1 is connected in the direction in which current flows from the gate Gt1 to the gate Gt2. The same applies to the other coupling diodes D2 to D5.

[0103] The gates Gt (gates Gs) of the transfer thyristors T are connected to a power supply line 71 via power supply line resistors Rg provided corresponding to the respective transfer thyristors T. The power supply line 71 is connected to a Vga terminal. A power supply potential Vga is supplied to the Vga terminal from a power supply potential supply unit 170 of the control unit 110.

[0104] The gate Gt1 of the transfer thyristor T is connected to the cathode of the start diode SD. On the other hand, the anode of the start diode SD is connected to the second transfer signal line 73.

[0105] The planar layout and cross section of the light-emitting chip 30 are the same as those of the first embodiment shown in Figures 3(a) and 3(b). The light-emitting chip 10 shown in Figure 3(b) uses a semiconductor laminate in which an n-cathode (DBR) layer 81, a light-emitting layer 82, a p-anode (DBR) layer 83, a tunnel junction layer 84, an n-cathode layer 85, a p-gate layer 86, an n-gate layer 87, and a p-anode layer 88 are laminated in this order on an n-type substrate 80. The light-emitting chip 30 uses a semiconductor laminate in which a p-anode (DBR) layer, a light-emitting layer, an n-cathode (DBR) layer, a tunnel junction layer, a p-anode layer, an n-gate layer, a p-gate layer, and an n-cathode layer are laminated in this order on a p-type substrate. In other words, n and p are in an inverted relationship.

[0106] As described above, by making the signal supplied from the control unit 110 negative, the light-emitting chip 30 operates in the same manner as the light-emitting chip 10. The same applies to the groove 350.

[0107] [Embodiment 3] In the light-emitting chips 10, 20, and 30 shown in the first and second embodiments, two adjacent transfer thyristors T in the transfer unit 12 are coupled by a coupling diode D. In the light-emitting chip 40 shown in the third embodiment, two adjacent transfer thyristors T in the transfer unit 12 are connected by a coupling transistor Q. The measuring device 100 is the same as that in the first embodiment.

[0108] (Light source device 3) Fig. 8 is an equivalent circuit diagram illustrating a light source device 3 to which the third embodiment is applied. In Fig. 8, the right direction on the paper surface is the +x direction. 8 includes a light emitting chip 40 and a control unit 110. The light emitting chip 40 is a common cathode, similar to the light emitting chip 10 of embodiment 1. The control unit 110 has the same configuration as the control unit 110 of the light source device 1 of embodiment 1, and is therefore referred to as the control unit 110.

[0109] (Light emitting chip 40) The light-emitting chip 40 includes a light-emitting unit 11 and a transfer unit 12. The light-emitting unit 11 and the transfer unit 12 in the light-emitting chip 40 have the same functions as those in the light-emitting chip 10. Therefore, the light-emitting chip 40 will also be referred to as the light-emitting unit 11 and the transfer unit 12. Like the light-emitting chip 10 of the first embodiment, the light-emitting chip 40 includes a φ1 terminal, a φ2 terminal, a Vga terminal, a φI terminal, and a Vst terminal. The light-emitting chip 40 includes a Vsub terminal. Like the light-emitting chip 10, the Vsub terminal is a back electrode 91 (see FIG. 10(b) described later) provided on the back surface of the substrate 80. In FIG. 8, the terminals of the elements connected to the substrate 80 (which is the same as the Vsub terminal) are indicated by the symbol ▽. These terminals have the same configuration as the light-emitting chip 10. The terminals excluding the Vsub terminal are connected to the control unit 110, like the light source device 1 of the first embodiment. In FIG. 8, resistors are indicated by rectangles.

[0110] Similar to the light-emitting chip 10 of the first embodiment, the light-emitting unit 11 includes a plurality of VCSELs and setting thyristors S connected in series. FIG. 8 shows six VCSELs (VCSEL1 to VCSEL6) and six setting thyristors S (setting thyristors S1 to S6). The anodes of the VCSELs and the cathodes of the setting thyristors S with the same number are connected. The six VCSELs and six setting thyristors S are arranged from one side (-x direction side) to the other side (+x direction side).

[0111] The transfer unit 12 includes a plurality of transfer thyristors T, coupling transistors Q, power line resistances Rg, current limiting resistances RL, and coupling resistances Rc. FIG. 8 shows six transfer thyristors T (transfer thyristors T1 to T6) and six coupling transistors Q (coupling transistors Q1 to Q6). The transfer unit 12 includes six power line resistances Rg, six current limiting resistances RL, and six coupling resistances Rc, but these are not numbered. One transfer thyristor T, coupling transistor Q, power line resistance Rg, current limiting resistance RL, and coupling resistance Rc form a transfer unit 12a. The six transfer units 12a are arranged from one side (-x direction side) to the other side (+x direction side). The transfer unit 12 includes a power line resistance Rg and a start resistance Rs at an end on one side (-x direction side). The transfer unit 12 further includes current limiting resistances R1 and R2.

[0112] In the transfer unit 12a, a setting thyristor S and a coupling transistor Q are connected. The coupling transistor Q in the transfer unit 12a is connected to the setting thyristor S of the light-emitting section 11. The setting thyristors S1 to S6 are connected to the coupling transistors Q1 to Q6 of the same number. The coupling transistors Q1 to Q6 are connected to the setting thyristors S1 to S6 of the same number. Although six transfer thyristors T, coupling transistors Q, setting thyristors S, and VCSELs are shown in FIG. 8, other numbers may be used.

[0113] Although not shown in Fig. 8, the transfer unit 12 includes a lower diode UD having a structure similar to that of a VCSEL, similar to the light-emitting chip 10 of the first embodiment shown in Fig. 2. The lower diode UD does not operate in the same manner as the light-emitting chip 10.

[0114] In the light-emitting chip 40, the Vga terminal is connected to a power supply line 71, the Vst terminal is connected to a reference potential line 74, the φ1 terminal is connected to a first transfer signal line 72, the φ2 terminal is connected to a second transfer signal line 73, and the φI terminal is connected to a light-up signal line 75. The Vsub terminal is grounded to the ground potential GND (0 V).

[0115] (Operation of transfer thyristor T, coupling transistor Q, VCSEL and setting thyristor S) Here, the basic operation of the light-emitting chip 40 will be described. The transfer thyristor T and the setting thyristor S are thyristors with an npnp structure. The thyristors include an n-type cathode K (hereinafter referred to as cathode K, and the same applies below), a p-type gate Gp (p-gate Gp), an n-type gate Gn (n-gate Gn), and a p-type anode A (anode A). The setting thyristor S does not use the p-gate Gp for control, so it is not shown. In the light-emitting chip 10 of the first embodiment, the gate of the transfer thyristor T is referred to as gate Gt, and the gate of the setting thyristor S is referred to as gate Gs. In the light-emitting chip 40, the p-type gate Gp (p-gate Gp) is used, so the gates are divided into p-type gate Gp (p-gate Gp) and n-type gate Gn (n-gate Gn). In the light-emitting chip 10, the gate Gt of the transfer thyristor T and the gate Gs of the setting thyristor S correspond to the n-gate Gn.

[0116] The coupling transistor Q is a multi-collector npn bipolar transistor. The coupling transistor Q has an n-type emitter E (emitter E), a p-type base B (base B), and n-type collectors Cf and Cs (collector Cf and Cs).

[0117] The above symbols are used without distinction between thyristors or coupling transistors. The same applies to the bipolar transistors that make up the thyristors described below. However, as will be described later, the thyristor is composed of a combination of a single-collector npn bipolar transistor and a single-collector pnp bipolar transistor (see Figure 9(a) described later). Therefore, they are written as emitter E, base B, and collector C. In the following, even when symbols are not attached to the figures, the symbols anode A, cathode K, n-gate Gn, p-gate Gp, emitter E, base B, and collector C will be used.

[0118] The transfer thyristor T, coupling transistor Q, setting thyristor S, and VCSEL are made of a III-V compound semiconductor such as GaAs. As mentioned above, the forward voltage (diffusion potential) Vd of the junction of this compound semiconductor is set to 1.5V. The saturation voltage Vc of the bipolar transistor made of the compound semiconductor is set to 0.3V. The power supply potential Vga is set to 5V ("H" (5V)). The first transfer signal φ1, the second transfer signal φ2, and the lighting signal φI are signals whose L level is 0V ("L" (0V)) and whose H level is 5V ("H" (5V)). The ground potential GND is set to the ground potential GND (0V).

[0119] 9(a) and 9(b) are diagrams illustrating the operation of the light-emitting chip 40 to which the third embodiment is applied. Fig. 9(a) is an equivalent circuit diagram, and Fig. 9(b) is a cross-sectional view of the transfer thyristor T1 and the coupling transistor Q1. Fig. 9(a) also shows the transfer thyristor T2.

[0120] 9(a), the transfer thyristor T1 is configured by combining an npn bipolar transistor Tr1 (hereinafter referred to as npn transistor Tr1) and a pnp bipolar transistor Tr2 (hereinafter referred to as pnp transistor Tr2). The base B of the npn transistor Tr1 is connected to the collector C of the pnp transistor Tr2, and the collector C of the npn transistor Tr1 is connected to the base B of the pnp transistor Tr2. The emitter E of the npn transistor Tr1 is the cathode K of the transfer thyristor T1, the collector C of the npn transistor Tr1 (base B of the pnp transistor Tr2) is the n-gate Gn of the transfer thyristor T1, the collector C of the pnp transistor Tr2 (base B of the npn transistor Tr1) is the p-gate Gp of the transfer thyristor T1, and the emitter E of the pnp transistor Tr2 is the anode A of the transfer thyristor T1.

[0121] The emitter E of the npn transistor Tr1, which is the cathode K of the transfer thyristor T1, is connected to a reference potential line 74 that is connected to a Vst terminal to which a reference potential Vst is supplied. The emitter E of the pnp transistor Tr2, which is the anode A of the transfer thyristor T1, is connected to a first transfer signal line 72. The n gate Gn is connected to a connection point between the start resistor Rs and the power supply line resistance Rg, which are connected in series. The other end of the start resistor Rs (the end that is not the connection point) is connected to a second transfer signal line 73. The other end of the power supply line resistance Rg (the end that is not the connection point) is connected to a power supply line 71. The first transfer signal line 72 is connected to a φ1 terminal and is supplied with a first transfer signal φ1. The second transfer signal line 73 is connected to a φ2 terminal and is supplied with a second transfer signal φ2. The power supply line 71 is connected to a Vga terminal and is supplied with a power supply potential Vga.

[0122] The coupling transistor Q1, which is an npn transistor, has a base B connected to the p-gate Gp of the transfer thyristor T1 (the base B of the npn transistor Tr1 and the collector C of the pnp transistor Tr2), and an emitter E connected to the reference potential line 74. The collector Cf of the coupling transistor Q1 is connected to the power supply line 71 via a coupling resistor Rc and a power supply line resistor Rg connected in series. The connection point between the coupling resistor Rc and the power supply line resistor Rg is connected to the n-gate Gn of the transfer thyristor T2.

[0123] The npn transistor Tr1 in the transfer thyristor T1 and the coupling transistor Q1 form a current mirror circuit. A current proportional to the current flowing through the npn transistor Tr1 flows through the coupling transistor Q1.

[0124] The collector Cs of the coupling transistor Q1 is connected to the n-gate Gn of the setting thyristor S1 and is also connected via a current limiting resistor RL to a light-up signal line 75. The light-up signal line 75 is connected to a φI terminal and is supplied with a light-up signal φI.

[0125] As described above, the VCSEL1 and the setting thyristor S1 are connected in series. The anode A of the VCSEL1 and the cathode K of the setting thyristor S1 are connected. The anode A of the setting thyristor S1 is connected to the light-on signal line 75. The cathode K of the VCSEL1 is connected to the substrate 80 at the substrate potential Vsub.

[0126] The anode A of the transfer thyristor T2 is connected to the second transfer signal line 73. As shown in FIG. 8 , the anode A of the odd-numbered transfer thyristors T is connected to the first transfer signal line 72, and the anode A of the even-numbered transfer thyristors T is connected to the second transfer signal line 73. Except for the connection relationship of the transfer thyristors T with the first transfer signal line 72 and the second transfer signal line 73, the connection relationship of the transfer thyristors T numbered 2 or higher, the coupling transistors, the setting thyristors S, and the VCSELs is the same as that of the transfer thyristor T1, the coupling transistor Q1, the setting thyristor S1, and the VCSEL1.

[0127] (Operation of transfer thyristor T) The operation of the transfer thyristors T1 and T2 will now be described. The power supply potential Vga (power supply line 71) is set to 5V. The reference potential Vst (reference potential line 74) is set to the ground potential GND (0V). The first transfer signal φ1, the second transfer signal φ2, and the light-up signal φI are set to “L” (0V). At this time, the npn transistor Tr1 and the pnp transistor Tr2 that configure the transfer thyristor T1 are in the off state. The n gate Gn of the transfer thyristor T1 is connected to the connection point of the start resistor Rs and the power supply line resistance Rg that are connected in series. The other side (the side that is not the connection point) of the start resistor Rs is connected to the second transfer signal line 73 that is “L” (0V), and the other side (the side that is not the connection point) of the power supply line resistance Rg is connected to the 5V power supply line 71. Therefore, the n gate Gn has a voltage that is the voltage difference (5V) divided by the start resistor Rs and the power supply line resistance Rg. If the resistance ratio between the start resistor Rs and the power supply line resistor Rg is 1:5, for example, the n gate Gn will be 0.83 V. This state will be referred to as the initial state.

[0128] Here, the first transfer signal φ1 (first transfer signal line 72) is shifted from "L" (0V) to "H" (5V). The emitter E of the pnp transistor Tr2 of the transfer thyristor T1 becomes "H" (5V). The voltage difference (4.17V) between the emitter E ("H" (5V)) and the base B (p-gate Gp) (0.83V) becomes equal to or greater than the forward voltage Vd (1.5V). Because a forward bias occurs between the emitter E and base B, the pnp transistor Tr2 shifts from the OFF state to the ON state. Then, the collector C of the pnp transistor Tr2 (base B of the npn transistor Tr1) becomes 4.7V, which is the emitter E ("H" (5V)) minus the saturation voltage Vc (0.3V). The voltage difference (4.7V) between the emitter E (0V) and base B (4.7V) of the npn transistor Tr1 becomes equal to or greater than the forward voltage Vd (1.5V). Because a forward bias occurs between the emitter E and base B, the npn transistor Tr1 transitions from the off state to the on state. Because the npn transistor Tr1 and the pnp transistor Tr2 in the transfer thyristor T1 transition to the on state, the transfer thyristor T1 transitions from the off state to the on state (turns on).

[0129] In the initial state, when the first transfer signal φ1 transitions from “L” (0 V) to “H” (5 V), the transfer thyristor T1 turns on and transitions from the OFF state to the ON state.

[0130] When the transfer thyristor T1 is turned on, the n gate Gn of the transfer thyristor T1 becomes 0.3 V, which is the saturation voltage Vc. The anode A becomes a voltage determined by the sum of the forward voltage Vd and the saturation voltage Vc (Vd+Vc) and the voltage drop due to the internal resistance of the transfer thyristor T. Here, it is assumed that the anode A becomes 1.9 V. In other words, when the transfer thyristor T1 is turned on, the first transfer signal line 72 shifts from 5 V to 1.9 V. The p gate Gp of the transfer thyristor T1 becomes 1.6 V.

[0131] As described above, the transfer thyristor T1 turns on when the voltage of the n gate Gn becomes lower than the voltage of the anode A by the forward voltage Vd (1.5 V) or more. The transfer thyristor T1 turns off when the voltage of the first transfer signal line 72 (the voltage between the anode A and the cathode K) becomes less than 1.9 V. For example, when the anode A becomes “L” (0 V), the voltage difference between the anode A and the cathode K becomes 0 V, and the transfer thyristor T1 turns off. On the other hand, if the voltage of the first transfer signal line 72 (the voltage difference between the anode A and the cathode K) is 1.9 V or more, the transfer thyristor T1 is maintained in the on state. Therefore, 1.9 V is referred to as the holding voltage. Even if the holding voltage is applied, if a current for maintaining the transfer thyristor T1 in the on state does not flow, the transfer thyristor T1 will not be maintained in the on state. The current that maintains the on state is referred to as the holding current.

[0132] Next, the operation of the coupling transistor Q1 will be described. If the transfer thyristor T1 is in the off state, the npn transistor Tr1 is in the off state. Therefore, the coupling transistor Q1 is also in the off state. The emitter E of the coupling transistor Q1 is connected to the reference potential line 74. Since the reference potential Vst is set to the ground potential GND (0V), the reference potential line 74 is also at the ground potential GND (0V). Therefore, the emitter E is also at the ground potential GND (0V). The collector Cf is at the power supply potential Vga (5V) via the power supply line resistance Rg and the coupling resistance Rc, which are connected in series. In addition, the collector Cs is at the potential (0V) of the lighting signal φI ("L" (0V)) via the current limiting resistance RL.

[0133] When the transfer thyristor T1 turns on, that is, when the npn transistor Tr1 enters the on state, the p-gate Gp of the transfer thyristor T1 becomes 1.6 V, as described above. Then, because the base B of the coupling transistor Q1 is connected to the p-gate Gp of the transfer thyristor T1, the forward voltage Vd (1.5 V) or higher is applied between the emitter E and base B, that is, a forward bias is applied. The coupling transistor Q1 transitions from the off state to the on state. The collector Cf becomes the saturation voltage Vc (0.3 V) (the collector Cs will be described later). The connection point between the power supply line resistance Rg and the coupling resistance Rc (the n-gate Gn of the transfer thyristor T2) becomes a voltage obtained by dividing the voltage difference (4.7 V) between the power supply voltage (5 V) of the power supply line 71 and the voltage (0.3 V) of the collector Cf by the power supply line resistance Rg and the coupling resistance Rc. If the resistance ratio between the power supply line resistance Rg and the coupling resistance Rc is 5:1, for example, the connection point between the power supply line resistance Rg and the coupling resistance Rc (the n gate Gn of the transfer thyristor T2) becomes 1.08V.

[0134] The anode A of the transfer thyristor T2 is connected to the second transfer signal line 73 to which the second transfer signal φ2 is supplied. Because the second transfer signal φ2 is “L” (0 V), the transfer thyristor T2 does not turn on. However, when the second transfer signal φ2 shifts from “L” (0 V) to “H” (5 V), the anode A of the transfer thyristor T2 becomes “H” (5 V), and the voltage difference (3.92 V) with the n gate Gn (1.08 V) becomes equal to or greater than the forward voltage Vd (1.5 V). In other words, a forward bias occurs between the n gate Gn and the anode A, and the transfer thyristor T2 turns on. In this way, the transfer thyristor T shifts its on state sequentially according to the first transfer signal φ1 and the second transfer signal φ2.

[0135] Next, the operation of the setting thyristor S1 and the VCSEL1 will be described. When the coupling transistor Q1 is turned on, the collector Cs, like the collector Cf, becomes the saturation voltage Vc (0.3 V). The n-gate Gn of the setting thyristor S1 is connected to the collector Cs of the coupling transistor Q1, so it becomes 0.3 V. Here, the light-up signal φI transitions from "L" (0V) to "H" (5V). The anode A of the setting thyristor S1 is connected to the light-up signal line 75 to which the light-up signal φI is supplied. The anode A of the setting thyristor S1 becomes "H" (5V). The cathode K of the VCSEL1 is connected to the substrate 80 (Vsub terminal) set to the ground potential GND (0V). Therefore, when the light-up signal φI transitions from "L" (0V) to "H" (5V), "H" (5V) is applied to the series connection of the setting thyristor S1 and the VCSEL. At the same time, a voltage difference (4.7V) is created between the anode An and gate Gn of the setting thyristor S1, and the anode An and gate Gn become forward biased. This turns on the setting thyristor S1, causing current to flow through the VCSEL1, lighting it up.

[0136] That is, the initial state is a state in which the power supply line 71 is set to the power supply potential Vga (5 V), the reference potential Vst and the substrate potential Vsub of the reference potential line 74 are set to the ground potential GND (0 V), and the first transfer signal φ1 and the second transfer signal φ2 are “L” (0 V). In the initial state, the transfer thyristor T1 is ready to transition to the ON state. Here, when the first transfer signal φ1 (first transfer signal line 72) transitions from “L” (0 V) to “H” (5 V), the transfer thyristor T1 turns on and transitions from the OFF state to the ON state. When the transfer thyristor T1 turns on, the coupling transistor Q1 transitions from the OFF state to the ON state. Here, when the light-up signal φI (light-up signal line 75) transitions from “L” (0 V) to “H” (5 V), a forward bias is applied between the anode An and the gate Gn of the setting thyristor S, and the VCSEL1 lights up. Furthermore, when the coupling transistor Q1 is turned on, the transfer thyristor T2 is able to transition to the on state. Then, when the second transfer signal φ2 (second transfer signal 73) transitions from "L" (0 V) to "H" (5 V), the transfer thyristor T2 turns on. Note that when the first transfer signal φ1 (first transfer signal line 73) transitions from "H" (5 V) to "L" (0 V), the cathode K and anode A of the transfer thyristor T1 become 0 V, and the transfer thyristor T1 is turned off. The other transfer thyristors T, coupling transistor Q, setting thyristor S, and VCSEL operate in the same way.

[0137] As shown in FIG. 9(b), the light-emitting chip 40 is configured with a semiconductor laminate in which multiple semiconductor layers are stacked (see FIG. 10(b) described later). The semiconductor laminate is the same as the semiconductor laminate of the light-emitting chip 10. FIG. 9(b) shows a portion in which a p-anode (DBR) layer 83, a tunnel junction layer 84, an n-cathode layer 85, a p-gate layer 86, an n-gate layer 87, and a p-anode layer 88, which constitute the transfer thyristor T1 and the coupling transistor Q1, are stacked. The transfer thyristor T1 is configured with the n-cathode layer 85 as the cathode K, the p-gate layer 86 as the p-gate Gp, the n-gate layer 87 as the n-gate Gn, and the p-anode layer 88 as the anode A. On the other hand, the coupling transistor Q1 is configured with the n-cathode layer 85 as the emitter E, the p-gate layer 86 as the base B, and the n-gate layer 87 as the collectors Cf and Cs. The p-anode (DBR) layer 83 is connected to a Vst terminal (reference potential terminal 341) that supplies a reference potential Vst of the transfer unit 12. The p-anode (DBR) layer 83, the tunnel junction layer 84, and the n-cathode layer 85 are at the same potential.

[0138] Here, the cathode K of the transfer thyristor T1 and the emitter E of the coupling transistor Q1 are electrically connected via an n-cathode layer 85. Similarly, the p-gate Gp of the transfer thyristor T1 and the base B of the coupling transistor Q1 are electrically connected via a p-gate layer 86. The n-gate Gn of the transfer thyristor T1 and the collectors Cf and Cs of the coupling transistor Q1 are both formed of an n-gate layer 87 but are separated from each other. The same is true for the other transfer thyristors T and coupling transistors Q.

[0139] 10(a) and 10(b) are an example of a planar layout diagram and a cross-sectional view of the light-emitting chip 40 to which the third embodiment is applied. FIG. 10(a) is an example of a planar layout diagram of the light-emitting chip 40, and FIG. 10(b) is an example of a cross-sectional view taken along line XB-XB in FIG. 10(a). In FIGS. 10(a) and 10(b), the protective layer (protective layer 90 in FIG. 4) and the light-shielding layer (light-shielding layer 95 in FIG. 4) are omitted. In addition, in FIG. 10(b), the connection wirings shown in FIG. 10(a) are omitted. Fig. 10(a) mainly shows the transfer thyristors T1 to T4, coupling transistors Q1 to Q4, setting thyristors S1 to S4, and VCSEL1 to VCSEL4 shown in Fig. 8. Fig. 10(b) shows a cross section of the setting thyristor S1, VCSEL1, transfer thyristor T1, coupling transistor Q1, coupling resistor Rc connected to coupling transistor Q1, and power line resistor Rg.

[0140] 10(b), the light-emitting chip 40 is configured by stacking an n-cathode (DBR) layer 81, a light-emitting layer 82, a p-anode (DBR) layer 83, a tunnel junction layer 84, an n-cathode layer 85, a p-gate layer 86, an n-gate layer 87, and a p-anode layer 88 on an n-type substrate 80. Elements such as the transfer thyristor T, the coupling transistor Q, the setting thyristor S, and the VCSEL are configured on a plurality of islands separated by removing some of the semiconductor layers by etching. Below, the islands (islands 300, 361 to 367) will be described, focusing on an island 361 where the setting thyristor S1 and the VCSEL1 are provided, and an island 362 where the transfer thyristor T1 and the coupling transistor Q1 are provided.

[0141] The island 300 is the part where the transfer section 12 (see Figure 8) such as the transfer thyristor T1 and the coupling transistor Q1 is provided, similar to the light-emitting chip 10, and the n-cathode (DBR) layer 81, the light-emitting layer 82, and the p-anode (DBR) layer 83 remain on the substrate 80 without being removed.

[0142] A VCSEL1 and a setting thyristor S1 are stacked on an island 361. An island 362 is provided with the transfer thyristor T1 and coupling transistor Q1 shown in FIG. 9(b). An island 363 is provided with a current limiting resistor RL, and an island 364 is provided with a power line resistor Rg and a coupling resistor Rc. An island 365 is provided with a power line resistor Rg and a start resistor Rs. An island 366 is provided with a current limiting resistor R1, and an island 367 is provided with a current limiting resistor R2.

[0143] The planar layout and cross section of the light-emitting chip 40 will be described below with reference to FIGS. Around the island 361, the p-anode layer 88, n-gate layer 87, p-gate layer 86, n-cathode layer 85, tunnel junction layer 84, and p-anode (DBR) layer 83 have been removed by etching. A p-ohmic electrode 381 that easily makes ohmic contact with the p-type semiconductor layer is provided on the p-anode layer 88. An n-ohmic electrode 391 that easily makes ohmic contact with the n-type semiconductor layer is provided on the n-gate layer 87 that is exposed by removing the p-anode layer 88. In the VCSEL1, the n-cathode (DBR) layer 81 is referred to as cathode K (see FIG. 9(a)), the light-emitting layer 82 is referred to as the light-emitting layer, and the p-anode (DBR) layer 83 is referred to as anode A. In the setting thyristor S1, the n-cathode layer 85 is referred to as cathode K, the p-gate layer 86 is referred to as p-gate Gp, the n-gate layer 87 is referred to as n-gate Gn, and the p-anode layer 88 is referred to as anode A. The n-ohmic electrode 391 is an electrode of the n-gate Gn of the setting thyristor S1 (n-gate Gn electrode). The n-ohmic electrode 391 may be written as n-gate Gn.

[0144] 10(b), a VCSEL1 is provided on a substrate 80, and a setting thyristor S1 is provided on the VCSEL1 via a tunnel junction layer 84. The tunnel junction layer 84 prevents a reverse bias between a p-anode (DBR) layer 83 of the VCSEL1 and an n-cathode layer 85 of the setting thyristor S1, which would otherwise make it difficult for a current to flow.

[0145] The island 361 is cylindrical except for the portion where the n ohmic electrode 391 is provided. The p ohmic electrode 381 is provided in a circular ring shape on the p anode layer 88 of the cylindrical island 361. A portion of the semiconductor layer constituting the p anode (DBR) layer 83 exposed by etching is oxidized from the exposed portion, forming a circular current blocking portion β through which current does not easily flow. On the other hand, the unoxidized central portion forms a current passing portion α through which current easily flows. The current passing portion α and current blocking portion β are the same as those of the light-emitting chip 10.

[0146] Around the island 362, the p-anode layer 88, the n-gate layer 87, the p-gate layer 86, the n-cathode layer 85, and the tunnel junction layer 84 are removed by etching (see FIG. 9(b)). A p-ohmic electrode 382 is provided on the p-anode layer 88. The p-ohmic electrode 382 is an electrode (anode A electrode) connected to the anode A of the transfer thyristor T1, and is connected to the first transfer signal line 72 to which the first transfer signal φ1 is supplied. N-ohmic electrodes 392, 393, and 394 are provided on the n-gate layer 87 exposed by removing the p-anode layer 88. The n-ohmic electrodes 392 and 394 are electrodes (collector Cf and Cs electrodes) connected to the collectors Cs and Cf of the coupling transistor Q1. Note that the n-gate layer 87 between the p-ohmic electrode 382 and the n-ohmic electrodes 392 and 394 is removed (see FIG. 9(b)). The n-ohmic electrode 393 is an electrode (n-gate Gn electrode) connected to the n-gate Gn of the transfer thyristor T1.

[0147] Around the island 364, the p anode layer 88, n gate layer 87, p gate layer 86, n cathode layer 85, and tunnel junction layer 84 are removed by etching. Three n ohmic electrodes 397, 398, and 399 are provided on the n gate layer 87 exposed by removing the p anode layer 88. The portion of the n gate layer 87 between the n ohmic electrodes 397 and 398 is a coupling resistance Rc, and the portion of the n gate layer 87 between the n ohmic electrodes 398 and 399 is a power line resistance Rg.

[0148] 10(b), island 363 is configured similarly to island 364, and has two n-ohmic electrodes 395 and 396 provided on the exposed n-gate layer 87. The n-gate layer 87 between the two n-ohmic electrodes 395 and 396 is a current-limiting resistor RL.

[0149] Island 365, which is not shown in Fig. 10(b), is configured similarly to island 364 and is provided with start resistor Rs and power line resistor Rg. Islands 366 and 367, which are not shown in Fig. 10(b), are configured similarly to island 363 and are provided with current limiting resistors R1 and R2.

[0150] A p-ohmic electrode 341 is provided on the exposed p-anode (DBR) layer 83 of the island 300. In the light-emitting chip 40, a portion along the periphery of the light-emitting chip 40 is removed by mesa etching down to the p-anode (DBR) layer 83 to form a groove 350. The periphery of the island 361 is also removed by mesa etching until the p-anode (DBR) layer 83 is exposed. Therefore, the periphery of the island 361 can also be considered to be the groove 350. This groove 350 is similar to that of the light-emitting chip 20 shown in FIG. 6. The transfer unit 12 of the light-emitting chip 40 is surrounded by the groove 350. A back electrode 91 is provided on the back surface of the n-type substrate 80.

[0151] Next, the connection relationships will be described. In Fig. 10(a), the wiring used for connection (power supply line 71, first transfer signal line 72, second transfer signal line 73, reference potential line 74, and light-up signal line 75) is shown by solid lines. A p-ohmic electrode 381, which is the anode A electrode of the setting thyristor S1 of the island 361, is connected to a light-up signal line 75 to which a light-up signal φI is supplied. An n-ohmic electrode 391, which is the n-gate Gn electrode of the setting thyristor S1 of the island 361, is connected to an n-ohmic electrode 392, which is the collector Cs electrode of the coupling transistor Q1 of the island 362. The n-ohmic electrode 392 is connected to an n-ohmic electrode 396 of a current limiting resistor RL provided in the island 363. An n-ohmic electrode 395 of the island 363 is connected to the light-up signal line 75.

[0152] A p-ohmic electrode 382, which is an anode A electrode of the transfer thyristor T1 of the island 362, is connected to a first transfer signal line 72. The first transfer signal line 72 is connected to a φ1 terminal to which a first transfer signal φ1 is supplied via a current-limiting resistor R1 provided in the island 366. An n-ohmic electrode 393, which is an n-gate Gn electrode of the transfer thyristor T1 of the island 362, is connected to an n-ohmic electrode (unnumbered) that is a connection point between the power supply line resistor Rg and the start resistor Rs provided in the island 365. An n-ohmic electrode 394, which is a collector Cf electrode of the coupling transistor Q1 of the island 362, is connected to one n-ohmic electrode 397 of the coupling resistor Rc of the island 364.

[0153] The other n-ohmic electrode 398 of the coupling resistance Rc of the island 364 is connected to an n-ohmic electrode (unnumbered) which is the n-gate Gn electrode of the transfer thyristor T2. The other n-ohmic electrode 399 of the power supply line resistance Rg of the island 364 is connected to the power supply line 71 to which the power supply potential Vga is supplied.

[0154] One n-ohmic electrode (no symbol) of the start resistance Rs of the island 365 is connected to the second transfer signal line 73. The other n-ohmic electrode (no symbol) of the power supply line resistance Rg of the island 365 is connected to the power supply line 71. The second transfer signal line 73 is connected to a φ2 terminal to which a second transfer signal φ2 is supplied via a current limiting resistance R2 provided in the island 367.

[0155] The first transfer signal line 72 is connected to the p-ohmic electrode which is the anode A electrode of the odd-numbered transfer thyristor T, and the second transfer signal line 73 is connected to the p-ohmic electrode which is the anode A electrode of the even-numbered transfer thyristor T.

[0156] The other transfer thyristors T, coupling transistors Q, setting thyristors S, and VCSELs are configured similarly to the transfer thyristor T1, coupling transistor Q1, setting thyristor S1, and VCSEL1.

[0157] The p ohmic electrode 341 of the exposed p anode (DBR) layer 83 of the island 300 is connected to a reference potential line 74. The reference potential line 74 is connected to a Vst terminal. A reference potential Vst is supplied to the Vst terminal. Note that the reference potential line 74 and the Vst terminal may be omitted, and the p ohmic electrode 341 may serve as the Vst terminal or the reference potential terminal 341. Hereinafter, the Vst terminal will be referred to as the reference potential terminal 341. The reference potential terminal 341 is another example of a reference potential terminal. A back electrode 91 on the back surface of the n-type substrate 80 is a Vsub terminal to which a substrate potential Vsub is supplied.

[0158] The transfer unit 12, which includes the transfer thyristor T, the coupling transistor Q, and the like, is provided on a lower diode UD that is configured with a p-anode (DBR) layer 83, a light-emitting layer 82, and an n-cathode (DBR) layer 81, similar to those of a VCSEL light-emitting element. The lower diode UD is referred to as a structure equivalent to the light-emitting element. The p-anode (DBR) layer 83 and the n-cathode (DBR) layer 81 of the equivalent structure form a p-n junction. This p-n junction electrically isolates the substrate potential Vsub of the substrate 80 (including the back electrode 91 and the n-cathode (DBR) layer 81) from a reference potential terminal 341 that supplies a reference potential Vst to the transfer unit 12.

[0159] As described above, the light-emitting chip 40 is mounted on the substrate 80 made of a single semiconductor. Although a common-cathode circuit is shown in the third embodiment, a common-anode circuit may also be used. The common-cathode circuit uses an n-type substrate, whereas the common-anode circuit uses a p-type substrate, with the n-type and p-type being reversed from the third embodiment.

[0160] [Embodiment 4] In the first, second and third embodiments, the light emitting chips 10, 20, 30 and 40 have been described. In the fourth embodiment, a method for operating the light-emitting chips 10, 20, 30, and 40 will be described. The light-emitting chip 20 is a modified example of the light-emitting chip 10. The light-emitting chip 30 is the light-emitting chip 10 with the polarity reversed. The light-emitting chip 30 can be operated by simply reversing the polarity of the potential in the light-emitting chip 10. The light-emitting chip 40 is the light-emitting chip 10 in which the element (coupling element) that couples two adjacent transfer thyristors T is changed from a diode to a transistor, and can be operated in the same manner as the light-emitting chip 10. A method for operating the light-emitting chip 10 will be described below.

[0161] In the equivalent circuit diagram of the light source device 1 in FIG. 2 , the substrate potential Vsub and the reference potential Vst are set to the ground potential GND (0 V), and the power supply potential Vga is set to “H” (5 V). The first transfer signal φ1, the second transfer signal φ2, and the lighting signal φI are set to signals having “H” (5 V) and “L” (0 V). Then, a voltage of up to 5 V (equivalent to “H” (5 V)) is applied to the series connection of the VCSEL and the setting thyristor S. Similarly, a voltage of up to 5 V (equivalent to “H” (5 V)) is also applied to the transfer thyristor T. As described above, the transfer thyristor T operates in the same manner as the setting thyristor S. Therefore, the voltage applied to the transfer thyristor T may be 5 V or less. If the reference potential Vst is set to, for example, 1 V, the voltage applied to the transfer thyristor T is reduced to 4 V. This prevents an excessive voltage (overvoltage) from being applied to the transfer thyristor T.

[0162] The reference potential Vst is applied to a reference potential terminal 340 shown in FIG. 3(b). The reference potential terminal 340 is connected to the p-anode (DBR) layer 83 of the transfer unit 12. An n-cathode (DBR) layer 81 is located below the p-anode (DBR) layer 83, with an emission layer 82 interposed therebetween. The p-anode (DBR) layer 83 and the n-cathode (DBR) layer 81 form a p-n junction. The n-cathode (DBR) layer 81 is at a substrate potential Vsub via an n-type substrate 80 and a back surface electrode 91. When the substrate potential Vsub is set to the ground potential GND (0V) and the reference potential Vst is set to 1V, the p-anode (DBR) layer 83 and the n-cathode (DBR) layer 81 are in a forward bias state. However, the reference potential Vst of 1 V is less than the forward voltage Vd (1.5 V) of the p-n junction, and no current flows between the p-anode (DBR) layer 83 and the n-cathode (DBR) layer 81. Even if leakage current occurs on the side surface P, which is the dicing surface of the light-emitting chip 10, the groove 350, where the p-anode (DBR) layer 83 is removed, prevents the leakage current from flowing to the reference potential terminal 340 of the transfer unit 12 via the side surface P of the light-emitting chip 10. As described above, current is also prevented from flowing from the n-cathode (DBR) layer 81 to the p-anode (DBR) layer 83 of the transfer unit 12 via the p-n junction. Note that if the voltage applied to the reference potential Vst is equal to or greater than the forward voltage Vd (1.5 V) of the p-n junction, current will flow from the n-cathode (DBR) layer 81 to the p-anode (DBR) layer 83 of the transfer unit 12. The voltage applied to the reference potential Vst is preferably less than the forward voltage Vd (1.5 V) of the pn junction.

[0163] Next, a method for operating the light-emitting chip 10 by low-side driving will be described. Low-side driving is a configuration in which an element such as a MOS transistor is positioned downstream of the current path of a light-emitting element. Low-side driving is recommended when you want to operate the light-emitting element at a higher speed.

[0164] 11 is an equivalent circuit diagram illustrating a light source device 4 to which the fourth embodiment is applied. In FIG. 11, the right direction on the paper surface is the +x direction. Note that the measurement device 100 using the light source device 4 is the same as that in the first embodiment. The light source device 4 shown in Fig. 11 includes a light-emitting chip 10 and a control unit 111. The light-emitting chip 10 is the light-emitting chip 10 described in embodiment 1. The control unit 111 is partially different from the control unit 110 described in embodiment 1. Below, the different parts will be described, and similar parts will be denoted by the same reference numerals and will not be described again.

[0165] (Control unit 111) The control unit 111 includes a transfer signal generating unit 120 , a lighting signal generating unit 140 , a power supply potential supplying unit 170 , a driver unit 180 , and a light-emitting potential supplying unit 190 . The transfer signal generating unit 120 generates a first transfer signal φ1 and a second transfer signal φ2 that sequentially switch the multiple transfer thyristors T in the transfer unit 12 (described later) to an ON state. The light-up signal generating unit 140 generates a light-up signal φI that turns on (emits) multiple VCSELs (described later). The power supply potential supplying unit 170 supplies a power supply potential Vga. The driver unit 180 controls the light-up current in response to the light-up signal φI. The light-up potential supplying unit 190 supplies a light-up potential VLD.

[0166] The driver unit 180 includes a driver Drv. The driver Drv uses, for example, an NMOS transistor as a driver element. The driver Drv is turned on / off by a lighting signal φI applied to the gate of the NMOS transistor. The source of the NMOS transistor is grounded and is at the ground potential GND (0V). The drain is connected to the Vsub terminal of the light-emitting chip 10 via a current-limiting resistor RI. When the driver Drv is turned on, it supplies the ground potential GND (0V) to the Vsub terminal of the light-emitting chip 10. The lighting signal φI is a signal that transitions between "H" (5V) and "L" (0V). "H" (5V) turns on the driver Drv, and "L" (0V) turns off the driver Drv. The source is one end of the driver Drv, and the drain is the other end of the driver Drv.

[0167] The light-emitting potential supply unit 190 supplies the light-emitting potential VLD to the φI terminal of the light-emitting chip 10. The light-emitting potential VLD is, for example, 5 V ("H" (5 V)). That is, in the light source device 4, the φI terminal of the light-emitting chip 10 is supplied with the light-emitting potential VLD, rather than the lighting signal φI. The VCSEL and the setting thyristor S are connected in series. The light-emitting potential VLD is applied to the anode of the setting thyristor S.

[0168] The Vst terminal that supplies the reference potential Vst is grounded to the ground potential GND (0 V).

[0169] The operation of the light source device 4 will now be described. The light-up signal φI is set to “L” (0 V). The driver Drv is off, and the Vsub terminal is not at the ground potential GND (0 V). The operation of the transfer unit 12 of the light-emitting chip 10 is the same as that of the first embodiment. When the transfer thyristor T is turned on, the gate Gt of the transfer thyristor T becomes "L" (0 V). The gate Gs of the setting thyristor S connected to the gate Gt of the transfer thyristor T also becomes "L" (0 V). This causes the threshold voltage of the setting thyristor S to become 1.5 V. At this time, the driver Drv is off, so no current flows through the VCSEL and setting thyristor S connected in series. Here, when the light-up signal φI becomes "H" (5V), the driver Drv turns on. The Sub terminal becomes the ground potential GND (0V). Then, the setting thyristor S turns on, and the VCSEL connected in series to the setting thyristor S lights up.

[0170] 12(a) and 12(b) are diagrams illustrating leakage current in a light source device 4 to which the fourth embodiment is applied. FIG. 12(a) is a cross-sectional view when a light-emitting chip 10′ without a groove 350 is used, and FIG. 12(b) is a cross-sectional view when a light-emitting chip 10 having a groove 350 is used. The horizontal direction of the drawings is the +y direction shown in FIG. 3(a). The cross-sectional view shown in FIG. 12(a) is the same as the cross-sectional view shown in FIG. 5(a). The cross-sectional view shown in FIG. 12(b) is the same as the cross-sectional view shown in FIG. 5(b). A case where the light-emitting chip 10′ shown in Fig. 12(a) is used will be described. Fig. 12(a) shows a state in which the driver Drv is shifted from on to off (indicated as off in Fig. 12(a)). In the light source device 4, the substrate 80 (rear electrode 91) of the light-emitting chip 10′ is grounded (GND (0V)) via the driver Drv. When the driver Drv is on (the lighting signal φI is “H” (5V)), the setting thyristor S is turned on, and a current flows through the series-connected setting thyristor S and VCSEL. The current flows from the p-ohmic electrode 321 to the substrate 80 and rear electrode 91, and then flows to ground (GND (0V)) via the driver Drv.

[0171] At this time, if the side surface of the light-emitting chip 10′ is damaged by dicing, the current will flow through the inside of the substrate 80 to the side surface P of the light-emitting chip 10 and then along the side surface P of the light-emitting chip 10 to the p-anode (DBR) layer 83 of the transfer unit 12. The p-anode (DBR) layer 83 of the transfer unit 12 is grounded (GND (0 V)) via the reference potential terminal 340. In addition, when the driver Drv is on, a leakage current path (leakage current path 360) is formed, which flows from the p-ohmic electrode 321 at the light-emitting potential VLD via the setting thyristor S, the VCSEL, and the substrate 80 to ground (GND (0 V)) via the driver Drv, and also flows from the p-ohmic electrode 321 at the light-emitting potential VLD via the setting thyristor S, the VCSEL, and the substrate 80, along the side surface P of the light-emitting chip 10′ to the reference potential terminal 340 at the ground potential GND (0 V).

[0172] When the driver Drv is switched from on to off, the current path from the p-ohmic electrode 321 at the light-emitting potential VLD via the setting thyristor S, the VCSEL, and the substrate 80 to ground (GND (0 V)) via the driver Drv is interrupted. However, the leakage current path 360 from the p-ohmic electrode 321 at the light-emitting potential VLD via the setting thyristor S, the VCSEL, and the substrate 80, along the side surface P of the light-emitting chip 10, and to the reference potential terminal 340 at ground potential GND (0 V) is not interrupted and continues to flow. In other words, if the leakage current can maintain the lighting of the VCSEL, the VCSEL will continue to light up. Even if the leakage current cannot maintain the lighting of the VCSEL, if the setting thyristor S can be maintained in the on state, when other VCSELs are turned on, the VCSELs connected to the setting thyristor S that is maintained in the on state will light up together with the other VCSELs. In other words, erroneous lighting occurs.

[0173] Next, a case where the light-emitting chip 10 shown in Fig. 12(b) is used will be described. Fig. 12(b) shows a state in which the driver Drv is shifted from on to off (denoted as off in Fig. 12(b)). When the light-emitting chip 10 having the groove 350 is used, when the driver Drv is on, the path from the p-ohmic electrode 321 at the light-emitting potential VLD via the setting thyristor S, the VCSEL, and the substrate 80 to the ground (GND (0 V)) via the driver Drv is the same as that of the light-emitting chip 10′. However, unlike the case shown in FIG. 12( a), the leakage current path 360 that attempts to flow from the p-ohmic electrode 321 at the light-emitting potential VLD via the setting thyristor S, the VCSEL, and the substrate 80, along the side surface P of the light-emitting chip 10 to the reference potential terminal 340 at the ground potential GND (0 V) is blocked by the groove 350 and does not reach the p-anode (DBR) layer 83 of the transfer unit 12 that is set to the ground potential GND (0 V) by the reference potential terminal 340. In the light-emitting chip 10 having the groove 350, even if the side surface P of the light-emitting chip 10 is damaged by dicing, the leakage current path 360 is not formed due to the groove 350 provided in the island 300. Therefore, the leakage current path 360 is indicated by a dashed line. The lit VCSEL is extinguished by turning off the driver Drv. The setting thyristor S is prevented from being maintained in the on state.

[0174] The p-anode (DBR) layer 83 and n-cathode (DBR) layer 81 of the transfer unit 12 form a p-n junction as described above. The p-anode (DBR) layer 83 is at ground potential GND (0V) via the reference potential terminal 340. On the other hand, the n-cathode (DBR) layer 81 is at the same potential as the substrate 80 (including the back electrode 91) and is grounded (GND (0V)) via the driver Drv. By passing through the driver Drv, the n-cathode (DBR) layer 81 is at least at a positive potential. The p-n junction between the p-anode (DBR) layer 83 and the n-cathode (DBR) layer 81 is in a reverse bias state. In addition, the region to which the reference potential terminal 340 of the transfer unit 12 is connected (the p-anode (DBR) layer 83 of the island 300) is electrically isolated from the substrate 80 (including the back electrode 91).

[0175] By using the light-emitting chip 10 in which the groove 350 is provided in the island 300 in which the transfer unit 12 is provided, the formation of the leakage current path 360 is suppressed in the light source device 4 that drives the light-emitting chip 10 in low-side driving mode, thereby suppressing erroneous lighting.

[0176] As described above, the reference potential terminal 340 described in the first and second embodiments and the reference potential terminal 341 described in the third embodiment may be set to a potential other than the ground potential GND (0V).

[0177] In the above-described first to fourth embodiments, the transfer unit 12 has been described as an example of a drive unit. In the transfer unit 12 shown in FIGS. 2, 7, and 8, a coupling diode D is used. In the transfer unit 12 shown in FIG. 8, a coupling transistor Q is used. These coupling elements are not limited to the coupling diode D and the coupling transistor Q, and other elements such as resistors and thyristors may also be used. Although the gate Gt of the transfer thyristor T and the gate Gs of the setting thyristor S are directly connected, a configuration in which the gate Gt of the transfer thyristor T and the gate Gs of the setting thyristor S are connected via a diode, a resistor, or the like may also be used.

[0178] In the above-described first to fourth embodiments, the transfer unit 12 that shifts the ON state of the transfer elements in the arranged order is used as an example of a drive unit, but the drive unit does not have to shift the ON state in the arranged order. The drive unit may be one that individually designates the light-emitting elements to be light-controlled.

[0179] By providing a separator that prevents the driver from extending to the periphery of the light-emitting chip, the substrate potential Vsub supplied to the light-emitting element can be made different from the reference potential Vst of the driver provided on the structure equivalent to the light-emitting element. The separator is effective when configuring circuits that use different reference potentials on a single semiconductor substrate.

[0180] (Addendum) (((1))) A substrate; a plurality of light-emitting elements provided on the substrate; a plurality of thyristors that, when turned on, cause the respective light-emitting elements to emit light or increase the amount of light emitted by the light-emitting elements; a driving unit provided on the substrate and configured to individually drive the plurality of thyristors to transition them to an ON state; a reference potential terminal that supplies a predetermined reference potential to the driving unit, wherein a region of the driving unit connected to the reference potential terminal is electrically isolated from a side surface of the substrate; A light emitting device comprising: (((2))) A semiconductor substrate; a plurality of light-emitting elements provided on the front surface side of the substrate, and a plurality of thyristors that, when turned on, cause the light-emitting elements to emit light or increase the amount of light emitted by the light-emitting elements; a driving unit provided on the front surface side of the substrate for individually driving the plurality of thyristors to transition them to an ON state; a reference potential terminal to which a predetermined reference potential is supplied to the driving unit; an isolation portion that suppresses a current flow between the reference potential terminal and the substrate; A light-emitting chip comprising: (((3))) The light-emitting chip according to (((2))), wherein the separating portion prevents the driving portion from being formed to extend to the outer periphery of the substrate. (((4))) The light-emitting chip according to (((2))), wherein the separating portion prevents a current path from being formed between the light-emitting element and the reference potential terminal, the current path passing through a side surface of the substrate. (((5))) the thyristor is stacked on the light-emitting element provided on the substrate, the driving unit is laminated on a structure equivalent to the light-emitting element provided on the substrate; The light-emitting chip according to (((2))). (((6))) the light-emitting element, the thyristor, and the driving unit are configured by a semiconductor laminate in which a plurality of semiconductor layers of different conductivity types are laminated, the separation portion is a groove provided in the semiconductor laminate and / or a region in which insulating ions are implanted into the semiconductor laminate; The light-emitting chip according to (((5))). (((7))) the light-emitting element and the structure have a diode structure in which a p-type semiconductor layer serving as an anode and an n-type semiconductor layer serving as a cathode are stacked, the trench or the region into which the insulating ions are implanted extends from the surface side of the substrate to at least the p-type semiconductor layer and the n-type semiconductor layer constituting the diode structure, the p-type semiconductor layer and the n-type semiconductor layer being farther from the substrate side; The light-emitting chip according to (((6))). (((8))) The light-emitting element has a current confinement layer, which is a region that is oxidized to make it difficult for a current to flow, The depth of the groove is a depth that reaches the current confinement layer. The light-emitting chip according to (((6))) or (((7))). (((9))) The light-emitting chip described in (((5))), wherein the reference potential is applied to the side of a diode structure farther from the substrate, in which a p-type semiconductor layer serving as the anode of the structure and an n-type semiconductor layer serving as the cathode are stacked. (((10))) The light-emitting chip according to (((6))), wherein the groove and / or the region into which insulating ions are implanted is provided so as to surround the driving section. (((11))) The light-emitting chip according to (((2))), wherein the driving unit sequentially transitions the on states of the plurality of thyristors. (((12))) A semiconductor substrate; a plurality of light-emitting elements provided on the front surface side of the substrate; a plurality of thyristors stacked on the light emitting element, which are turned on to cause the light emitting element to emit light or increase the amount of light emitted by the light emitting element; a reference potential terminal provided on a structure equivalent to the light emitting element and supplied with a predetermined reference potential; a separation portion that prevents a current path from being formed between the reference potential terminal and the light emitting element via a side surface of the substrate; A light-emitting chip comprising: (((13))) a light-emitting chip according to any one of (((2))) to (((12))); a driver having one end set to a ground potential and the other end connected to the substrate of the light-emitting chip, and transitioning to an ON state at a predetermined timing to cause a current for light emission to flow through the light-emitting element; A light emitting device comprising: (((14))) a light-emitting device according to (((13))); an acquisition unit that acquires information about an object based on light reflected from the object and emitted from the light emitting device; A measuring device comprising:

[0181] According to the light-emitting device of (((1))) and the light-emitting chips of (((2))) and (((12))), it is possible to suppress erroneous lighting compared to a configuration in which leakage current from the light-emitting element can flow to the reference potential terminal of the driving unit. The light-emitting chip according to (((3))) is less susceptible to damage caused by dicing of the side surface of the light-emitting chip than when the drive unit is configured to extend to the outer periphery of the substrate. According to the light-emitting chip according to (((4))), damage caused by dicing is tolerable. According to the light emitting chip of (((5))), the light emitting elements of the light emitting chip can be arranged at a higher density than when a thyristor is not stacked on the light emitting elements. According to the light-emitting chip of (((6))), the driving unit and the dicing surface can be electrically isolated. According to the light-emitting chip according to (((7))), the effect of electrically isolating the driving unit and the dicing surface can be enhanced. According to the light-emitting chip of (((8))), the separating portion can be formed in the same process as that for forming the current blocking portion. According to the light-emitting chip of (((9))), electrical isolation is achieved by the pn junction. According to the light-emitting chip of (((10))), the reference potential and the substrate potential can be separated more reliably than when the driving unit is not enclosed. According to the light-emitting chip of (((11))), lighting control of the light-emitting elements is easier than when the on states are not shifted in sequence. According to the light emitting device of (((13))), the light emitting element can be operated at a higher speed than in the high side driving. According to the measuring device according to (((14))), a measuring device capable of performing three-dimensional measurement is provided. [Explanation of symbols]

[0182] 1, 2, 3, 4...light source device, 5...3D sensor, 10, 10', 20, 30, 40...light-emitting chip, 11...light-emitting section, 12...transfer section, 80...substrate, 81...n-cathode (DBR) layer, 82...light-emitting layer, 83...p-anode (DBR) layer, 84...tunnel junction layer, 85...n-cathode layer, 86...p-gate layer, 87...n-gate layer, 88...p-anode layer, 100...measurement device, 110, 111...control section, 200...measurement control section, 340, 341...reference potential terminal, S...setting thyristor, T...transfer thyristor, VCSEL...vertical-cavity surface-emitting laser

Claims

1. A substrate; a plurality of light-emitting elements provided on the substrate; a plurality of thyristors that, when turned on, cause the respective light-emitting elements to emit light or increase the amount of light emitted by the light-emitting elements; a driving unit provided on the substrate and configured to individually drive the plurality of thyristors to transition them to an ON state; a reference potential terminal that supplies a predetermined reference potential to the driving unit, wherein a region of the driving unit connected to the reference potential terminal is electrically isolated from a side surface of the substrate; A light emitting device comprising:

2. A semiconductor substrate; a plurality of light-emitting elements provided on the front surface side of the substrate, and a plurality of thyristors that, when turned on, cause the light-emitting elements to emit light or increase the amount of light emitted by the light-emitting elements; a driving unit provided on the front surface side of the substrate for individually driving the plurality of thyristors to transition them to an ON state; a reference potential terminal to which a predetermined reference potential is supplied to the driving unit; an isolation portion that suppresses a current flow between the reference potential terminal and the substrate; A light-emitting chip comprising:

3. The light-emitting chip according to claim 2 , wherein the separating portion prevents the driving portion from extending to an outer periphery of the substrate.

4. The light-emitting chip according to claim 2 , wherein the separating portion prevents a current path from being formed between the light-emitting element and the reference potential terminal via a side surface of the substrate.

5. the thyristor is stacked on the light-emitting element provided on the substrate, the driving unit is laminated on a structure equivalent to the light-emitting element provided on the substrate; The light-emitting chip according to claim 2 .

6. the light-emitting element, the thyristor, and the driving unit are configured by a semiconductor laminate in which a plurality of semiconductor layers of different conductivity types are laminated, The light-emitting chip according to claim 5 , wherein the separating portion is a groove provided in the semiconductor laminate and / or a region in which insulating ions are implanted into the semiconductor laminate.

7. the light-emitting element and the structure have a diode structure in which a p-type semiconductor layer serving as an anode and an n-type semiconductor layer serving as a cathode are stacked, the groove or the region into which the insulating ions are implanted extends from the surface side of the substrate to at least the p-type semiconductor layer and the n-type semiconductor layer constituting the diode structure, the p-type semiconductor layer and the n-type semiconductor layer being farther from the substrate side; The light-emitting chip according to claim 6 .

8. The light-emitting element has a current confinement layer, which is a region that is oxidized to make it difficult for a current to flow, The light-emitting chip according to claim 6 , wherein the depth of the groove reaches the current confinement layer.

9. The reference potential is applied to the side of a diode structure in which a p-type semiconductor layer serving as the anode of the structure and an n-type semiconductor layer serving as the cathode are stacked, the side being farther from the substrate. The light-emitting chip according to claim 5 .

10. The light-emitting chip according to claim 6 , wherein the groove and / or the region into which insulating ions are implanted is provided so as to surround the driving portion.

11. The driving unit sequentially shifts the on-state of the plurality of thyristors. The light-emitting chip according to claim 2 .

12. A semiconductor substrate; a plurality of light-emitting elements provided on the front surface side of the substrate; a plurality of thyristors stacked on the light emitting element, which are turned on to cause the light emitting element to emit light or increase the amount of light emitted by the light emitting element; a reference potential terminal provided on a structure equivalent to the light emitting element and supplied with a predetermined reference potential; a separation portion that prevents a current path from being formed between the reference potential terminal and the light emitting element via a side surface of the substrate; A light-emitting chip comprising:

13. The light-emitting chip according to any one of claims 2 to 12, a driver having one end set to a ground potential and the other end connected to the substrate of the light-emitting chip, and transitioning to an ON state at a predetermined timing to cause a current for light emission to flow through the light-emitting element; A light emitting device comprising:

14. A light emitting device according to claim 13; an acquisition unit that acquires information about an object based on light reflected by the object from the light emitting device; A measuring device comprising:

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