Field-effect transistor and method for manufacturing the same

Abstract

To suppress leak currents and oxidation of SiC in the interface between the gate insulating film and an SiC substrate.SOLUTION: A method for manufacturing a field-effect transistor includes: forming a first gate insulating film on a surface of a SiC substrate by deposition; forming a silicon film on a surface of the first gate insulating film by deposition; forming a second gate insulating film on a surface of the silicon film by deposition; and annealing the SiC substrate in nitrogen oxide gas after formation of the second gate insulating film.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a field effect transistor and a method for manufacturing the same.

[0002] A technique is known in which a SiC substrate (i.e., a silicon carbide substrate) provided with a gate insulating film is annealed in nitrogen oxide gas (e.g., NO, NO, etc.). Annealing in this manner causes nitridation of the SiC substrate at the interface between the SiC substrate and the gate insulating film. This reduces the defect density at the interface between the SiC substrate and the gate insulating film. However, with this technique, not only nitridation but also oxidation occurs at the interface between the SiC substrate and the gate insulating film. Because defects are generated by the oxidation of the SiC substrate, there is a limit to how much this technique can reduce the defect density.

[0003] Patent Document 1 discloses a technique for forming a thin silicon film on the surface of a SiC substrate and then forming a gate insulating film on the silicon film. In this technique, oxidation of the SiC substrate at the interface between the SiC substrate and the gate insulating film is suppressed by oxidizing the silicon film. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2021-192397 Summary of the Invention [Problem to be solved by the invention]

[0005] By performing annealing in nitrogen oxide gas with a thin silicon film present on the surface of a SiC substrate, the silicon film is oxidized, thereby suppressing oxidation of the SiC substrate. In other words, this method allows the SiC substrate to be nitrided while suppressing oxidation of the SiC substrate. However, this method may result in the silicon film remaining without being sufficiently oxidized. That is, the silicon film may remain at the interface between the gate insulating film and the SiC substrate. When the silicon film remains in this manner, leakage current occurs through the silicon film. This specification proposes a technology for suppressing oxidation of the SiC substrate at the interface between the gate insulating film and the SiC substrate, while also suppressing leakage current. [Means for solving the problem]

[0006] The method for manufacturing a field-effect transistor disclosed in this specification includes the steps of forming a first gate insulating film on a surface of a SiC substrate by a deposition method, forming a silicon film on the surface of the first gate insulating film by a deposition method, forming a second gate insulating film on the surface of the silicon film by a deposition method, and annealing the SiC substrate in nitrogen oxide gas after the formation of the second gate insulating film.

[0007] The deposition method may be any of CVD (chemical vapor deposition), LPE (liquid phase epitaxy), ALD (atomic layer deposition), MBE (molecular beam epitaxy), etc. The first gate insulating film, the silicon film, and the second gate insulating film may be formed by different deposition methods.

[0008] In this manufacturing method, a silicon film is formed between a first gate insulating film and a second gate insulating film. When the SiC substrate is annealed in nitrogen oxide gas, the silicon film is oxidized by the nitrogen oxide gas, thereby suppressing oxidation of the SiC substrate. Therefore, this manufacturing method can effectively reduce the defect density at the interface between the SiC substrate and the gate insulating film. Furthermore, even if a portion of the silicon film remains unoxidized during annealing, the silicon film is insulated from the SiC substrate because the first gate insulating film exists between the silicon film and the SiC substrate. Therefore, leakage current through the silicon film can be suppressed. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 2 is an explanatory diagram of the manufacturing method of the first embodiment. [Figure 2] FIG. 2 is an explanatory diagram of the manufacturing method of the first embodiment. [Figure 3] FIG. 2 is an explanatory diagram of the manufacturing method of the first embodiment. [Figure 4] FIG. 2 is an explanatory diagram of the manufacturing method of the first embodiment. [Figure 5] FIG. 2 is an explanatory diagram of the manufacturing method of the first embodiment. [Figure 6] FIG. 2 is an explanatory diagram of the manufacturing method of the first embodiment. [Figure 7] 1 is a cross-sectional view of a field-effect transistor manufactured by the manufacturing method of Example 1. FIG. [Figure 8] FIG. 10 is a cross-sectional view of a field effect transistor in which the silicon film 34 remains. [Figure 9] FIG. 10 is an explanatory diagram of a manufacturing method according to a second embodiment. [Figure 10] FIG. 10 is an explanatory diagram of a manufacturing method according to a second embodiment. [Figure 11] FIG. 10 is an explanatory diagram of a manufacturing method according to a second embodiment. [Figure 12] FIG. 10 is an explanatory diagram of a manufacturing method according to a second embodiment. [Figure 13] FIG. 10 is an explanatory diagram of a manufacturing method according to a second embodiment. [Figure 14] FIG. 10 is an explanatory diagram of a manufacturing method according to a second embodiment. [Figure 15] FIG. 10 is an explanatory diagram of a manufacturing method according to a second embodiment. [Figure 16]FIG. 10 is a cross-sectional view of a field-effect transistor manufactured by the manufacturing method of Example 2. [Figure 17] FIG. 10 is a cross-sectional view of a field effect transistor in which the silicon film 34 remains. [Figure 18] FIG. 10 is an explanatory diagram of a manufacturing method according to a third embodiment. [Figure 19] FIG. 10 is an explanatory diagram of a manufacturing method according to a third embodiment. [Figure 20] FIG. 10 is an explanatory diagram of a manufacturing method according to a third embodiment. [Figure 21] FIG. 10 is an explanatory diagram of a manufacturing method according to a third embodiment. [Figure 22] FIG. 10 is an explanatory diagram of a manufacturing method according to a third embodiment. [Figure 23] FIG. 10 is an explanatory diagram of a manufacturing method according to a third embodiment. [Figure 24] FIG. 10 is a cross-sectional view of a field-effect transistor manufactured by the manufacturing method of Example 3. [Figure 25] FIG. 10 is a cross-sectional view of a field effect transistor in which the silicon film 34 remains. DETAILED DESCRIPTION OF THE INVENTION

[0010] In the exemplary manufacturing method disclosed herein, the first gate insulating film may be made of silicon oxide or silicon nitride, and the second gate insulating film may be made of silicon oxide or silicon nitride.

[0011] In one example of the manufacturing method disclosed in the present specification, the SiC substrate may have an n-type source region, a p-type body region, and an n-type drain region, and the first gate insulating film, the silicon film, and the second gate insulating film may be formed to cover the source region, the body region, and the drain region.

[0012] The field effect transistor disclosed in this specification includes a SiC substrate, a first gate insulating film covering a surface of the SiC substrate, a silicon film covering the surface of the first gate insulating film, a second gate insulating film covering the surface of the silicon film, and a gate electrode covering the surface of the second gate insulating film. [Example]

[0013] In the manufacturing method of Example 1, a field effect transistor is manufactured from a SiC substrate 12 shown in FIG. 1. The SiC substrate 12 has a p-type body region 20, an n-type drain region 22, and an n-type source region 24. The drain region 22 and the source region 24 are disposed in positions exposed on the upper surface 12a of the SiC substrate 12. The body region 20 is distributed from the region between the drain region 22 and the source region 24 to the region below the drain region 22 and the source region 24. Between the drain region 22 and the source region 24, the body region 20 is exposed on the upper surface 12a. The drain region 22 is separated from the source region 24 by the body region 20.

[0014] In the manufacturing method of Example 1, first, a first gate insulating film forming step is performed. In the first gate insulating film forming step, as shown in FIG. 2, a first gate insulating film 31 is formed on the upper surface 12a of the SiC substrate 12 by a deposition method. The body region 20, the drain region 22, and the source region 24 are covered with the first gate insulating film 31. The deposition method used in the first gate insulating film forming step is not particularly limited, but a method capable of suppressing oxidation of the SiC substrate 12, such as plasma CVD or low-temperature thermal CVD, can be used. The first gate insulating film 31 may be made of silicon oxide or silicon nitride.

[0015] Next, a silicon film formation process is performed. In the silicon film formation process, as shown in FIG. 3, a silicon film 34 is formed on the entire upper surface of the first gate insulating film 31 by a deposition method. Therefore, the upper portions of the body region 20, the drain region 22, and the source region 24 are covered with the silicon film 34. The deposition method used in the silicon film formation process is not particularly limited, but a method capable of suppressing oxidation of the SiC substrate 12, such as plasma CVD or low-temperature thermal CVD, can be used. The silicon film 34 is a film made of elemental silicon. The silicon film 34 may be single crystal silicon, polycrystalline silicon, or amorphous silicon.

[0016] Next, a second gate insulating film formation step is performed. In the second gate insulating film formation step, as shown in FIG. 4, a second gate insulating film 32 is formed on the entire upper surface of the silicon film 34 by a deposition method. Therefore, the upper parts of the body region 20, the drain region 22, and the source region 24 are covered with the second gate insulating film 32. The deposition method used in the second gate insulating film formation step is not particularly limited, but a method that can suppress oxidation of the SiC substrate 12, such as plasma CVD or low-temperature thermal CVD, can be used. The second gate insulating film 32 may be made of silicon oxide or silicon nitride.

[0017] Next, a nitrogen termination process is performed. In the nitrogen termination process, the SiC substrate 12 is annealed in nitrogen oxide gas. Examples of the nitrogen oxide gas that can be used include NO gas and NO gas. Annealing the SiC substrate 12 in nitrogen oxide gas nitrides the SiC substrate 12 at the interface 12x between the SiC substrate 12 and the first gate insulating film 31. In the nitrogen termination process, the silicon film 34 is oxidized by the nitrogen oxide gas to form a silicon oxide film 34a, as shown in FIG. 5 . The oxidation of the silicon film 34 suppresses oxidation of the SiC substrate 12 at the interface 12x. Thus, in the nitrogen termination process, the SiC substrate 12 can be nitrided while suppressing oxidation of the SiC substrate 12 at the interface 12x. This effectively reduces the density of defects (i.e., interface states) at the interface 12x. The silicon oxide film 34a oxidized in the nitrogen termination process is integrated with the first gate insulating film 31 and the second gate insulating film 32 to form a gate insulating film.

[0018] Next, as shown in Fig. 6, the gate insulating film is removed from above the drain region 22 and the source region 24 to form openings 42 and 44. Next, as shown in Fig. 7, a gate electrode 36 is formed on the gate insulating film. Furthermore, a drain electrode 52 is formed in the opening 42, and a source electrode 54 is formed in the opening 44. Through the above steps, an n-channel field effect transistor 10 is completed.

[0019] When a potential equal to or higher than the gate threshold is applied to the gate electrode 36, a channel is formed in a region 20a adjacent to the gate insulating film in the body region 20. Electrons flow from the source region 24 to the drain region 22 through the channel. In the field-effect transistor 10, the interface state density is low at the interface 12x between the gate insulating film and the SiC substrate 12. Therefore, the channel resistance of the field-effect transistor 10 is low.

[0020] Furthermore, in the nitrogen termination step, the silicon film 34 may not be entirely oxidized, and the silicon film 34 may remain between the first gate insulating film 31 and the second gate insulating film 32, as shown in Fig. 8. Even when the silicon film 34 remains in this manner, the silicon film 34 is insulated from the SiC substrate 12 by the first gate insulating film 31. Therefore, it is possible to prevent leakage current from flowing between the source and drain via the silicon film 34. [Example]

[0021] In the manufacturing method of Example 2, a field effect transistor is manufactured from a SiC substrate 12 shown in FIG. 9. The SiC substrate 12 has a p-type body region 20, an n-type drain region 22, and an n-type source region 24. The drain region 22 has a high-concentration region 22a and a low-concentration region 22b. The low-concentration region 22b is a so-called drift region and has a lower n-type impurity concentration than the high-concentration region 22a. The source region 24 is disposed at a position exposed on the upper surface 12a of the SiC substrate 12. The body region 20 is disposed below the source region 24. The low-concentration region 22b is disposed below the body region 20. The low-concentration region 22b is separated from the source region 24 by the body region 20. The high-concentration region 22a is disposed below the low-concentration region 22b and is exposed on the lower surface 12b of the SiC substrate 12.

[0022] In the manufacturing method of Example 2, a trench formation process is first performed. In the trench formation process, as shown in Fig. 10, the upper surface 12a of the SiC substrate 12 is selectively etched to form a trench 14 in the upper surface 12a. Here, the trench 14 is formed so as to penetrate the source region 24 and the body region 20 and reach the low-concentration region 22b.

[0023] Next, a first gate insulating film formation step is performed. In the first gate insulating film formation step, as shown in FIG. 11 , a first gate insulating film 31 is formed by a deposition method on the inner surface of the trench 14 and on the upper surface 12a of the SiC substrate 12. The body region 20, the low-concentration region 22b, and the source region 24 are covered with the first gate insulating film 31. The deposition method used in the first gate insulating film formation step is not particularly limited, but a method capable of suppressing oxidation of the SiC substrate 12, such as plasma CVD or low-temperature thermal CVD, can be used. The first gate insulating film 31 may be made of silicon oxide or silicon nitride.

[0024] Next, a silicon film formation process is performed. In the silicon film formation process, as shown in FIG. 12, a silicon film 34 is formed on the entire surface of the first gate insulating film 31 by a deposition method. Therefore, the body region 20, the low-concentration region 22b, and the source region 24 on the side surface of the trench 14 are covered with the silicon film 34. The deposition method used in the silicon film formation process is not particularly limited, but a method capable of suppressing oxidation of the SiC substrate 12, such as plasma CVD or low-temperature thermal CVD, can be used. The silicon film 34 is a film made of elemental silicon. The silicon film 34 may be single-crystal silicon, polycrystalline silicon, or amorphous silicon.

[0025] Next, a second gate insulating film formation step is performed. In the second gate insulating film formation step, as shown in FIG. 13, a second gate insulating film 32 is formed on the entire surface of the silicon film 34 by a deposition method. Therefore, the body region 20, the low-concentration region 22b, and the source region 24 on the side surface of the trench 14 are covered with the second gate insulating film 32. The deposition method used in the second gate insulating film formation step is not particularly limited, but a method capable of suppressing oxidation of the SiC substrate 12, such as plasma CVD or low-temperature thermal CVD, can be used. The second gate insulating film 32 may be made of silicon oxide or silicon nitride.

[0026] Next, a nitrogen termination process is performed. In the nitrogen termination process, the SiC substrate 12 is annealed in nitrogen oxide gas. Examples of the nitrogen oxide gas that can be used include NO gas and NO gas. When the SiC substrate 12 is annealed in the nitrogen oxide gas, the SiC substrate 12 is nitrided at the interface 12x between the SiC substrate 12 and the first gate insulating film 31. Furthermore, in the nitrogen termination process, as shown in FIG. 14 , the silicon film 34 is oxidized by the nitrogen oxide gas to form a silicon oxide film 34a. The oxidation of the silicon film 34 suppresses oxidation of the SiC substrate 12 at the interface 12x. Thus, in the nitrogen termination process, the SiC substrate 12 can be nitrided while suppressing oxidation of the SiC substrate 12 at the interface 12x. Therefore, the density of defects (i.e., interface states) at the interface 12x can be effectively reduced. The silicon oxide film 34a oxidized in the nitrogen termination process is integrated with the first gate insulating film 31 and the second gate insulating film 32 to form a gate insulating film.

[0027] Next, as shown in FIG. 15, a gate electrode 36 is formed in the trench 14. Next, the gate insulating film covering the upper surface 12a of the SiC substrate 12 is removed. Next, an interlayer insulating film 38 is formed on the gate electrode 36. Next, as shown in FIG. 16, a source electrode 54 is formed on the upper surface 12a of the SiC substrate 12 in contact with the source region 24. The source electrode 54 is insulated from the gate electrode 36 by the interlayer insulating film 38. Next, a drain electrode 52 is formed on the lower surface 12b of the SiC substrate 12 in contact with the high-concentration region 22a. Through the above steps, an n-channel field-effect transistor 100 is completed.

[0028] When a potential equal to or higher than the gate threshold is applied to the gate electrode 36, a channel is formed in a region 20a adjacent to the gate insulating film in the body region 20 (i.e., a region near the side surface of the trench 14). Electrons flow from the source region 24 to the drain region 22 through the channel. In the field-effect transistor 100, the interface state density is low at the interface 12x between the gate insulating film and the SiC substrate 12. Therefore, the channel resistance of the field-effect transistor 100 is low.

[0029] Furthermore, in the nitrogen termination step, the silicon film 34 may not be entirely oxidized, and the silicon film 34 may remain between the first gate insulating film 31 and the second gate insulating film 32, as shown in Fig. 17. Even when the silicon film 34 remains in this way, the silicon film 34 is insulated from the SiC substrate 12 by the first gate insulating film 31. Therefore, it is possible to prevent leakage current from flowing between the source and the drain via the silicon film 34. [Example]

[0030] In the manufacturing method of Example 3, a field-effect transistor is manufactured from a SiC substrate 12 shown in FIG. 18. The SiC substrate 12 has a p-type body region 20, an n-type drain region 22, and an n-type source region 24. The drain region 22 has a high-concentration region 22a and a low-concentration region 22b. The low-concentration region 22b is a so-called drift region and has a lower n-type impurity concentration than the high-concentration region 22a. The source region 24 is disposed at a position exposed on the upper surface 12a of the SiC substrate 12. The body region 20 is disposed around the source region 24. The body region 20 is exposed on the upper surface 12a of the SiC substrate 12 at a position adjacent to the source region 24. The low-concentration region 22b is disposed around the body region 20. The low-concentration region 22b is separated from the source region 24 by the body region 20. The low-concentration region 22b is exposed on the upper surface 12a of the SiC substrate 12 at a position adjacent to the body region 20. The high concentration region 22 a is disposed below the low concentration region 22 b and is exposed at the lower surface 12 b of the SiC substrate 12 .

[0031] 19 , in the manufacturing method of Example 3, similarly to Example 1, a first gate insulating film 31, a silicon film 34, and a second gate insulating film 32 are formed by a deposition method on the upper surface 12a of the SiC substrate 12. Here, the surfaces of the source region 24, the body region 20, and the low-concentration region 22b are covered with the first gate insulating film 31, the silicon film 34, and the second gate insulating film 32.

[0032] Next, a nitrogen termination process is performed. In the nitrogen termination process, the SiC substrate 12 is annealed in nitrogen oxide gas. Examples of the nitrogen oxide gas that can be used include NO gas and NO gas. When the SiC substrate 12 is annealed in the nitrogen oxide gas, the SiC substrate 12 is nitrided at the interface 12x between the SiC substrate 12 and the first gate insulating film 31. Furthermore, in the nitrogen termination process, as shown in FIG. 20 , the silicon film 34 is oxidized by the nitrogen oxide gas to form a silicon oxide film 34a. The oxidation of the silicon film 34 suppresses oxidation of the SiC substrate 12 at the interface 12x. Thus, in the nitrogen termination process, the SiC substrate 12 can be nitrided while suppressing oxidation of the SiC substrate 12 at the interface 12x. Therefore, the density of defects (i.e., interface states) at the interface 12x can be effectively reduced. The silicon oxide film 34a oxidized in the nitrogen termination process is integrated with the first gate insulating film 31 and the second gate insulating film 32 to form a gate insulating film.

[0033] Next, as shown in FIG. 21, an opening 42 is formed by removing a portion of the gate insulating film. Parts of the source region 24 and the body region 20 are exposed in the opening 42. Next, as shown in FIG. 22, a gate electrode 36 is formed on the gate insulating film. Next, as shown in FIG. 23, an interlayer insulating film 38 is formed to cover the gate electrode 36. Next, as shown in FIG. 24, a source electrode 54 is formed to cover the interlayer insulating film 38. The source electrode 54 contacts the source region 24 and the body region 20 in the opening 42. Next, a drain electrode 52 is formed on the lower surface 12b of the SiC substrate 12. Through the above steps, an n-channel field effect transistor 200 is completed.

[0034] When a potential equal to or higher than the gate threshold is applied to the gate electrode 36, a channel is formed in the region 20a adjacent to the gate insulating film in the body region 20. Electrons flow from the source region 24 to the drain region 22 through the channel. In the field-effect transistor 10, the interface state density is low at the interface 12x between the gate insulating film and the SiC substrate 12. Therefore, the channel resistance of the field-effect transistor 200 is low.

[0035] 25, the silicon film 34 may not be entirely oxidized, and may remain between the first gate insulating film 31 and the second gate insulating film 32. Even when the silicon film 34 remains in this manner, the silicon film 34 is insulated from the SiC substrate 12 by the first gate insulating film 31. This prevents leakage current from flowing between the source and drain via the silicon film 34.

[0036] As described above, in the manufacturing methods of Examples 1 to 3, leakage current can be suppressed even if the silicon film 34 remains. Therefore, it is possible to form a relatively thick silicon film 34, and oxidation of the SiC substrate 12 can be suppressed even if the nitrogen termination treatment is performed for a long period of time. This makes it easier to manage the nitrogen termination treatment process.

[0037] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0038] 10: Field effect transistor, 12: SiC substrate, 20: Body region, 22: Drain region, 24: Source region, 31: First gate insulating film, 32: Second gate insulating film, 34: Silicon film, 34a: Silicon oxide film

Claims

1. A method for manufacturing a field effect transistor, comprising: forming a first gate insulating film (31) on a surface of the SiC substrate (12) by a deposition method; forming a silicon film (34) on the surface of the first gate insulating film by a deposition method; forming a second gate insulating film (32) on the surface of the silicon film by a deposition method; annealing the SiC substrate in nitrogen oxide gas after forming the second gate insulating film; A manufacturing method comprising the steps of:

2. the first gate insulating film is made of silicon oxide or silicon nitride, the second gate insulating film is made of silicon oxide or silicon nitride; The method of claim 1.

3. The SiC substrate has an n-type source region (24), a p-type body region (20), and an n-type drain region (22); the first gate insulating film, the silicon film, and the second gate insulating film are formed to cover the source region, the body region, and the drain region; The method of claim 1.

4. A field effect transistor, a SiC substrate; a first gate insulating film covering a surface of the SiC substrate; a silicon film covering a surface of the first gate insulating film; a second gate insulating film covering a surface of the silicon film; a gate electrode covering a surface of the second gate insulating film; A field effect transistor having

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