Bonded substrate and manufacturing method for the bonded substrate

Abstract

To provide a bonded substrate in which defective reading of an identification mark is suppressed as compared with a conventional bonded substrate.SOLUTION: The present invention provides a bonded substrate 100. In the bonded substrate 100 having a heat radiation layer, a ceramic plate 10, and a metal circuit layer 20 in this order, an identification mark 30 is provided on at least one of the heat radiation layer and the metal circuit layer 20. The identification mark 30 has a code region and an outer peripheral region located on an outer periphery of the code region. The code region includes: a first region including a plurality of grooves having a first a depth and a plurality of grooves having a first b depth larger than the first a depth; and a second region including a plurality of grooves having a second depth larger than the first a depth. The outer peripheral region includes a third region including the plurality of grooves having a third depth larger than the first a depth.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a bonded substrate and a method for manufacturing the bonded substrate. [Background technology]

[0002] Insulating ceramic substrates are sometimes used as individual substrates mounted on electronic devices. A multi-piece wiring board for obtaining such individual substrates is known to have a plurality of wiring board regions arranged vertically and horizontally, with dummy regions provided on the periphery, and a symbol pattern consisting of voids in the inner layer of each wiring board region (see, for example, Patent Document 1). By analyzing such a symbol pattern using an ultrasonic flaw detector or X-rays, the arrangement positions of the wiring board regions can be detected.

[0003] Among symbol patterns, two-dimensional codes are increasingly being adopted due to their ability to store a large amount of information. Two-dimensional codes are codes that imprint or print data, such as letters and numbers, on a substrate using two-dimensional graphic patterns. Many types of two-dimensional codes are known, depending on the shape of the pattern. For example, matrix-type two-dimensional codes have a grid-like pattern within a specified area. Matrix-type two-dimensional codes have processed areas (processed areas) and unprocessed areas within the specified area, allowing information to be recorded and read based on the number and arrangement of these processed areas. To read such two-dimensional codes, a method is used in which a pattern (finder pattern) for detecting the position of the two-dimensional code is first read, followed by reading the information within the two-dimensional code area.

[0004] For identification marks such as two-dimensional codes, substrates having identification marks provided on a ceramic substrate are known from the viewpoint of traceability (e.g., Patent Documents 2 and 3). Patent Document 2 describes a bonded substrate including a ceramic plate including a plurality of partitions defined by partition lines formed on at least one of a first main surface and a second main surface, and a pair of metal plates bonded to the ceramic plate so as to cover the first main surface and the second main surface, respectively, at least one of the pair of metal plates having a plurality of first identification marks on a surface. Patent Document 3 also describes a circuit board having a circuit formation portion and a dummy portion, the circuit board including a ceramic plate and a plurality of conductor portions bonded to a main surface of the ceramic plate, the plurality of conductor portions including a first conductor portion provided in the dummy portion and a second conductor portion provided in the circuit formation portion, and the circuit board having a first identification mark on a surface of the first conductor portion. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-210028 [Patent Document 2] International Publication No. 2023 / 008199 [Patent Document 3] International Publication No. 2023 / 008200 Summary of the Invention [Problem to be solved by the invention]

[0006] In the above-described circuit board, there have been cases where the identification mark formed on the metal plate has not been read properly.

[0007] An object of the present disclosure is to provide a bonded substrate in which reading errors of an identification mark are reduced compared to conventional bonded substrates, and a method for manufacturing the same. [Means for solving the problem]

[0008] Through research by the present inventors, it was found that when a two-dimensional code is formed on the main surface of a metal layer (e.g., a heat dissipation layer or a metal circuit layer), grain boundaries and scratches between metal grains caused by the conditions for forming the metal layer are also apparent on the main surface of the metal layer, which is one of the causes of read errors. More specifically, it was found that grain boundaries and the like present on the surface of the metal layer can be mistaken for processed areas of the two-dimensional code, and the presence of such grain boundaries and the like can prevent the finder pattern from being accurately read, making the boundary between the two-dimensional code and other areas unclear and resulting in poor determination of the area where the code is provided. Furthermore, when grain boundaries are located in unprocessed areas within the two-dimensional code, the difference from the processed area becomes unclear, hindering reading of the information. The present disclosure has been made based on the above findings.

[0009] This disclosure provides the following [1].

[0010] [1] A bonded substrate having a heat dissipation layer, a ceramic plate, and a metal circuit layer in this order, an identification mark on at least one of the heat dissipation layer and the metal circuit layer; the identification mark has a code area and an outer peripheral area located on the outer periphery of the code area, The coding region a first region including a plurality of grooves having a depth 1a and a plurality of grooves having a depth 1b greater than the depth 1a; a second region including a plurality of grooves having a second depth greater than the 1a depth; the outer peripheral region includes a third region having a plurality of grooves having a third depth greater than the 1a depth; Bonding substrate.

[0011] In the above-mentioned bonding substrate, an identification mark provided on at least one of the heat dissipation layer and the metal circuit layer has an outer peripheral region including multiple grooves around the code region, thereby reducing the effect of grain boundaries extending in the in-plane direction on the main surface of the heat dissipation layer or the metal circuit layer on reading the identification mark. Furthermore, the above-mentioned bonding substrate also has a second region including multiple grooves as a region other than the first region within the code region, thereby making it possible to recognize the number and arrangement of multiple first regions including multiple grooves of different depths. Due to the above-mentioned effects, the above-mentioned bonding substrate reduces reading errors of the identification mark compared to conventional bonding substrates.

[0012] The bonded substrate may be any of the following [2] to

[13] .

[0013] [2] The bonded substrate according to [1], wherein the ratio of the first depth to the second depth is 0.60 or less. [3] The bonded substrate according to [1] or [2], wherein the ratio of the 1a depth to the third depth is 0.60 or less. [4] The bonded substrate according to any one of [1] to [3], wherein the groove width of the groove having the second depth in the second region is 1.5 times or more the groove width of the groove having the 1a depth in the first region. [5] The bonded substrate according to any one of [1] to [4], wherein the groove width of the groove having the third depth in the third region is 0.8 to 1.2 times the groove width of the groove having the second depth in the second region. [6] The bonded substrate according to any one of [1] to [5], wherein the width between adjacent grooves in the second region is less than 5.0 times the groove width of the groove having the second depth. [7] The bonded substrate according to any one of [1] to [6], wherein the width between adjacent grooves in the third region is less than 5.0 times the groove width of the groove having the third depth. [8] The coding region has a parallelogram shape; The bonded substrate according to any one of [1] to [7], wherein the minimum width of the outer peripheral region is at least 0.05 times the length of the long side of the code region. [9] The bonded substrate according to any one of [1] to [8], wherein the shortest distance between the end of the code region and the end of the outer circumferential region opposite to the code region side is 80 μm or more.

[10] The code region is a Data Matrix code, The bonded substrate according to any one of [1] to [9], wherein the minimum width of the outer peripheral region is at least twice the length of one side of the unit cell.

[11] The bonded substrate according to any one of [1] to

[10] , wherein at least one of the heat dissipation layer and the metal circuit layer contains copper.

[0014] One aspect of the present disclosure also provides the following

[12] .

[0015]

[12] A method for manufacturing a laminate including a heat dissipation layer, a ceramic plate, and a metal circuit layer in this order, comprising forming an identification mark on at least one of the heat dissipation layer and the metal circuit layer; the identification mark has a code area and an outer peripheral area located on the outer periphery of the code area, The coding region a first region including a plurality of grooves having a depth 1a and a plurality of grooves having a depth 1b greater than the depth 1a; a second region including a plurality of grooves having a second depth greater than the 1a depth; the outer peripheral region includes a third region having a plurality of grooves having a third depth greater than the 1a depth; A method for manufacturing a bonded substrate.

[0016] The above-described method for manufacturing a bonded substrate includes a step of forming a predetermined identification mark having a predetermined peripheral region, and therefore, it is possible to manufacture a bonded substrate in which reading errors of the identification mark are reduced compared to conventional bonded substrates.

[0017] The manufacturing method may be the following

[13] .

[0018]

[13] The manufacturing method according to

[12] , wherein the step is a step of forming the identification mark by laser processing. [Effects of the Invention]

[0019] According to the present disclosure, it is possible to provide a bonded substrate and a manufacturing method thereof in which reading errors of an identification mark are reduced compared to conventional bonded substrates. [Brief explanation of the drawings]

[0020] [Figure 1] FIG. 1 is a perspective view showing an example of a bonded substrate. [Figure 2] FIG. 2 is a schematic diagram for explaining the configuration of the identification mark. [Figure 3] FIG. 3 is a schematic diagram showing an example in which the code region is a data matrix code. [Figure 4] FIG. 4 is a schematic diagram showing a part of a cross section perpendicular to the main surface of the metal circuit layer taken along line IV-IV in FIG. [Figure 5] FIG. 5 is a schematic diagram showing an example of a manufacturing process for the first region. [Figure 6] FIG. 6 is a photograph showing the identification mark portions of the bonded substrates produced in Examples 1 to 4 and Comparative Example 1 as viewed from above. [Figure 7] FIG. 7 is an SEM image of a cross section of the identification mark of the bonded substrate of Example 1. [Figure 8] FIG. 8 is an SEM image of a cross section of the identification mark of the bonded substrate of Example 2. [Figure 9] FIG. 9 is an SEM image of a cross section of the identification mark of the bonded substrate of Example 3. DETAILED DESCRIPTION OF THE INVENTION

[0021] An embodiment of the present disclosure will be described below, with reference to the drawings where appropriate. However, the following embodiment is an example for explaining the present disclosure and is not intended to limit the present disclosure to the following content. In the description, the same elements or elements having the same functions will be designated by the same reference numerals, and redundant explanations will be omitted where appropriate. Furthermore, unless otherwise specified, positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings. Furthermore, the dimensional ratios of each element are not limited to those shown in the drawings.

[0022] (bonded substrate) One embodiment of a bonding substrate according to the present disclosure includes a heat dissipation layer, a ceramic plate, and a metal circuit layer, in this order. The bonding substrate includes an identification mark on at least one of the heat dissipation layer and the metal circuit layer. The identification mark may be provided on the main surface of the heat dissipation layer opposite the ceramic plate, or on the main surface of the metal circuit layer opposite the ceramic plate. The identification mark may be formed directly on the heat dissipation layer or the metal circuit layer, or may be formed on a plating layer provided on the heat dissipation layer or the metal circuit layer. In this case, the bonding substrate includes a first plating layer, a heat dissipation layer, a ceramic plate, a metal circuit layer, and a second plating layer, in this order, and the identification mark is provided directly on the first plating layer or the second plating layer.

[0023] FIG. 1 is a perspective view showing an example of a bonded substrate. The bonded substrate 100 of FIG. 1 has a heat dissipation layer (not shown), a ceramic plate 10, and a metal circuit layer 20. The heat dissipation layer is provided on the surface of the ceramic plate 10 opposite the metal circuit layer 20. The metal circuit layer 20 is bonded to a main surface of the ceramic plate 10, and may be bonded via a bonding layer (not shown). The heat dissipation layer is bonded to a main surface of the ceramic plate 10, and may be bonded via a bonding layer (not shown). The metal circuit layer 20 has an identification mark 30 on a main surface 20A opposite to the ceramic plate 10. FIG. 1 shows an example in which the bonded substrate 100 has one identification mark 30, but this is not limited thereto and the bonded substrate 100 may have two or more identification marks 30. 1 shows an example in which the identification mark 30 is provided in a peripheral region including the end of the metal circuit layer 20, but the position of the identification mark 30 is not limited thereto. For example, if the metal circuit layer 20 has a circuit pattern, the identification mark may be provided so as to avoid the pattern. Although the bonding substrate 100 is shown as having the identification mark 30 on the metal circuit layer 20, the identification mark may also be provided on the heat dissipation layer. The following description will be based on an example in which the identification mark 30 is provided on the metal circuit layer 20.

[0024] The ceramic plate 10 may be, for example, a nitride sintered plate, a ceramic plate containing aluminum nitride or silicon nitride, an aluminum nitride plate, or a silicon nitride plate. From the viewpoint of excellent thermal conductivity and insulation, the ceramic plate 10 may be, for example, a silicon nitride plate.

[0025] The shape of the ceramic plate 10 may be, for example, square, rectangular, or circular.

[0026] The thickness of the ceramic plate 10 may be, for example, 0.20 to 1.50 mm, 0.25 to 1.00 mm, 0.50 to 1.00 mm, or 0.50 to 0.80 mm.

[0027] The thickness of the plate or layer in this specification refers to the arithmetic mean value of the thickness measured with a micrometer at any 10 points on the plate or layer to be measured.

[0028] The thickness of the metal circuit layer 20 may be any thickness that allows the identification mark 30 to be formed, and may be, for example, 0.1 mm or more, 0.2 mm or more, or 0.3 mm or more. From the viewpoint of improving heat cycle characteristics, the upper limit of the thickness of the metal circuit layer 20 may be, for example, 2.0 mm or less, or 1.2 mm or less.

[0029] The metal circuit layer 20 may contain metals such as copper, aluminum, magnesium, iron, silicon, tin, zinc, silver, nickel, and chromium, and may be made of copper from the viewpoint of excellent heat dissipation. The metal circuit layer 20 may be a rolled copper plate or the like. When the metal circuit layer contains copper, the copper may be oxygen-free copper. The metal circuit layer 20 may be a polycrystalline body, and for example, a copper plate or an aluminum plate may be made of a polycrystalline body.

[0030] When metal circuit layer 20 contains copper, grain boundaries are likely to become apparent on main surface 20A of metal circuit layer 20, which is thought to make it easier for reading errors to occur in identification mark 30 formed on main surface 20A of metal circuit layer 20. However, the bonding substrate according to the present disclosure can suppress the effects of grain boundaries as described above by having the above-described configuration, which includes the formation of multiple grooves in identification mark 30. Therefore, the effects of the present disclosure are more pronounced when metal circuit layer 20 contains copper.

[0031] The heat dissipation layer is a metal layer for heat dissipation. The thickness of the heat dissipation layer, the metal type constituting the heat dissipation layer, and the like can be applied by substituting the above description of the metal circuit layer 20 for the heat dissipation layer. The metal type constituting the heat dissipation layer may be the same as or different from that of the metal circuit layer 20, but it is desirable that they be the same from the viewpoint of more easily preventing warping of the bonded substrate.

[0032] The identification mark 30 may be provided to identify the bonded substrate 100. The identification mark 30 may be a code associated with some information. Examples of the information include information related to the lot, manufacturing history, product type, application, quality, and manufacturing conditions. By using the identification mark 30, it is possible to optimize manufacturing conditions and improve quality, process control accuracy, traceability, and the like.

[0033] The identification mark 30 may be, for example, encoded with one or more of the following pieces of information (a), (b), (c), and (d): (a) Information about the raw materials used to manufacture the green sheets for the bonded substrate (b) Information on molding conditions for the above green sheets (c) Information about the release agent used when laminating the above green sheets (d) Serial number (serial number) of the above green sheet or bonded substrate

[0034] The identification mark 30 is configured to be detectable by an imaging device such as a camera or video. The imaging device may have an information processing unit that compares the captured image with pre-recorded information and outputs information based on the comparison result.

[0035] FIG. 2 is a schematic diagram illustrating the configuration of an identification mark. The identification mark 30 formed on the main surface 20A of the metal circuit layer 20 has a code region 40 and a peripheral region 50 located on the periphery of the code region 40. FIG. 2 illustrates an example in which the code region 40 and the peripheral region 50 are in contact with each other. The code region 40 has a first region 41 and a second region 42. The code region 40 includes at least the first region 41 and the second region 42, and by providing two or more types of regions, information can be recorded. For example, the first region 41 may be a region with a higher processing density than the second region 42, or may be a region with a higher processing density than the peripheral region 50. FIG. 2 illustrates an example in which the code region 40 has a parallelogram shape. However, the shape is not limited to this as long as it is suitable for recording information. The shapes of the first region 41 and the second region 42 may also be modified to correspond to the information to be recorded. 2, the first region 41 and the second region 42 are shown as continuous regions, but the present invention is not limited to this and the first region 41 and the second region 42 may be a collection of multiple unit regions. The identification mark 30 has multiple grooves with different depths.

[0036] The shortest distance L1 between the end of the code region 40 and the end of the outer peripheral region 50 opposite the code region 40 may be 60 μm or more, 120 μm or more, 180 μm or more, or 240 μm or more. When the shortest distance L1 is within the above range, the influence of scratches and grain boundaries on the metal circuit layer 20 around the periphery of the code region can be more sufficiently reduced, and reading errors of the identification mark can be more sufficiently suppressed. The upper limit of the shortest distance L1 may be, for example, 600 μm or less, 500 μm or less, 400 μm or less, or 300 μm or less. When the upper limit of the shortest distance L1 is within the above range, the printing time for the outer peripheral region can be shortened, and the identification mark can be printed efficiently, thereby further shortening the manufacturing time of the bonded substrate. The maximum value of the distance between the end of the code region 40 and the end of the outer peripheral region 50 opposite the code region 40 may be, for example, 600 μm or less, 500 μm or less, 400 μm or less, or 300 μm or less. By making the maximum value within the above range, it is possible to set multiple identification marks within a limited area by making the peripheral area relatively small, and it is also possible to set other components such as wiring and semiconductor elements around the identification mark.

[0037] The minimum width of the outer peripheral region 50 (shortest distance L1) may be 0.05 times or more the long side L2 of the code region 40. The shortest distance L1 between the edge of the code region and the edge of the outer peripheral region may be, for example, 0.08 times or more, or 0.10 times or more the long side L2 of the code region. When the ratio of the shortest distance L1 to the long side L2 (the value of L1 / L2) is within the above range, the outer peripheral region located on the periphery of the code region sufficiently suppresses the effects of scratches and grain boundaries on the surface of the metal circuit layer, thereby more sufficiently suppressing reading errors of the identification mark. The upper limit of the ratio of the shortest distance L1 to the long side L2 (the value of L1 / L2) may be, for example, 0.20 or less, 0.18 or less, 0.16 or less, or 0.14 or less. When the upper limit of the value of L1 / L2 is within the above range, the printing time for the outer peripheral region can be shortened, allowing the identification mark to be printed efficiently, thereby further shortening the production time of the bonded substrate.

[0038] The code region 40 may be a code classified as a two-dimensional code, such as a data matrix code or a QR code (registered trademark). The external shape of a data matrix code is generally a parallelogram. When the code region is a data matrix code, the code region 40 is composed of a plurality of unit cells 31, and it can be said that the unit cells are arranged to fill the parallelogram region. In the code region of a conventional bonded substrate, the unit cells are composed of two types of units: processed and unprocessed. However, when the grain boundary of the metal circuit layer is located in the unprocessed portion, the unprocessed portion may be mistaken for a processed portion. The inventors have found that this is also a cause of read failure, although not as severe as the effect of read failure of the finder pattern. Furthermore, read failure can be further improved by processing the unprocessed portion. When the code region 40 is a data matrix code, the 1a depth D of the unit cells 31 is 1a and a plurality of grooves 1A having a depth D 1a The first depth D is greater than 1b A unit cell having a plurality of grooves 1B having a depth D 1a and a plurality of grooves having a first depth D 1a The first depth D is greater than 1b If a unit cell does not have grooves having a second depth D1 but has grooves having a second depth D2, the first region can be said to be made up of a plurality of first unit cells, and the second region can be said to be made up of a plurality of second unit cells. In this case, the code region 40, which is a Data Matrix code, can be made up of only the first region and the second region.

[0039] 3 is a schematic diagram showing an example in which the code region 40 is a data matrix code. When the code region 40 is a data matrix code, the minimum width (shortest distance L1) of the outer peripheral region 50 is set to the length L of one side of the unit cell 31. cThe shortest distance L1 between the end of the code area 40 and the end of the outer peripheral area 50 on the opposite side to the code area 40 side (when the identification mark 30 has a parallelogram shape, the shortest distance L1 can also be considered as the minimum value of the width of the outer peripheral area) may be equal to or greater than the length L of one side of the unit cell 31 of the data matrix code. c The upper limit of the shortest distance L1 is set to the length L of one side of the unit cell 31 of the data matrix code, and the shortest distance L1 may be set to, for example, 1 time or more, 2 times or more, 3 times or more, or 4 times or more. By setting the shortest distance L1 so as to satisfy the above conditions, it is possible to more sufficiently reduce the influence of scratches and grain boundaries of the metal circuit layer 20 on the periphery of the code area, and to further suppress reading errors of the identification mark. c Based on this, the minimum distance L1 may be, for example, 20 times or less, 15 times or less, or 10 times or less. By setting the minimum distance L1 so as to satisfy the above condition, the printing time for the outer peripheral region can be shortened and the identification marks can be printed efficiently, which can further shorten the manufacturing time of the bonded substrate. In an embodiment in which the bonded substrate 100 has a plurality of identification marks 30, the upper limit of the minimum distance L1 may be set so that adjacent identification marks do not interfere with each other. The shape of the unit cell 31 is usually square, but when it is rectangular, the length L of one side of the unit cell 31 described above can be set to 1 / 2. c When referring to the length, it means the length of the short side of the unit cell 31.

[0040] 4 is a schematic diagram showing a part of a cross section perpendicular to the main surface of the metal circuit layer taken along line IV-IV in FIG. 2. The cross section is taken in a direction perpendicular to the direction in which the grooves arranged in one direction extend. The identification mark 30 has a plurality of grooves with different depths. The code region 40 has a 1a depth D 1a and a plurality of grooves (first A grooves 43) having a first b depth D greater than the first a depth. 1b and a second region 42 having a plurality of grooves (second grooves 46) having a second depth D2 greater than the 1a depth. The outer peripheral region 50 includes a third region 51 having a plurality of grooves (third grooves 52) having a third depth D3 greater than the 1a depth.

[0041] The first region 41 has a depth D 1a and a plurality of grooves (first A grooves 43) having a first b depth D greater than the first a depth. 1b The first A groove 43 and the first B groove 44 may be formed by laser processing using irradiation of laser light, for example.

[0042] The depth of the 1A groove 43 (1a depth D 1a ) may be 0.50 μm or more, 0.75 μm or more, or 1.00 μm or more, and may be 3.00 μm or less, 2.50 μm or less, or 2.00 μm or less. 1a When is within the above numerical range, the 1A groove can be easily recognized, and reading errors of the identification mark can be more sufficiently suppressed.

[0043] The depth of the 1A groove 43 (1a depth D 1a ) may be, for example, 0.60 times or less, 0.52 times or less, 0.40 times or less, or 0.25 times or less, based on the depth (second depth D2) of the second groove 46 described later. 1a However, by keeping the depth of the 1A groove 43 within the above range, the difference between the 1A groove and the 2nd groove becomes conspicuous, and the number and arrangement of the 1st regions 41 in the code region 40 become more clearly recognizable, so that it is possible to further suppress reading failure of the identification mark 30. From the viewpoint of making the contrast between the 1st region 41 and the 2nd region 42 clearer, the depth of the 1A groove 43 (1a depth D 1a ) may be adjusted, and the lower limit may be, for example, 0.03 times or more, 0.04 times or more, or 0.05 times or more based on the depth of the second groove 46 (second depth D2).

[0044] The depth of the 1A groove 43 (1a depth D 1a ) may be, for example, 0.60 times or less, 0.52 times or less, 0.40 times or less, or 0.25 times or less, based on the depth (third depth D3) of the third groove 52 described later. 1aHowever, by keeping the depth within the above range, the difference between the first A groove 43 and the third groove 52 becomes more noticeable, and the number and arrangement of the outer peripheral regions 50 in the code region 40 become more clearly recognizable, so that reading errors of the identification mark 30 can be further suppressed. 1a ) may be adjusted, and the lower limit may be, for example, 0.03 times or more, 0.04 times or more, or 0.05 times or more based on the depth of the third groove 52 (third depth D3).

[0045] The groove width of the first A groove 43 (first A groove width W 1a ) may be 5.00 μm or more, 7.50 μm or more, or 10.00 μm or more, and may be 15.00 μm or less, 13.00 μm or less, 12.00 μm or less, or 11.00 μm or less.

[0046] The width between adjacent first A grooves 43 in the first region 41 (i.e., the distance between the center positions of two adjacent first A grooves) is the first A groove width W 1a The width W may be, for example, less than 3 times, less than 2 times, or less than 1 time. By forming the 1A grooves so that the width between adjacent 1A grooves is within the above range, the influence of grain boundaries on the surface of the metal circuit layer can be further reduced, the number and arrangement of first regions in the code region can be more clearly recognized, and reading errors of the identification mark can be more sufficiently suppressed. The lower limit of the width between adjacent 1A grooves 43 is the 1A groove width W 1a The standard may be, for example, 0.3 times or more, 0.5 times or more, or 0.8 times or more. By forming the 1A grooves so that the width between adjacent 1A grooves is within the above range, the printing time for the first region can be shortened and the identification mark can be printed efficiently, which can further shorten the production time of the bonded substrate.

[0047] The width between adjacent 1A grooves 43 in the first region 41 may be 5.00 μm or more, 7.50 μm or more, or 10.00 μm or more. By forming the grooves so that the width between adjacent 1A grooves 43 in the first region 41 falls within the above range, the printing time for the code region can be shortened and the identification mark can be printed efficiently, thereby further shortening the manufacturing time for the bonded substrate. The width between adjacent 1A grooves 43 in the first region 41 may be 20.00 μm or less, 15.00 μm or less, or 12.50 μm or less. By forming the grooves so that the width between adjacent 1A grooves 43 in the first region 41 falls within the above range, the influence of grain boundaries on the surface of the metal circuit layer can be further reduced, the number and arrangement of first regions in the code region can be more clearly recognized, and reading errors of the identification mark can be more sufficiently suppressed.

[0048] The depth of the first B groove 44 (first B depth D 1b ) may be 2.00 μm or more, 3.00 μm or more, or 4.00 μm or more, and may be 16.00 μm or less, 12.00 μm or less, 8.00 μm or less, or 5.00 μm or less.

[0049] The groove width of the first B groove 44 (first B groove width W 1b ) may be 15.00 μm or more, 17.50 μm or more, or 20.00 μm or more, and may be 30.00 μm or less, 27.50 μm or less, 25.00 μm or less, or 22.00 μm or less.

[0050] The second region 42 has a depth D 1a The second grooves 46 may be formed by laser processing using irradiation of laser light, for example.

[0051] The depth of the second groove 46 (second depth D2) may be 2.00 μm or more, 2.50 μm or more, or 3.00 μm or more, and may be 10.00 μm or less, 7.50 μm or less, or 5.00 μm or less.

[0052] The second groove width W2 of the second groove 46 is 1 / 1 the first A groove width W of the first A groove 43 in the first region. 1a Based on this, the second groove width W2 may be, for example, 1.2 times or more, 1.3 times or more, 1.5 times or more, 1.6 times or more, or 1.9 times or more. By forming the grooves in the second region so that the second groove width and the 1A groove width satisfy the above relationship, it becomes possible to more clearly recognize the number and arrangement of the first regions in the code region, and it is possible to more sufficiently prevent reading errors of the identification mark. The upper limit of the second groove width W2 of the second groove 46 is set equal to or greater than the 1A groove width W of the 1A groove 43 in the first region. 1a When the second groove width and the first A groove width are to be widened, that is, when the first A groove width W of the first A groove 43 in the first region is widened, the width W of the first A groove 43 in the first region may be, for example, 4.0 times or less, 3.0 times or less, or 2.5 times or less. 1a When attempting to achieve a groove width greater than 4.0 times the width of the first A groove, the amount of processing required to form the identification mark increases, which tends to increase the amount of particles scattered around. On the other hand, by setting the upper limit of the second groove width W2 of the second groove 46 so that the relationship described above is satisfied and adjusting the second groove width W2 to be relatively narrow, it is possible to reduce the amount of scattered particles. That is, when the grooves in the second region are formed so that the second groove width and the first A groove width satisfy the relationship described above, few particles scattered from the metal circuit layer during groove formation are scattered around the groove, making it possible to mount other components such as wiring and semiconductor devices around the identification mark without requiring processing to remove these scattered particles. Note that when the metal circuit layer is processed using laser processing, the scattered particles may be fine particles (so-called fumes) scattered from the metal during laser processing.

[0053] The second groove width W2 of the second groove 46 may be 15.00 μm or more, 17.50 μm or more, or 20.00 μm or more, and may be 30.00 μm or less, 25.00 μm or less, or 22.50 μm or less.

[0054] The width between adjacent second grooves 46 in the second region 42 (i.e., the distance between the centers of two adjacent second grooves) may be, for example, less than 6.0 times, less than 5.0 times, less than 4.0 times, less than 3.0 times, or less than 2.5 times the second groove width W2. By forming the grooves so that the width between adjacent second grooves in the second region falls within the above range, the influence of grain boundaries on the surface of the metal circuit layer can be further reduced, the number and arrangement of first regions in the code region can be more clearly recognized, and reading errors of the identification mark can be more sufficiently suppressed. The lower limit of the width between adjacent second grooves 46 in the second region may be, for example, 1.5 times or more, 2.0 times or more, or 2.4 times or more the second groove width. By forming the grooves so that the width between adjacent second grooves in the second region falls within the above range, the printing time for the second region can be shortened and the identification mark can be printed efficiently, thereby further shortening the manufacturing time of the bonded substrate.

[0055] The width between adjacent second grooves 46 in the second region 42 may be 20.00 μm or more, 22.50 μm or more, or 25.00 μm or more. By forming the grooves so that the width between adjacent second grooves 46 in the second region 42 falls within the above range, the difference between the first A grooves 43 formed in the first region 41 and the second grooves 46 formed in the second region 42 becomes more clearly recognizable, thereby further reducing readability of the identification mark 30. The width between adjacent second grooves 46 in the second region 42 may be 75.00 μm or less, 50.00 μm or less, or 25.00 μm or less. By forming the grooves so that the width between adjacent second grooves in the second region falls within the above range, the influence of grain boundaries on the surface of the metal circuit layer is further reduced, allowing the number and arrangement of first regions in the code region to be more clearly recognized, and more sufficiently reducing readability of the identification mark.

[0056] The outer peripheral region 50 has a depth equal to the depth of the first A groove 43 provided in the first region 41 (the first A depth D 1aThe code area 40 includes a third region 51 having a plurality of grooves (third grooves 52) having a third depth D3 greater than the third depth D3. The peripheral region 50 may consist of the third region 51. By forming the third grooves 52 on the outer periphery of the code area 40, reading errors due to scratches on the surface of the metal circuit layer or grain boundaries are prevented. The third grooves 52 may be formed by laser processing using laser light irradiation, for example.

[0057] The depth of the third groove 52 (third depth D3) may be 2.00 μm or more, 2.50 μm or more, or 3.00 μm or more, and may be 10.00 μm or less, 7.50 μm or less, or 5.00 μm or less.

[0058] The third groove width W3 of the third groove 52 may be, for example, 0.8 to 1.2 times, 0.9 to 1.1 times, or 1 time the second groove width W2 of the second groove 46. By forming the third groove 52 in the third region 51 so that the third groove width W3 and the second groove width W2 satisfy the above relationship, the third groove 52 is more easily recognized as a groove similar to the second groove 46 in the second region 42, and the difference between the 1A groove 43 in the first region 41 and the second groove 46 in the second region 42 and the third groove 52 in the third region 51 is more clearly recognized, thereby further reducing reading errors of the identification mark 30.

[0059] The third groove width W3 of the third groove 52 may be 15.00 μm or more, 17.50 μm or more, or 20.00 μm or more, and may be 30.00 μm or less, 25.00 μm or less, or 22.50 μm or less.

[0060] The width between adjacent third grooves 52 in the third region 51 (i.e., the distance between the centers of two adjacent third grooves) may be, for example, less than 6.0 times, less than 5.0 times, less than 4.0 times, less than 3.0 times, or less than 2.5 times the third groove width W3. By forming the grooves so that the width between adjacent third grooves in the third region falls within the above range, the influence of grain boundaries on the surface of the metal circuit layer can be further reduced, the number and arrangement of first regions in the code region can be more clearly recognized, and reading errors of the identification mark can be more sufficiently suppressed. The lower limit of the width between adjacent third grooves 52 in the third region 51 may be, for example, 1.5 times or more, 2.0 times or more, or 2.4 times or more the third groove width W3. By forming the grooves so that the width between adjacent third grooves in the third region falls within the above range, the printing time for the third region can be shortened and the identification mark can be printed efficiently, thereby further shortening the manufacturing time of the bonded substrate.

[0061] The width between adjacent third grooves 52 in the third region 51 may be 20.00 μm or more, 22.50 μm or more, or 25.00 μm or more. By forming the grooves so that the width between adjacent third grooves 52 in the third region 51 falls within the above range, the difference between the 1A grooves 43 formed in the first region 41 and the third grooves 52 formed in the third region 51 becomes more clearly recognizable, thereby further reducing readability of the identification mark 30. The width between adjacent third grooves 52 in the third region 51 may be 75.00 μm or less, 50.00 μm or less, or 25.00 μm or less. By forming the grooves so that the width between adjacent third grooves in the third region falls within the above range, the influence of grain boundaries on the surface of the metal circuit layer is further reduced, making it possible to more clearly recognize the number and arrangement of first regions in the code region, and more sufficiently reducing readability of the identification mark.

[0062] (Method of manufacturing bonded substrate) One embodiment of a method for manufacturing a bonded substrate includes forming an identification mark on a heat dissipation layer and a metal circuit layer of a laminate having a heat dissipation layer, a ceramic plate, and a metal circuit layer in this order. The identification mark has a code area and a peripheral area located on the periphery of the code area. The identification mark has a plurality of grooves with different depths. The code area includes a first area having a plurality of grooves with the depth 1a and a plurality of grooves with a depth 1b greater than the depth 1a, and a second area having a plurality of grooves with a second depth greater than the depth 1a. The peripheral area includes a third area having a plurality of grooves with a third depth greater than the depth 1a.

[0063] The step of forming the identification mark may be performed by laser processing, in which a laser beam is irradiated onto the metal circuit layer to form multiple grooves of different depths. The wavelength of the laser beam may be, for example, 532 nm or less, or may be 532 nm. Examples of lasers having the wavelength include green lasers that utilize SHG (second harmonic generation).

[0064] The process of forming the identification mark may include, for example, a process of laser processing the entire area of ​​the area where the identification mark is to be formed so as to arrange multiple grooves each having a predetermined groove width Wx in one direction (base formation process), and a process of laser processing a predetermined portion of the area so as to form 1A grooves each having a depth of 1a (code area formation process), or a process of laser processing a predetermined portion of the area where the code area is to be formed so as to form 1A grooves each having a depth of 1a, and a process of laser processing the outer periphery of the area so as to arrange multiple grooves each having a predetermined groove width Wx in one direction (peripheral area formation process). The order of performing the laser irradiation to form the grooves each having the groove width Wx and the laser irradiation to form the 1A grooves each having the depth of 1a is not particularly limited.

[0065] 5A and 5B are schematic diagrams illustrating an example of a manufacturing process for a first region in a manufacturing method for a bonded substrate. (A) of FIG. 5A shows a cross section of metal circuit layer 20 before laser irradiation. In the first region, a laser processing step (underlayer forming step) is performed to arrange multiple grooves having a predetermined groove width Wx in one direction across the entire surface of the region where an identification mark is to be formed, thereby forming first grooves 45 having a first depth as shown in (B) of FIG. 5B. Subsequently, a laser processing step (code region forming step) is performed to form grooves having a depth 1a, thereby forming first grooves 43 and 44 as shown in (C) of FIG. 5B. First groove 44 is formed by irradiating first groove 45 with a laser beam for forming first groove 43 having a depth 1a. Therefore, first groove 44 has a greater depth than first groove 45.

[0066] Although several embodiments have been described above, the present disclosure is not limited to the above embodiments. Furthermore, the descriptions of the above embodiments can be mutually applied. [Example]

[0067] The present disclosure will be described in more detail with reference to examples and comparative examples, but the present disclosure is not limited to the following examples.

[0068] Example 1 [Fabrication of bonded substrate] A 0.32 mm thick silicon nitride plate was prepared as the ceramic plate, a brazing filler metal containing Ag, Cu, Sn, and TiH2 was applied to the silicon nitride plate, and two 0.3 mm thick oxygen-free copper plates (manufactured by Mitsubishi Materials Corporation) were prepared as the heat dissipation layer and metal circuit layer, and placed on both sides of the ceramic plate and laminated to produce a laminate. Using a hot press, the aluminum nitride plate and the copper plate were joined by heating and pressurizing the laminate at 800°C for 30 minutes in a nitrogen atmosphere while applying a uniform pressure of 0.04 MPa to the laminate in a direction perpendicular to the main surface of the aluminum nitride plate using a hot press machine.

[0069] The main surface of the copper plate opposite the ceramic plate was irradiated with laser light using a marking device (manufactured by Keyence Corporation, product name: T-Centric-YVO4SHG laser marker / controller MD-T1000) under the conditions shown in Table 1 to form an identification mark. More specifically, first, laser light with a wavelength of 532 nm was irradiated onto the main surface of the copper plate opposite the ceramic plate under the condition X shown in Table 1, and marks with a depth D arranged in one direction over the entire area of ​​a 2.31 mm × 2.31 mm square were formed. X Next, a plurality of grooves having a depth of D X The laser beam with a wavelength of 532 nm is again irradiated to a predetermined region in the region where the grooves are formed under the condition Y shown in Table 1, and a depth D is formed at each of the positions of the plurality of first regions designated in advance. Y By forming multiple grooves of 14 cells x 14 cells, a data matrix code was formed on the copper plate, and a bonded substrate having an identification mark on the metal circuit layer was produced. X The grooves may be irradiated with laser beams additionally, and the depth of the grooves irradiated with laser beams multiple times is referred to as depth D X’ It is also called a "groove." Note that, since the scan speed is set higher under condition Y than under condition X, the time that the laser beam is irradiated onto a certain point on the metal circuit layer is shortened, resulting in the formation of a groove with a small depth. When the above-mentioned identification mark is imagined as a parallelogram circumscribing the first region closest to the periphery within the 1.80 mm x 1.80 mm square region, this corresponds to the code region, and the region that is the difference between the code region and the 2.31 mm x 2.31 mm square region (the region located on the periphery of the code region) corresponds to the periphery region (corresponding to the width indicated as the quiet zone under condition Y in Table 1). Also, the depth D X’ Multiple grooves with depth D Y The region where the plurality of grooves are formed corresponds to the first region, and the depth D X The region having only the plurality of grooves corresponds to the second region. Y The plurality of grooves in the second region correspond to the first A grooves, and the depth D X The grooves in the outer circumferential region correspond to the second grooves, and the depth D X The plurality of grooves corresponds to the third groove.

[0070] Example 2 A bonded substrate was produced in the same manner as in Example 1, except that the scanning speed under condition X was changed to 500 mm / s.

[0071] Example 3 A bonded substrate was produced in the same manner as in Example 1, except that the scanning speed in condition X was changed to 750 mm / s.

[0072] Example 4 A bonded substrate was produced in the same manner as in Example 2, except that the area to be irradiated with laser light under condition X was changed to a 2.05 mm x 2.05 mm square area, and the width of the quiet zone under condition Y was changed to 1 (cell).

[0073] (Comparative Example 1) A bonded substrate was produced in the same manner as in Example 1, except that the laser light irradiation was not performed under condition X. This bonded substrate corresponds to a bonded substrate having a conventional identification mark.

[0074] [Table 1]

[0075] [Evaluation of Identification Marks 1: Surface Image Analysis] The identification marks of the bonded substrates fabricated in Examples 1 to 4 and Comparative Example 1 were evaluated. First, SEM images of the identification mark portion were taken from the top using a Schottky field emission scanning electron microscope (manufactured by JEOL Ltd., product name: JSM-7900F). Next, the SEM image of the surface of the bonded substrate was analyzed using the same device to measure the width of the peripheral region. The width of the peripheral region in Examples 1 to 4, based on the length of one side of the unit cell of the identification mark, was 2 for Example 1, 2 for Example 2, 2 for Example 3, and 1 for Example 4. The width of the peripheral region in Examples 1 to 4 was 0.25 μm for Example 1, 0.25 μm for Example 2, 0.25 μm for Example 3, and 0.12 μm for Example 4. Note that no peripheral region was formed in Comparative Example 1. For reference, photographs of the identification mark portions of the bonded substrates fabricated in Examples 1 to 4 and Comparative Example 1 viewed from the top are shown in FIG. 6.

[0076] [Evaluation of identification marks 2: Cross-sectional image analysis] The identification marks were evaluated for each of the bonded substrates produced in Examples 1 to 4 and Comparative Example 1. First, the bonded substrate was cut using a precision automatic polishing machine / target system (manufactured by Struers). SEM images of the cross sections of the cut bonded substrate were taken using a Schottky field emission scanning electron microscope (manufactured by JEOL Ltd., product name: JSM-7900F). The SEM images of the cross sections of the bonded substrate were analyzed using the same device to measure the depth of each groove and the distance between grooves. The results are shown in Table 2. Note that the width of groove 1A, the distance between grooves 1A, and the depth of groove 1A in Example 1 could not be measured accurately because the distance between grooves 2A in the second region was short and the width of the unprocessed portion of the metal circuit layer in the first region was smaller than the width of groove 1A, so the results were "- ※ For reference, SEM images of cross sections of the identification mark portions of the bonded substrates produced in Examples 1 to 3 are shown in Figs. 7, 8 and 9, respectively.

[0077] [Table 2]

[0078] [Readability evaluation] For each of the bonded substrates produced in Examples 1 to 4 and Comparative Example 1, the identification marks were read as images using a fixed two-dimensional code reader (manufactured by Keyence Corporation, product name: SR-D100HA), and the read images were imported into analysis software (manufactured by Keyence Corporation, product name: AutoID Network Navigator). The readability of the identification marks was evaluated based on the output results of the following items 1 to 11 output from the analysis software. The results output from the above analysis software comply with the specifications of ISO / IEC TR 29158 (AIM DPM-1-2006). The results are shown in Table 3. Note that the evaluation results in Table 3 indicate that the evaluation is higher as the grade approaches A from F.

[0079] (Item 1: Decode success or failure) The decode success / failure (Decode) is an item that evaluates whether the two-dimensional code can be decoded. (Item 2: Cell contrast) Cell contrast is an item that evaluates the difference between the average brightness value of bright cells and the average brightness value of dark cells. (Item 3: Cell Modulation) Cell modulation is an item for evaluating the degree of variation in luminance of a unit cell. (Item 4: Reflectance margin) The reflectance margin means the degree of variation in cell luminance taking into account the correct black and white of the cell, and is measured by the following method. (Item 5: Fixed pattern damage) Fixed Pattern Damage is an item that evaluates the degree of damage to the fixed pattern (so-called "finder pattern") of a Data Matrix code.

[0080] (Item 6: Axial non-uniformity) Axial nonuniformity is an item for evaluating the degree of distortion in the vertical and horizontal sizes of the identification mark. (Item 7: Grid non-uniformity) Grid nonuniformity is an item that evaluates the maximum deviation of the unit cell position. (Item 8: Unused error correction) Unused Error Correction is an item that evaluates the percentage of error corrections that were not used when reading and decoding the information (codeword) contained in the identification mark.

[0081] (Item 9: Overall Judgment) The overall evaluation was based on the evaluation of the item with the lowest rating among the above-mentioned evaluations of decoding success / failure, cell contrast, cell modulation, reflection margin, fixed pattern damage, axial non-uniformity, grid non-uniformity, and unused error correction.

[0082] (Item 10: Print stretch (horizontal)) Print Growth (Horizontal) is an item for evaluating the expansion / contraction of unit cells (horizontal mark cells) located at the edge of the code area among unit cells arranged in the horizontal direction. (Item 11: Print stretch (vertical)) Print Growth Vertical is an item for evaluating the expansion / contraction of unit cells (vertical mark cells) located at the edge of the code area among unit cells arranged in the vertical direction.

[0083] [Table 3]

[0084] As shown in Table 3, the evaluation of decoding success (i.e., restoration of information from the two-dimensional code) for all of the bonded substrates of Examples 1 to 4 was A. This also confirms that by forming multiple grooves around the code area of ​​the identification mark (providing an outer peripheral area), the effects of grain boundaries and scratches present on the main surface of the metal circuit layer are reduced, and reading errors of the identification mark can be suppressed.

[0085] As shown in Table 3, the bonded substrates of Examples 1 to 3 received an overall rating of B or higher. It was confirmed that by having the minimum width of the peripheral region at least twice the length of one side of the unit cell, the readability of the identification mark was further improved compared to substrates without a peripheral region or substrates where the minimum width was 1 time the length of one side of the unit cell.

[0086] As shown in Table 3, the bonded substrates of Examples 1 and 2 received an overall rating of B or higher, and an evaluation of A for fixed pattern damage. Fixed pattern damage is an index indicating the degree of damage to the fixed pattern of the data matrix code (the so-called "finder pattern"), and is an index that has a high degree of influence on reading errors of the identification mark. The bonded substrates of Examples 1 and 2 had particularly small distances between the second grooves in the second region of the code region and between the third grooves in the third region of the outer peripheral region, resulting in high processing density. This confirmed that the effects of scratches and grain boundaries on the surface of the metal circuit layer on the periphery of the code region could be further reduced, making it easier to recognize the finder pattern.

[0087] As shown in Table 3, the bonded substrate of Example 1 was evaluated as A in all evaluation items. The bonded substrate of Example 1 has a small distance between the second grooves in the second region of the code area and a small distance between the third grooves in the third region of the outer peripheral area, and thus has a high processing density. It was confirmed that this processing provides a better effect of suppressing reading errors of the identification mark than substrates with a lower processing density. [Explanation of symbols]

[0088] 10...ceramic plate, 20...metal circuit layer, 20A...main surface, 30...identification mark, 31...unit cell, 40...code region, 41...first region, 42...second region, 43...1A groove, 44...1B groove, 45...first groove, 46...second groove, 50...peripheral region, 51...third region, 52...third groove, 100...bonded substrate.

Claims

1. A bonded substrate having a heat dissipation layer, a ceramic plate, and a metal circuit layer in this order, an identification mark on at least one of the heat dissipation layer and the metal circuit layer; the identification mark has a code area and an outer peripheral area located on the outer periphery of the code area, The coding region a first region including a plurality of grooves having a depth 1a and a plurality of grooves having a depth 1b greater than the depth 1a; a second region including a plurality of grooves having a second depth greater than the first depth; the outer peripheral region includes a third region having a plurality of grooves having a third depth greater than the 1a depth; Bonding substrate.

2. The bonded substrate according to claim 1 , wherein the ratio of the first depth to the second depth is 0.60 or less.

3. The bonded substrate according to claim 1 , wherein the ratio of the first depth to the third depth is 0.60 or less.

4. 3. The bonded substrate according to claim 1, wherein the groove width of the groove having the second depth in the second region is 1.5 times or more of the groove width of the groove having the 1a depth in the first region.

5. 3. The bonded substrate according to claim 1, wherein a groove width of the groove having the third depth in the third region is 0.8 to 1.2 times a groove width of the groove having the second depth in the second region.

6. The bonded substrate according to claim 1 or 2, wherein the width between adjacent grooves in the second region is less than 5.0 times the groove width of the groove having the second depth.

7. 3. The bonded substrate according to claim 1, wherein the width between adjacent grooves in the third region is less than 5.0 times the groove width of the groove having the third depth.

8. the coding region has a parallelogram shape; The bonded substrate according to claim 1 or 2, wherein the minimum width of the outer peripheral region is at least 0.05 times the length of the long side of the code region.

9. 3. The bonded substrate according to claim 1, wherein the shortest distance between an end of the code region and an end of the outer peripheral region opposite to the code region is 80 [mu]m or more.

10. the code region is a Data Matrix code, The bonded substrate according to claim 1 or 2, wherein the minimum width of the outer peripheral region is at least twice the length of one side of the unit cell.

11. The bonded substrate according to claim 1 , wherein at least one of the heat dissipation layer and the metal circuit layer contains copper.

12. a step of forming an identification mark on at least one of a heat dissipation layer and a metal circuit layer of a laminate having a heat dissipation layer, a ceramic plate, and a metal circuit layer in this order; the identification mark has a code area and an outer peripheral area located on the outer periphery of the code area, The coding region a first region including a plurality of grooves having a depth 1a and a plurality of grooves having a depth 1b greater than the depth 1a; a second region including a plurality of grooves having a second depth greater than the first depth; the outer peripheral region includes a third region having a plurality of grooves having a third depth greater than the 1a depth; A method for manufacturing a bonded substrate.

13. The manufacturing method according to claim 12 , wherein the step is a step of forming the identification mark by laser processing.

Images