Printed circuit board and electronic control device

Abstract

To improve reliability of a printed circuit board.SOLUTION: A print substrate 2 includes: dielectric layers 21 to 29; conductor pattern layers 11 to 20; a positive electrode terminal through hole 31; a negative electrode terminal through hole 32; a positive electrode inner layer via 37; and a negative electrode inner layer via 38. The positive electrode inner layer via 37 and the negative electrode inner layer via 38 each penetrate dielectric layers 22 to 29 from a second-layer dielectric layer 22 to the nine-layer dielectric layers 29, a positive electrode inner layer via conductor 37a and the negative electrode inner layer via 38 are formed on an inner peripheral surface, and at least a part thereof is included in an inner layer via arrangement region. The positive electrode terminal through hole 31 and the positive electrode inner layer via 37 are connected to each other, and the negative electrode terminal through hole 32 and the negative electrode inner layer via 38 are connected to each other by at least one layer of the second-layer conductor pattern layer 12 to a tenth-layer conductor pattern layer 20.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a printed circuit board and an electronic control device. [Background technology]

[0002] When connecting a printed circuit board and the terminals of electronic components to be connected to the printed circuit board by soldering, the heat generated during soldering is not easily transmitted to the back side, resulting in poor solderability. When solder connectivity is poor, cracks will form inside the solder when thermal stress is applied, and as the cracks gradually increase, the electrical connection will be lost, leading to failure.

[0003] Patent document 1 describes a technology that efficiently transfers heat during soldering to the back surface by arranging multiple vias around the through holes into which the terminals of electronic components are inserted that are thermally connected to the through holes. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-17560 Summary of the Invention [Problem to be solved by the invention]

[0005] As a result of detailed investigations by the inventors, the following problem was discovered. In the printed circuit board described in Patent Document 1, when a capacitor is mounted on the printed circuit board, the distance between a pattern having the same potential as the positive terminal of the capacitor and a pattern having the same potential as the negative terminal of the capacitor may be shorter than the distance between the positive and negative terminals of the capacitor. As a result, if electrolyte leaks from a capacitor mounted on the printed circuit board, the electrolyte may spread onto the wiring pattern, causing migration and resulting in a short circuit of the capacitor.

[0006] The present disclosure aims to improve the reliability of printed circuit boards. [Means for solving the problem]

[0007] One aspect of the present disclosure is a printed circuit board (2) comprising a plurality of dielectric layers (21-29) from the first layer to the (N-1)th layer, where N is an integer greater than or equal to 3, a plurality of conductor pattern layers (11-20) from the first layer to the Nth layer, a first through hole (31), a second through hole (32), and inner layer vias (37, 38).

[0008] A plurality of conductive pattern layers are laminated alternately with a plurality of dielectric layers. The first through-hole penetrates multiple dielectric layers from the first layer to the (N-1)th layer, has a first through-hole conductor (31a) formed on its inner surface, and has a positive terminal (101) of the capacitor (100) inserted therein.

[0009] The second through-hole penetrates the plurality of dielectric layers from the first layer to the (N-1)th layer, has a second through-hole conductor (32a) formed on its inner circumferential surface, and has a negative terminal (102) of the capacitor inserted therein.

[0010] The inner layer vias penetrate each of the dielectric layers from any one of the second to (N-1)th dielectric layers to the (N-1)th dielectric layer, have inner layer via conductors (37a, 38a) formed on their inner circumferential surfaces, and are at least partially included within the inner layer via arrangement area. The inner layer via arrangement area is the area directly below the capacitor when the capacitor is arranged on the first conductive pattern layer by inserting the positive and negative terminals into the first and second through holes, respectively, and is sandwiched between the first straight line (L1) and the second straight line (L2).

[0011] The first and second straight lines are arranged parallel to each other, separated by a through hole distance (TD), which is the distance between the first through hole and the second through hole, and are two straight lines arranged between the first through hole and the second through hole, intersecting perpendicularly with the through hole connecting straight line (L3) connecting the center (C1) of the first through hole and the center (C2) of the second through hole.

[0012] At least one of the first through-hole and the second through-hole is connected to the inner layer via by at least one of the conductive pattern layers from the second layer to the Nth layer.

[0013] The printed circuit board of the present disclosure configured as described above includes an inner layer via connected to at least one of the first through hole and the second through hole, thereby increasing the number of paths for heat conduction between the first conductive pattern layer and the Nth conductive pattern layer, thereby facilitating heat conduction between the first conductive pattern layer and the Nth conductive pattern layer. This facilitates heat conduction during soldering between the first conductive pattern layer and the Nth conductive pattern layer through the first and second through holes. Therefore, the printed circuit board of the present disclosure can suppress deterioration of solderability when soldering the positive and negative terminals of the capacitor into the first and second through holes, respectively.

[0014] Furthermore, in the printed circuit board of the present disclosure, the inner vias arranged in the inner via arrangement area are not exposed on the mounting surface of the printed circuit board on which the capacitor is mounted, which makes it possible to prevent the capacitor from shorting out between the first through hole and the second through hole when electrolyte leaks from the capacitor mounted on the printed circuit board.

[0015] As described above, the printed circuit board of the present disclosure can improve the reliability of the printed circuit board. Another aspect of the present disclosure is an electronic control device (1) including a capacitor (100) and a printed circuit board (2) on which the capacitor is mounted.

[0016] The printed circuit board comprises a plurality of dielectric layers (21-29) from the first layer to the (N-1)th layer, a plurality of conductor pattern layers (11-20) from the first layer to the Nth layer, a first through hole (31), a second through hole (32), and inner layer vias (37, 38). At least one of the conductor pattern layers from the second layer to the Nth layer connects at least one of the first through hole and the second through hole to the inner layer via.

[0017] The electronic control device of the present disclosure configured in this manner is a device that includes the printed circuit board of the present disclosure, and can obtain the same effects as the printed circuit board of the present disclosure. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 2 is a block diagram showing the configuration of an electronic control device. [Figure 2] 1 is a cross-sectional view showing the configuration of a printed circuit board according to a first embodiment. [Figure 3] 3A and 3B are diagrams illustrating the shape of a conductive pattern layer on a mounting surface. [Figure 4] 1A and 1B are diagrams showing the shape of a conductive pattern layer on a dielectric layer inside a substrate. [Figure 5] 10A and 10B are diagrams showing the shape of a conductive pattern layer on a soldering surface. [Figure 6] FIG. 10 is a cross-sectional view showing the configuration of a printed circuit board according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0019] [First embodiment] A first embodiment of the present disclosure will be described below with reference to the drawings. The electronic control device 1 of this embodiment is a device that controls a control target (not shown), and as shown in Fig. 1, includes a printed circuit board 2. The electronic control device 1 is configured by accommodating the printed circuit board 2 in a housing (not shown).

[0020] On the printed circuit board 2, a microcomputer 3, a drive circuit 4, and a power supply circuit 5 are mounted. The microcomputer 3 executes various control processes for controlling the controlled object, and outputs a control signal indicating a control amount for controlling the controlled object to the drive circuit 4.

[0021] Based on a control signal from the microcomputer 3, the drive circuit 4 outputs a drive signal for driving the controlled object to the controlled object. The power supply circuit 5 is a circuit that generates a predetermined power supply voltage for operating the microcomputer 3 and the drive circuit 4.

[0022] 2, the printed circuit board 2 includes ten conductor pattern layers 11, 12, 13, 14, 15, 16, 17, 18, 19, and 20, and nine dielectric layers 21, 22, 23, 24, 25, 26, 27, 28, and 29. The printed circuit board 2 is formed by alternately stacking the ten conductor pattern layers 11 to 20 and the nine dielectric layers 21 to 29 along a stacking direction D1.

[0023] Therefore, the conductor pattern layer 11 is arranged on the dielectric layer 21. The conductor pattern layer 12 is arranged between the dielectric layer 21 and the dielectric layer 22. The conductor pattern layer 13 is arranged between the dielectric layer 22 and the dielectric layer 23. The conductor pattern layer 14 is arranged between the dielectric layer 23 and the dielectric layer 24. The conductor pattern layer 15 is arranged between the dielectric layer 24 and the dielectric layer 25. The conductor pattern layer 16 is arranged between the dielectric layer 25 and the dielectric layer 26. The conductor pattern layer 17 is arranged between the dielectric layer 26 and the dielectric layer 27. The conductor pattern layer 18 is arranged between the dielectric layer 27 and the dielectric layer 28. The conductor pattern layer 19 is arranged between the dielectric layer 28 and the dielectric layer 29. The dielectric layer 29 is arranged on the conductor pattern layer 20.

[0024] The printed circuit board 2 is formed with a positive terminal through-hole 31 into which a positive terminal 101 of the capacitor 100 is inserted, and a negative terminal through-hole 32 into which a negative terminal 102 of the capacitor 100 is inserted. The capacitor 100 is, for example, a component of the power supply circuit 5. In this embodiment, the capacitor 100 is an aluminum electrolytic capacitor.

[0025] The positive electrode terminal through-hole 31 and the negative electrode terminal through-hole 32 are formed to penetrate the dielectric layers 21 to 29. A conductor 31a is formed over the entire inner circumferential surface of the positive electrode terminal through-hole 31. A conductor 32a is formed over the entire inner circumferential surface of the negative electrode terminal through-hole 32. Hereinafter, the conductor 31a and the conductor 32a will be referred to as the positive electrode terminal through-hole conductor 31a and the negative electrode terminal through-hole conductor 32a, respectively.

[0026] The printed circuit board 2 includes a solder resist 33. The solder resist 33 is disposed on the conductive pattern layer 11 and on the area of ​​the dielectric layer 21 where the conductive pattern layer 11 is not disposed. However, the solder resist 33 is disposed so as not to cover the openings of the positive electrode terminal through-hole 31 and the negative electrode terminal through-hole 32. This forms resist openings 33a so that the openings of the positive electrode terminal through-hole 31 and the negative electrode terminal through-hole 32 are exposed.

[0027] The positive electrode terminal 101 and the negative electrode terminal 102 of the capacitor 100 are linear conductors. The positive electrode terminal 101 and the negative electrode terminal 102 are inserted into the positive electrode terminal through-hole 31 and the negative electrode terminal through-hole 32, respectively, through the resist opening 33a. The ends of the positive electrode terminal 101 and the negative electrode terminal 102 protrude from the openings of the positive electrode terminal through-hole 31 and the negative electrode terminal through-hole 32 on the surface of the plate-shaped printed circuit board 2 opposite to the surface on which the resist opening 33a is formed.

[0028] Hereinafter, of the two surfaces of the printed circuit board 2 formed in a plate shape, the surface on which the main body 103 of the capacitor 100 is arranged will be referred to as the mounting surface 2a. Also, of the two surfaces of the printed circuit board 2, the surface on which the ends of the positive terminal 101 and the negative terminal 102 of the capacitor 100 protrude will be referred to as the soldering surface 2b.

[0029] With the positive terminal 101 and negative terminal 102 of the capacitor 100 inserted into the positive terminal through-hole 31 and the negative terminal through-hole 32, respectively, the capacitor 100 is fixed to the printed circuit board 2 by filling solder 34 between the positive terminal 101 and the positive terminal through-hole 31 and between the negative terminal 102 and the negative terminal through-hole 32.

[0030] As shown in FIGS. 2, 3, 4 and 5, a plurality of positive electrode through vias 35 are formed around the positive electrode terminal through hole 31, and a plurality of negative electrode through vias 36 are formed around the negative electrode terminal through hole 32.

[0031] The positive electrode through via 35 and the negative electrode through via 36 are formed to penetrate the dielectric layers 21 to 29. A conductor 35a is formed over the entire inner circumferential surface of the positive electrode through via 35. A conductor 36a is formed over the entire inner circumferential surface of the negative electrode through via 36. Hereinafter, the conductor 35a and the conductor 36a will be referred to as the positive electrode through via conductor 35a and the negative electrode through via conductor 36a, respectively.

[0032] 3, the positive electrode through via 35 and the negative electrode through via 36 are arranged outside an inner layer via arrangement region R1 described later. In FIG. 3, a region R2 indicated by a dashed circle is a region corresponding to directly below the capacitor 100.

[0033] The inner layer via arrangement region R1 is a region directly below the capacitor 100 and between a first line L1 (to be described later) and a second line L2 (to be described later). The first straight line L1 and the second straight line L2 are arranged parallel to each other and separated by the distance TD between the positive terminal through hole 31 and the negative terminal through hole 32 (hereinafter referred to as the through hole distance TD), and are two straight lines that intersect perpendicularly with the through hole connecting line L3 that connects the center C1 of the positive terminal through hole 31 and the center C2 of the negative terminal through hole 32, and are arranged between the positive terminal through hole 31 and the negative terminal through hole 32.

[0034] As shown in Figures 2 and 3, the conductor pattern layer 11 includes a first positive electrode connection pattern 111 that connects the positive electrode terminal through-hole conductor 31a and the positive electrode through-hole via conductor 35a, and a first negative electrode connection pattern 112 that connects the negative electrode terminal through-hole conductor 32a and the negative electrode through-hole via conductor 36a.

[0035] 2 and 4, a plurality of positive electrode inner layer vias 37 are formed around the positive electrode terminal through hole 31, and a plurality of negative electrode inner layer vias 38 are formed around the negative electrode terminal through hole 32. The positive electrode inner layer vias 37 and the negative electrode inner layer vias 38 are arranged within the inner layer via arrangement region R1.

[0036] The positive electrode inner layer via 37 and the negative electrode inner layer via 38 are formed to penetrate the dielectric layers 22 to 29. A conductor 37a is formed over the entire inner circumferential surface of the positive electrode inner layer via 37. A conductor 38a is formed over the entire inner circumferential surface of the negative electrode inner layer via 38. Hereinafter, the conductor 37a and the conductor 38a will be referred to as the positive electrode inner layer via conductor 37a and the negative electrode inner layer via conductor 38a, respectively.

[0037] The conductive pattern layer 12 includes a first positive electrode connection pattern 121 that connects the positive electrode terminal through-hole conductor 31a and the positive electrode through-via conductor 35a, and a first negative electrode connection pattern 122 that connects the negative electrode terminal through-hole conductor 32a and the negative electrode through-via conductor 36a.

[0038] The conductive pattern layer 12 includes a second positive electrode connection pattern 123 that connects the positive electrode terminal through-hole conductor 31a and the positive electrode inner layer via conductor 37a, and a second negative electrode connection pattern 124 that connects the negative electrode terminal through-hole conductor 32a and the negative electrode inner layer via conductor 38a.

[0039] As shown in Figure 2, the conductor pattern layers 13, 14, 15, 16, 17, 18, 19, and 20 each include a first positive electrode connection pattern 131, 141, 151, 161, 171, 181, 191, and 201 that connect the positive electrode terminal through-hole conductor 31a and the positive electrode through-hole via conductor 35a, and a first negative electrode connection pattern 132, 142, 152, 162, 172, 182, 192, and 202 that connect the negative electrode terminal through-hole conductor 32a and the negative electrode through-hole via conductor 36a.

[0040] The conductor pattern layers 13, 14, 15, 16, 17, 18, 19, 20 each include a second positive electrode connection pattern 133, 143, 153, 163, 173, 183, 193, 203 that connects the positive electrode terminal through-hole conductor 31a and the positive electrode inner layer via conductor 37a, and a second negative electrode connection pattern 134, 144, 154, 164, 174, 184, 194, 204 that connects the negative electrode terminal through-hole conductor 32a and the negative electrode inner layer via conductor 38a, respectively.

[0041] The printed circuit board 2 configured in this manner includes first to ninth dielectric layers 21 to 29, first to tenth conductive pattern layers 11 to 20, a positive electrode terminal through hole 31, a negative electrode terminal through hole 32, a positive electrode inner layer via 37, and a negative electrode inner layer via 38.

[0042] The conductive pattern layers 11 to 20 and the dielectric layers 21 to 29 are alternately laminated. Positive terminal through-hole 31 passes through first to ninth dielectric layers 21 to 29, has positive terminal through-hole conductor 31a formed on its inner circumferential surface, and has positive terminal 101 of capacitor 100 inserted therein.

[0043] Negative electrode terminal through-hole 32 passes through first to ninth dielectric layers 21 to 29, has a negative electrode terminal through-hole conductor 32a formed on its inner circumferential surface, and has negative electrode terminal 102 of capacitor 100 inserted therein.

[0044] The positive electrode inner layer via 37 penetrates each of the second to ninth dielectric layers 22 to 29, has a positive electrode inner layer via conductor 37a formed on its inner circumferential surface, and is at least partially included in the inner layer via arrangement region R1. The inner layer via arrangement region R1 is the region directly below the capacitor 100 when the capacitor 100 is arranged on the first conductive pattern layer 11 by inserting the positive electrode terminal 101 and the negative electrode terminal 102 into the positive electrode terminal through hole 31 and the negative electrode terminal through hole 32, respectively, and is sandwiched between the first line L1 and the second line L2.

[0045] The negative electrode inner layer via 38 penetrates each of the second to ninth dielectric layers 22 to 29, has a negative electrode inner layer via conductor 38a formed on its inner circumferential surface, and is at least partially included within the inner layer via arrangement region R1.

[0046] At least one of the second to tenth conductive pattern layers 12 to 20 connects the positive electrode terminal through hole 31 and the positive electrode inner layer via 37, and the negative electrode terminal through hole 32 and the negative electrode inner layer via .

[0047] By including the positive electrode inner layer via 37 connected to the positive electrode terminal through hole 31 and the negative electrode inner layer via 38 connected to the negative electrode terminal through hole 32, the printed circuit board 2 can increase the number of paths for heat conduction between the first conductive pattern layer 11 and the tenth conductive pattern layer 20, thereby facilitating heat conduction between the first conductive pattern layer 11 and the tenth conductive pattern layer 20. This facilitates heat conduction during soldering between the first conductive pattern layer 11 side and the tenth conductive pattern layer 20 side in the positive electrode terminal through hole 31 and the negative electrode terminal through hole 32. Therefore, the printed circuit board 2 can suppress deterioration of solderability when soldering the positive electrode terminal 101 and the negative electrode terminal 102 of the capacitor 100 into the positive electrode terminal through hole 31 and the negative electrode terminal through hole 32, respectively.

[0048] Furthermore, in the printed circuit board 2, the positive electrode inner layer vias 37 and the negative electrode inner layer vias 38 arranged in the inner layer via arrangement region R1 are not exposed on the mounting surface 2a on which the capacitor 100 is mounted on the printed circuit board 2. This makes it possible for the printed circuit board 2 to prevent a situation in which the capacitor 100 is shorted between the positive electrode terminal through hole 31 and the negative electrode terminal through hole 32 when electrolyte leaks from the capacitor 100 mounted on the printed circuit board 2.

[0049] At least a portion of the positive electrode inner layer vias 37 and the negative electrode inner layer vias 38 may be included in a central area CA shown in Fig. 4. The central area CA is an area of ​​the inner layer via arrangement area R1 that is sandwiched between the positive electrode terminal through hole 31 and the negative electrode terminal through hole 32. Such a printed circuit board 2 is highly effective in preventing short circuits because it can prevent the occurrence of short circuits in the central area CA, where there is a high possibility that the capacitor 100 will short between the positive electrode terminal through hole 31 and the negative electrode terminal through hole 32 if electrolyte leaks from the capacitor 100 mounted on the printed circuit board 2.

[0050] As a result, the reliability of the printed circuit board 2 can be improved. In the embodiment described above, the positive terminal through-hole 31 corresponds to the first through-hole conductor, the negative terminal through-hole 32 corresponds to the second through-hole, the positive terminal through-hole conductor 31a corresponds to the first through-hole conductor, and the negative terminal through-hole conductor 32a corresponds to the second through-hole conductor.

[0051] The positive electrode inner layer via 37 and the negative electrode inner layer via 38 correspond to inner layer vias, and the positive electrode inner layer via conductor 37a and the negative electrode inner layer via conductor 38a correspond to inner layer via conductors. [Second embodiment] A second embodiment of the present disclosure will be described below with reference to the drawings. In the second embodiment, only the parts that are different from the first embodiment will be described. The same reference numerals will be used to designate common components.

[0052] The electronic control device 1 of the second embodiment differs from the first embodiment in that the shapes of the positive electrode inner layer via 37 and the negative electrode inner layer via 38 are changed and additional inner layer vias 61 and 62 are added. As shown in FIG. 6, the positive electrode inner layer via 37 is composed of divided vias 41 and 42 and a third positive electrode connection pattern 155.

[0053] Divided via 41 is formed to penetrate dielectric layers 23-24. A conductor 41a is formed over the entire inner circumferential surface of divided via 41. Divided via 42 is formed to penetrate dielectric layers 25-29. A conductor 42a is formed over the entire inner circumferential surface of divided via 42. Hereinafter, conductors 41a and 42a will be referred to as divided via conductors 41a and 42a, respectively.

[0054] The divided via 41 is connected to the positive electrode terminal through-hole 31 by the second positive electrode connection patterns 143 and 153. The divided via 42 is connected to the positive electrode terminal through-hole 31 by the second positive electrode connection patterns 173, 183, 193, and 203.

[0055] The conductive pattern layer 15 includes a third positive electrode connecting pattern 155 that connects the divided via conductor 41a and the divided via conductor 42a. The negative electrode inner layer via 38 is composed of divided vias 51 and 52 and a third negative electrode connection pattern 156.

[0056] Divided via 51 is formed to penetrate dielectric layers 23-24. A conductor 51a is formed over the entire inner circumferential surface of divided via 51. Divided via 52 is formed to penetrate dielectric layers 25-29. A conductor 52a is formed over the entire inner circumferential surface of divided via 52. Hereinafter, conductors 51a and 52a will be referred to as divided via conductors 51a and 52a, respectively.

[0057] The divided via 51 is connected to the negative electrode terminal through-hole 32 by the second negative electrode connection patterns 144 and 154. The divided via 52 is connected to the negative electrode terminal through-hole 32 by the second negative electrode connection patterns 174, 184, 194, and 204.

[0058] The conductive pattern layer 15 includes a third negative electrode connecting pattern 156 that connects the divided via conductor 51a and the divided via conductor 52a. The additional inner vias 61, 62 are formed in the inner via arrangement region R1 so as to penetrate the dielectric layers 28 to 29. Conductors 61a, 62a are formed over the entire inner circumferential surfaces of the additional inner vias 61, 62. Hereinafter, the conductors 61a, 62a will be referred to as additional inner via conductors 61a, 62a, respectively.

[0059] The conductive pattern layer 18 includes a fourth positive electrode connection pattern 187 connecting the divided via conductor 42a and the additional inner layer via conductor 61a, and a fourth negative electrode connection pattern 188 connecting the divided via conductor 52a and the additional inner layer via conductor 62a.

[0060] In the printed circuit board 2 configured in this manner, the positive electrode inner layer via 37 is formed by divided vias 41 and 42 that penetrate at least one dielectric layer. The divided via 41 penetrates the dielectric layers 23 and 24. The divided via 42 penetrates the dielectric layers 25 to 29. The negative electrode inner layer via 38 is formed by divided vias 51 and 52 that penetrate at least one dielectric layer. The divided via 51 penetrates the dielectric layers 23 and 24. The divided via 52 penetrates the dielectric layers 25 to 29. Specifically, the positive electrode inner layer via 37 is formed non-linearly along the stacking direction D1 by connecting the divided vias 41 and 42 with the third positive electrode connection pattern 155. The negative electrode inner layer via 38 is formed non-linearly along the stacking direction D1 by connecting the divided vias 51 and 52 with the third negative electrode connection pattern 156.

[0061] Such a printed circuit board 2 allows the shape of the positive electrode inner layer via 37 and the negative electrode inner layer via 38 to be changed by changing the arrangement of the divided vias 41, 51 and the divided vias 42, 52 according to the wiring pattern within the printed circuit board 2, thereby ensuring freedom of circuit design.

[0062] The printed circuit board 2 further includes additional inner layer vias 61 and 62 that penetrate the third to ninth dielectric layers 23 to 29 in the inner layer via arrangement region R1 and have additional inner layer via conductors 61a and 62a formed on their inner circumferential surfaces. The additional inner layer vias 61 and 62 are connected to the positive electrode inner layer via 37 and the negative electrode inner layer via 38 by a fourth positive electrode connection pattern 187 and a fourth negative electrode connection pattern 188, respectively.

[0063] By providing the additional inner layer vias 61, 62, the printed circuit board 2 can increase the number of paths for conducting heat between the first conductive pattern layer 11 and the tenth conductive pattern layer 20, thereby facilitating heat conduction between the first conductive pattern layer 11 and the tenth conductive pattern layer 20. As a result, the printed circuit board 2 can further suppress deterioration of solderability when soldering the positive terminal 101 and the negative terminal 102 of the capacitor 100 into the positive terminal through hole 31 and the negative terminal through hole 32, respectively.

[0064] Although one embodiment of the present disclosure has been described above, the present disclosure is not limited to the above embodiment and can be implemented in various modifications. [Variation 1] In the above embodiment, the first to tenth conductive pattern layers 11 to 20 are provided, but the number of conductive pattern layers may be three or more.

[0065] [Variation 2] In the above embodiment, the positive electrode inner layer via 37 and the negative electrode inner layer via 38 penetrate the dielectric layers 22 to 29. However, the positive electrode inner layer via 37 and the negative electrode inner layer via 38 may penetrate the dielectric layers from any one of the dielectric layers 23 to 29 to the dielectric layer 29. For example, the positive electrode inner layer via 37 and the negative electrode inner layer via 38 may penetrate the dielectric layers 25 to 29.

[0066] [Variation 3] In the above embodiment, the additional inner vias 61, 62 penetrate the dielectric layers 28 to 29. However, the additional inner vias 61, 62 may penetrate the dielectric layers from any one of the dielectric layers 22 to 29 to the dielectric layer 29. For example, the additional inner vias 61, 62 may penetrate the dielectric layers 22 to 29.

[0067] [Variation 4] In the above embodiment, the positive electrode inner layer via 37 and the negative electrode inner layer via 38 are entirely contained within the inner layer via arrangement region R1. However, at least a portion of the positive electrode inner layer via 37 and the negative electrode inner layer via 38 may be contained within the inner layer via arrangement region R1.

[0068] In the above embodiments, multiple functions of one component may be realized by multiple components, or one function of one component may be realized by multiple components. Furthermore, multiple functions of multiple components may be realized by one component, or one function realized by multiple components may be realized by one component. Furthermore, part of the configuration of the above embodiments may be omitted. Furthermore, at least part of the configuration of the above embodiments may be added to or substituted for the configuration of another of the above embodiments. [Technical idea disclosed in this specification] [Item 1] A plurality of dielectric layers (21 to 29) from the first layer to the (N-1)th layer, where N is an integer of 3 or more; a plurality of conductor pattern layers (11 to 20) from a first layer to an Nth layer alternately stacked with the plurality of dielectric layers; a first through-hole (31) that penetrates through the plurality of dielectric layers from the first layer to the (N-1)th layer, has a first through-hole conductor (31a) formed on its inner circumferential surface, and into which a positive terminal (101) of a capacitor (100) is inserted; a second through-hole (32) that penetrates through the plurality of dielectric layers from the first layer to the (N-1)th layer, has a second through-hole conductor (32a) formed on its inner circumferential surface, and into which the negative electrode terminal (102) of the capacitor is inserted; The first through hole and the second through hole are arranged parallel to each other with a through hole distance (TD) between them, and two straight lines are defined as a first straight line (L1) and a second straight line (L2) that perpendicularly intersect a through hole connecting straight line (L3) connecting the center (C1) of the first through hole and the center (C2) of the second through hole and are arranged between the first through hole and the second through hole. The positive terminal and the negative terminal are inserted into the first through hole and the second through hole, respectively. When the capacitor is arranged on the conductor pattern layer of the first layer, the area sandwiched between the first straight line and the second straight line is an inner layer via arrangement area (R1), and inner layer vias (37, 38) penetrate each of the dielectric layers from any one of the dielectric layers from the second layer to the (N-1)th layer to the dielectric layer of the (N-1)th layer, have inner layer via conductors (37a, 38a) formed on their inner circumferential surfaces, and at least a portion of which is included in the inner layer via arrangement area, A printed circuit board (2) in which at least one of the first through hole and the second through hole is connected to the inner layer via by at least one of the conductive pattern layers from the second layer to the Nth layer.

[0069] [Item 2] The printed circuit board according to item 1, The inner layer via is a printed circuit board formed by a plurality of divided vias (41, 42, 51, 52) that penetrate at least one of the dielectric layers.

[0070] [Item 3] Item 2: The printed circuit board according to item 2, The inner layer vias are formed in a non-linear manner along the stacking direction in which the multiple dielectric layers are stacked by connecting multiple divided vias with at least one of the conductor pattern layers (155, 156).

[0071] [Item 4] The printed circuit board according to any one of items 1 to 3, In the inner layer via arrangement region, the dielectric layers are arranged from any one of the dielectric layers from the second layer to the (N-1)th layer to the (N-1)th layer, and the dielectric layers are arranged in an inner circumferential surface of the dielectric layers. The dielectric layers are further provided with additional inner layer vias (61, 62) each having an additional inner layer via conductor (61a, 62a) formed thereon, The additional inner layer via is connected to the inner layer via by at least one of the conductor pattern layers (187, 188).

[0072] [Item 5] The printed circuit board according to any one of items 1 to 4, The printed circuit board has at least some of the inner layer vias included in a central area (CA) of the inner layer via arrangement area that is sandwiched between the first through hole and the second through hole.

[0073] [Item 6] A capacitor (100) and a printed circuit board (2) on which the capacitor is mounted, The printed circuit board is A plurality of dielectric layers (21 to 29) from the first layer to the (N-1)th layer, where N is an integer of 3 or more; a plurality of conductor pattern layers (11 to 20) from a first layer to an Nth layer alternately stacked with the plurality of dielectric layers; a first through-hole (31) that penetrates through the plurality of dielectric layers from the first layer to the (N-1)th layer, has a first through-hole conductor (31a) formed on its inner circumferential surface, and into which a positive terminal (101) of the capacitor is inserted; a second through-hole (32) that penetrates through the plurality of dielectric layers from the first layer to the (N-1)th layer, has a second through-hole conductor (32a) formed on its inner circumferential surface, and into which the negative electrode terminal (102) of the capacitor is inserted; The first through hole and the second through hole are arranged parallel to each other with a through hole distance (TD) between them, and two straight lines are defined as a first straight line (L1) and a second straight line (L2) that perpendicularly intersect a through hole connecting straight line (L3) connecting the center (C1) of the first through hole and the center (C2) of the second through hole and are arranged between the first through hole and the second through hole. The positive terminal and the negative terminal are inserted into the first through hole and the second through hole, respectively. When the capacitor is arranged on the conductor pattern layer of the first layer, the area sandwiched between the first straight line and the second straight line is an inner layer via arrangement area (R1), and inner layer vias (37, 38) penetrate each of the dielectric layers from any one of the dielectric layers from the second layer to the (N-1)th layer to the dielectric layer of the (N-1)th layer, have inner layer via conductors (37a, 38a) formed on their inner circumferential surfaces, and at least a portion of which is included in the inner layer via arrangement area, An electronic control device (1) in which at least one of the first through-hole and the second through-hole is connected to the inner layer via by at least one of the conductive pattern layers from the second layer to the Nth layer.

[0074] [Item 7] Item 6. The electronic control device according to item 6, The inner layer via is formed by a plurality of divided vias (41, 42, 51, 52) that penetrate at least one of the dielectric layers.

[0075] [Item 8] Item 7. The electronic control device according to item 7, The inner layer via is formed non-linearly along the stacking direction in which the multiple dielectric layers are stacked by connecting multiple divided vias with at least one of the conductor pattern layers (155, 156).

[0076] [Item 9] The electronic control device according to any one of items 6 to 8, In the inner layer via arrangement region, additional inner layer vias (61, 62) are further provided, which penetrate each of the dielectric layers from any one of the dielectric layers from the second layer to the (N-2)th layer to the dielectric layer from the (N-1)th layer, and have additional inner layer via conductors (61a, 62a) formed on their inner circumferential surfaces, The additional inner layer vias are connected to the inner layer vias by at least one of the conductor pattern layers (187, 188).

[0077] [Item 10] The electronic control device according to any one of items 6 to 9, At least some of the inner layer vias are included in a central area (CA) of the inner layer via arrangement area that is sandwiched between the first through hole and the second through hole. [Explanation of symbols]

[0078] 1...Electronic control device, 2...Printed circuit board, 11 to 20...Conductive pattern layers, 21 to 29...Dielectric layers, 31...Positive terminal through hole, 31a...Positive terminal through hole conductor, 32...Negative terminal through hole, 32a...Negative terminal through hole conductor, 37...Positive electrode inner layer via, 37a...Positive electrode inner layer via conductor, 38...Negative electrode inner layer via, 38a...Negative electrode inner layer via conductor, 100...Capacitor, 101...Positive electrode terminal, 102...Negative terminal

Claims

1. a plurality of dielectric layers (21 to 29) from a first layer to an (N-1)th layer, where N is an integer of 3 or more; a plurality of conductor pattern layers (11 to 20) from a first layer to an Nth layer alternately stacked with the plurality of dielectric layers; a first through-hole (31) that penetrates through the plurality of dielectric layers from the first layer to the (N-1)th layer, has a first through-hole conductor (31a) formed on its inner circumferential surface, and into which a positive terminal (101) of a capacitor (100) is inserted; a second through-hole (32) that penetrates through the plurality of dielectric layers from the first layer to the (N-1)th layer, has a second through-hole conductor (32a) formed on its inner circumferential surface, and into which the negative electrode terminal (102) of the capacitor is inserted; The first through hole and the second through hole are arranged parallel to each other with a through hole distance (TD) between them, and two straight lines are defined as a first straight line (L1) and a second straight line (L2) that perpendicularly intersect a through hole connecting straight line (L3) connecting a center (C1) of the first through hole and a center (C2) of the second through hole and are arranged between the first through hole and the second through hole. The positive terminal and the negative terminal are inserted into the first through hole and the second through hole, respectively. When the capacitor is arranged on the conductor pattern layer of the first layer, the area sandwiched between the first straight line and the second straight line is an inner layer via arrangement area (R1), and inner layer vias (37, 38) penetrate each of the dielectric layers from any one of the dielectric layers from the second layer to the (N-1)th layer to the dielectric layer of the (N-1)th layer, have inner layer via conductors (37a, 38a) formed on their inner circumferential surfaces, and at least a portion of which is included in the inner layer via arrangement area, A printed circuit board (2) in which at least one of the conductor pattern layers from the second layer to the Nth layer connects at least one of the first through hole and the second through hole to the inner layer via.

2. 2. The printed circuit board according to claim 1, The inner layer via is formed by a plurality of divided vias (41, 42, 51, 52) penetrating at least one of the dielectric layers.

3. 3. The printed circuit board according to claim 2, The inner layer via is formed in a non-linear manner along the stacking direction in which the multiple dielectric layers are stacked by connecting multiple divided vias with at least one of the conductor pattern layers (155, 156).

4. The printed circuit board according to any one of claims 1 to 3, In the inner layer via arrangement region, the dielectric layers are each formed from any one of the dielectric layers from the second layer to the (N-1)th layer to the (N-1)th layer, and the dielectric layers are each formed with an additional inner layer via conductor (61a, 62a) on an inner peripheral surface thereof. The additional inner layer via is connected to the inner layer via by at least one of the conductor pattern layers (187, 188).

5. The printed circuit board according to any one of claims 1 to 3, At least a portion of the inner layer vias is included in a central area (CA) of the inner layer via arrangement area, the central area being sandwiched between the first through hole and the second through hole.

6. A capacitor (100) and a printed circuit board (2) on which the capacitor is mounted, The printed circuit board is a plurality of dielectric layers (21 to 29) from a first layer to an (N-1)th layer, where N is an integer of 3 or more; a plurality of conductor pattern layers (11 to 20) from a first layer to an Nth layer alternately stacked with the plurality of dielectric layers; a first through-hole (31) that penetrates through the plurality of dielectric layers from the first layer to the (N-1)th layer, has a first through-hole conductor (31a) formed on its inner circumferential surface, and into which a positive terminal (101) of the capacitor is inserted; a second through-hole (32) that penetrates through the plurality of dielectric layers from the first layer to the (N-1)th layer, has a second through-hole conductor (32a) formed on its inner circumferential surface, and into which the negative electrode terminal (102) of the capacitor is inserted; The first through hole and the second through hole are arranged parallel to each other with a through hole distance (TD) between them, and two straight lines are defined as a first straight line (L1) and a second straight line (L2) that perpendicularly intersect a through hole connecting straight line (L3) connecting a center (C1) of the first through hole and a center (C2) of the second through hole and are arranged between the first through hole and the second through hole. The positive terminal and the negative terminal are inserted into the first through hole and the second through hole, respectively. When the capacitor is arranged on the conductor pattern layer of the first layer, the area sandwiched between the first straight line and the second straight line is an inner layer via arrangement area (R1), and inner layer vias (37, 38) penetrate each of the dielectric layers from any one of the dielectric layers from the second layer to the (N-1)th layer to the dielectric layer of the (N-1)th layer, have inner layer via conductors (37a, 38a) formed on their inner circumferential surfaces, and at least a portion of which is included in the inner layer via arrangement area, An electronic control device (1) in which at least one of the conductor pattern layers from the second layer to the Nth layer connects at least one of the first through hole and the second through hole to the inner layer via.

7. 7. The electronic control device according to claim 6, The electronic control device, wherein the inner layer via is formed by a plurality of divided vias (41, 42, 51, 52) penetrating at least one of the dielectric layers.

8. 8. The electronic control device according to claim 7, The inner layer via is formed non-linearly along the stacking direction in which the multiple dielectric layers are stacked by connecting multiple divided vias with at least one of the conductor pattern layers (155, 156).

9. The electronic control device according to any one of claims 6 to 8, In the inner layer via arrangement region, the dielectric layers are each formed with an additional inner layer via (61, 62) that penetrates through the dielectric layers from any one of the second layer to the (N-2)th layer to the (N-1)th layer, and has an additional inner layer via conductor (61a, 62a) formed on an inner peripheral surface thereof, The additional inner layer vias are connected to the inner layer vias by at least one of the conductor pattern layers (187, 188).

10. The electronic control device according to any one of claims 6 to 8, An electronic control device in which at least a portion of the inner layer vias are included in a central area (CA) of the inner layer via arrangement area that is sandwiched between the first through hole and the second through hole.

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