Multilayer ceramic electronic component, manufacturing method thereof, circuit module, and electronic apparatus

Abstract

To provide a multilayer ceramic electronic component capable of making high capacity and high reliability compatible, and a method of manufacturing a multilayer ceramic electronic component.SOLUTION: A multilayer ceramic electronic component comprises: a plurality of dielectric layers laminated along a first axis; a plurality of internal electrode layers each disposed between the dielectric layers which are adjacent along the first axis; and an oxide layer which is disposed between the dielectric layer and the internal electrode layer. The dielectric layer contains a compound which is expressed by a general formula: ABO3-α (0≤α≤1) and has a perovskite structure. The internal electrode layer contains nickel and copper. A content of copper with respect to nickel in the internal electrode layer is 0.5 at% or more to 8.5 at% or less, a content of nickel in the oxide layer with respect to a content of nickel in the internal electrode is 90 at% or less, and a content of oxygen in the oxide layer with respect to a content of oxygen in the dielectric layer is 90 at% or less. An average thickness of the oxide layer is 1.5 nm or more to 3.7 nm or less.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to a multilayer ceramic electronic component, a manufacturing method thereof, a circuit module, and an electronic device. [Background technology]

[0002] Multilayer ceramic electronic components such as multilayer ceramic capacitors (MLCCs) have been developed for use in a variety of electronic devices, including smartphones and personal computers.

[0003] In conventional multilayer ceramic electronic components, the internal electrode layers are often composed primarily of nickel (Ni) and the dielectric layers are often composed primarily of barium titanate (BT). One known method for manufacturing multilayer ceramic electronic components involves forming and laminating a dispersion of metal particles, such as nickel (Ni) or barium titanate (BT), mixed with an organic binder in an organic solvent. The resulting dispersion is then heated at a temperature of 1000°C or less to remove excess organic binder, followed by firing in a reducing atmosphere to suppress oxidation of the Ni in the internal electrode layers.

[0004] Multilayer ceramic electronic components require good adhesion between the internal electrode layers and the dielectric layers after firing. For example, Patent Document 1 discloses that a multilayer ceramic capacitor, which is composed of alternately stacked dielectric layers and internal electrode layers, and the internal electrode layers contain a main component consisting of Ni, Cu or an alloy thereof, at least one element selected from the group consisting of elements in Groups 3B to 6B of the periodic table, and at least one element selected from Mn, Co, and Fe, suppresses the occurrence of discontinuous portions in the conductor pattern even after firing.

[0005] Furthermore, multilayer ceramic electronic components are required to have high capacity and high-temperature load reliability. For example, Patent Document 2 discloses that a multilayer electronic component has a main body including dielectric layers and internal electrodes alternately stacked with the dielectric layers sandwiched therebetween, and external electrodes disposed on the main body and connected to the internal electrodes, the internal electrodes including Cu and Ni, and the coefficient of variation (CV) of Cu / Ni (weight ratio) in a region 5 nm deep from the interface with the dielectric layer is 25.0% or less, and achieves high capacity and high-temperature load reliability. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-332572 [Patent Document 2] Japanese Patent Publication No. 2022-081390 Summary of the Invention [Problem to be solved by the invention]

[0007] In conventional methods for manufacturing multilayer ceramic electronic components, if the organic binder contained in the internal electrode layers and the dielectric layers is degreased in the atmosphere, the metal particles in the internal electrode layers are partially oxidized during the degreasing, resulting in a problem of reduced capacity and reliability under high-temperature load of the multilayer ceramic electronic component.

[0008] An object of the present disclosure is to provide a multilayer ceramic electronic component that can achieve both high capacity and high reliability, and a method for manufacturing a multilayer ceramic electronic component. [Means for solving the problem]

[0009] According to one aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device comprising: a plurality of dielectric layers stacked along a first axis; a plurality of internal electrode layers each disposed between adjacent dielectric layers along the first axis; and an oxide layer disposed between the dielectric layers and the internal electrode layers, wherein the dielectric layers are represented by a general formula ABO 3-α (0≦α≦1) and contains a compound having a perovskite structure, the internal electrode layers contain nickel and copper, the content of copper relative to the nickel in the internal electrode layers is 0.5 at% or more and 8.5 at% or less, the content of nickel in the oxide layers relative to the content of nickel in the internal electrode layers is 90 at% or less, and the content of oxygen in the oxide layers relative to the content of oxygen in the dielectric layers is 90 at% or less, and the average thickness of the oxide layers is 1.5 nm or more and 3.7 nm or less. [Effects of the Invention]

[0010] According to the present disclosure, it is possible to provide a multilayer ceramic electronic component that can achieve both high capacity and high reliability, and a method for manufacturing a multilayer ceramic electronic component. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a partial cross-sectional perspective view illustrating a multilayer ceramic capacitor according to one embodiment of the present disclosure. [Figure 2] FIG. 2 is a cross-sectional view illustrating a cross section taken along line AA in FIG. [Figure 3] FIG. 3 is a cross-sectional view illustrating a cross section taken along line BB in FIG. [Figure 4] FIG. 4 is a partial enlarged cross-sectional view of the dielectric layers, internal electrode layers, and oxide layers in region D of the element body 10 in FIG. [Figure 5] FIG. 5 is an explanatory diagram of a method for identifying an oxide layer. [Figure 6] FIG. 6 is a flowchart of a method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present disclosure. [Figure 7A]FIG. 7A is a diagram illustrating an internal electrode layer pattern forming step in a method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present disclosure. [Figure 7B] FIG. 7B is a diagram illustrating a laminate forming step in the method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present disclosure. [Figure 8] Figure 8 shows an example of the measurement results of three-dimensional atom probe analysis. DETAILED DESCRIPTION OF THE INVENTION

[0012] In this specification and the drawings, components having substantially the same functional configuration may be denoted by the same reference numerals, and redundant description may be omitted. Furthermore, in this specification and the drawings, the number, position, size, shape, etc. of each component are not limited to the embodiments of the present disclosure and may be any number, position, size, shape, etc. that is preferable for implementing the embodiments of the present disclosure. Furthermore, the drawings appropriately show mutually orthogonal X-, Y-, and Z-axes. The X-, Y-, and Z-axes define a fixed coordinate system fixed to a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component. If the outer shape of the multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component, is approximately rectangular, the X-, Y-, and Z-axes may correspond to the length, width, and height of the multilayer ceramic capacitor. Hereinafter, a multilayer ceramic electronic component of this embodiment and a method for manufacturing the multilayer ceramic electronic component of this embodiment will be described using a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component.

[0013] In this specification, unless otherwise specified, the use of "to" indicating a range of values ​​means that the values ​​before and after it are included as the lower and upper limits.

[0014] [Multilayer ceramic electronic components] The multilayer ceramic electronic component of this embodiment includes a plurality of dielectric layers stacked along a first axis, a plurality of internal electrode layers each disposed between adjacent dielectric layers along the first axis, and an oxide layer disposed between the dielectric layers and the internal electrode layers. The multilayer ceramic electronic component of this embodiment may further include other layers or members as necessary.

[0015] (1) Structure of multilayer ceramic electronic components Fig. 1 is a partial cross-sectional perspective view illustrating a multilayer ceramic capacitor 100. Fig. 2 and Fig. 3 are cross-sectional views illustrating examples of the multilayer ceramic capacitor. Fig. 2 is a cross-sectional view illustrating a cross section taken along line AA in Fig. 1. Fig. 3 is a cross-sectional view illustrating a cross section taken along line BB in Fig. 1.

[0016] The multilayer ceramic capacitor 100 comprises an element body 10 having a substantially rectangular parallelepiped shape, a first external electrode 20a, and a second external electrode 20b.

[0017] In the element body 10, two opposing surfaces are referred to as the top surface and the bottom surface, and the four surfaces connecting the top surface and the bottom surface are referred to as side surfaces. Typically, when a multilayer ceramic capacitor is mounted on a circuit board, the surface facing the board is referred to as the bottom surface, but this is not limited to this. In the example of FIGS. 1 to 3, a first external electrode 20a and a second external electrode 20b are provided on two opposing side surfaces of the element body 10, namely, a first side surface 10a and a second side surface 10b (see FIG. 2). The first external electrode 20a extends from the first side surface 10a to four adjacent surfaces. The second external electrode 20b extends from the second side surface 10b to four adjacent surfaces. However, the first external electrode 20a and the second external electrode 20b are spaced apart from each other. The external electrodes may be provided on any surface of the element body 10, not limited to two opposing side surfaces.

[0018] The stacking direction in which the dielectric layers 11 and the internal electrode layers 12 are stacked is the first axis, and in Figures 1 to 3, the first axis, which is the stacking direction in which the dielectric layers 11 and the internal electrode layers 12 are stacked, is the Z axis, which is the direction in which the internal electrode layers face each other.

[0019] The axis perpendicular to the first axis, which is the stacking direction, is the second axis. In Figures 1 to 3, the second axis perpendicular to the first axis, which is the stacking direction, is the X-axis. The second axis is along the length direction of the element body 10, and is the axis along the direction in which the first side surface 10a and the second side surface 10b of the element body 10 face each other, and the direction in which the first external electrode 20a and the second external electrode 20b face each other.

[0020] The third axis is an axis perpendicular to the first axis, which is the stacking direction, and perpendicular to the second axis. The third axis is an axis along the width of the internal electrode layer 12. In Figures 1 to 3, the third axis, which is an axis perpendicular to the first axis, which is the stacking direction, and perpendicular to the second axis, is the Y axis, which is an axis along the direction in which the third side surface 10c and the fourth side surface 10d, which are the two side surfaces other than the first side surface 10a and the second side surface 10b, of the four side surfaces of the element body 10, face each other (see Figure 3). The X axis, Y axis, and Z axis are orthogonal to each other.

[0021] The stacking direction is not limited to the Z-axis direction and can be any direction. Therefore, for example, the first axis, which is the stacking direction, may be the X-axis in the X-direction or the Y-axis in the Y-direction.

[0022] In the present application, figures illustrating a specific embodiment may be used to explain a general embodiment, and the content described using the coordinate axis system used in the embodiment is applied to the general embodiment by replacing it with a general coordinate axis system in which the stacking direction is the first axis. For example, the X-axis, Y-axis, and Z-axis used in Figures 1 to 3 in the specific embodiment, in which the stacking direction coincides with the Z-axis, can be replaced with the second axis, third axis, and first axis in the general embodiment.

[0023] The element body 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 are alternately stacked. The internal electrode layers 12 include a plurality of first internal electrode layers 12a and a plurality of second internal electrode layers 12b. The first internal electrode layers 12a and the second internal electrode layers 12b are alternately stacked. The edges of the first internal electrode layers 12a extend to the surface of the element body 10 on which the first external electrode 20a is provided, that is, the first side surface 10a in the examples of FIGS. 1 to 3. The edges of the second internal electrode layers 12b extend to the surface of the element body 10 on which the second external electrode 20b is provided, that is, the second side surface 10b in the examples of FIGS. 1 to 3. As a result, the first internal electrode layers 12a and the second internal electrode layers 12b are alternately electrically connected to the first external electrode 20a and the second external electrode 20b. Therefore, the multilayer ceramic capacitor 100 has a configuration in which capacitor units are stacked. In addition, in a laminate of dielectric layers 11 and internal electrode layers 12, the internal electrode layers 12 are arranged as the outermost layers in the lamination direction, and the outer surfaces of the laminate in the lamination direction, i.e., the upper and lower surfaces in the examples of FIGS. 1 to 3, are covered with cover layers 13. The cover layers 13 are mainly composed of a ceramic material. For example, the composition of the cover layers 13 may be the same as or different from that of the dielectric layers 11. Note that the configuration is not limited to that shown in FIGS. 1 to 3 as long as the first internal electrode layers 12a and the second internal electrode layers 12b are exposed in different regions on the surface of the laminate and are conductive to different external electrodes. The different regions on the surface of the laminate may be respective surface regions on opposing surfaces of the laminate, respective surface regions on adjacent surfaces of the laminate, or different surface regions on the same surface of the laminate. As long as the different external electrodes are spaced apart from each other, the first internal electrode layers 12a and the second internal electrode layers 12b may extend from the surfaces exposed in the surface regions of the laminate to other surfaces.

[0024] As will be described in detail later, the element body 10 has a plurality of oxide layers 40 (see FIG. 4) between the dielectric layers 11 and the internal electrode layers 12. The oxide layers 40 are not shown in FIGS. 1 to 3.

[0025] The size of the multilayer ceramic capacitor 100 is not particularly limited, and may be, for example, 0.25 mm long, 0.125 mm wide, and 0.125 mm high; 0.4 mm long, 0.2 mm wide, and 0.2 mm high; 0.6 mm long, 0.3 mm wide, and 0.3 mm high; 1.0 mm long, 0.5 mm wide, and 0.5 mm high; 3.2 mm long, 1.6 mm wide, and 1.6 mm high; or 4.5 mm long, 3.2 mm wide, and 2.5 mm high. However, the above-listed sizes of the multilayer ceramic capacitor 100 are merely examples, and the multilayer ceramic capacitor is not limited to these sizes. The size of the multilayer ceramic capacitor 100 may be, for example, length > width ≥ height; width > length ≥ height; height > length ≥ width; or height > width ≥ length. Note that, for example, length represents the size in the X-axis direction, width represents the size in the Y-axis direction, and height represents the size in the Z-axis direction.

[0026] As described above, the multilayer ceramic capacitor 100 of this embodiment has a plurality of dielectric layers 11 stacked along the Z-axis, which is the first axis, and a plurality of internal electrode layers 12 arranged between adjacent dielectric layers 11 along the first axis. Furthermore, the multilayer ceramic capacitor 100 of this embodiment has oxide layers 40 arranged between the dielectric layers 11 and the internal electrode layers 12. The dielectric layers 11, the internal electrode layers 12, and the oxide layers 40 will be described below.

[0027] (2) Dielectric layer The dielectric layer 11 is a compound represented by the general formula ABO 3-α The compound contains a perovskite structure represented by (0≦α≦1).

[0028] (2-1) Components contained in the dielectric layer <Compounds with perovskite structure> When a compound having a perovskite structure has a stoichiometric composition, α, which indicates the amount of deviation from the stoichiometric composition, is 0 and is represented by the general formula ABO3. In the compound having a perovskite structure represented by the general formula, α may be greater than 0 and equal to or less than 1. In other words, the compound having a perovskite structure represented by the general formula may have more oxygen deficiencies than the stoichiometric composition.

[0029] The general formula ABO 3-α In the general formula ABO, it is preferable that "A" is one or more elements selected from the group consisting of Ba (barium), Sr (strontium), Ca (calcium), and Mg (magnesium). 3-α In the general formula ABO, it is preferable that "B" is one or more elements selected from the group consisting of Ti (titanium), Zr (zirconium), and Hf (hafnium). 3-α In the compound having a perovskite structure represented by the formula (I), the elements "A" and "B" are located at the A site and the B site of the perovskite structure, respectively.

[0030] Specific examples of compounds having a perovskite structure include barium titanate (BaTiO3), calcium zirconate (CaZrO3), calcium titanate (CaTiO3), strontium titanate (SrTiO3), magnesium titanate (MgTiO3), and BaTiO3, which forms a perovskite structure. 1-x-y Ca x Sr y Ti 1-z Zr z One or more species selected from the group consisting of O3 (0≦x≦1, 0≦y≦1, 0≦z≦1) can be used.

[0031] Ba 1-x-y Ca x Sr y Ti 1-z Zr zExamples of O3 include barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate, and barium calcium titanate zirconate. Note that any compound having a perovskite structure may contain oxygen deficiencies.

[0032] The dielectric layer 11 preferably contains barium titanate as a compound having a perovskite structure, as this compound has particularly excellent dielectric properties. The dielectric layer 11 may contain barium titanate as a main component, or may be composed solely of barium titanate. Barium titanate has excellent dielectric properties, such as an extremely high relative permittivity and low dielectric loss. Therefore, when the dielectric layer 11 contains barium titanate as a compound having a perovskite structure, the capacitance of the multilayer ceramic capacitor 100 can be increased.

[0033] In this specification, the term "main component" refers to the component that is contained in the largest proportion of the substance amount among the components contained.

[0034] Furthermore, the compound having a perovskite structure may be contained as a main component in the dielectric layer 11. For example, the dielectric layer 11 may contain 50 mol % or more, or 90 mol % or more of the compound having a perovskite structure, or may consist solely of the compound having a perovskite structure.

[0035] <Additives> The dielectric layer 11 may contain an additive as an optional component.

[0036] The additive contained in the dielectric layer 11 is not particularly limited, and examples thereof include zirconium (Zr), magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), rare earth elements (scandium (Sc), cerium (Ce), neodymium (Nd), yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), Examples of the oxide include an oxide containing one or more elements selected from the group consisting of thulium (Tm), and ytterbium (Yb); or an oxide containing one or more elements selected from the group consisting of cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), and silicon (Si); or a glass containing one or more elements selected from the group consisting of cobalt, nickel, lithium, boron, sodium, potassium, and silicon.

[0037] (2-2) Average thickness of the dielectric layer The average thickness of the dielectric layers 11 is not particularly limited, but from the viewpoint of enabling the capacitance to be increased by increasing the number of layers while miniaturizing the multilayer ceramic capacitor 100, it is preferably, for example, 1.0 μm or less, and more preferably 0.8 μm or less. From the viewpoint of improving productivity and yield, the average thickness of the dielectric layers 11 is preferably, for example, 0.2 μm or more, and more preferably 0.4 μm or more. The lower limit and upper limit of the average thickness of the dielectric layers 11 can be appropriately combined, and it is preferably 0.2 μm or more and 1.0 μm or less, and more preferably 0.4 μm or more and 0.8 μm or less.

[0038] 1 and 2, a sample is prepared by polishing a multilayer ceramic capacitor 100 along the Y axis up to the center along the Y axis, thereby exposing the XZ plane where the dielectric layers 11 and internal electrode layers 12 are laminated. Two dielectric layers 11 located in the center along the Z axis, which is the first axis, are selected from the exposed XZ plane, and two dielectric layers 11 located at the top and bottom along the Z axis, which is the first axis, are further selected. The selected dielectric layers 11 are selected from within the capacitive section 14.

[0039] Then, for the selected dielectric layer 11, the thickness is measured at the center along the X-axis, which is the second axis, and this is defined as the thickness of the dielectric layer 11. Using the same procedure, the thicknesses of the dielectric layers 11 are measured for all six selected dielectric layers 11, and the average value is calculated. This average value is defined as the average thickness of the dielectric layers 11 in the multilayer ceramic capacitor 100. The thickness of the dielectric layers 11 can be measured using, for example, an SEM (Scanning Electron Microscope) or an STEM (Scanning Transmission Electron Microscope). The dielectric layers 11 and the internal electrode layers 12 have different compositions, and therefore can be distinguished by differences in brightness when observed in electron beam images.

[0040] (3) Internal electrode layers (3-1) Components contained in the internal electrode layer 2, the region where the first internal electrode layer 12a connected to the first external electrode 20a and the second internal electrode layer 12b connected to the second external electrode 20b face each other is a region where capacitance is generated in the multilayer ceramic capacitor 100. Therefore, the region where capacitance is generated is referred to as a capacitance portion 14. In other words, the capacitance portion 14 is a region where adjacent internal electrode layers connected to different external electrodes face each other with a dielectric layer interposed therebetween.

[0041] The region where the first internal electrode layers 12a connected to the first external electrode 20a face each other in the stacking direction without the second internal electrode layer 12b connected to the second external electrode 20b intervening therebetween is referred to as the first end margin 15a. The region where the second internal electrode layers 12b connected to the second external electrode 20b face each other in the stacking direction without the first internal electrode layer 12a connected to the first external electrode 20a intervening therebetween is referred to as the second end margin 15b. Each end margin is a region where internal electrode layers connected to the same external electrode face each other in the stacking direction without the internal electrode layer connected to a different external electrode intervening therebetween. The first end margin 15a and the second end margin 15b are regions that do not generate electrical capacitance.

[0042] The side margin 16 is a region provided outside the capacitive section 14 in a direction along the Y-axis in the example of Fig. 3, which is a third axis perpendicular to the stacking direction and perpendicular to the second axis. In other words, the side margin 16 is an outer region adjacent to the capacitive section 14 when viewed from the stacking direction, and is an outer region adjacent to the capacitive section 14 on the side where the internal electrode layer 12 is not drawn out. The side margin 16 is also a region that does not generate electrical capacitance.

[0043] The internal electrode layers 12 contain nickel (Ni) and copper (Cu). From the viewpoint of realizing high capacity, the copper content in the internal electrode layers 12 is 0.5 at% or more and 8.5 at% or less, and preferably 0.5 at% or more and 6.0 at% or less, relative to nickel (Ni). From the viewpoint of achieving both high capacity and high reliability, the copper content is more preferably 1.0 at% or more and 6.0 at% or less. The copper content relative to nickel is the atomic ratio of copper when nickel is 100 at%.

[0044] The internal electrode layer 12 may contain, in addition to nickel (Ni) and copper (Cu), other components generally used in the internal electrode layers of multilayer ceramic capacitors. Examples of other components used in the internal electrode layers of multilayer ceramic capacitors include base metals such as tin (Sn) or alloys containing such base metals; precious metals such as platinum (Pt), palladium (Pd), silver (Ag), and gold (Au) or alloys containing such precious metals. These may be used alone or in combination of two or more.

[0045] The internal electrode layer 12 may contain, as a main component, any of nickel, copper, and the components used in the internal electrode layers of the multilayer ceramic capacitor. However, it is preferable that the internal electrode layer 12 contains, as a main component, nickel, because nickel has excellent electrical properties and can reduce costs.

[0046] The main component of the first internal electrode layer 12a and the main component of the second internal electrode layer 12b may be the same or different. For example, the main components of the first internal electrode layer 12a and the second internal electrode layer 12b may both be the same, i.e., nickel, or may both be the same, i.e., copper.

[0047] The contents of nickel, copper, and other components in the internal electrode layers 12 can be confirmed by performing elemental analysis of the internal electrode layers 12 using various measuring instruments and calculating the atomic ratio of each component to all detected elements. Measuring instruments that can be used for elemental analysis include an energy dispersive X-ray spectrometer (EDS) or wavelength dispersive X-ray spectrometer (WDS) attached to a scanning electron microscope (SEM) or a scanning transmission electron microscope (STEM), an electron probe micro analyzer (EPMA), a laser irradiation inductively coupled plasma mass spectrometer (LA-ICP-MS), and the like.

[0048] (3-2) Average thickness of internal electrode layers The average thickness of the internal electrode layers 12 is not particularly limited, but is preferably 0.8 μm or less, and more preferably 0.6 μm or less, from the viewpoint of increasing the number of layers and increasing the capacitance while miniaturizing the multilayer ceramic capacitor 100. Also, from the viewpoint of improving productivity and yield, the average thickness of the internal electrode layers 12 is preferably 0.2 μm or more, and more preferably 0.4 μm or more. The lower limit and upper limit of the average thickness of the internal electrode layers 12 can be appropriately combined, and is preferably 0.2 μm or more and 0.8 μm or less, and more preferably 0.4 μm or more and 0.6 μm or less.

[0049] 1 and 2, a sample is prepared by polishing a multilayer ceramic capacitor 100 along the Y axis up to the center along the Y axis, exposing the XZ plane where the dielectric layers 11 and the internal electrode layers 12 are laminated. Two internal electrode layers 12 are selected from the exposed XZ plane, which are located in the center along the Z axis, which is the first axis, and two internal electrode layers 12 are selected from the top and bottom along the Z axis, which is the first axis. The selected internal electrode layers 12 are selected from within the capacitive section 14.

[0050] Then, for the selected internal electrode layer 12, the thickness is measured at the center along the X-axis, which is the second axis, and this is defined as the thickness of the internal electrode layer 12. Using the same procedure, the thicknesses of the internal electrode layers 12 are measured for all of the selected six internal electrode layers 12, and an average value is calculated. This average value is defined as the average thickness of the internal electrode layers 12 in the multilayer ceramic capacitor 100. The thickness of the internal electrode layers 12 can be measured, for example, with an SEM (Scanning Electron Microscope) or a STEM (Scanning Transmission Electron Microscope).

[0051] (4) Oxide layer (4-1) Average thickness of the oxide layer Fig. 4 is an enlarged partial cross-sectional view of the dielectric layer 11, the internal electrode layer 12, and the oxide layer 40 in the region D of the element body 10 in Fig. 3. Fig. 5 is an explanatory diagram of a method for identifying the oxide layer.

[0052] The inventors of the present disclosure have conducted extensive research and found that by disposing an oxide layer 40 having an average thickness of 1.5 nm or more and 3.7 nm or less between the dielectric layer 11 and the internal electrode layer 12, it is possible to achieve both high capacity and high reliability.

[0053] The oxide layer 40 is disposed between the dielectric layer 11 and the internal electrode layer 12, i.e., at the boundary between the dielectric layer 11 and the internal electrode layer 12. The oxide layer 40 is observed using a three-dimensional atom probe (3DAP). A method for identifying the oxide layer 40 will be described with reference to FIGS. 1, 2, and 5, taking an example in which the main component of the internal electrode layer 12 is nickel.

[0054] 1 and 2, a multilayer ceramic capacitor 100 is polished along the Y axis up to the center along the Y axis to prepare a sample in which the XZ plane where the dielectric layers 11 and the internal electrode layers 12 are laminated is exposed. Of the exposed XZ plane, two internal electrode layers 12 located in the center along the Z axis, which is the first axis, are selected, and further two internal electrode layers 12 located at the top and bottom along the Z axis, which is the first axis, are selected. At this time, the selected internal electrode layers 12 are selected from within the capacitive section 14.

[0055] Then, for the selected dielectric layer 11, a sample is prepared by cutting out a conical region with a diameter of the base circle of 50 nm to 200 nm and a height of 200 nm to 600 nm from a location including the interface between the central dielectric layer 11 and the internal electrode layer 12 along the X-axis, which is the second axis. This sample is measured from the dielectric layer 11 side toward the internal electrode layer 12 side using a three-dimensional atom probe, and elemental analysis is performed.

[0056] In Figure 5, the horizontal axis represents the measurement distance (nm) from the dielectric layer 11 side toward the internal electrode layer 12 side. In Figure 5, if the position of the end on the dielectric layer 11 side where measurement starts is defined as position A and the distance from position A to an arbitrary position x is expressed as measurement distance d(x) nm, then the measurement distance at position A is expressed as d(A) nm = 0 nm. If the distance from position A to position N on the end on the internal electrode layer 12 side where measurement ends is d(N) nm, then the position at measurement distance d(N) nm is expressed as d(N). The vertical axis represents the Ni concentration (at%) or O concentration (at%) measured by the 3D atom probe.

[0057] Regarding the O concentration, the average O concentration c(A) is calculated from position A, the end where measurement begins, to position (A+0.5), 0.5 nm into the measurement, i.e., the range from the position of measurement distance d(A) nm to the position of measurement distance d(A+0.5) nm. Then, the concentration c(B) is defined as 90% of the average O concentration c(A). Position B, where this concentration c(B) is located, is the position of measurement distance d(B) nm, and this position B is the boundary between the dielectric layer 11 and the oxide layer 40, and is designated "interface I."

[0058] Furthermore, regarding the Ni concentration, the average value c(C) of the Ni concentration is calculated in the range from the end position N where the measurement ends to the position (N-0.5) 0.5 nm back toward the dielectric layer 11, that is, in the range from the position of the measurement distance d(N) nm to the measurement distance d(N-0.5) nm. Then, the concentration c(D) is defined as 90% of the average Ni concentration c(C). The position C where this concentration c(D) is located is the position of the measurement distance d(C) nm, and this position C is the boundary between the oxide layer 40 and the internal electrode layer 12, and is defined as "interface II."

[0059] In this disclosure, the oxide layer 40 refers to the region between interface I and interface II. Therefore, the measured distance (nm) between interface I and interface II corresponds to the thickness of the oxide layer 40. Using the same procedure, the thicknesses of the oxide layers 40 are measured for all of the boundaries between the six selected dielectric layers 11 and internal electrode layers 12, and the average value is calculated. This average value is defined as the average thickness of the oxide layer 40 in the multilayer ceramic capacitor 100.

[0060] The average thickness of the oxide layer 40 is 1.5 nm or more and 3.7 nm or less, and from the viewpoint of realizing high capacity, it is preferably 2.0 nm or more and 3.7 nm or less, and from the viewpoint of achieving both high capacity and high reliability, it is more preferably 2.0 nm or more and 3.45 nm or less.

[0061] (4-2) Components contained in the oxide layer The oxide layer 40 contains an oxide, and the nickel content in the oxide layer 40 relative to the nickel content in the internal electrode layer 12 is 90 at % or less, and the oxygen content in the oxide layer 40 relative to the oxygen content in the dielectric layer 11 is 90 at % or less. The valence of the oxide ions in the oxide is not particularly limited, and examples thereof include monovalent ions and divalent ions. The nickel content in the internal electrode layer 12, the nickel content in the oxide layer 40, the oxygen content in the dielectric layer 11, and the oxygen content in the oxide layer 40 can each be measured using the above-mentioned three-dimensional atom probe.

[0062] The oxide in the oxide layer 40 contains at least oxygen. The oxygen in the oxide layer 40 may be bonded to at least one selected from the group consisting of nickel and copper contained in the internal electrode layer 12. That is, the oxide layer 40 may contain nickel oxide or copper oxide. In addition, when the internal electrode layer 12 contains other components used in the internal electrode layers of a multilayer ceramic capacitor, the oxide layer 40 may contain a component in which oxygen is bonded to the other component.

[0063] The multilayer ceramic capacitor 100 has an oxide layer 40 containing nickel and copper between the internal electrode layer 12 and the dielectric layer 11. Because Fig. 4 is a schematic diagram, the oxide layer 40 is shown as a continuous layer with a constant thickness, but this is not limited to this form. The oxide layer 40 may be discontinuous, for example, and may have a thickness that varies depending on the location, as long as the average thickness is 1.5 nm or more and 3.7 nm or less.

[0064] The multilayer ceramic electronic component of this embodiment can be suitably manufactured by a manufacturing method for a multilayer ceramic electronic component of this embodiment, which will be described later.

[0065] The multilayer ceramic electronic component of this embodiment can achieve both high capacity and high reliability. From this perspective, the mean time to failure of 20 multilayer ceramic electronic components measured in an accelerated life test in which a voltage of 9 V / μm is applied at 125°C and the capacitance of the multilayer ceramic electronic component preferably satisfy the following formula 1, and more preferably the value calculated by formula 1 is 1500 or greater. [Formula 1] Mean failure time × (capacity / 100) 2 ≧1200

[0066] [Manufacturing method for multilayer ceramic capacitors] The method for manufacturing a multilayer ceramic electronic component of this embodiment includes an internal electrode layer pattern forming step, a laminate forming step, a first heating step, and a second heating step. The method for manufacturing a multilayer ceramic electronic component of this embodiment may further include other steps such as a raw material powder preparing step, a slurry preparing step, a coating step, a pressure bonding step, a singulation step, a reoxidation treatment step, an external electrode forming step, and a plating treatment step.

[0067] FIG. 6 is a flowchart illustrating a method for manufacturing the multilayer ceramic capacitor 100.

[0068] Conventionally, inexpensive base metals such as Ni, used in the internal electrode layers of multilayer ceramic electronic components, generally have a low equilibrium oxygen partial pressure. Therefore, firing at high temperatures in air results in the formation of oxides and reduced electrical conductivity. Therefore, firing is typically performed in a reducing atmosphere to suppress oxidation of the metal in the internal electrode layers. Meanwhile, ceramics require an organic binder during firing to impart plasticity and shape retention. This organic binder, if present after firing, reduces capacity and must be removed from the final product. From the perspective of organic binder removal, it is desirable to fire ceramics in an oxidizing atmosphere. Furthermore, degreasing the organic binder in air can partially oxidize the metal particles in the internal electrode layers, resulting in reduced capacity and reliability under high-temperature loads. Thus, there is a trade-off between the atmospheric conditions for suppressing metal oxidation and the atmospheric conditions for removing the organic binder during firing in the manufacture of multilayer ceramic electronic components.

[0069] The inventors of the present disclosure have conducted extensive research and found that by adding a specific amount of copper oxide to the metal paste that forms the internal electrode layer pattern, in addition to nickel and an organic binder, the thickness of the oxide layer formed on the internal electrode layer can be reduced and made thinner, and further, by controlling the thickness of the oxide layer within a specific range, it is possible to manufacture a multilayer ceramic electronic component that can achieve both high capacity and high reliability. The mechanism by which the thickness of the oxide layer formed on the internal electrode layer is reduced by adding a specific amount of copper oxide to the metal paste that forms the internal electrode layer pattern is not clear, but since the free energy of formation of copper oxide is smaller than the free energy of formation of nickel oxide, it is thought that by adding a specific amount of copper oxide to the metal paste, which is more easily reduced than nickel, the copper oxide is reduced preferentially to nickel during firing, thereby suppressing the formation of an oxide layer on the surface of the nickel-containing internal electrode layer.

[0070] (1) Raw material powder preparation process (S1) In the raw material powder preparation step (S1), a ceramic raw material powder is prepared as a dielectric material for forming the dielectric layer 11. The dielectric layer 11 is formed of a ceramic material represented by the general formula ABO 3-α Since it contains a compound with a perovskite structure represented by the general formula ABO 3-α The material from which a ceramic containing a compound having a perovskite structure represented by the following formula can be obtained is used as the raw ceramic powder.

[0071] For example, barium titanate (BaTiO3) is a tetragonal compound with a perovskite structure and exhibits a high dielectric constant. Barium titanate is generally obtained by reacting a titanium source such as titanium dioxide with a barium source such as barium carbonate.

[0072] Various methods have been known for synthesizing ceramic raw material powders, such as a solid phase method, a sol-gel method, a hydrothermal method, etc. Any of these methods can be used in this embodiment.

[0073] From the viewpoint of thinning the dielectric layer 11, the number average particle size of the ceramic raw material powder is preferably 50 nm to 200 nm, and more preferably 50 nm to 100 nm.

[0074] In the raw material powder preparation step (S1), predetermined additives can be added to the ceramic raw material powder depending on the purpose. The additive compounds include one or more elements selected from the group consisting of zirconium (Zr), niobium (Nb), molybdenum (Mo), tantalum (Ta), tungsten (W), magnesium (Mg), manganese (Mn), vanadium (V), and chromium (Cr); scandium (Sc), yttrium (Y), cerium (Ce), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), and erbium (Er). Examples of suitable sintering aids include oxides containing one or more rare earth elements selected from the group consisting of thulium (Tm), ytterbium (Yb), cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), and silicon (Si); and glasses containing one or more elements selected from the group consisting of cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), and silicon (Si). These may be used alone or in combination. Among these, silicon dioxide (SiO), which is primarily an oxide of silicon (Si), functions favorably as a sintering aid.

[0075] In the raw material powder preparation step (S1), for example, a raw material powder of ceramic can be prepared by wet-mixing a compound containing additives and additive compounds as needed, followed by drying and pulverization. Furthermore, after drying and pulverization, the raw material powder can be further pulverized as needed to adjust the particle size, or the particle size can be adjusted by combining with a classification process. The raw material powder as a dielectric material can be obtained by the above steps.

[0076] (2) Slurry preparation step (S2) In the slurry preparation step (S2), a slurry containing the raw material powder obtained in the raw material powder preparation step (S1) is prepared.

[0077] The slurry may contain, in addition to the raw material powder obtained in the raw material powder preparation step (S1), an organic binder, an organic solvent, a plasticizer, etc. The organic binder is not particularly limited, and known resins such as polyvinyl butyral (PVB) resin can be used. The organic solvent is not particularly limited, and examples thereof include ethanol and toluene.

[0078] The method for preparing the slurry is not particularly limited, and examples thereof include a method in which raw material powder, an organic binder, an organic solvent, and a plasticizer are added and wet mixed. Note that when the ceramic raw material powder and the like are mixed in the raw material powder preparation step (S1), an organic binder and the like may also be added and wet mixed.

[0079] (3) Coating process (S3) In the coating step (S3), the slurry prepared in the slurry preparation step (S2) is coated onto a substrate.

[0080] In the coating step (S3), the obtained slurry can be coated on a substrate by, for example, a die coater method or a doctor blade method. This forms a dielectric layer precursor sheet 71. An example of the dielectric layer precursor sheet 71 is a ceramic precursor sheet. The thickness of the dielectric layer precursor sheet 71 can be appropriately selected depending on the average thickness of the desired dielectric layer 11.

[0081] The substrate is not particularly limited, but is preferably made of a material from which the dielectric layer precursor sheet 71 can be peeled off, and an example of this is a polyethylene terephthalate (PET) film.

[0082] In the coating step (S3), the slurry may be coated onto the substrate and then dried. An example of the coating step (S3) is omitted in the drawings.

[0083] (4) Internal electrode layer pattern formation process (S4) In the internal electrode layer pattern forming process (S4), 3-αAn internal electrode layer pattern 72 is formed on a dielectric layer precursor sheet 71 containing a ceramic raw material powder containing a compound having a perovskite structure represented by (0≦α≦1) using a metal paste containing nickel, copper oxide, and an organic binder. Specifically, the internal electrode layer pattern 72 is formed on the dielectric layer precursor sheet 71 obtained in the coating step (S3) using a metal paste containing nickel (Ni), copper oxide (CuO), and an organic binder.

[0084] FIG. 7A is a diagram illustrating an internal electrode layer pattern forming step in a method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present disclosure.

[0085] The particle size of copper oxide (CuO) is not particularly limited, but is preferably smaller than the thickness of the internal electrode layer 12, and from the viewpoint of thinning the internal electrode layer 12, is more preferably 10 nm to 100 nm.

[0086] Regarding the content of copper oxide (CuO) in the metal paste, from the viewpoint of realizing high capacity, CuO is added so that the copper (Cu) content relative to nickel (Ni) in the finished product is 0.5 at% to 8.5 at% or less, preferably 0.5 at% to 6.0 at% or less, and from the viewpoint of achieving both high capacity and high reliability, CuO is more preferably added so that the content is 1.0 at% to 6.0 at% or less. When copper oxide (CuO) is added, it may be dispersed in advance in an organic solvent such as terpineol.

[0087] As described above, the first internal electrode layer 12a and the second internal electrode layer 12b are mainly composed of nickel (Ni) or an alloy containing nickel (Ni), and may contain copper (Cu). The metal paste may further contain a base metal such as tin (Sn) or an alloy containing this, or a noble metal such as platinum (Pt), palladium (Pd), silver (Ag), or gold (Au), or an alloy containing these.

[0088] Furthermore, ceramic particles can be added to the metal conductive paste as a co-material. The main component of the ceramic particles is not particularly limited, but is preferably the same as the ceramic that is the main component of the dielectric layer 11. The particle size of the ceramic particles as the co-material is not particularly limited, but is preferably smaller than the thickness of the internal electrode layer 12, more preferably 10 nm to 100 nm from the viewpoint of thinning the internal electrode layer 12, and even more preferably 10 nm to 50 nm from the viewpoint of dispersibility of the composition.

[0089] The internal electrode layer pattern 72a in the first internal electrode layer 12a and the internal electrode layer pattern 72b in the second internal electrode layer 12b may be formed using metal pastes of the same composition or different compositions, as long as they contain nickel, copper oxide, and an organic binder. That is, the main component of the first internal electrode layer 12a and the main component of the second internal electrode layer 12b may be the same or different. As an example, the main component of both the first internal electrode layer 12a and the second internal electrode layer 12b may be the same, that is, nickel.

[0090] In the internal electrode layer pattern forming process (S4), the metal paste can be prepared by kneading nickel, copper oxide, and an organic binder, and further, if necessary, other metals or alloys or co-materials. Copper may be added in the form of a simple substance or a compound.

[0091] In the internal electrode layer pattern forming step (S4), as illustrated in Fig. 7A, a metal paste containing nickel, copper oxide, and an organic binder can be printed on the surface of the dielectric layer precursor sheet 71 by a printing method such as screen printing or gravure printing. In addition, the method for forming the internal electrode layer pattern in the internal electrode layer pattern forming step (S4) is not limited to the printing method, and a plating method, a vacuum deposition method, a sputtering method, a CVD method, etc. may also be used. As a result, a first internal electrode layer pattern 72a for the first internal electrode layer 12a or a second internal electrode layer pattern 72b for the second internal electrode layer 12b is formed on the surface of the dielectric layer precursor sheet 71.

[0092] Alternatively, a dielectric pattern paste for the reverse pattern layer can be obtained by adding an organic binder such as an ethyl cellulose-based binder and an organic solvent such as a terpineol-based binder to the raw material powder obtained in the raw material powder preparation step (S1) and kneading them in a roll mill. As illustrated in Fig. 7A, a dielectric pattern paste is formed in a peripheral region on a dielectric layer precursor sheet 71 where the first internal electrode layer pattern 72a and the second internal electrode layer pattern 72b are not formed, thereby arranging the dielectric pattern 73 and filling in the step between the first internal electrode layer pattern 72a and the second internal electrode layer pattern 72b. The dielectric layer precursor sheet 71 on which the internal electrode layer pattern 72 and the dielectric pattern 73 are formed is referred to as a lamination unit.

[0093] (5) Laminate formation process (S5) In the laminate formation step (S5), a laminate is formed by laminating a plurality of dielectric layer precursor sheets 71, on which the internal electrode layer patterns 72 have been formed, along the first axis.

[0094] FIG. 7B is a diagram illustrating a laminate forming step in the method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present disclosure.

[0095] 7B, while peeling the base material from the dielectric layer precursor sheet 71, the dielectric layer precursor sheet 71 on which the first internal electrode layer pattern 72a and the dielectric pattern 73 are formed and the dielectric layer precursor sheet 71 on which the second internal electrode layer pattern 72b and the dielectric pattern 73 are formed are laminated in this order. At this time, it is preferable to laminate the lamination units so that the internal electrode layers 12 and the dielectric layers 11 are alternately arranged and so that the edges of the internal electrode layers 12 are alternately exposed on both end faces in the length direction of the dielectric layer 11 and are alternately drawn out to a pair of external electrodes.

[0096] The number of layers in the laminate unit is not particularly limited and can be appropriately selected depending on the purpose, and can be, for example, 100 to 500 layers.

[0097] Furthermore, cover layers 13 may be further laminated on the upper and lower surfaces of the laminate of dielectric layer precursor sheets 71. The number of cover layers 13 to be laminated is not particularly limited and can be appropriately selected depending on the purpose, and can be, for example, 2 to 10 layers.

[0098] In the laminate formation step (S5), the laminate obtained as described above, preferably a laminate of dielectric layer precursor sheets 71 covered on the upper and lower surfaces with cover layers 13, is thermocompressed to form a laminate.

[0099] (6) Singulation process (S6) In the singulation step (S6), the laminate obtained in the laminate formation step (S5) is singulated.

[0100] In the singulation step (S6), the method of singulation is not particularly limited, and existing methods such as dicing and laser cutting can be used.

[0101] The size of the individual pieces is not particularly limited and can be selected appropriately depending on the desired size of the multilayer ceramic capacitor 100 .

[0102] (7) First heating step (S7) In the first heating step (S7), the laminate obtained in the laminate formation step (S5) or the laminate singulated in the singulation step (S6) is heated at a temperature equal to or higher than the degreasing temperature of the organic binder and lower than the firing temperature.

[0103] The heating temperature in the first heating step (S7) is not particularly limited as long as it is equal to or higher than the degreasing temperature of the organic binder and lower than the firing temperature, but it is preferable to heat at 800°C or higher and 1000°C or lower. The heating time in the first heating step (S7) is also not particularly limited, but it is preferable to hold the laminate at a temperature of 800°C or higher and 1000°C or lower for 3 minutes or lower and 5 minutes or lower. Among these, holding the laminate at a temperature of 800°C or higher and 1000°C or lower for 3 minutes or lower and 5 minutes or lower in the first heating step (S7) is particularly preferable from the viewpoint of reducing the thickness of the oxide layer 40 and achieving both high capacity and high reliability.

[0104] Organic binders are generally burned off at approximately 500°C. Therefore, the organic binder can also be degreased in the first heating step (S7). Note that in the first heating step (S7), the temperature of the laminate may be gradually increased until it reaches a heating temperature equal to or higher than the degreasing temperature of the organic binder.

[0105] The oxygen partial pressure in the first heating step (S7) is not particularly limited, but is preferably 10 -12 atm over 10 -7 atm or less is preferable, and 10 -10 atm over 10 -7 atm or less is preferable, and 10 -8 atm over 10 -7 Atm or less is more preferable.

[0106] The atmospheric conditions in the first heating step (S7) are preferably a reducing atmosphere.

[0107] (8) Second heating step (S8) In the second heating step (S8), the dielectric layer 11 is formed from the dielectric layer precursor sheet 71, the internal electrode layer 12 is formed from the internal electrode layer pattern so that the copper content relative to the nickel is 0.5 at% or more and 8.5 at% or less, and the laminate is heated so as to form an oxide layer 40 having an average thickness of 1.5 nm or more and 3.7 nm or less between the dielectric layer and the internal electrode layer. By the second heating step (S8), the nickel content in the oxide layer 40 relative to the nickel content in the internal electrode layer 12 becomes 90 at% or less, and the oxygen content in the oxide layer 40 relative to the oxygen content in the dielectric layer 11 becomes 90 at% or less. The second heating step (S8) is performed after the first heating step (S7).

[0108] The heating temperature in the second heating step (S8) is not particularly limited, but is preferably 1100°C or higher and 1300°C or lower. The heating time in the second heating step (S8) is also not particularly limited, but is preferably maintained for 10 minutes to 2 hours. Among these, it is particularly preferred that in the second heating step (S8), the laminate that has been subjected to the first heating step (S7) be maintained at a temperature of 1100°C or higher and 1300°C or lower for 10 minutes to 2 hours.

[0109] The oxygen partial pressure in the second heating step (S8) is not particularly limited, but is preferably 10 -12 atm over 10 -7 atm or less is preferable, and 10 -10 atm over 10 -7 atm or less is preferable, and 10 -8 atm over 10 -7 As described above, since the metal paste used to form the internal electrode layer pattern contains copper oxide, the thickness of the oxide layer 40 of the internal electrode layer can be reduced even under such an oxygen partial pressure.

[0110] The atmospheric conditions in the second heating step (S8) are preferably a reducing atmosphere.

[0111] (9) Reoxidation treatment step (S9) In the reoxidation treatment step (S9), heat treatment is performed in a mixed gas of water vapor in a reducing atmosphere at 600°C to 1000°C, or in air at 500°C to 700°C. This allows oxygen to be returned to the partially reduced main phase of the dielectric layer 11 fired in a reducing atmosphere. Note that the reoxidation treatment step (S9) is performed in a manner that does not oxidize the internal electrode layers 12.

[0112] (10) External electrode formation process (S10) In the external electrode formation process (S10), a metal paste is applied to two opposing side surfaces, the first side surface 10a and the second side surface 10b, of the laminate obtained in the second heating process (S8) or the laminate that has undergone the reoxidation treatment process (S9).

[0113] In the external electrode forming step (S10), a metal paste can be applied to the first side surface 10a and the second side surface 10b of the laminate by, for example, a dipping method, a plating process, etc. In this way, the first external electrode 20a and the second external electrode 20b are formed.

[0114] In the external electrode forming step (S10), it is preferable to apply a metal paste to the first side surface 10a and the second side surface 10b of the laminate and then dry it.

[0115] The metal paste used in the external electrode forming step (S10) may have the same composition as or a different composition from the metal paste used in the internal electrode layer pattern forming step (S4), except for the organic binder. The metal paste used in the external electrode forming step (S10) may be, for example, a metal paste containing nickel (Ni) as the main component and containing ceramic particles, powder of an additive metal element, or the like as co-materials. The metal paste used in the external electrode forming step (S10) may contain a glass component. The inclusion of a glass component can reduce voids inside the external electrode and increase its strength.

[0116] (11) Plating process (S11) In the plating step (S11), the exposed portions of the first external electrode 20a and the second external electrode 20b are plated using a metal such as copper (Cu), nickel (Ni), or tin (Sn).

[0117] Through the above steps, the multilayer ceramic capacitor 100 can be manufactured.

[0118] The above steps are merely an example, and the method for manufacturing the multilayer ceramic capacitor of this embodiment is not limited to the above-described embodiment.

[0119] [Other embodiments] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. For example, the first external electrode 20a and the second external electrode 20b can be formed after the singulation step, and then the first external electrode 20a and the second external electrode 20b can be sintered simultaneously with firing the dielectric layer precursor sheet 71 in the first heating step and the second heating step.

[0120] For example, although the above embodiment is applied to a multilayer ceramic capacitor having two terminal electrodes, it may also be applied to a multilayer ceramic capacitor having three or more terminals.

[0121] Although the above embodiment describes a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component, the present disclosure is applicable to multilayer ceramic electronic components in general, such as chip varistors and chip thermistors.

[0122] [Circuit Module] The circuit module of this embodiment includes the multilayer ceramic electronic component of this embodiment. A specific example of the circuit module is one in which the multilayer ceramic capacitor 100 is mounted on an electronic circuit board.

[0123] In addition to the multilayer ceramic capacitor 100, various other electronic components can also be mounted on the circuit module.

[0124] [Electronic equipment] The electronic device of this embodiment includes the circuit module of this embodiment. Specific examples of the electronic device include smartphones, tablets, game consoles, automotive electrical components, and servers, but may also include various other electronic devices. [Example]

[0125] The present disclosure will be specifically explained below with reference to examples and comparative examples, but the present disclosure is not limited to these examples in any way.

[0126] [Example 1] The multilayer ceramic capacitor 100 was manufactured according to the flowchart shown in FIG.

[0127] <Raw material powder preparation step (S1) and slurry preparation step (S2)> Barium titanate powder was wet mixed with polyvinyl butyral (PVB) resin as an organic binder, ethanol, toluene, dioctyl phthalate (DOP) as a plasticizer, and silicon dioxide (SiO2) as a sintering aid to prepare a slurry.

[0128] <Coating process (S3)> The obtained slurry was applied onto a polyethylene terephthalate (PET) film using a die coater and dried to prepare a dielectric layer precursor sheet.

[0129] <Internal electrode layer pattern formation process (S4)> A metal conductive paste was prepared by adding copper oxide dispersed in terpineol to a mixture of nickel powder as the main component and polyvinyl butyral resin as an organic binder so that the copper content relative to nickel in the finished product would be 0.5 at%. The metal conductive paste was printed by screen printing on a dielectric layer precursor sheet to form an internal electrode layer pattern that alternately leads to a pair of external electrodes, thereby forming a laminate unit. This laminate unit has a dielectric layer precursor sheet and an internal electrode layer pattern formed on the surface of the dielectric layer precursor sheet.

[0130] <Laminate formation step (S5)> While peeling off the PET film from the dielectric layer precursor sheet, 400 laminated units were stacked to form a laminate. Five cover layers were then stacked on the top and bottom surfaces of the laminate of laminated units, followed by thermocompression bonding to form a laminate. The cover layers had the same composition as the dielectric layer precursor sheet.

[0131] <Singulation process (S6)> The laminate was cut into individual pieces of 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height by dicing, to obtain chip-shaped laminates (hereinafter sometimes referred to as "ceramic laminate precursors").

[0132] <First heating step (S7)> The ceramic laminate precursor was heated at an oxygen partial pressure of 10 -7 The mixture was fired at 950°C for 5 minutes in a reducing atmosphere of 1 atm.

[0133] <Second heating step (S8)> Next, oxygen partial pressure 10 -7 The mixture was fired at 1200°C for 1 hour in a reducing atmosphere of 1 atm.

[0134] <Reoxidation treatment step (S9)> After the second heating step (S8), a reoxidation treatment was further carried out at 900° C. in a nitrogen gas atmosphere.

[0135] <External electrode formation process (S10)> In the laminate that had undergone the reoxidation treatment step (S9), the two opposing side surfaces, the first side surface 10a and the second side surface 10b, were plated with nickel (Ni) to form the first external electrode 20a and the second external electrode 20b.

[0136] As a result of the above, a multilayer ceramic capacitor 100 was produced, having a chip shape of 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, with the dielectric layers 11 having an average thickness of 0.4 μm, the internal electrode layers 12 having an average thickness of 0.6 μm, and the oxide layers 40 having an average thickness of 3.64 nm, and with 400 layers stacked.

[0137] (Examples 2 to 8 and Comparative Examples 1 to 3) The multilayer ceramic capacitors of Examples 2 to 8 and Comparative Examples 1 to 3 were produced in the same manner as in Example 1, except that in the internal electrode layer pattern forming step (S4) of Example 1, the amount of copper oxide added was changed so that the copper content relative to nickel in the finished product would be as shown in Table 1 below.

[0138] (Comparative Examples 4 to 7) The multilayer ceramic capacitors of Comparative Examples 4 to 7 were produced in the same manner as in Example 1, except that the first heating step (S7) was not performed and the second heating step (S8) was performed after the singulation step (S6).

[0139] The multilayer ceramic capacitors of Examples 1 to 8 and Comparative Examples 1 to 7 were subjected to the following methods: "measurement of the Cu content relative to Ni in the internal electrode layers," "measurement of the average thickness of the oxide layers," "measurement and evaluation of the capacitance," and "measurement and evaluation of the reliability." The evaluation results are shown in Table 1 below.

[0140] <Measurement of Cu content relative to Ni content in internal electrode layers> The multilayer ceramic capacitors 100 of Examples 1 to 8 and Comparative Examples 1 to 7 were each polished along the Y axis up to the center along the Y axis to prepare samples in which the XZ planes on which the dielectric layers 11 and internal electrode layers 12 were laminated were exposed. Of the exposed XZ planes, two internal electrode layers 12 located in the center along the Z axis, which is the first axis, were selected, and further two internal electrode layers 12 located at the top and bottom along the Z axis, which is the first axis, were selected. At this time, the selected internal electrode layers 12 were selected from within the capacitive section 14.

[0141] The contents of nickel, copper, and other components in the internal electrode layer 12 were analyzed for each measurement point using an energy dispersive X-ray spectrometer (EDS) attached to a scanning electron microscope (SEM), and the proportion of Cu was calculated based on the amounts of Cu and Ni (at%) from the measurement results obtained for each element, assuming Ni to be 100. The results obtained for each measurement point were averaged to determine the Cu content relative to Ni in the internal electrode layer of the sample.

[0142] <Measurement of the average thickness of the oxide layer> The multilayer ceramic capacitors 100 of Examples 1 to 8 and Comparative Examples 1 to 7 were each polished along the Y axis up to the center along the Y axis to prepare samples in which the XZ planes on which the dielectric layers 11 and internal electrode layers 12 were laminated were exposed. Of the exposed XZ planes, two internal electrode layers 12 located in the center along the Z axis, which is the first axis, were selected, and further two internal electrode layers 12 located at the top and bottom along the Z axis, which is the first axis, were selected. At this time, the selected internal electrode layers 12 were selected from within the capacitive section 14.

[0143] For the selected dielectric layer 11, a conical region with a diameter of the bottom circle of 100 nm and a height of 400 nm was cut out from a location including the interface between the central dielectric layer 11 and the internal electrode layer 12 along the second axis, the X-axis, using a focused ion beam (FIB) device (manufactured by FEI), and used as a sample for measuring the average thickness of the oxide layer 40.

[0144] The measurement sample was subjected to elemental analysis using a three-dimensional atom probe (LEAP5000XS, manufactured by AMETEK Corporation) in a measurement mode of laser pulse at a laser wavelength of 355 nm, from the dielectric layer 11 side to the internal electrode layer 12 side, and the element distribution inside the measurement sample was obtained three-dimensionally at the atomic level. Using the profile data of various elements obtained by the measurement from the dielectric layer 11 side to the internal electrode layer 12 side, the film thickness of the oxide layer 40 was evaluated.

[0145] The average O concentration c(A) was calculated from position A, the end where the measurement started, to position (A+0.5), 0.5 nm into the measurement, i.e., from the position at measurement distance d(A) nm to the position at measurement distance d(A+0.5) nm. The concentration c(B) was determined to be 90% of the average O concentration c(A). Position B, where this concentration c(B) was found, was at a measurement distance of d(B) nm. Position B was the boundary between the dielectric layer 11 and the oxide layer 40, and was designated "interface I."

[0146] Furthermore, regarding the Ni concentration, the average value c(C) of the Ni concentration was calculated in the range from the end position N where the measurement was completed to the position (N-0.5) 0.5 nm back toward the dielectric layer 11, that is, in the range from the position of the measurement distance d(N) nm to the measurement distance d(N-0.5) nm. Then, the concentration c(D) was defined as 90% of the average Ni concentration c(C). The position C where this concentration c(D) was located was the position of the measurement distance d(C) nm, and this position C was defined as the boundary between the oxide layer 40 and the internal electrode layer 12, and was defined as "interface II."

[0147] Next, the range from interface I to interface II was designated as the "oxidation layer 40," and the thickness of the oxidation layer 40 was calculated from the profile data of various elements obtained by measurement in the direction from the dielectric layer 11 side to the internal electrode layer 12 side.

[0148] Using the same procedure, the thickness of the oxide layer 40 was measured for all of the boundaries between the six selected dielectric layers 11 and the internal electrode layers 12, and the average value of the thicknesses of these oxide layers 40 was calculated as the "average thickness of the oxide layer."

[0149] 8 shows the measurement results of Example 6 as an example of the measurement results of the three-dimensional atom probe analysis. By performing the three-dimensional atom probe analysis, the content ratio of each element contained in the dielectric layer 11, the internal electrode layer 12, and the oxide layer 40 can be measured and calculated.

[0150] From the measurement results, the graphs of copper oxide (CuO) contained in the internal electrode layer 12 and oxygen (O) resulting from oxidation during firing were used to calculate the average O concentration c(A) in the range from the end position A where the measurement started to the position (A+0.5) 0.5 nm further along in the measurement, i.e., the range from the position of measurement distance d(A) nm to the measurement distance d(A+0.5) nm. Then, the concentration c(B) was defined as 90% of the average O concentration c(A). The position B where this concentration c(B) was located was the position of measurement distance d(B) nm, and this position B was defined as the boundary between the dielectric layer 11 and the oxide layer 40, leading to the "interface I." Furthermore, from the graphs resulting from nickel (Ni) contained as a main component in the internal electrode layer 12, the average Ni concentration c(C) was calculated in the range from the end position N where the measurement ended to the position (N-0.5) 0.5 nm back toward the dielectric layer 11, i.e., the range from the position of measurement distance d(N) nm to the measurement distance d(N-0.5) nm. The concentration c(D) was 90% of the average Ni concentration c(C). The position C where this concentration c(D) was located was at a measurement distance d(C) nm, and this position C was defined as the boundary between the oxide layer 40 and the internal electrode layer 12, leading to the "interface II."

[0151] <Capacity measurement and evaluation> The multilayer ceramic capacitors of Examples 1 to 8 and Comparative Examples 1 to 7 were left at 150°C for 1 hour, and then left under standard conditions for 24 hours, after which they were measured using an LCR meter (manufactured by Keysight Technologies (Agilent)) under conditions of 0.5V-1kHz. The capacitance of the multilayer ceramic capacitor of Comparative Example 1 was taken as 100%, and the ratio of the capacitance of the multilayer ceramic capacitors of Examples 1 to 8 and Comparative Examples 2 to 7 to the capacitance of Comparative Example 1 was calculated. From this ratio, evaluation was performed based on the following evaluation criteria. -Evaluation criteria for capacitance- A (Pass): The capacitance of the measured sample is 80% or more of the capacitance of the multilayer ceramic capacitor of Comparative Example 1. B (Pass): The capacitance of the measured sample is 65% or more and less than 80% of the capacitance of the multilayer ceramic capacitor of Comparative Example 1. C (Fail): The capacitance of the measured sample is less than 65% of the capacitance of the multilayer ceramic capacitor of Comparative Example 1.

[0152] <Mean Time to Failure (MTTF) Measurement and Evaluation> The multilayer ceramic capacitors of Examples 1 to 8 and Comparative Examples 1 to 7 were subjected to an accelerated life test in which a voltage of 9 V / μm was applied at 125° C. For each of the multilayer ceramic capacitors of Examples 1 to 8 and Comparative Examples 1 to 7, the mean time to failure (MTTF) was measured for 20 measurement samples and evaluated based on the following evaluation criteria. -MTTF evaluation criteria- A (Pass): MTTF is 2000 minutes or more B (Pass): MTTF is between 1000 and 2000 minutes C (Fail): MTTF is less than 1000 minutes

[0153] <Overall rating> The value was calculated from the capacitance ratio and the mean time to failure (MTTF) using the following formula 1, and evaluated based on the following evaluation criteria. This was used as the overall evaluation. [Formula 1] Reliability x (Capacity / 100) 2 -Evaluation criteria for overall evaluation- A (Pass): The value calculated by Formula 1 is 1500 or more B (Pass): The value calculated by Formula 1 is between 1200 and 1500 C (Fail): The value calculated by formula 1 is less than 1200

[0154] [Table 1]

[0155] In Example 1 and Comparative Example 4, Example 2 and Comparative Example 5, and Example 4 and Comparative Example 6, the copper content relative to nickel in the internal electrode layer 12 is equal, but Comparative Examples 4 to 6 do not include the first heating step, which results in a thicker oxide layer 40, and it was confirmed that reliability and capacity were not compatible.

[0156] Comparative Example 2, which has a lower copper content relative to nickel than Example 1, includes the first heating step, but the amount of copper migration due to the first heating step is thought to be insufficient because the copper content relative to nickel in the internal electrode layer 12 is low, which is thought to be why reliability has not been improved.

[0157] Although Comparative Example 3 includes the first heating step, it is believed that a large amount of copper migrates during the first heating step due to the excessive copper content relative to nickel in the internal electrode layer 12. This is thought to result in a thin oxide layer 40, which makes it impossible to achieve both reliability and capacity.

[0158] In Comparative Example 3 and Comparative Example 7, the copper content relative to nickel in the internal electrode layer 12 is the same. However, Comparative Example 7 does not have the first heating step, which results in a thicker oxide layer 40, and it was confirmed that reliability and capacity are not compatible.

[0159] From these results, it can be concluded that in order to achieve both reliability and capacity, it is necessary for the first heating step to cause an appropriate amount of copper migration in the internal electrode layers 12. By appropriately adjusting the content of copper relative to nickel in the internal electrode layers 12 after firing with the first heating step, it is possible to make the oxide layer 40 have an appropriate thickness after firing.

[0160] The copper content relative to nickel in the internal electrode layers 12 after firing with the first heating step is preferably 0.5 at% to 8.5 at% and the average thickness of the oxide layer 40 is preferably 1.5 nm to 3.7 nm, in order to achieve both capacity and reliability. From the viewpoint of achieving high capacity, the copper content relative to nickel is preferably 0.5 at% to 6.0 at% and the average thickness of the oxide layer is preferably 2.0 nm to 3.7 nm, and from the viewpoint of achieving high capacity and high reliability, the copper content relative to nickel is more preferably 1.0 at% to 6.0 at% and the average thickness of the oxide layer is more preferably 2.0 nm to 3.45 nm.

[0161] As described above, the present disclosure has been described based on specific embodiments and examples, but these embodiments and examples are presented merely as examples, and the present disclosure is not limited to the above embodiments and examples. The above embodiments can be implemented in various other forms, and various combinations, omissions, substitutions, additions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as set forth in the claims.

[0162] Aspects of the present disclosure include, for example, the following. <1> a plurality of dielectric layers stacked along a first axis; a plurality of internal electrode layers each disposed between adjacent dielectric layers along the first axis; an oxide layer disposed between the dielectric layer and the internal electrode layer, The dielectric layer is a compound of the general formula ABO 3-α Contains a compound having a perovskite structure represented by (0≦α≦1), the internal electrode layers contain nickel and copper, and the content of the copper relative to the nickel in the internal electrode layers is 0.5 at % or more and 8.5 at % or less; the content of nickel in the oxide layer relative to the content of nickel in the internal electrode layer is 90 at % or less, and the content of oxygen in the oxide layer relative to the content of oxygen in the dielectric layer is 90 at % or less, In the multilayer ceramic electronic component, the average thickness of the oxide layer is 1.5 nm or more and 3.7 nm or less. <2> the mean time to failure of 20 of the multilayer ceramic electronic components measured in an accelerated life test in which a voltage of 9 V / μm is applied at 125° C., and the capacitance of the multilayer ceramic electronic components satisfy the following formula 1: <1> 1. The multilayer ceramic electronic component according to claim 1. [Formula 1] Mean failure time × (capacity / 100) 2 ≧1200 <3> the dielectric layer contains barium titanate as the compound having a perovskite structure; <1> or the above <2> 1. The multilayer ceramic electronic component according to claim 1. <4> The aforementioned <1> From the above <3> A circuit module is provided with the multilayer ceramic electronic component according to any one of the above items. <5> The aforementioned <4> An electronic device having the circuit module described above. <6> General formula ABO 3-α an internal electrode layer pattern forming step of forming an internal electrode layer pattern on a dielectric layer precursor sheet containing a raw material powder of a ceramic containing a compound having a perovskite structure represented by (0≦α≦1) using a metal paste containing nickel, copper oxide, and an organic binder; a laminate forming step of forming a laminate by laminating a plurality of the dielectric layer precursor sheets, on which the internal electrode layer patterns are formed, along a first axis; a first heating step of heating the laminate at a temperature equal to or higher than a degreasing temperature of the organic binder and lower than a firing temperature; a second heating step of heating the laminate so as to form a dielectric layer from the dielectric layer precursor sheet, form an internal electrode layer from the internal electrode layer pattern so that the content of copper relative to the nickel is 0.5 at% or more and 8.5 at% or less, and form an oxide layer having an average thickness of 1.5 nm or more and 3.7 nm or less between the dielectric layer and the internal electrode layer; Including, The method for manufacturing a multilayer ceramic electronic component is characterized in that the nickel content in the oxide layer relative to the nickel content in the internal electrode layer is 90 at % or less, and the oxygen content in the oxide layer relative to the oxygen content in the dielectric layer is 90 at % or less. <7> The first heating step is performed by holding the temperature at 800°C or higher and 1000°C or lower for 3 minutes or longer and 5 minutes or shorter. <6> 1. A method for producing the multilayer ceramic electronic component according to claim 1. <8> The second heating step is -12 atm over 10 -7 The method is carried out in an atmosphere having an oxygen partial pressure of atm or less. <6> or the above <7> 1. A method for producing the multilayer ceramic electronic component according to claim 1. [Explanation of symbols]

[0163] 100 Multilayer ceramic capacitors 10 Base 10a First side 10b Second side 11 Dielectric layer 12 Internal electrode layer 12a 1st internal electrode layer 12b Second internal electrode layer 13 Cover Layer 14 Capacity part 15a First End Margin 15b Second End Margin 16 Side Margin 20a 1st external electrode 20b 2nd external electrode C area D area 40 Oxide layer S1 Raw material powder preparation process S2 Slurry preparation process S3 Coating process S4 Internal electrode layer pattern formation process S5 Laminate formation process S6 singulation process S7 First heating process S8 Second heating process S9 Reoxidation treatment process S10 External electrode formation process S11 Plating process 71 Dielectric layer precursor sheet 72 Internal electrode layer pattern 72a First internal electrode layer pattern 72b Second internal electrode layer pattern 73 Dielectric Pattern d0 End where measurement starts d1 Measurement distance with density c2 d2 Measurement distance with density c4 dN End point at which measurement ends c1 Average O concentration c2: 90% of the average O concentration c1 c3 Average Ni concentration c4 Average Ni concentration: 90% of c3

Claims

1. a plurality of dielectric layers stacked along a first axis; a plurality of internal electrode layers each disposed between adjacent dielectric layers along the first axis; an oxide layer disposed between the dielectric layer and the internal electrode layer, The dielectric layer is formed of a material having the general formula ABO ３－α (0≦α≦1) the internal electrode layers contain nickel and copper, and the content of the copper relative to the nickel in the internal electrode layers is 0.5 at% or more and 8.5 at% or less; a content of nickel in the oxide layer relative to a content of nickel in the internal electrode layer is 90 at % or less, and a content of oxygen in the oxide layer relative to a content of oxygen in the dielectric layer is 90 at % or less, The average thickness of the oxide layer is 1.5 nm or more and 3.7 nm or less.

2. 2. The multilayer ceramic electronic component according to claim 1, wherein a mean time to failure of 20 of the multilayer ceramic electronic components measured in an accelerated life test in which a voltage of 9 V / μm is applied at 125° C. and a capacitance of the multilayer ceramic electronic component satisfy the following formula 1: [Formula 1] Mean time between failures × (capacity / 100) ２ ≧1200

3. 3. The multilayer ceramic electronic component according to claim 1, wherein the dielectric layers contain barium titanate as the compound having a perovskite structure.

4. A circuit module comprising the multilayer ceramic electronic component according to claim 1 or 2.

5. An electronic device comprising the circuit module according to claim 4.

6. General formula ABO ３－α an internal electrode layer pattern forming step of forming an internal electrode layer pattern on a dielectric layer precursor sheet containing a raw material powder of a ceramic containing a compound having a perovskite structure represented by (0≦α≦1), using a metal paste containing nickel, copper oxide, and an organic binder; a laminate forming step of forming a laminate by laminating a plurality of the dielectric layer precursor sheets, on which the internal electrode layer patterns are formed, along a first axis; a first heating step of heating the laminate at a temperature equal to or higher than a degreasing temperature of the organic binder and lower than a firing temperature; a second heating step of heating the laminate so as to form a dielectric layer from the dielectric layer precursor sheet, form an internal electrode layer from the internal electrode layer pattern so that a copper content relative to the nickel is 0.5 at% or more and 8.5 at% or less, and form an oxide layer having an average thickness of 1.5 nm or more and 3.7 nm or less between the dielectric layer and the internal electrode layer; Including, a content of nickel in the oxide layer relative to a content of nickel in the internal electrode layer is 90 at % or less, and a content of oxygen in the oxide layer relative to a content of oxygen in the dielectric layer is 90 at % or less.

7. 7. The method for producing a multilayer ceramic electronic component according to claim 6, wherein the first heating step comprises holding the laminate at a temperature of 800° C. to 1000° C. for 3 minutes to 5 minutes.

8. The second heating step －１２ atm over 10 －７ 8. The method for producing a multilayer ceramic electronic component according to claim 6, wherein the step is carried out in an atmosphere having an oxygen partial pressure of not more than 1 atm.

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