Semiconductor optical element

Abstract

To provide a semiconductor optical element that excels in characteristics.SOLUTION: The semiconductor optical element comprises: a first electrode having an insulating semiconductor layer, a first conductive semiconductor layer located on top of the insulating semiconductor layer, an optical function layer located on top of the first conductive semiconductor layer and forming a mesa structure, a second conductive semiconductor layer located on top of the optical function layer, and a first pad electrode for inputting electric signals, and connected to the first conductive semiconductor layer; and a second electrode having a second pad electrode for inputting electric signals and connected to the second conductive semiconductor layer. The first conductive semiconductor layer includes a first region, a second region, and a high resistance region superimposed on the whole or part of the second region in a plan view. The first region is superimposed on the entire area of the first pad electrode in a plan view, and the second region is superimposed on the entire area of the second pad electrode in a plan view. The high resistance region is located avoiding the optical function layer in a plan view, and the outer edge of the high resistance region partitions the first region and the second region in a plan view.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor optical device. [Background technology]

[0002] Semiconductor optical devices used in optical communications include an optical functional layer where light emission, absorption, etc. occur, and two electrodes for inputting electrical signals to the optical functional layer. Semiconductor optical devices in which the two electrodes are arranged on the same surface of a semiconductor substrate are known (Patent Documents 1 and 2). Another known structure of semiconductor optical devices is a buried heterostructure (hereinafter referred to as BH structure) that includes a mesa structure and has semiconductor layers buried on both sides of the mesa structure. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 5-136447 [Patent Document 2] Patent Publication No. 2013-222795 Summary of the Invention [Problem to be solved by the invention]

[0004] Electrodes are necessary to transmit electrical signals input from external devices to the optical functional layer. To connect to external devices, electrodes also include a portion of a certain size. This portion is called, for example, an electrode pad. These electrode pads can also cause parasitic capacitance. To reduce parasitic capacitance, it is known to electrically isolate the region below the electrode pad from other regions. For example, Patent Document 1 discloses growing a semiconductor multilayer structure on a semi-insulating substrate, and then forming a diffusion region in which p-type or insulating impurities are diffused from the top surface of the semiconductor multilayer to the semi-insulating substrate, thereby reducing the parasitic capacitance of the electrode pad (bonding pad). Patent Document 2 also discloses reducing parasitic capacitance by forming a groove around the electrode pad that reaches the semi-insulating substrate.

[0005] In Patent Document 1, a p-type or insulating impurity diffusion region is formed by diffusing impurities from the top surface of the semiconductor multilayer. However, applying a similar formation method to a semiconductor optical device with a BH structure raises the following concerns. First, when diffusing impurities from the top surface of the semiconductor multilayer to the region extending to the semi-insulating substrate, the diffusion process is difficult to control, and the impurities may not be placed in the desired region. For example, if the diffusion region does not extend to the semi-insulating substrate, sufficient parasitic capacitance reduction may not be achieved. This problem is particularly pronounced when the semiconductor multilayer is thick. Second, to reduce parasitic capacitance, it is effective to position the diffusion region as close as possible to the optical functional layer. However, if the diffusion region is positioned directly next to the optical functional layer (here, the absorption layer), as in Patent Document 1, optical effects may occur. For example, there is a concern that the diffusion region may increase the amount of light absorption.

[0006] Furthermore, when the electrode pad is surrounded by a groove as in Patent Document 2, the wiring length from the electrode pad to the mesa structure becomes long. In particular, when surrounded by a groove, electrodes must also be placed on the side surfaces of the groove. When the wiring length is long, the inductance component increases, which is disadvantageous for high-speed operation.

[0007] An object of the present invention is to provide a semiconductor optical device that reduces parasitic capacitance and has excellent high-speed operating characteristics. [Means for solving the problem]

[0008] a first pad electrode for inputting an electrical signal and connected to the first conductive type semiconductor layer; and a second pad electrode for inputting an electrical signal and connected to the second conductive type semiconductor layer. The first conductive type semiconductor layer includes a first region, a second region, and a high resistance region overlapping part or all of the second region in a planar view. The first region overlaps the entire first pad electrode in a planar view, and the second region overlaps the entire second pad electrode in a planar view. The high resistance region is positioned to avoid the optical function layer in a planar view. The outer edge of the high resistance region separates the first region from the second region in a planar view. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a top view of a semiconductor optical device according to a first embodiment. [Figure 2] 2 is a schematic cross-sectional view of the semiconductor optical device shown in FIG. 1 taken along line II-II. [Figure 3A] 3 is a schematic cross-sectional view of the semiconductor optical device shown in FIG. 1 taken along line III-III. [Figure 3B] 3 is a schematic cross-sectional view of the semiconductor optical device shown in FIG. 1 taken along line III-III. [Figure 3C] 3 is a schematic cross-sectional view of the semiconductor optical device shown in FIG. 1 taken along line III-III. [Figure 4] FIG. 4 is a diagram for explaining the effect of the first embodiment. [Figure 5] FIG. 2 is a top view of a semiconductor optical device according to a first modification of the first embodiment. [Figure 6]FIG. 10 is a top view of a semiconductor optical device according to a second modification of the first embodiment. [Figure 7] FIG. 10 is a top view of a semiconductor optical device according to a second embodiment. [Figure 8] 8 is a schematic cross-sectional view of the semiconductor optical device shown in FIG. 7 taken along line VIII-VIII. [Figure 9] FIG. 10 is a top view of a semiconductor optical device according to a third embodiment. [Figure 10] 10 is a schematic cross-sectional view of the semiconductor optical device shown in FIG. 9 taken along line XX. [Figure 11] 10 is a schematic cross-sectional view taken along line XI-XI of the semiconductor optical device shown in FIG. 9. [Figure 12] FIG. 11 is a top view of a semiconductor optical device according to a first modified example of the third embodiment. [Figure 13] FIG. 11 is a top view of a semiconductor optical device according to a second modification of the third embodiment. [Figure 14] FIG. 13 is a top view of a semiconductor optical device according to a third modification of the third embodiment. [Figure 15] FIG. 11 is a top view of a semiconductor optical device according to a fourth modification of the third embodiment. [Figure 16] FIG. 10 is a top view of a semiconductor optical device according to a fourth embodiment. [Figure 17] 17 is a schematic cross-sectional view of the semiconductor optical device shown in FIG. 16 taken along line XVII-XVII. [Figure 18] FIG. 10 is a top view of a semiconductor optical device according to a fifth embodiment. [Figure 19] 19 is a schematic cross-sectional view of the semiconductor optical device shown in FIG. 18 taken along line XIX-XIX. [Figure 20] 19 is a schematic cross-sectional view of the semiconductor optical device shown in FIG. 18 taken along line XX-XX. [Figure 21] FIG. 13 is a top view of a semiconductor optical device according to a modification of the fifth embodiment. [Figure 22] 22 is a schematic cross-sectional view of the semiconductor optical device shown in FIG. 21 taken along line XXII-XXII. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Elements with the same reference numerals in all the drawings have the same or equivalent functions, and their repeated explanation will be omitted. Note that the size of the figures does not necessarily correspond to the magnification.

[0011] [First embodiment] Fig. 1 is a top view of a semiconductor optical device according to a first embodiment, Fig. 2 is a cross-sectional view schematically showing a cross section taken along line II-II in Fig. 1, and Fig. 3A is a cross-sectional view schematically showing a cross section taken along line III-III in Fig. 1.

[0012] The semiconductor optical device may be an edge-emitting electroabsorption modulator, a directly modulated laser, or an edge-incident optical receiver, all of which require broadband operation. Here, an electroabsorption modulator will be used as an example. The semiconductor optical device has a first facet 23 and a second facet 25. Light is incident on the first facet 23. The incident light is absorbed in response to a high-frequency electrical signal applied between the first electrode 15 and the second electrode 17, and a high-frequency optical signal is output from the second facet 25. Note that the incident and output sides may be reversed. The first facet 23 and the second facet 25 may be covered with an insulating film for protection and reflectance control.

[0013] The semiconductor optical device includes a first-conductivity-type semiconductor layer 3, an optical function layer 5, a second-conductivity-type semiconductor layer 9, and a second-conductivity-type contact layer 11 on a substrate 1. Here, the substrate 1 is an insulating (or semi-insulating) semiconductor substrate. The first-conductivity-type semiconductor layer 3 is an n-type semiconductor layer here and functions as a layer for contact with the cladding layer and the first electrode 15. The first-conductivity-type semiconductor layer 3 may be composed of multiple layers. For example, it may include a first-conductivity-type contact layer. In other words, the first-conductivity-type semiconductor layer 3 represents a first-conductivity-type semiconductor layer for transmitting an electrical signal applied to the first electrode 15 to the optical function layer 5, and may be formed of multiple layers or multiple materials. The optical function layer 5 includes at least a multiple quantum well. Here, the optical function layer 5 functions as an absorption layer that absorbs light in response to an applied voltage. The second-conductivity-type semiconductor layer 9 is a p-type semiconductor layer here and functions as a cladding layer. The second-conductivity-type semiconductor layer 9 may be composed of multiple layers. The second-conductivity-type contact layer 11 is a semiconductor layer connected to the second electrode 17. The conductivity of the second-conductivity-type contact layer 11 is higher than that of the second-conductivity-type semiconductor layer 9, and it is disposed to reduce the contact resistance between the second electrode 17 and the semiconductor layer. The second-conductivity-type contact layer 11 does not necessarily have to be disposed. In other words, the second-conductivity-type semiconductor layer 9 represents a second-conductivity-type semiconductor layer for transmitting an electrical signal applied to the second electrode 17 to the optical function layer 5, and may be formed of multiple layers or multiple materials. Furthermore, other layers may be included between the first-conductivity-type semiconductor layer 3 and the optical function layer 5 and / or between the second-conductivity-type semiconductor layer 9 and the optical function layer 5. For example, an optical confinement layer may be disposed. The substrate 1 is, for example, InP doped with Fe. The first-conductivity-type semiconductor layer 3 and the second-conductivity-type semiconductor layer 9 are, for example, InP. The optical function layer 5 is, for example, InGaAsP, and the second-conductivity-type contact layer 11 is, for example, InGaAs. These materials are merely examples. The semiconductor layers are formed so as to extend from the first facet 23 to the second facet 25, but this is not limiting. A window structure may be disposed on the second facet 25 side, which is the light output side. When a window structure is included, the mesa structure 21, which will be described later, does not extend to the second facet 25.

[0014] Note that another insulating semiconductor layer (e.g., a buffer layer) may be disposed between the substrate 1 and the first conductivity type semiconductor layer 3. Alternatively, a conductive substrate may be used as the substrate 1, and an insulating semiconductor layer may be disposed thereon, followed by the first conductivity type semiconductor layer 3. In other words, the first conductivity type semiconductor layer 3 does not refer to a layer formed in contact with the substrate 1, but rather refers to a first conductivity type semiconductor layer disposed above the insulating semiconductor layer. In this embodiment, the insulating semiconductor layer is the substrate 1.

[0015] As shown in FIG. 3A, the semiconductor optical device has a mesa structure 21. The mesa structure 21 includes a portion of the first-conductivity-type semiconductor layer 3, an optical functional layer 5, a second-conductivity-type semiconductor layer 9, and a second-conductivity-type contact layer 11. The mesa structure 21 extends in a first direction D1. Buried layers 13 are disposed on both side surfaces of the mesa structure 21 in a second direction D2, which is perpendicular to the first direction D1 in a plan view. The buried layer 13 is a semiconductor layer. Here, the buried layer 13 is a semi-insulating semiconductor layer. For example, the buried layer 13 is InP doped with Fe. The buried layer 13 may also have a stacked structure of a p-type semiconductor layer and an n-type semiconductor layer. The mesa structure 21 extends from a first facet 23 to a second facet 25. In FIG. 1, the interface between the top surface of the mesa structure 21 and the buried layer 13 is indicated by a dotted line. Here, the height from the substrate 1 to the upper surface of the burying layer 13 is higher than the height from the substrate 1 to the upper surface of the mesa structure 21. The uppermost surface of the burying layer 13 is approximately flat, but an inclined surface as shown in Fig. 3A is provided in the vicinity of the mesa structure 21. Note that the height from the substrate 1 to the upper surface of the burying layer 13 and the height from the substrate 1 to the upper surface of the mesa structure 21 may be approximately the same.

[0016] An insulating film 19 is disposed on the surface of the semiconductor optical device, with the exception of a portion thereof. The insulating film 19 is disposed on the upper surface of the burying layer 13. The insulating film 19 is not disposed on a portion of the upper surface of the mesa structure 21. Furthermore, the insulating film 19 is not disposed on a portion of the bottom surface of a recess 27, which will be described later.

[0017] Recess The semiconductor optical device has a recess 27. The recess 27 is a portion dug from the surface of the burying layer 13 to the first conductivity type semiconductor layer 3. The recess 27 shown in FIG. 1 does not reach the first end face 23 or the second end face 25, but this is not a limitation. An insulating film 19 is disposed on part of the bottom and side surfaces of the recess 27. At the bottom of the recess 27, the first conductivity type semiconductor layer 3 is exposed from the insulating film 19. The first conductivity type semiconductor layer 3 and the first electrode 15 are electrically and physically connected in this exposed region. The side surfaces of the recess 27 are illustrated as being perpendicular to the substrate 1, but this is not a limitation. For example, the side surfaces may be inclined so that the upper side of the recess 27 is wider than the bottom of the recess 27.

[0018] [1st electrode] The semiconductor optical device includes a first electrode 15. The first electrode 15 is located at the bottom of the recess 27 and includes a first connection electrode 15A connected to the first-conductivity-type semiconductor layer 3. If a first-conductivity-type contact layer is provided, the first connection electrode 15A is connected to the first-conductivity-type contact layer. In other words, the first connection electrode 15A indicates the region of the first electrode 15 that is physically connected to the first-conductivity-type semiconductor layer (the first-conductivity-type semiconductor layer 3 or the first-conductivity-type contact layer) that is electrically connected to the optical function layer 5. In other words, the first connection electrode 15A indicates the region of the first electrode 15 that is connected to the first-conductivity-type semiconductor layer to transmit an electrical signal to the optical function layer 5. The first electrode 15 includes a first pad electrode 15C disposed on the upper surface of the buried layer 13 and a first bridge electrode 15B that connects the first connection electrode 15A and the first pad electrode 15C. These three electrodes are integrally formed. In the first direction D1, the first pad electrode 15C is longer than the first bridge electrode 15B. The first pad electrode 15C is connected to a wire or wiring for connection to an external device, etc., and therefore requires a certain area. In other words, the first pad electrode 15C indicates the area of ​​the first electrode 15 that is electrically connected to the outside. Here, the first pad electrode 15C is rectangular, but is not limited to this and may be circular, elliptical, rectangular with rounded corners, or polygonal. The length in the first direction D1 is defined at its longest point. The first bridge electrode 15B is a factor in generating parasitic capacitance, so it is desirable that it be as small as possible. Therefore, it has the shortest shape in the first direction D1.

[0019] [Second electrode] The semiconductor optical device has a second electrode 17. In this embodiment, the first electrode 15 and the second electrode 17 are arranged on the left and right sides of the mesa structure 21 in the second direction D2. The second electrode 17 includes a second connection electrode 17A that connects to the second-conductivity-type contact layer 11 on the upper surface of the mesa structure 21. If the second-conductivity-type contact layer 11 is not arranged, the second connection electrode 17A connects to the second-conductivity-type semiconductor layer 9. In other words, the second connection electrode 17A indicates a region of the second electrode 17 that is physically connected to the second-conductivity-type semiconductor layer (the second-conductivity-type semiconductor layer 9 or the second-conductivity-type contact layer 11) that is electrically connected to the optical function layer 5. This is broadly referred to as the second connection electrode 17A (second electrode 17) being connected to the second-conductivity-type semiconductor layer 9. The second electrode 17 includes a second pad electrode 17C that is arranged on the upper surface of the buried layer 13. The second pad electrode 17C also includes a second bridge electrode 17B connecting the second connection electrode 17A and the second pad electrode 17C. These three electrodes are integrally formed. As shown in FIG. 2, the connection region between the second connection electrode 17A and the second conductivity-type contact layer 11 does not span the entire optical function layer 5 in the first direction D1, but this is not limited to this and may span the entire optical function layer 5. The second pad electrode 17C is longer than the second bridge electrode 17B in the first direction D1. The second pad electrode 17C is connected to a wire or wiring for connection to an external device, so a certain area is required. In other words, the second pad electrode 17C represents the region of the second electrode 17 that is electrically connected to the outside. Note that, although the second pad electrode 17C is rectangular here, this is not limited thereto and may be circular, elliptical, rectangular with rounded corners, or polygonal. Note that the length in the first direction D1 is defined as the longest point. Furthermore, the first pad electrode 15C and the second pad electrode 17C preferably have the same surface area, but this is not a limitation. The second bridge electrode 17B is preferably as small as possible because it can cause parasitic capacitance. Therefore, it has the narrowest shape in the first direction D1. The first electrode 15 and the second electrode 17 are both metal layers, and may be made of the same material and have different layer structures.

[0020] [High resistance region] The semiconductor optical device includes a first region 71, a second region 72, and a high-resistance region 90 that overlaps part or all of the second region 72 in a planar view. The high-resistance region 90 does not overlap the optical function layer 5 in a planar view. In other words, the high-resistance region 90 is disposed so as to avoid the optical function layer in a planar view. In a third direction D3, the upper surface of the high-resistance region 90 is disposed closer to the substrate 1 than the lower surface of the optical function layer 5. Here, the third direction D3 indicates the direction in which the semiconductor layers are stacked relative to the surface of the substrate 1 (i.e., the normal direction to the surface of the substrate 1). The upper surface of the high-resistance region 90 is located at the same position as the interface between the first-conductivity-type semiconductor layer 3 and the buried layer 13. Note that, as shown in FIG. 3B, the upper surface of the high-resistance region 90 may be located lower than the interface between the first-conductivity-type semiconductor layer 3 and the buried layer 13, as long as it is located below the lower surface of the optical function layer 5. As shown in FIG. 3C , the top surface of the high-resistance region 90 may be higher than the interface between the first-conductivity-type semiconductor layer 3 and the buried layer 13. The outer edge of the high-resistance region 90 in the second direction D2 is the interface between the first-conductivity-type semiconductor layer 3 and the high-resistance region 90. The interface of the high-resistance region 90 in the second direction D2 that is closer to the mesa structure 21 is referred to as the first interface B1, and the interface on the opposite side is referred to as the second interface B2. The first interface B1 overlaps with the second bridge electrode 17B in a plan view. The second interface B2 overlaps with the second pad electrode 17C in a plan view. The second interface B2 may also overlap with the second bridge electrode 17B. In the first direction D1, the high-resistance region 90 extends from the first end face 23 to the second end face 25. For illustrative purposes, FIG. 1 shows a perspective view of the high-resistance region 90. In reality, as shown in FIG. 3A , the high-resistance region 90 does not appear on the surface of the semiconductor optical device, but is located below the burying layer 13. The high-resistance region 90 is located so as to separate the first-conductivity-type semiconductor layer 3. The first region 71 is a region of the first-conductivity-type semiconductor layer 3 closer to the first pad electrode 15C than the first interface B1 and overlaps, in plan view, with the entire first pad electrode 15C electrically connected to the optical function layer 5. The second region 72 is a region of the first-conductivity-type semiconductor layer 3 closer to the second pad electrode 17C than the first interface B1 and overlaps, in plan view, with the entire second pad electrode 17C. The first connection electrode 15A is connected to the first-conductivity-type semiconductor layer 3 in the first region 71.Here, the width of the high resistance region 90 (the length in the second direction D2) is arbitrary as long as it can electrically separate the first region 71 from the second region 72 excluding the high resistance region 90. For example, the width of the high resistance region 90 is several tens of μm.

[0021] The high-resistance region 90 is formed by doping a portion of the first-conductivity-type semiconductor layer 3 (a region that will eventually become the high-resistance region 90) with second-conductivity-type or insulating impurities. For example, if the first-conductivity-type semiconductor layer 3 is n-type, the high-resistance region 90 is formed by doping Zn, a p-type dopant, by diffusion. At this time, in the second direction D2, the second region 72 (including the high-resistance region 90) and the first region 71 have an npn structure, which prevents the flow of both forward and reverse bias currents. In other words, the first region 71 and the second region 72 excluding the high-resistance region 90 are electrically isolated from each other. Furthermore, doping with insulating impurities can make a portion of the first-conductivity-type semiconductor layer 3 insulating / semi-insulating. Here, insulating / semi-insulating refers to a region having a resistivity sufficient to provide sufficient electrical insulation between the first region 71 and the second region 72 excluding the high-resistance region 90.

[0022] Alternatively, the high-resistance region 90 may be formed by regrowing a second-conductivity-type semiconductor layer or a semi-insulating semiconductor layer. While the manufacturing method is not limited, for example, after forming a first-conductivity-type semiconductor layer 3 on the substrate 1, the first-conductivity-type semiconductor layer 3 is removed from the region that will later become the high-resistance region 90. A second-conductivity-type or semi-insulating semiconductor layer may be regrown in the removed region. Note that the regrown semiconductor layer (i.e., the semiconductor layer that forms the high-resistance region 90) and the first-conductivity-type semiconductor layer 3 are preferably made of the same material, such as InP. Here, "same material" refers to the same basic composition (here, InP) excluding doped materials. In this formation method, the top surface of the high-resistance region 90 in the third direction D3 does not necessarily coincide with the top surface of the first-conductivity-type semiconductor layer 3. Therefore, as shown in FIGS. 3B and 3C, the top surface of the high-resistance region 90 may be higher or lower than the top surface of the first-conductivity-type semiconductor layer 3. The buried layer 13 is formed so as to be disposed on the high resistance region 90 after the high resistance region 90 is formed.

[0023] The lower surface of the high-resistance region 90 in the third direction D3 may be closer to the substrate 1 than the lower surface of the first-conductivity-type semiconductor layer 3. For example, when the high-resistance region 90 is formed by diffusing impurities, it is preferable to diffuse the impurities deep enough to reach the substrate 1 so that the first-conductivity-type semiconductor layer 3 can be reliably separated into the first region 71 and the second region 72 excluding the high-resistance region 90. Also, when forming the high-resistance region 90 by regrowth, it is preferable to over-etch the substrate 1 slightly so that no first-conductivity-type semiconductor layer 3 remains when removing the region of the first-conductivity-type semiconductor layer 3 that will become the high-resistance region 90 (the regrown region). As a result, the lower surface of the high-resistance region 90 is closer to the substrate 1 than the lower surface of the first-conductivity-type semiconductor layer 3. Also, the lower surface of the high-resistance region 90 does not necessarily have to be closer to the substrate 1 than the lower surface of the first-conductivity-type semiconductor layer 3; it may be in the same position.

[0024] [effect] The reason why the high-resistance region 90 reduces the parasitic capacitance of the electrodes will be explained using FIG. 4. In the first embodiment, the high-resistance region 90 can reduce the parasitic capacitance caused by a portion of the second pad electrode 17C and the second bridge electrode 17B. For simplicity, the explanation will be given using the second pad electrode 17C. An electrical signal is applied between the first electrode 15 and the second electrode 17. At this time, a voltage is applied between the second pad electrode 17C and the first conductivity type semiconductor layer 3. An insulating film 19 and a buried layer 13 are disposed below the second pad electrode 17C. Because these are insulating / semi-insulating layers, the space between the second pad electrode 17C and the first conductivity type semiconductor layer 3 can function as a capacitor. This capacitor hinders high-speed operation. Here, a high-resistance region 90 is disposed between the region of the first-conductivity-type semiconductor layer 3 below the second pad electrode 17C (the region of the second region 72 excluding the high-resistance region 90) and the region of the first-conductivity-type semiconductor layer 3 electrically connected to the first electrode 15 (the first region 71). Therefore, the region of the second region 72 excluding the high-resistance region 90 is effectively electrically isolated from the electrical path between the first electrode 15 and the second electrode 17 via the mesa structure 21. In other words, the high-resistance region 90 electrically isolates the region of the first-conductivity-type semiconductor layer 3 below the second pad electrode 17C (the region of the second region 72 excluding the high-resistance region 90) from the first-conductivity-type semiconductor layer 3 (the first region 71) below the second connection electrode 17A, which is electrically connected to the mesa structure 21. Therefore, the parasitic capacitance caused by the second pad electrode 17C does not affect actual operation. As a result, a semiconductor optical device capable of high-speed operation is realized. In the following, although the parasitic capacitance itself does not strictly disappear, it is referred to as being reduced because it does not affect actual operation. For example, when the first conductivity type is n-type and the high-resistance region 90 is a p-type semiconductor layer (second conductivity-type semiconductor layer) containing p-type impurities, the generation of parasitic capacitance is also suppressed in the second pad electrode 17C in the region overlapping with the high-resistance region 90 in plan view. More strictly speaking, in the case of reverse bias operation, the parasitic capacitance caused by the second electrode 17 overlapping the region from the first interface B1 toward the side surface of the semiconductor optical device (when facing the opposite side from the mesa structure 21) can be reduced.In the case of a forward bias, the parasitic capacitance caused by the second electrode 17 overlapping the first-conductivity-type semiconductor layer 3 located outside the second interface B2 of the semiconductor optical device can be reduced. When the high-resistance region 90 is an insulating / semi-insulating semiconductor layer, the parasitic capacitance (the parasitic capacitance caused by the second bridge electrode 17B overlapping the first-conductivity-type semiconductor layer 3) can be reduced regardless of the direction of the applied bias. The second bridge electrode 17B also contributes to the generation of parasitic capacitance, but as described above, the parasitic capacitance may or may not be reduced depending on the direction of the applied bias and whether the high-resistance region 90 is conductive or semi-insulating. Furthermore, in the first embodiment, the buried layer 13 is a region with a sufficiently high resistance compared to the second-conductivity-type semiconductor layer 9 and the like. Therefore, the electric field in the buried layer 13 hardly spreads, and the same parasitic capacitance reduction effect can be achieved as when the high-resistance region 90 is formed up to the surface of the buried layer 13.

[0025] Furthermore, in the first embodiment, the high-resistance region 90 does not damage the buried layer 13 (semiconductor layer) because the impurities are not diffused from above the buried layer 13. In other words, the buried layer 13 does not include the high-resistance region 90. Furthermore, the high-resistance region 90 is not disposed at the same height as the optical function layer 5 in the third direction D3. In the structure of Patent Document 1, the impurity diffusion region is disposed next to the active region corresponding to the optical function layer 5. The positional accuracy of the impurity diffusion is not very high. If the impurities diffuse into the optical function layer 5, the characteristics and reliability of the optical function layer 5 will be significantly degraded. To avoid this, the impurity diffusion region needs to be located away from the mesa structure. The further the diffusion region is from the mesa structure, the weaker the effect of reducing parasitic capacitance (because the area where the second electrode 17 overlaps with the first region 71 of the first conductivity-type semiconductor layer 3 in plan view increases). However, in the first embodiment, the high-resistance region 90 is not disposed side-by-side at the same height as the optical function layer 5. The upper surface of the high-resistance region 90 in the third direction D3 is positioned closer to the substrate 1 than the lower surface of the optical function layer 5. Therefore, the high-resistance region 90 is unlikely to affect the optical function layer 5, and the high-resistance region 90 can be positioned closer to the optical function layer 5 (mesa structure 21) in the second direction D2. Specifically, the first interface B1 between the high-resistance region 90 and the first region 71 of the first conductivity-type semiconductor layer 3 can be positioned close enough to overlap with the second bridge electrode 17B in a planar view. In this embodiment, the buried layer 13 has a sloped region in contact with the mesa structure 21 and a flat region outside of that. The high-resistance region 90 is positioned to avoid the sloped region in a planar view. However, the high-resistance region 90 may be positioned in a region overlapping the sloped region. For example, the distance between the first interface B1 and the mesa structure 21 in the second direction D2 is preferably 5 μm or more and 40 μm or less. More preferably, it is 15 μm or more and 25 μm or less. However, the dimensions are only an example.

[0026] [Variation 1] FIG. 5 is a top view of a semiconductor optical device according to Modification 1 of the first embodiment. The difference from the first embodiment is that the high-resistance region 90 is disposed from the first interface B1 to the side surface of the semiconductor optical device. That is, in Modification 1, the high-resistance region 90 covers the entire second region 72. Modification 1 also reduces the parasitic capacitance caused by the second pad electrode 17C. However, as described above, when the first conductivity type is n-type and the high-resistance region is a p-type semiconductor layer, the parasitic capacitance reduction effect cannot be obtained during forward bias driving. Naturally, the parasitic capacitance reduction effect can be obtained during reverse bias driving or when the high-resistance region 90 is a semi-insulating semiconductor layer. In Modification 5, the outer edge of the high-resistance region 90 separates the first region 71 from the second region 72 in a planar view.

[0027] [Variation 2] FIG. 6 is a top view of a semiconductor optical device according to Modification 2 of the first embodiment. The difference from the first embodiment is the shape of the high-resistance region 90. In this modification, the high-resistance region 90 is U-shaped in plan view, with the curved portion being linear. Here, the second region 72 is a region surrounded by the outer edge (first interface B1) of the high-resistance region 90 and the side surface of the semiconductor optical device. In Modification 2, the first region 71 and the second region 72 excluding the high-resistance region 90 are also electrically isolated by the outer edge (first interface B1) of the high-resistance region 90, thereby reducing parasitic capacitance caused by the second pad electrode 17C. The high-resistance region 90 may be arranged in an L-shape in plan view. For example, in FIG. 6, the high-resistance region 90 on the second end face 25 side of the high-resistance region 90 may extend to the second end face 25 as in the first embodiment, and instead, the region extending to the side surface of the semiconductor optical device may be eliminated, resulting in an L-shape.

[0028] [Second embodiment] Fig. 7 is a top view of a semiconductor optical device according to a second embodiment. Fig. 8 is a cross-sectional view schematically showing the VIII-VIII cross section of Fig. 7. The difference from the first embodiment is that two high-resistance regions are provided.

[0029] The semiconductor optical device includes a first high-resistance region 290. Here, the first high-resistance region 290 is the same as the high-resistance region 90 of the first embodiment. The semiconductor optical device also includes a second high-resistance region 292. The second high-resistance region 292 overlaps a portion of the first electrode 15 in plan view. More specifically, the second high-resistance region 292 is arranged to electrically isolate the first-conductivity-type semiconductor layer 3, similar to the first high-resistance region 290. A third interface B3 between the second high-resistance region 292 and the first-conductivity-type semiconductor layer 3 on the mesa structure side overlaps with the first bridge electrode 15B in plan view. A fourth interface B4 between the second high-resistance region 292 and the first-conductivity-type semiconductor layer 3, located on the opposite side to the third interface B3, overlaps with the first pad electrode 15C in plan view. The second high-resistance region 292 extends from the first end face 23 to the second end face 25. The other features are the same as those of the first high resistance region 290.

[0030] The first conductive type semiconductor layer 3 is electrically separated into three regions by the first high resistance region 290 and the second high resistance region 292. The third region 273 is located below the mesa structure 21 and serves as an electrical path when the optical function layer 5 is driven. The first region 271 is separated from the third region 273 by the second high resistance region 292. The second region 272 is separated from the third region 273 by the first high resistance region 290. The effect of the first high resistance region 290 is the same as that described in the first embodiment. The second high resistance region 292 can reduce parasitic capacitance caused by a portion of the first bridge electrode 15B and the first pad electrode 15C. The mechanism is the same as that for reducing the parasitic capacitance of the second electrode 17.

[0031] The second embodiment can reduce the parasitic capacitance caused by the first electrode 15 in addition to the second electrode 17, thereby realizing a semiconductor optical device with superior high-speed response. Note that it is also possible to dispose only the second high-resistance region 292 without disposing the first high-resistance region 290. Furthermore, the form of the high-resistance region 90 described in the modification of the first embodiment may be applied to the first high-resistance region 290 or the second high-resistance region 292.

[0032] [Third embodiment] Fig. 9 is a top view of a semiconductor optical device according to a third embodiment, Fig. 10 is a cross-sectional view schematically showing a cross section taken along line XX in Fig. 9, and Fig. 11 is a cross-sectional view schematically showing a cross section taken along line XI-XI in Fig. 9.

[0033] In the third embodiment, the recess 27 is arranged so that its longitudinal direction is along the first direction D1, and is positioned in a region in the second direction D2 where it overlaps with the second bridge electrode 17B and the second pad electrode 17C. In other words, the first electrode 15 and the second electrode 17 are arranged on the same side in the second direction D2 as viewed from the mesa structure 21. Furthermore, the mesa structure 21 is not arranged at the center of the semiconductor optical device in the second direction D2. In the third embodiment, the heights of the burying layer 13 and the mesa structure 21 from the substrate 1 are approximately the same. Note that, as in the first embodiment, the burying layer 13 may be higher than the mesa structure 21.

[0034] The high-resistance region 390 is arranged in an L-shape in plan view to surround the second pad electrode 17C. The high-resistance region 390 is arranged to overlap only the second bridge electrode 17B of the second electrode 17, but a portion of the high-resistance region 390 may overlap the second pad electrode 17C. As in the first embodiment, the first region 371 and the second region 372 are electrically separated by the outer edge of the high-resistance region 390. Here, the first region 371 is electrically connected to the mesa structure 21. This embodiment can reduce parasitic capacitance caused by the second electrode 17, particularly the second pad electrode 17C. The high-resistance region 390 has a narrower width in the second direction D2 in plan view than the high-resistance region 90 of the first embodiment.

[0035] [Variation 1] FIG. 12 is a top view of a semiconductor optical device according to Modification 1 of the third embodiment. This modification differs from the third embodiment in that it includes a second high-resistance region 392. The second high-resistance region 392 is arranged in an L-shape surrounding the first pad electrode 15C in a plan view. The second high-resistance region 392 electrically isolates the first conductive type semiconductor layer 3 from the first region 371, forming a third region 373. The second high-resistance region 392 may overlap the first pad electrode 15C in a plan view. In Modification 1, the first conductive type semiconductor layer 3 is divided into a first region 371, a second region 372, and a third region 373 by the outer edges of the high-resistance region 390 and the second high-resistance region 392. Modification 1 not only reduces the parasitic capacitance of the second electrode 17, but also reduces the parasitic capacitance of the first electrode 15.

[0036] [Variation 2] 13 is a top view of a semiconductor optical device according to Modification 2 of the third embodiment. The difference from Modification 1 of the third embodiment is that the high-resistance region 390 and the second high-resistance region 392 are integrally formed. In other words, the first conductivity-type semiconductor layer 3 is partitioned into a first region 371, a second region 372, and a third region 373 by the outer edge of one high-resistance region 390. At least a portion of the second electrode 17 overlaps the second region 372 in a planar view. At least a portion of the first electrode 15 overlaps the first region 371 in a planar view. Modification 2 provides the same effects as Modification 1.

[0037] [Variation 3] 14 is a top view of a semiconductor optical device according to Modification 3 of the third embodiment. The difference from the third embodiment is that the recess 327 and the second pad electrode 17C are arranged on either side of the mesa structure 21. As shown in Modification 3, the region where the first conductivity type semiconductor layer 3 and the first electrode 15 are connected may be on either side of the mesa structure 21 in the second direction D2.

[0038] [Variation 4] FIG. 15 is a top view of a semiconductor optical device according to Modification 4 of the third embodiment. This modification differs from Modification 3 of the third embodiment in that the high-resistance region 390 has a T-shape in plan view. The outer edges of the high-resistance region 390 divide the first-conductivity-type semiconductor layer 3 into a first region 371, a second region 372, and a third region 373. Modification 4 also reduces the parasitic capacitance caused by the first electrode 15 and the second electrode 17. As in Modification 1, the two high-resistance regions may be arranged separately. As described above, the shape of the high-resistance region can take various forms depending on the arrangement of the electrodes, etc. The high-resistance region may be arranged so as to electrically isolate the first-conductivity-type semiconductor layer 3. As described above, the edges forming the first, second, and third regions may be not only the interfaces between the high-resistance region and the first-conductivity-type semiconductor layer, but also the end faces or side faces of the semiconductor optical device.

[0039] [Fourth embodiment] Fig. 16 is a top view of a semiconductor optical device according to a fourth embodiment, and Fig. 17 is a cross-sectional view schematically showing the XVII-XVII cross section of Fig. 16.

[0040] The semiconductor optical device is a buried type semiconductor optical device known as a PBH type. The semiconductor optical device includes a first conductivity type semiconductor layer 403, an optical function layer 405, a second conductivity type semiconductor layer 409, and a second conductivity type contact layer 411 on a substrate 401. Here, the substrate 401 is an insulating (semi-insulating) semiconductor substrate. The first conductivity type semiconductor layer 403 is an n-type semiconductor layer and functions as a layer for contact with the cladding layer and the first electrode 415. Note that the first conductivity type semiconductor layer 403 may be composed of multiple layers. The optical function layer 405 includes at least a multiple quantum well. Here, the optical function layer 405 functions as an absorption layer that absorbs light in response to an applied voltage. The second conductivity type semiconductor layer 409 is a p-type semiconductor layer and functions as a cladding layer. Note that the second conductivity type semiconductor layer 409 may be composed of multiple layers. The second conductivity type contact layer 411 is a semiconductor layer connected to the second electrode 417. The conductivity of the second conductivity type contact layer 411 is higher than that of the second conductivity type semiconductor layer 409, and is disposed to reduce the contact resistance between the second electrode 417 and the semiconductor layer. Note that the second conductivity type contact layer 411 does not necessarily have to be disposed.

[0041] As shown in FIG. 17 , the semiconductor optical device has a mesa structure 421. The mesa structure 421 includes a portion of a first conductivity type semiconductor layer 403 and an optical function layer 405. The mesa structure 421 extends in a first direction D1. Buried layers 413 are disposed on both side surfaces of the mesa structure 421 in a second direction D2 that is perpendicular to the first direction D1 in a plan view. The buried layers 413 are semiconductor layers. The buried layer 413 has a multi-layer structure of p-type semiconductor layers and n-type semiconductor layers, and constitutes an electrical blocking layer (high-resistance layer). The mesa structure 421 is formed extending in the first direction D1 from the first end facet 23 to the second end facet 25. A second conductivity type semiconductor layer 409 and a second conductivity type contact layer 411 are disposed on the upper surfaces of the mesa structure 421 and the buried layer 413. The mesa structure 421 may include a second conductivity type semiconductor layer on the optical function layer 405 .

[0042] An insulating film 419 is disposed near the surface of the semiconductor optical device, except for a partial region. The insulating film 419 is disposed on the upper surface of the second conductivity type contact layer 411. The insulating film 419 is not disposed in a part above the mesa structure 421. Furthermore, the insulating film 419 is not disposed on a part of the bottom surface of a first recess 427, which will be described later.

[0043] Recess The semiconductor optical device has a first recess 427. The first recess 427 is a portion carved from the surface of the semiconductor multilayer to the first conductive type semiconductor layer 403. The first recess 427 does not reach the first end face 23 or the second end face 25, but this is not limitative. The first conductive type semiconductor layer 403 and the first electrode 415 are electrically and physically connected at the bottom of the first recess 427. The semiconductor optical device has a second recess 429. The second recess 429 is a groove extending from the surface of the semiconductor multilayer to the buried layer 413. The second recess 429 reaches the first end face 23 and the second end face 25. The second recess 429 has a depth sufficient to separate at least the second conductive type semiconductor layer 409. An insulating film 419 is disposed on a portion of the bottom of the second recess 429.

[0044] [electrode] The semiconductor optical device has a first electrode 415. The first electrode 415 includes three portions, as in the first embodiment. The semiconductor optical device has a second electrode 417. The second electrode 417 includes three portions, as in the first embodiment. A second bridge electrode 417B is disposed along the side and bottom surfaces of the second recess 429.

[0045] [High resistance region] The semiconductor optical device has a high-resistance region 490. In the third direction D3, the upper surface of the high-resistance region 490 is disposed closer to the substrate 401 than the lower surface of the optical function layer 405. The lower surface of the high-resistance region 490 is substantially flush with the lower surface of the first-conductivity-type semiconductor layer 403. However, as in the first embodiment, the lower surface of the high-resistance region 490 may be disposed closer to the substrate 1 than the lower surface of the first-conductivity-type semiconductor layer 403. The high-resistance region 490 overlaps with the second bridge electrode 417B in a planar view. The high-resistance region 490 overlaps with the second recess 429 in a planar view. The high-resistance region 490 may be wider than the second recess 429 in the second direction D2.

[0046] The fourth embodiment also provides the effects described above. It may also be combined with the modifications described in the other embodiments. Thus, the effects of the present invention can be obtained even in a PBH type in which a second conductivity type semiconductor layer is widely disposed on the top surface of the mesa structure.

[0047] [Fifth embodiment] Fig. 18 is a top view of a semiconductor optical device according to a fifth embodiment, Fig. 19 is a cross-sectional view schematically showing a cross section taken along line XXI-XXI in Fig. 18, and Fig. 20 is a cross-sectional view schematically showing a cross section taken along line XX-XX in Fig. 18.

[0048] The semiconductor optical device has a modulator section 530, a waveguide section 540, and a semiconductor laser section 580 integrated on a substrate 501. The semiconductor laser section 580 outputs continuous light. The waveguide section 540 transmits the output light of the semiconductor laser section 580 to the modulator section 530. The first end face 523 is also the end face on the semiconductor laser section 580 side, and is formed with a high-reflection film (not shown). A low-reflection film may be formed on the first end face 523. A low-reflection film (not shown) is formed on the second end face 525. The modulator section 530 and the waveguide section 540, and the waveguide section 540 and the semiconductor laser section 580 are optically connected by butt joint connections. Here, the modulator section 530 has the same structure as the semiconductor optical device of the first embodiment.

[0049] [Semiconductor laser part] The semiconductor laser section 580 includes a first conductivity type semiconductor layer 503, an active layer 581, a second conductivity type semiconductor layer 509, and a second conductivity type contact layer 511 on a substrate 501. The first conductivity type semiconductor layer 503 and the second conductivity type semiconductor layer 509 of the semiconductor laser section 580 are configured from the same layers as the first conductivity type semiconductor layer 503 and the second conductivity type semiconductor layer 509 of the modulator section 530, but may be formed separately. The active layer 581 includes at least a multiple quantum well. The active layer 581 generates continuous light when a current is injected into it. Other layers may be included between the first conductivity type semiconductor layer 503 and the active layer 581 and / or between the second conductivity type semiconductor layer 509 and the active layer 581. For example, an optical confinement layer may be disposed. A diffraction grating layer may also be included. Here, the semiconductor laser section 580 is a DFB laser that outputs light in the 1.3 μm band. The oscillation wavelength may be in the 1.55 μm band or in another wavelength band. Furthermore, the semiconductor laser section 580 is not limited to a DFB laser, but may be a DBR laser. The interface between a waveguide layer 507 of the waveguide section 540 (described later) and an active layer 581 of the semiconductor laser section 580 is butt-jointed.

[0050] [Waveguide section] The waveguide section 540 includes a first conductivity type semiconductor layer 503, a waveguide layer 507, and a second conductivity type semiconductor layer 509 disposed on the substrate 501. The first conductivity type semiconductor layer 503 and the second conductivity type semiconductor layer 509 of the waveguide section 540 are configured from the same layers as the first conductivity type semiconductor layer 503 and the second conductivity type semiconductor layer 509 of the modulator section 530, but may be formed separately. The waveguide layer 507 is a bulk semiconductor layer. Other layers may be included between the first conductivity type semiconductor layer 503 and the waveguide layer 507 and / or between the second conductivity type semiconductor layer 509 and the waveguide layer 507. For example, an optical confinement layer may be disposed. The interface between the waveguide layer 507 of the waveguide section 540 and the optical function layer 505 of the modulator section 530 is butt-jointed.

[0051] The mesa structure 521 extends from the first end face 523 to the second end face 525. A burying layer 513 is disposed on the side surface of the mesa structure 521 in the second direction D2. In other words, the semiconductor laser portion 580 and the waveguide portion 540 have the mesa structure 521.

[0052] The semiconductor laser section 580 has a laser recess 589. The laser recess 589 is a portion carved from the surface of the burying layer 513 to the first-conductivity-type semiconductor layer 503. The laser recess 589 does not reach the waveguide section 540. Furthermore, the laser recess 589 does not reach the first end facet 523. The semiconductor laser section 580 has a first laser electrode 585 and a second laser electrode 587. The first laser electrode 585 is electrically and physically connected to the first-conductivity-type semiconductor layer 503 at the bottom surface of the laser recess 589. The second laser electrode 587 is disposed from the top of the mesa structure 521 to the top of the burying layer 513. The second laser electrode 587 is electrically and physically connected to the second-conductivity-type contact layer 511 at the top of the mesa structure 521. Note that the first laser electrode 585 and the second laser electrode 587 are rectangular in plan view, but are not limited to this.

[0053] Semiconductor optical devices in which a modulator and a semiconductor laser are integrated on a single substrate are well known. When the semiconductor optical device is driven, a high-frequency electrical signal is applied to the modulator. Meanwhile, a direct current (DC voltage) is injected into the semiconductor laser. At this time, if the electrical signal applied to the modulator is transmitted to the semiconductor laser and the laser light is modulated, this is undesirable in terms of optical characteristics. In the fifth embodiment, a waveguide section 540 is disposed between the modulator section 530 and the semiconductor laser section 580. The waveguide section 540 can increase the distance between the modulator section 530 and the semiconductor laser section 580, thereby reducing electrical crosstalk. Furthermore, to increase the electrical resistance between the two, the second conductivity-type contact layer 511 is not disposed in the waveguide section 540.

[0054] The semiconductor optical device has a high-resistance region 590. In the first embodiment, the high-resistance region 590 extends from the first end face 23 to the second end face 25, electrically isolating the first region 71 and the second region 72. However, in the fifth embodiment, the high-resistance region 590 extends to the second end face 525 but does not extend to the first end face 523. Instead, the high-resistance region 590 is disposed in the waveguide section 540 region so as to cross between two side surfaces of the semiconductor optical device in the second direction D2 (i.e., from one end to the other end in the second direction D2). That is, as shown in FIG. 18 , the high-resistance region 590 is T-shaped in plan view. With this configuration, the first conductivity-type semiconductor layer 503 is partitioned into two regions in the modulator section 530 region: a first region 571 below the mesa structure 521 and a second region 572 below the second pad electrode 517C.

[0055] Furthermore, the high-resistance region 590 disposed in the waveguide section 540 also has the effect of improving electrical insulation between the modulator section 530 and the semiconductor laser section 580. As shown in FIG. 19 , the first-conductivity-type semiconductor layer 503 is disposed from the modulator section 530 to the semiconductor laser section 580. Electrical crosstalk may occur through the first-conductivity-type semiconductor layer 503. In the fifth embodiment, the high-resistance region 590 electrically separates the first-conductivity-type semiconductor layer 503 of the modulator section 530 from the first-conductivity-type semiconductor layer 503 of the semiconductor laser section 580. As shown in FIG. 20 , in the mesa structure 521, the high-resistance region 590 extends to the lower surface of the waveguide layer 507. For ease of explanation, a detailed semiconductor multilayer structure is not shown here. However, if a semi-insulating semiconductor layer (e.g., an optical confinement layer) is disposed below the waveguide layer 507, the high-resistance region 590 would be disposed to extend to the lower surface of the semi-insulating semiconductor layer. That is, in the region within the mesa structure 521 and closer to the substrate 501 than the waveguide layer 507, the high-resistance region 590 is arranged so that semiconductor layers of the same conductivity type are not continuously arranged between the modulator section 530 and the semiconductor laser section 580. Note that, as shown in FIG. 20 , the thickness of the high-resistance region 590 in the third direction D3 is thick only in the region of the mesa structure 521. In other words, the thickness of the high-resistance region 590 arranged below the buried layer 513, including the high-resistance region 590 arranged in the modulator section 530, is thinner than the high-resistance region 590 arranged in the mesa structure 521. However, without being limited thereto, the thickness of the high-resistance region 590 arranged below the mesa structure 521 may be the same throughout the entire region.

[0056] The high resistance regions described in the above embodiments and modifications may be combined with this embodiment.

[0057] [Variations] Fig. 21 is a top view of a semiconductor optical device according to a modification of the fifth embodiment. Fig. 22 is a cross-sectional view schematically showing the cross section XXII-XXII of Fig. 22. The difference from the fifth embodiment is that an upper high-resistance region 594 is provided.

[0058] The upper high-resistance region 594 is disposed in the waveguide portion 540 in a plan view. The upper high-resistance region 594 is disposed so as to cross between two side surfaces of the semiconductor optical device. As shown in FIG. 22 , the upper high-resistance region 594 is disposed in the second-conductivity-type semiconductor layer 509. The upper surface of the upper high-resistance region 594 substantially coincides with the upper surface of the semiconductor multilayer. In this case, the upper surface of the upper high-resistance region 594 coincides with the upper surface of the second-conductivity-type semiconductor layer 509. If the second-conductivity-type contact layer 511 is disposed in the waveguide portion 540, the upper surface of the upper high-resistance region 594 coincides with the upper surface of the second-conductivity-type contact layer 511. The upper high-resistance region 594 is formed by implanting impurity ions, such as protons, into the second-conductivity-type semiconductor layer 509 from the surface of the semiconductor multilayer. The positional accuracy of the proton implantation is lower than that of semiconductor multilayer growth. If the protons reach the waveguide layer 507, this is undesirable in terms of optical properties. Therefore, the lower surface of the upper high resistance region 594 does not reach the waveguide layer 507. However, ideally, it is desirable that the lower surface of the upper high resistance region 594 coincide with the upper surface of the waveguide layer 507.

[0059] The upper high-resistance region 594 can limit the path of current passing through the second conductivity type semiconductor layer 509. As a result, it is possible to further reduce parasitic capacitance and electrical crosstalk between the modulator section 530 and the semiconductor laser section 580.

[0060] In the above examples, the first conductivity type is described as n-type and the second conductivity type is described as p-type, but this is not limited thereto. The first conductivity type may be p-type and the second conductivity type may be n-type. Furthermore, the optical function layer is described as an absorption layer, but it may be an active layer that generates light in response to an applied voltage signal. Furthermore, in the above description, the high resistance region is shown in a shape formed by a combination of straight lines, but this is not limited thereto and may be a shape that includes curves in a plan view.

[0061] The present invention relates to a semiconductor optical device including a first-conductivity-type semiconductor layer, an optical function layer, and a second-conductivity-type semiconductor layer stacked on an insulating semiconductor layer, and including a first electrode connected to the first-conductivity-type semiconductor layer and a second electrode connected to the second-conductivity-type semiconductor layer. This reduces the parasitic capacitance of the electrodes located on the first-conductivity-type semiconductor layer, improving high-frequency characteristics. An embodiment of the present invention achieves this by including the first electrode connected to the first-conductivity-type semiconductor layer and the second electrode connected to the second-conductivity-type semiconductor layer, and by defining the first region and the second region in a planar view by the outer edge of a high-resistance region. The second region, excluding the high-resistance region, is electrically isolated from the first region, thereby reducing parasitic capacitance caused by the electrodes overlapping with the second region. In other words, the effect of parasitic capacitance caused by the electrodes overlapping with the second region during actual operation can be reduced. The upper surface of the high-resistance region is located closer to the substrate (the insulating semiconductor layer) than the lower surface of the optical function layer in the stacking direction of the semiconductor layers. The high-resistance region is formed by diffusing second-conductivity or insulating impurities into the first-conductivity semiconductor layer. Alternatively, the high-resistance region is formed by removing a portion of the first-conductivity semiconductor layer and placing a second-conductivity or insulating semiconductor layer in the removed region. The optical function layer has a mesa structure, with a buried layer disposed on the side of the mesa structure and the high-resistance region disposed below the buried layer. The high-resistance region may extend from the incident end face to the emitting end face of the semiconductor optical device in a planar view. The high-resistance region may be U-shaped, L-shaped, or T-shaped in a planar view. The interface between the high-resistance region and the first region may overlap with a bridge electrode included in the first electrode and / or the second electrode in a planar view. Furthermore, the outer edge of the high-resistance region may partition the first-conductivity semiconductor layer into a first region electrically connected to the optical function layer, a second region electrically connected to the optical function layer, and a third region not electrically connected to the optical function layer. By overlapping at least a portion of the first electrode with the first region in a planar view, parasitic capacitance caused by the first electrode can be reduced. The second region may be configured as a region surrounded by the high-resistance region and the end face and / or side face of the semiconductor optical element in a plan view. The semiconductor optical element may include a modulator section including an optical function layer, a semiconductor laser section, and a waveguide section connecting the two sections. The high-resistance region is disposed in the modulator section.In addition, the high resistance region may be arranged in the waveguide portion so as to cross the side surface of the semiconductor optical element in a planar view, and the high resistance region of the waveguide portion and the high resistance region of the modulator portion may form a second region of the first conductivity type semiconductor layer that is not electrically connected to the optical function layer.

[0062] [Note] (1) A semiconductor optical device according to one aspect of the present disclosure includes: an insulating semiconductor layer; a first conductivity type semiconductor layer disposed on the insulating semiconductor layer; an optical function layer disposed on the first conductivity type semiconductor layer and forming a mesa structure; a second conductivity type semiconductor layer disposed on the optical function layer; a first electrode having a first pad electrode for inputting an electrical signal and connected to the first conductivity type semiconductor layer; a second electrode having a second pad electrode for inputting an electrical signal and connected to the second conductivity type semiconductor layer; the first conductivity type semiconductor layer includes a first region, a second region, and a high resistance region that overlaps a part or all of the second region in a plan view; the first region overlaps with the entire area of ​​the first pad electrode in a plan view, the second region overlaps with the entire area of ​​the second pad electrode in a plan view, the high resistance region is disposed so as to avoid the optical function layer in a plan view, The outer edge of the high resistance region separates the first region and the second region in a plan view. (2) A semiconductor optical device according to another aspect of the present disclosure, The upper surface of the high resistance region is located closer to the insulating semiconductor layer than the lower surface of the optical function layer. (3) A semiconductor optical device according to another aspect of the present disclosure, a buried layer disposed on a side surface of the mesa structure in a direction perpendicular to the direction in which the mesa structure extends in a plan view; The high resistance region is disposed below the buried layer. (4) A semiconductor optical device according to another aspect of the present disclosure, the first electrode further includes a first connection electrode connected to the first conductivity type semiconductor layer, and a first bridge electrode connecting between the first connection electrode and the first pad electrode; the first bridge electrode is shorter than the first pad electrode in the direction in which the mesa structure extends; The outer edge of the high resistance region on the mesa structure side overlaps with the first bridge electrode in a plan view. (5) A semiconductor optical device according to another aspect of the present disclosure, the second electrode further includes a second connection electrode connected to the second conductive type semiconductor layer, and a second bridge electrode connecting between the second connection electrode and the second pad electrode; the second bridge electrode is shorter than the second pad electrode in the direction in which the mesa structure extends; The outer edge of the high resistance region on the mesa structure side overlaps the second bridge electrode in a plan view. (6) A semiconductor optical device according to another aspect of the present disclosure, further comprising an input end face and an output end face; The high resistance region extends from the input end face to the output end face. (7) A semiconductor optical device according to another aspect of the present disclosure, The second region is entirely the high resistance region. (8) A semiconductor optical device according to another aspect of the present disclosure, The high resistance region is L-shaped or U-shaped in plan view. (9) A semiconductor optical device according to another aspect of the present disclosure, the first conductivity type semiconductor layer further includes a third region electrically connected to the optical function layer and a second high resistance region overlapping a part or all of the first region in a planar view; the second high resistance region is disposed so as to avoid the optical function layer in a plan view, an upper surface of the second high resistance region is disposed closer to the insulating semiconductor layer than a lower surface of the optical function layer; The outer edge of the second high resistance region separates the third region and the first region in a plan view. (10) A semiconductor optical device according to another aspect of the present disclosure, The upper surface of the high resistance region is at the same level as or higher than the interface between the first conductivity type semiconductor layer and the buried layer when viewed from the semiconductor layer. (11) A semiconductor optical device according to another aspect of the present disclosure, a first end surface through which light is input to the optical function layer; a second end surface through which output light is output from the optical function layer; Equipped with the first conductive type semiconductor layer is electrically connected to the optical function layer in the first region; The second region is surrounded in part or in whole by the outer edge of the high resistance region, the first end face, the second end face, and a side face where the first end face and the second end face intersect. (12) A semiconductor optical device according to another aspect of the present disclosure, The buried layer is the insulating semiconductor layer. (13) A semiconductor optical device according to another aspect of the present disclosure, a modulator portion including the optical function layer; a semiconductor laser portion; a waveguide section connecting the modulator section and the semiconductor laser section, the high resistance region includes a first portion that is disposed in the modulator portion and extends parallel to the mesa structure, and a second portion that is disposed in the waveguide portion and extends in a direction perpendicular to the mesa structure in a plan view and is connected to the first portion; The first region and the second region are partitioned in a plan view by an outer edge of the first portion and an outer edge of the second portion. (14) A semiconductor optical device according to another aspect of the present disclosure, the mesa structure is disposed across the modulator section and the semiconductor laser section, The height of the high resistance region of the modulator section is lower than the height of the high resistance region disposed in the mesa structure of the waveguide section when viewed from the insulating semiconductor layer. (15) A semiconductor optical device according to another aspect of the present disclosure, the waveguide portion includes a waveguide layer between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, the second conductivity type semiconductor layer is disposed across the modulator section and the semiconductor laser section, The second conductivity type semiconductor layer of the waveguide portion includes an upper high resistance region whose lower surface is located above the upper surface of the waveguide layer. (16) A semiconductor optical device according to another aspect of the present disclosure, the mesa structure includes the second conductivity type semiconductor layer, The buried layer is also disposed on the side surface of the second conductive type semiconductor layer within the mesa structure. (17) A semiconductor optical device according to another aspect of the present disclosure, the second conductive type semiconductor layer is disposed on the mesa structure; The buried layer is disposed on a side of the mesa structure and between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. (18) A semiconductor optical device according to another aspect of the present disclosure, a recess extending from an upper surface of the buried layer to the first conductivity type semiconductor layer; The first connection electrode is connected to the first conductivity type semiconductor layer at the bottom surface of the recess. [Explanation of symbols]

[0063] 1, 401, 501 board 3, 403, 503 First conductive type semiconductor layer 5, 405, 505 Optical functional layer 9, 409, 509 Second conductivity type semiconductor layer 11, 411, 511 Second conductivity type contact layer 13, 413, 513 embedding layer 15, 415, 515 1st electrode 15A, 415A First connecting electrode 15B, 415B First bridge electrode 15C, 415C 1st pad electrode 17, 417, 517 2nd electrode 17A, 417A Second connecting electrode 17B, ​​417B Second bridge electrode 17C, 417C, 517C Second pad electrode 19, 419, 519 insulating film 21, 421, 521 Mesa structure 23, 523 1st end face 25, 525 2nd end face 27, 327, 427 recesses 71, 271, 371, 471, 571 1st area 72, 272, 372, 472, 572 2nd area 90, 390, 490, 590 high resistance region 273, 373 Third area 290, 390 1st high resistance region 292, 392 2nd high resistance region 429 Second Recess 507 Waveguide layer 530 Modulator section 540 Waveguide section 580 Semiconductor laser section 581 Active layer 585 First laser electrode 587 Second laser electrode 589 Laser recess 594 Upper high resistance region D1 1st direction D2 2nd direction D3 Third direction B1 1st interface B2 2nd interface B3 3rd interface B4 4th interface

Claims

1. an insulating semiconductor layer; a first conductivity type semiconductor layer disposed on the insulating semiconductor layer; an optical function layer disposed on the first conductivity type semiconductor layer and forming a mesa structure; a second conductivity type semiconductor layer disposed on the optical function layer; a first electrode having a first pad electrode for inputting an electrical signal and connected to the first conductivity type semiconductor layer; a second electrode having a second pad electrode for inputting an electrical signal and connected to the second conductivity type semiconductor layer; the first conductivity type semiconductor layer includes a first region, a second region, and a high resistance region that overlaps a part or all of the second region in a plan view; the first region overlaps with the entire area of ​​the first pad electrode in a plan view, the second region overlaps with the entire area of ​​the second pad electrode in a plan view, the high resistance region is disposed so as to avoid the optical function layer in a plan view, an outer edge of the high-resistance region separates the first region and the second region in a plan view;

2. 2. The semiconductor optical device according to claim 1, an upper surface of the high resistance region is located closer to the insulating semiconductor layer than a lower surface of the optical function layer;

3. 2. The semiconductor optical device according to claim 1, a buried layer disposed on a side surface of the mesa structure in a direction perpendicular to the direction in which the mesa structure extends in a plan view; The semiconductor optical device, wherein the high resistance region is disposed below the buried layer.

4. 2. The semiconductor optical device according to claim 1, the first electrode further includes a first connection electrode connected to the first conductivity type semiconductor layer, and a first bridge electrode connecting the first connection electrode and the first pad electrode; the first bridge electrode is shorter than the first pad electrode in the direction in which the mesa structure extends; an outer edge of the high-resistance region on the mesa structure side overlaps with the first bridge electrode in a plan view;

5. 2. The semiconductor optical device according to claim 1, the second electrode further includes a second connection electrode connected to the second conductive type semiconductor layer, and a second bridge electrode connecting the second connection electrode and the second pad electrode; the second bridge electrode is shorter than the second pad electrode in the direction in which the mesa structure extends; an outer edge of the high-resistance region on the mesa structure side overlaps with the second bridge electrode in a plan view;

6. 2. The semiconductor optical device according to claim 1, further comprising an input end face and an output end face; The high resistance region extends from the input end face to the output end face.

7. 2. The semiconductor optical device according to claim 1, the second region is entirely the high resistance region.

8. 2. The semiconductor optical device according to claim 1, The semiconductor optical element, wherein the high resistance region is L-shaped or U-shaped in plan view.

9. 2. The semiconductor optical device according to claim 1, the first conductivity type semiconductor layer further includes a third region electrically connected to the optical function layer and a second high resistance region overlapping a part or all of the first region in a planar view, the second high resistance region is disposed so as to avoid the optical function layer in a plan view, an upper surface of the second high resistance region is disposed closer to the insulating semiconductor layer than a lower surface of the optical function layer; an outer edge of the second high-resistance region separates the third region from the first region in a plan view.

10. 2. The semiconductor optical device according to claim 1, A semiconductor optical element, wherein the top surface of the high resistance region is at the same level as or higher than the interface between the first conductivity type semiconductor layer and the buried layer when viewed from the semiconductor layer.

11. 2. The semiconductor optical device according to claim 1, a first end surface through which light is input to the optical function layer; a second end surface through which output light is output from the optical function layer; Equipped with the first conductive type semiconductor layer is electrically connected to the optical function layer in the first region; the second region is surrounded in whole or in part by an outer edge of the high-resistance region, the first end face, the second end face, and a side face where the first end face and the second end face intersect.

12. 2. The semiconductor optical device according to claim 1, The semiconductor optical device, wherein the buried layer is the insulating semiconductor layer.

13. 2. The semiconductor optical device according to claim 1, a modulator portion including the optical function layer; a semiconductor laser portion; a waveguide section connecting the modulator section and the semiconductor laser section, the high resistance region includes a first portion that is disposed in the modulator portion and extends parallel to the mesa structure, and a second portion that is disposed in the waveguide portion and extends in a direction perpendicular to the mesa structure in a plan view and is connected to the first portion, The semiconductor optical element, wherein the first region and the second region are partitioned in a planar view by an outer edge of the first portion and an outer edge of the second portion.

14. 14. The semiconductor optical device according to claim 13, the mesa structure is disposed across the modulator section and the semiconductor laser section, a height of the high resistance region of the modulator section, as viewed from an insulating semiconductor layer, lower than a height of the high resistance region disposed in the mesa structure of the waveguide section;

15. 14. The semiconductor optical device according to claim 13, the waveguide portion includes a waveguide layer between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, the second conductivity type semiconductor layer is disposed across the modulator section and the semiconductor laser section, The second conductivity type semiconductor layer of the waveguide portion includes an upper high resistance region whose lower surface is located above the upper surface of the waveguide layer.

16. 4. The semiconductor optical device according to claim 3, the mesa structure includes the second conductivity type semiconductor layer, The semiconductor optical device, wherein the buried layer is also disposed on a side surface of the second conductive type semiconductor layer within the mesa structure.

17. 2. The semiconductor optical device according to claim 1, the second conductive type semiconductor layer is disposed on the mesa structure; The buried layer is disposed on a side of the mesa structure and between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer.

18. 2. The semiconductor optical device according to claim 1, a recess extending from an upper surface of the buried layer to the first conductivity type semiconductor layer; The first connection electrode is connected to the first conductivity type semiconductor layer at the bottom surface of the recess.

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