Printed circuit board and manufacturing method thereof

Abstract

To provide a printed circuit board including metal posts with substantially no plating deviation and guaranteed flatness, and a manufacturing method thereof.SOLUTION: The present invention relates to a printed circuit board and a manufacturing method thereof, which includes a metal post 150 and an insulating layer 141 covering a portion of the metal post, and in which, on the basis of an imaginary line L1 that is substantially at the same level as the uppermost upper surface of the insulating layer, the metal post includes a first conductor portion 151 arranged below the imaginary line, a second conductor portion 152 arranged above the imaginary line, and a third conductor portion 156 that protrudes at least partially from a side surface of the first conductor portion below the imaginary line.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a printed circuit board and a method for manufacturing the same. [Background technology]

[0002] Recently, the use of copper posts has been increasing in order to reduce pitch rather than simply using solder balls when mounting electronic components on package substrates or connecting main boards and package modules. The most common method for forming copper posts is to fabricate the required number of package substrate layers and then form the copper posts through a plating process using a seed layer on the outermost layer. However, forming a seed layer on the surface of the solder resist can result in insufficient adhesion, so an additional process can be added to create physical roughness. However, this can damage the insulating material surface and pose potential mold-related quality risks in the semiconductor assembly process. Furthermore, selective plating of only the copper posts can result in a narrow plating area and significant thickness variation between copper posts at the panel level. To address this issue, copper plating thicker than the target thickness and then grinding can be considered, but this can result in polishing deviations within the panel and increased costs due to the additional process. Summary of the Invention [Problem to be solved by the invention]

[0003] One of several objects of the present invention is to provide a printed circuit board including metal posts with substantially no plating deviation and with guaranteed flatness, and a method for manufacturing the same.

[0004] Another of several objects of the present invention is to provide a printed circuit board including highly reliable metal posts and a method for manufacturing the same.

[0005] Still another of several objects of the present invention is to provide a printed circuit board and a method for manufacturing the same that can reduce costs and simplify processes. [Means for solving the problem]

[0006] One of several solutions proposed through the present invention is to process a via portion in an insulating layer with a protective layer attached, form a gap between the protective layer and the insulating layer from the side of the via portion and penetrating part of the protective layer and / or the insulating layer, perform a plating process to fill the via portion and the gap before peeling off the protective layer, and then peel off the protective layer, thereby forming one or more metal posts with a structure that is substantially free of plating deviation and has excellent flatness and reliability through a relatively simple process.

[0007] For example, one example of a printed circuit board may include a metal post and an insulating layer covering a portion of the metal post, and based on an imaginary line substantially at the same level as the uppermost surface of the insulating layer, the metal post may include a first conductor portion arranged below the imaginary line, a second conductor portion arranged above the imaginary line, and a third conductor portion below the imaginary line and at least a portion of which protrudes from a side surface of the first conductor portion.

[0008] For example, a method for manufacturing a printed circuit board according to one example may include the steps of: preparing a substrate including an insulating layer and a protective layer disposed on the insulating layer; forming a via portion that penetrates the protective layer in a thickness direction from an upper surface of the protective layer and further penetrates at least a portion of the insulating layer; forming a gap portion at a boundary between the insulating layer and the protective layer from a side portion of the via portion in a direction substantially perpendicular to the thickness direction and that penetrates a portion of each of the insulating layer and the protective layer; forming a seed layer that is disposed on a bottom surface of the via portion, a wall surface of the via portion, and an upper surface of the protective layer and fills at least a portion of the gap portion; forming a metal layer that is disposed on the seed layer and fills at least a portion of the via portion; removing a portion of each of the seed layer and the metal layer to expose at least a portion of an upper surface of the protective layer; and removing the protective layer. [Effects of the Invention]

[0009] Among the various advantages of the present invention, one advantage is that it can provide a printed circuit board including metal posts with substantially no plating deviation and with assured flatness, and a method for manufacturing the same.

[0010] Another of the various effects of the present invention is that it can provide a highly reliable printed circuit board including metal posts and a method for manufacturing the same.

[0011] Among the various effects of the present invention, yet another effect is that it is possible to provide a printed circuit board and a method for manufacturing the same that can reduce costs and simplify processes. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a block diagram illustrating an example of an electronic device system. [Figure 2] FIG. 1 is a perspective view schematically illustrating an example of an electronic device. [Figure 3] FIG. 1 is a cross-sectional view schematically illustrating an example of a printed circuit board. [Figure 4] FIG. 4 is a plan view showing a schematic top view of the printed circuit board of FIG. 3. [Figure 5] 4 is a process diagram schematically showing an example of manufacturing the metal post of FIG. 3. FIG. [Figure 6] FIG. 10 is a cross-sectional view schematically illustrating another example of a printed circuit board. [Figure 7] FIG. 7 is a plan view showing a schematic top view of the printed circuit board of FIG. 6. [Figure 8] 7A to 7C are process diagrams schematically illustrating an example of manufacturing the metal post of FIG. 6. [Figure 9] FIG. 10 is a cross-sectional view schematically illustrating yet another example of a printed circuit board. [Figure 10] FIG. 10 is a plan view showing a schematic top view of the printed circuit board of FIG. 9. [Figure 11]10 is a process diagram schematically showing an example of manufacturing the metal post of FIG. 9. FIG. [Figure 12] FIG. 10 is a cross-sectional view schematically illustrating yet another example of a printed circuit board. [Figure 13] FIG. 13 is a plan view showing a schematic top view of the printed circuit board of FIG. 12. [Figure 14] 13 is a process diagram schematically showing an example of manufacturing the metal post of FIG. 12. FIG. [Figure 15] FIG. 10 is a cross-sectional view schematically illustrating yet another example of a printed circuit board. [Figure 16] FIG. 16 is a plan view showing a schematic top view of the printed circuit board of FIG. 15. [Figure 17] 16A to 16C are process diagrams schematically illustrating an example of manufacturing the metal post of FIG. 15. [Figure 18] FIG. 10 is a cross-sectional view schematically illustrating yet another example of a printed circuit board. [Figure 19] FIG. 19 is a plan view showing a schematic top view of the printed circuit board of FIG. 18. [Figure 20] 19A to 19C are process diagrams schematically illustrating an example of manufacturing the metal post of FIG. 18. [Figure 21] FIG. 10 is a cross-sectional view schematically illustrating yet another example of a printed circuit board. [Figure 22] FIG. 22 is a plan view showing a schematic top view of the printed circuit board of FIG. 21. [Figure 23] 22 is a process diagram schematically showing an example of manufacturing the metal post of FIG. 21. FIG. [Figure 24] FIG. 10 is a cross-sectional view schematically illustrating yet another example of a printed circuit board. [Figure 25] FIG. 25 is a plan view showing a schematic top view of the printed circuit board of FIG. 24. [Figure 26] 25 is a process diagram schematically showing an example of manufacturing the metal post of FIG. 24. [Figure 27] FIG. 10 is a cross-sectional view schematically illustrating yet another example of a printed circuit board. [Figure 28] FIG. 28 is a plan view showing a schematic top view of the printed circuit board of FIG. 27. [Figure 29] 28 is a process diagram schematically showing an example of manufacturing the metal post of FIG. 27. [Figure 30] FIG. 10 is a cross-sectional view schematically illustrating yet another example of a printed circuit board. [Figure 31] FIG. 31 is a plan view showing a schematic top view of the printed circuit board of FIG. 30. [Figure 32] 31 is a process diagram schematically showing an example of manufacturing the metal post of FIG. 30. [Figure 33] FIG. 10 is a cross-sectional view schematically illustrating yet another example of a printed circuit board. [Figure 34] FIG. 34 is a plan view showing a schematic top view of the printed circuit board of FIG. 33. [Figure 35] 34 is a process diagram schematically showing an example of manufacturing the metal post of FIG. 33. [Figure 36] FIG. 10 is a cross-sectional view schematically illustrating yet another example of a printed circuit board. [Figure 37] FIG. 37 is a plan view showing a schematic top view of the printed circuit board of FIG. 36. [Figure 38] 37A to 37C are process diagrams schematically showing an example of manufacturing the metal post of FIG. 36. [Figure 39] FIG. 10 is a cross-sectional view schematically illustrating yet another example of a printed circuit board. [Figure 40] FIG. 40 is a plan view showing a schematic top view of the printed circuit board of FIG. 39. [Figure 41] 40 is a process diagram schematically showing an example of manufacturing the metal post of FIG. 39. [Figure 42] FIG. 10 is a cross-sectional view schematically illustrating yet another example of a printed circuit board. [Figure 43] 43 is a process diagram schematically showing an example of manufacturing the metal post of FIG. 42. FIG. [Figure 44] 43 is a process diagram schematically showing an example of manufacturing the metal post of FIG. 42. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0013] The present invention will now be described with reference to the accompanying drawings, in which the shapes and sizes of elements may be exaggerated or reduced for clarity.

[0014] electronic equipment FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0015] Referring to the drawing, an electronic device 1000 houses a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These components are also connected to other electronic components described below to form various signal lines 1090.

[0016] Examples of chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphics processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). It goes without saying that the chip-related components 1020 may include other types of chip-related electronic components. It goes without saying that these chip-related components 1020 may be combined with one another. The chip-related components 1020 may be in the form of a package including the above-mentioned chips and electronic components.

[0017] The network-related components 1030 may include, but are not limited to, Wi-Fi (e.g., IEEE 802.11 family), WiMAX (e.g., IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and any other wireless and wired protocols designated as such, as well as any of a number of other different wireless or wired standards and protocols. It should be understood that the network-related components 1030 may also be combined with the chip-related components 1020.

[0018] The other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCC (multi-layer ceramic capacitors), etc. However, the other components are not limited to these, and may also include passive elements in the form of chip components used for various other applications. It goes without saying that the other components 1040 may be combined with the chip-related components 1020 and / or the network-related components 1030.

[0019] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically coupled to the main board 1010. Examples of the other electronic components include, but are not limited to, a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. These may also include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), etc. Needless to say, other electronic components used for various purposes may also be included depending on the type of electronic device 1000.

[0020] The electronic device 1000 may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, the electronic device 1000 is not limited to these, and it goes without saying that the electronic device 1000 may be any other electronic device that processes data.

[0021] FIG. 2 is a perspective view schematically illustrating an example of an electronic device.

[0022] Referring to the drawings, the electronic device may be, for example, a smartphone 1100. The smartphone 1100 houses a motherboard 1110, to which various components 1120 are physically and / or electrically connected. The smartphone 1100 also houses other components, such as a camera module 1130 and / or a speaker 1140, which may or may not be physically and / or electrically connected to the motherboard 1110. Some of the components 1120 may be the above-mentioned chip-related components, such as, but not limited to, a component package 1121. The component package 1121 may be in the form of a printed circuit board on which electronic components, including active and / or passive components, are surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active and / or passive components are embedded. It goes without saying that the electronic device is not necessarily limited to the smartphone 1100, but may be other electronic devices as described above.

[0023] printed circuit board FIG. 3 is a cross-sectional view schematically showing an example of a printed circuit board, and FIG. 4 is a plan view schematically showing a top view of the printed circuit board of FIG.

[0024] Referring to the drawing, a printed circuit board 100A according to an example embodiment may include a metal post 150 and an insulating layer 141 covering a portion of the metal post 150. The metal post 150 may include a first conductor portion 151 disposed below an imaginary line L1, the first conductor portion 151 being disposed below the imaginary line L1, the second conductor portion 152 being disposed above the imaginary line L1, and a third conductor portion 156 having at least a portion protruding from a side surface of the first conductor portion 151 below the imaginary line L1, where the imaginary line L1 is substantially at the same level as the uppermost surface of the insulating layer 141. The uppermost surface of the insulating layer 141 may refer to the region disposed at the uppermost level when the upper surface of the insulating layer 141 is not uniform. A plurality of such metal posts 150 may be disposed, and the upper surfaces of the metal posts 150 may be disposed at substantially the same level. For example, the metal post 150 can be manufactured by processing a via portion in the insulating layer 141 with a protective layer attached, forming a seed layer S and a metal layer M in a plating process before peeling off the protective layer, and then peeling off the protective layer. Therefore, a plurality of metal posts 150 can be formed with a relatively simple process and substantially no plating deviation. Therefore, a package substrate structure with ensured flatness can be realized. Furthermore, during the process, a gap G can be formed in a region adjacent to the upper surface of the insulating layer 141, and the gap G can be filled with the seed layer S. Therefore, a third conductor 156 can be formed on the side surface of the metal post 150. Therefore, the reliability of the metal post 150 can be further improved.

[0025] Meanwhile, at least another portion of the third conductor portion 156 may protrude from the side surface of the second conductor portion 152 above the imaginary line L1. For example, the thickness of at least one portion of the third conductor portion 156 may be substantially smaller outward from the side surfaces of the first and second conductor portions 151 and 152, respectively. Therefore, the third conductor portion 156 may have a substantially sharp cross-section, but is not limited thereto. Furthermore, the third conductor portion 156 may continuously surround the side surfaces of the first and second conductor portions 151 and 152. Therefore, the third conductor portion 156 may have a substantially donut shape in plan view, but is not limited thereto. The portion of the third conductor portion 156 protruding from the side surface of the first conductor portion 151 may have a larger cross-sectional area than the other portion of the third conductor portion 156 protruding from the side surface of the second conductor portion 152. With such a shape and arrangement, the reliability of the metal post 150 can be more effectively improved.

[0026] Furthermore, the upper surface of the second conductor portion 152 may serve as the upper surface of the metal post 150 and may be substantially flat overall. In this case, it may be more effective in reducing thickness and / or height variations among the plurality of metal posts 150. Furthermore, the first and second conductor portions 151 and 152 may each include a region with a tapered side surface. For example, each of the first and second conductor portions 151 and 152 may have a tapered shape in which the width of the upper end is greater than the width of the lower end. In this case, the side surfaces of the first and second conductor portions 151 and 152 may have substantially the same slope as each other, but are not limited thereto. As a result, the metal post 150 may have a tapered shape, which may be more effective in achieving a fine pitch.

[0027] Meanwhile, the printed circuit board 100A according to an example may further include a pad 123P. The insulating layer 141 may cover a portion of the pad 123P, and the metal post 150 may be connected to an upper surface of the pad 123P exposed from the insulating layer 141. The metal post 150 may include a seed layer S and a metal layer M. At least a portion of the metal layer M may be disposed below the virtual line L1, and at least another portion may be disposed above the virtual line L1. The seed layer S may cover at least a portion of the lower surface and side surfaces of the metal layer M. The seed layer S may be in contact with at least a portion of the side surface of the metal layer M disposed above the virtual line L1 and may be spaced apart from the upper surface of the metal layer M. For example, the seed layer S may cover the side surfaces of the metal layer M but not the upper surface. The first to third conductor portions 151, 152, and 156 may include the seed layer S and / or the metal layer M. With such a structure, the flatness of the metal post 150 can be more easily ensured, and the reliability of the metal post 150 can be more easily improved.

[0028] Furthermore, the printed circuit board 100A according to one example may have a multilayer board structure including a plurality of insulating layers 111, 112, 113, 141, and 142, a plurality of wiring layers 121, 122, 123, and 124 disposed on or within the insulating layers 111, 112, 113, 141, and 142, respectively, and a plurality of via layers 131, 132, and 133 each penetrating at least a portion of at least one of the insulating layers 111, 112, 113, 141, and 142. For example, the printed circuit board 100A according to one example may be a core-type multilayer board. However, the present invention is not limited to this, and the printed circuit board 100A may be a coreless-type multilayer board as needed. The uppermost wiring layer 123 of the plurality of wiring layers 121, 122, 123, and 124 may include the pad 123P described above, and the uppermost insulating layer 141 of the plurality of insulating layers 111, 112, 113, 141, and 142 may include the insulating layer 141 described above. For example, a substrate used in the printed circuit board 100A according to an example may include a plurality of insulating layers 111, 112, 113, 141, and 142, a plurality of wiring layers 121, 122, 123, and 124, and a plurality of via layers 131, 132, and 133, and the metal post 150 may be disposed on the uppermost side of such a substrate. However, the present invention is not limited thereto, and metal posts 150 may also be disposed on the lowermost side of the substrate in substantially the same shape. Such metal posts 150 may be used as posts for mounting electronic components or as posts for joining to another substrate such as a main board.

[0029] The components of the printed circuit board 100A according to an example will be described in more detail below with reference to the drawings.

[0030] A substrate including a plurality of insulating layers 111, 112, 113, 141, 142, a plurality of wiring layers 121, 122, 123, 124, and a plurality of via layers 131, 132, 133 may be a core-type multilayer substrate. For example, the substrate may include a core insulating layer 111, first and second core wiring layers 121, 122 disposed on the upper and lower surfaces of the core insulating layer 111, a core via layer 131 penetrating the core insulating layer 111 and connecting the first and second core wiring layers 121, 122, one or more first built-up insulating layers 112 disposed on the upper surface of the core insulating layer 111, one or more first built-up wiring layers 123 disposed on or within the one or more first built-up insulating layers 112, one or more first built-up via layers 132 each penetrating at least one of the one or more first built-up insulating layers 112, and a core via layer 131 disposed on the lower surface of the core insulating layer 111. The substrate may include one or more second build-up insulating layers 113 disposed on the uppermost first build-up insulating layer 112, one or more second build-up wiring layers 124 disposed on or within the one or more second build-up insulating layers 113, one or more second build-up via layers 133 penetrating at least one of the one or more second build-up insulating layers 113, a first outermost insulating layer 141 disposed on the uppermost first build-up insulating layer 112 of the one or more first build-up insulating layers 112, and a second outermost insulating layer 142 disposed on the lowermost second build-up insulating layer 113 of the one or more second build-up insulating layers 113. However, the substrate is not limited thereto, and may be a coreless multilayer substrate. Alternatively, the substrate may be a multilayer substrate with a hybrid structure including both a core-type substrate portion and a coreless-type substrate portion.

[0031] The core insulating layer 111 may include an insulating material. Examples of the insulating material include, but are not limited to, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, a material in which these insulating resins are mixed with an inorganic filler such as silica, or a resin impregnated into a core material such as glass fiber (glass cloth, glass fabric) together with an inorganic filler, for example, an insulating material such as CCL (Copper Clad Laminate). The core insulating layer 111 may have a thickness greater than each of the one or more first and second build-up insulating layers 112 and 113, but is not limited to this.

[0032] The first and second build-up insulation layers 112 and 113 may each include an insulating material. Examples of the insulating material include, but are not limited to, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, a material in which these insulating resins are mixed with an inorganic filler such as silica, or a resin in which a core material such as glass fiber is impregnated with an inorganic filler, such as prepreg, ABF (Ajinomoto Build-up Film), PID (Photo Imageable Dielectric), and RCC (Resin Coated Copper). The number of layers in the first and second build-up insulation layers 112 and 113 is not particularly limited, and they may have the same number of layers, but are not limited to this.

[0033] The first and second core wiring layers 121 and 122 may each include a metal. Examples of the metal include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof. Preferably, copper (Cu) may be included. The first and second core wiring layers 121 and 122 may each include, but are not limited to, an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). The electroless plating layer may be a sputtered layer instead of chemical copper, or both may be included. If necessary, copper foil may be further included. The first and second core wiring layers 121 and 122 may each perform various functions depending on the design of the layer. For example, they may include a ground pattern, a power pattern, a signal pattern, etc. These patterns may each include a line pattern, a plain pattern, and / or a pad pattern.

[0034] The first and second build-up wiring layers 123 and 124 may each include a metal. Examples of metals that can be used include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Preferably, copper (Cu) may be included. The first and second build-up wiring layers 123 and 124 may each include, but are not limited to, an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). The electroless plating layer may be a sputtered layer instead of chemical copper, or may include both, or may further include copper foil. The first and second build-up wiring layers 123 and 124 may each perform various functions depending on the design of the layer. For example, they may include a ground pattern, a power pattern, a signal pattern, etc. These patterns may each include a line pattern, a plane pattern, and / or a pad pattern. For example, the first build-up wiring layer 123 may include a pad 123P.

[0035] The core via layer 131 may include a through via. The through via may include a metal layer filling the through hole. Alternatively, the through via may include a metal layer formed on the wall surface of the through hole and a plug filling the metal layer. The metal layer may include metals such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Preferably, it may include copper (Cu). The plug may include an ink of an insulating material. The metal layer may include, but is not limited to, an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). A sputtered layer may be formed instead of the chemical copper as the electroless plating layer, and both may be included as needed. The core via layer 131 may perform various functions depending on the design. For example, it may include a ground via, a power via, a signal via, etc. The core via layer 131 may have a substantially cylindrical shape, but is not limited thereto, and may also have a substantially hourglass shape.

[0036] The first and second build-up via layers 132 and 133 may each include a microvia. The microvia may be a filled via that fills a via hole, or a conformal via that is arranged along the wall surface of the via hole. The microvias may be arranged in a stacked and / or staggered manner. The first and second build-up via layers 132 and 133 may each include a metal, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Preferably, the metal may include copper (Cu). The first and second build-up via layers 132 and 133 may each include, but are not limited to, an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). A sputtered layer may be formed instead of the chemical copper as the electroless plating layer, or both may be included. The first and second built-up via layers 132 and 133 may perform various functions depending on the design of the layer, such as ground vias, power vias, signal vias, etc. The microvias of the first built-up via layer 132 and the microvias of the second built-up via layer 133 may have tapered shapes in opposite directions.

[0037] The first and second outermost insulating layers 141 and 142 may each include an insulating material. Examples of the insulating material include, but are not limited to, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material in which the insulating resin is mixed with an inorganic filler such as silica, e.g., Ajinomoto Build-up Film (ABF) or Solder Resist (SR). The first and second outermost insulating layers 141 and 142 are disposed on the upper and lowermost sides of the substrate to protect the internal components. The first outermost insulating layer 141 may include the insulating layer 141 described above. The second outermost insulating layer 142 may have SMD (Solder Mask Defined) and / or NSMD (Non-Solder Mask Defined) type openings.

[0038] The metal post 150 may include a metal. Examples of the metal include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof. Preferably, the metal post 150 includes copper (Cu). The metal post 150 may include a seed layer S and a metal layer M. The seed layer S may include an electroless plating layer (or chemical copper) and / or a stopper layer. The metal layer M may include an electrolytic plating layer (or electrolytic copper). The metal post 150 may perform various functions depending on the design. For example, the metal post 150 may include a ground metal post, a power metal post, a signal metal post, etc. The metal post 150 may be used as a post for mounting electronic components and / or a post for bonding to another substrate such as a main board. The metal post 150 may be divided into multiple regions, for example, first to third conductor portions 151, 152, and 156. The first to third conductor portions 151, 152, and 156 may be integrated with each other without any boundaries. For example, the first to third conductor portions 151, 152, and 156 may include the same seed layer S and / or metal layer M. There may be a plurality of metal posts 150, and the plurality of metal posts 150 may have little plating deviation. Therefore, the top surfaces of the plurality of metal posts 150 may be disposed at substantially the same level.

[0039] FIG. 5 is a process diagram schematically showing an example of a method for manufacturing the metal post of FIG.

[0040] First, a substrate including the pads 123P, an insulating layer 141 covering at least a portion of the pads 123P, and a protective layer 191 disposed on the upper surface of the insulating layer 141 can be prepared. The substrate may be the substrate described above. The insulating layer 141 can be formed by ABF coating or SR lamination and drying. The protective layer 191 may be a protective film attached to the insulating layer 141, such as, but not limited to, a polyethylene terephthalate film. Next, a via portion V can be formed that penetrates the protective layer 191 and the insulating layer 141 in the thickness direction and exposes at least a portion of the upper surface of the pad 123P. The via portion V can be formed by CO2 laser processing or the like. Next, a gap portion G can be formed at the boundary between the protective layer 191 and the insulating layer 141, penetrating a portion of each of the insulating layer 141 and the protective layer 191 from the side of the via portion V in a direction substantially perpendicular to the thickness direction. The gap portion G can be formed by a desmear process. For example, a gap of about 5 μm to 15 μm may be formed at the interface between the protective layer 191 and the insulating layer 141 as the desmearing proceeds.

[0041] Next, a seed layer S may be formed on the bottom surface of the via portion V, for example, on the exposed upper surface of the pad 123P, the wall surface of the via portion V, and the upper surface of the protective layer 191, filling at least a portion of the gap G. The seed layer S may be formed by electroless plating, for example, chemical copper. Next, a metal layer M may be formed on the seed layer S, filling at least a portion of the via portion V. The metal layer M may be formed by electrolytic plating, for example, electrolytic copper. Next, portions of the seed layer S and the metal layer M may be removed. For example, portions of the seed layer S and the metal layer M may be removed by an etching process to expose the protective layer 191. For example, the seed layer S and the metal layer M may be etched so that the upper surface of the metal layer M and the upper surface of the protective layer 191 are substantially coplanar. Next, the protective layer 191 may be removed. The protective layer 191 may be removed by peeling off the protective layer 191. By removing the protective layer 191, the via portion V can remain so as to penetrate only the insulating layer 141.

[0042] The metal posts 150 can be formed through a series of processes, and these processes can be performed even when the substrate is at panel level. Therefore, when forming a plurality of metal posts 150, plating deviation can be minimized to achieve a structure with ensured flatness. In addition, the metal posts 150 include the third conductor portions 156, which can provide excellent reliability. Meanwhile, the height of the metal posts 150 can be determined by the amount of etching of the metal layer M. Other details may be substantially the same as those described above.

[0043] FIG. 6 is a cross-sectional view schematically showing another example of a printed circuit board, and FIG. 7 is a plan view schematically showing a top view of the printed circuit board of FIG.

[0044] Referring to the drawings, in the printed circuit board 100B according to another example, compared to the printed circuit board 100A according to the above example, at least one 150-2 of the plurality of metal posts 150-1 and 150-2 may have a wider maximum cross-sectional width than at least one other 150-1. For example, the second conductor portion 152-2 of at least one metal post 150-2 may have a wider maximum cross-sectional width than the second conductor portion of at least one other metal post 150-1. Therefore, metal posts 150-1 and 150-2 of various sizes can be formed. Meanwhile, the first and third conductor portions 151-2 and 156-2 of at least one metal post 150-2 may have substantially similar structures, materials, etc. to the first and third conductor portions of the other at least one metal post 150-1. Furthermore, in at least one metal post 150-2, the first and second conductor portions 151-2 and 152-2 may have side surfaces that are stepped relative to each other on the cross-section. The other explanations may be substantially the same as those described above.

[0045] FIG. 8 is a process diagram schematically showing an example of manufacturing the metal post of FIG.

[0046] First, a substrate is prepared, and a plurality of via portions V1, V2 may be formed. The plurality of via portions V1, V2 may have different opening sizes in the protective layer 191. For example, the second via portion V2 may have a larger opening size in the protective layer 191 than the first via portion V1. Next, a plurality of gap portions G1, G2 may be formed. The plurality of gap portions G1, G2 may have different sizes. For example, the second gap portion G2 may have a larger area than the first gap portion G1 in cross section. Next, a seed layer S and a metal layer M may be formed. Next, portions of the seed layer S and the metal layer M may be removed. Next, the protective layer 191 may be removed. Metal posts 150-1, 150-2 may be formed through a series of processes, and other descriptions may be substantially the same as those described above.

[0047] FIG. 9 is a cross-sectional view schematically showing yet another example of a printed circuit board, and FIG. 10 is a plan view schematically showing a top view of the printed circuit board of FIG.

[0048] Referring to the drawings, in a printed circuit board 100C according to another example, compared to the printed circuit board 100A according to the above example, the top surface of at least one 150-3 of the plurality of metal posts 150-1 and 150-3 may be positioned higher than the top surface of at least one other 150-1. For example, the second conductor portion 152-3 of the at least one metal post 150-3 may have a greater maximum cross-sectional thickness or height than the second conductor portion of the at least one other metal post 150-1. For example, the height of some 150-3 of the plurality of metal posts 150-1 and 150-3 may be increased as needed. The second conductor portion 152-3 of the at least one metal post 150-3 may be divided into an upper region and a lower region having side surfaces with different slopes. The upper and lower regions may have a step on their sides, and the minimum width of the upper region may be greater than the maximum width of the lower region, but is not limited thereto. The minimum width of the upper region may be smaller than the maximum width of the lower region. Alternatively, the upper and lower regions may be connected without a step between their side surfaces, in which case the minimum width of the upper region and the maximum width of the lower region may be the same. The seed layer S may be disposed on the lower surface of the upper region of the second conductor portion 152-3 of at least one metal post 150-3, but not on the side surfaces of the upper region. The remaining configuration of the at least one metal post 150-3, e.g., the first conductor portion 151-3, the third conductor portion 156-3, etc., may be substantially identical to the first conductor portion, the third conductor portion, etc., of the other at least one metal post 150-1. Other details may be substantially identical to those described above.

[0049] FIG. 11 is a process diagram schematically showing an example of manufacturing the metal post of FIG.

[0050] First, a substrate is prepared, and a plurality of via portions V may be formed. Next, a plurality of gap portions G may be formed. Next, a seed layer S and a metal layer M may be formed. Next, portions of the seed layer S and the metal layer M may be removed. For example, portions of the seed layer S and the metal layer M may be removed by an etching process to expose the protective layer 191. At this time, a dry film 192 may be formed on at least one via portion V, and other portions of the seed layer S and the metal layer M below the dry film 192 may not be removed. As a result, the heights of the second conductor portions 152-1 and 152-3 formed after etching may vary. Then, the dry film 192 may be removed by peeling, etc. Meanwhile, the shape and size of the second conductor portion 152-3 may be formed in various ways as described above depending on the shape and size of the dry film 192. Next, the protective layer 191 may be removed. The metal posts 150-1 and 150-3 may be formed through a series of processes, and other descriptions may be substantially the same as those described above.

[0051] FIG. 12 is a cross-sectional view schematically showing yet another example of a printed circuit board, and FIG. 13 is a plan view schematically showing a top view of the printed circuit board of FIG.

[0052] Referring to the drawings, a printed circuit board 100D according to another example may further include a first metal pattern 160 compared to the printed circuit board 100A according to the above example. An insulating layer 141 may cover a portion of the first metal pattern 160. The first metal pattern 160 may include a trace pattern and / or a pad pattern. The first metal pattern 160 may include a 4-1 conductor portion 161 disposed below the imaginary line L, a 5-1 conductor portion 162 disposed above the imaginary line L1, and a 6-1 conductor portion 166 having at least a portion protruding from a side surface of the 4-1 conductor portion 161 below the imaginary line L1 and at least another portion protruding from a side surface of the 5-1 conductor portion 162 above the imaginary line L1. The 5-1 conductor portion 162 and the 6-1 conductor portion 166 of the first metal pattern 160 may have substantially similar structures, materials, etc. to the second conductor portion and the third conductor portion of the metal post 150, respectively. The upper surface of the first metal pattern 160 may be disposed at substantially the same level as the upper surface of the metal post 150, and the lower surface of the first metal pattern 160 may be disposed higher than the lower surface of the metal post 150. The 4-1 conductor portion 161 of the first metal pattern 160 may have a smaller cross-sectional area, thickness, and / or depth than the first conductor portion of the metal post 150. The 4-1 conductor portion 161 of the first metal pattern 160 may have, for example, a dish-like cross section. The first metal pattern 160 may also include a seed layer S and a metal layer M. For example, the 4-1, 5-1, and 6-1 conductor portions 161, 162, and 166 may each include a seed layer S and / or a metal layer M. Other descriptions may be substantially the same as those described above.

[0053] FIG. 14 is a process diagram schematically showing an example of manufacturing the metal post of FIG.

[0054] First, a substrate is prepared, and a via portion V may be formed. Then, another via portion V' may be formed, penetrating the protective layer 191 in the thickness direction and exposing at least a portion of the top surface of the insulating layer 141. Next, a gap G may be formed. Then, a groove W may be formed below the other via portion V', penetrating a portion of each of the protective layer 191 and the insulating layer 141 in the thickness direction and having a substantially tapered side in cross section. The gap G and the groove W may be formed by a desmear process. Next, a seed layer S may be formed. The seed layer S may fill at least a portion of each of the gap G and the groove W. Next, a metal layer M may be formed. The metal layer M may fill at least a portion of each of the via portion V and the other via portion V'. Next, portions of the seed layer S and the metal layer M may be removed. Next, the protective layer 191 may be removed. The metal post 150 and the first metal pattern 160 may be formed through a series of processes, and the rest of the description may be substantially the same as described above.

[0055] FIG. 15 is a cross-sectional view schematically showing yet another example of a printed circuit board, and FIG. 16 is a plan view schematically showing a top view of the printed circuit board of FIG.

[0056] Referring to the drawings, in a printed circuit board 100E according to yet another example, compared to the printed circuit board 100D according to yet another example described above, the 4-2 conductor portion 171 of the second metal pattern 170 may be formed thicker and / or deeper than the 4-1 conductor portion of the first metal pattern described above. The 5-2 conductor portion 172, the 6-2 conductor portion 176, etc. of the second metal pattern 170 may have cross-sectional structures substantially similar to the second conductor portion, the third conductor portion, etc. of the metal post 150 described above. The second metal pattern 170 may also include a seed layer S and a metal layer M. For example, the 4-2, 5-2, and 6-2 conductor portions 171, 172, and 176 may each include a seed layer S and / or a metal layer M. Other details may be substantially the same as those described above.

[0057] FIG. 17 is a process diagram schematically showing an example of manufacturing the metal post of FIG.

[0058] First, a substrate is prepared, and a via portion V may be formed. A trench portion T may be formed that penetrates a portion of the protective layer 191 and the insulating layer 141 in the thickness direction and exposes at least a portion of the insulating layer 141. The depth of the via portion V may be deeper than the depth of the trench portion T. Next, a gap portion G may be formed. Another gap portion J may be formed from the side of the trench portion T, penetrating a portion of each of the protective layer 191 and the insulating layer 141 in a direction substantially perpendicular to the thickness direction. The gap portion G and the other gap portion J may be formed by a desmear process. Next, a seed layer S may be formed. The seed layer S may be further disposed on the bottom surface of the trench portion T, the wall surface of the trench portion T, and the upper surface of the protective layer 191, and may further fill at least a portion of the other gap portion J. Next, a metal layer M may be formed. The metal layer M may further fill at least a portion of the trench portion T. Next, portions of the seed layer S and the metal layer M may be removed. Next, the protective layer 191 may be removed. The metal posts 150 and the second metal patterns 170 can be formed through a series of processes, and other details may be substantially the same as those described above.

[0059] FIG. 18 is a cross-sectional view schematically showing yet another example of a printed circuit board, and FIG. 19 is a plan view schematically showing a top view of the printed circuit board of FIG.

[0060] Referring to the drawings, a printed circuit board 100F according to another example may further include a surface treatment layer Q disposed on the upper surface of the metal post 150, as compared to the printed circuit board 100A according to the above example. For example, the surface treatment layer Q may include, but is not limited to, one or more of a tin (Sn) layer and a gold (Au) layer. The surface treatment layer Q may cover the upper surface of the metal post 150, for example, the upper surface of the second conductor portion 152, and may be spaced apart from the side surface of the metal post 150, for example, the side surface of the second conductor portion 152, but is not limited to this. The surface treatment layer Q may improve bonding reliability. Other details may be substantially the same as those described above.

[0061] FIG. 20 is a process diagram schematically showing an example of manufacturing the metal post of FIG.

[0062] First, a substrate is prepared, and a via portion V may be formed. Next, a gap portion G may be formed. Next, a seed layer S and a metal layer M may be formed. Next, portions of the seed layer S and the metal layer M may be removed. Next, a surface treatment layer Q may be formed on the exposed upper surfaces of the seed layer S and the metal layer M. The surface treatment layer Q may be formed by, but is not limited to, electrolytic gold plating, electroless gold plating, OSP (Organic Solderability Preservative) or electroless tin plating, electroless silver plating, electroless nickel plating / displacement gold plating, DIG (Direct Immersion Gold) plating, HASL (Hot Air Solder Leveling), or the like. Next, the protective layer 191 may be removed. If necessary, the surface treatment layer Q may be formed after removing the protective layer 191. The above-described metal post 150 and the surface treatment layer Q covering it may be formed through a series of processes, and other details may be substantially the same as those described above.

[0063] FIG. 21 is a cross-sectional view schematically showing yet another example of a printed circuit board, and FIG. 22 is a plan view schematically showing a top view of the printed circuit board of FIG.

[0064] Referring to the drawings, a printed circuit board 100G according to another example differs from the printed circuit board 100A according to the above example in that the upper surface of the second conductor portion 152' may include a central region r1 and a corner region r2 that surrounds the central region r1 and at least a portion of which protrudes upward from the central region r1. The protruding height of at least a portion of the corner region r2 may be approximately 5 μm or less. For example, the central region r1 of the upper surface of the second conductor portion 152' of the metal post 150' may be substantially flat, and the corner regions r2 may be substantially sharper as they extend upward. Furthermore, the maximum height of the central region r1 relative to the imaginary line L1 may be smaller than the maximum height of the corner regions r2. Furthermore, the second conductor portion 152' of the metal post 150' may be formed thicker, and the side surface of the second conductor portion 152' may include multiple regions with different slopes. The second conductor portion 152' having such a shape may be formed during the process of peeling a portion of the plating layer from the protective layer, which may be a structural result that supports the process described below. The seed layer S may contact a portion of the side surface of the metal layer M in a region disposed above the imaginary line L1, and may be spaced apart from another portion of the side surface. The seed layer S may also be spaced apart from the top surface of the metal layer M. For example, the seed layer S may not cover the top surface of the metal layer M or a portion of the side surface of the metal layer M connected to the top surface of the metal layer M. Such a shape and arrangement may more effectively improve the reliability of the metal posts 150′. Furthermore, it may be more effective in reducing thickness and / or height variations among the plurality of metal posts 150′. Furthermore, it may be more effective in achieving a fine pitch. Other aspects may be substantially the same as those described above.

[0065] FIG. 23 is a process diagram schematically showing an example of manufacturing the metal post of FIG.

[0066] First, a substrate is prepared, and a via portion V is formed. Next, a gap portion G is formed. Next, a seed layer S and a metal layer M are formed. Next, portions of the seed layer S and the metal layer M can be removed. For example, portions of the seed layer S and the metal layer M can be peeled off from the protective layer 191. As a result, the protective layer 191 can be exposed. At this time, based on an imaginary line L2 that is substantially at the same level as the uppermost surface of the protective layer 191, other portions of the metal layer M can remain above the imaginary line L2. Furthermore, at least some of the corner regions surrounding the central region of the upper surface of the metal layer M can protrude above the central region. For example, the above-described sharp shape can be formed. However, this is not limited thereto. When physically peeling off portions of the seed layer S and the metal layer M from the protective layer 191, if a mask is attached to the upper surface of the other portions of the metal layer M, the upper surface of the metal layer M may have an overall flat shape rather than the above-described sharp shape. Meanwhile, if the top surface of the protective layer 191 is not uniform, the uppermost surface may refer to the region located at the uppermost level. As such, the height of the metal post 150' may be determined by the thickness of the protective layer 191 and the thickness of the electroplated layer. Next, the protective layer 191 may be removed. The above-described metal post 150' may be formed through a series of processes, and other details may be substantially the same as those described above.

[0067] FIG. 24 is a cross-sectional view schematically showing yet another example of a printed circuit board, and FIG. 25 is a plan view schematically showing a top view of the printed circuit board of FIG.

[0068] Referring to the drawings, in a printed circuit board 100H according to yet another example, compared to the printed circuit board 100G according to the above-described yet another example, at least one 150'-2 of the plurality of metal posts 150'-1, 150'-2 may have a wider maximum cross-sectional width than at least one other metal post 150'-1. For example, the second conductor portion 152'-2 of at least one metal post 150'-2 may have a wider maximum cross-sectional width than the second conductor portion of at least one other metal post 150'-1. This allows the metal posts 150'-1, 150'-2 to be formed in various sizes. Meanwhile, the first and third conductor portions 151-2, 156-2 of at least one metal post 150'-2 may have similar structures, materials, etc. to the first and third conductor portions of at least one other metal post 150'-1. In addition, at least one metal post 150'-2 may have a step between the respective side surfaces of the first and second conductor portions 151-2 and 152'-2 in cross section. The other descriptions may be substantially the same as those described above.

[0069] FIG. 26 is a process diagram schematically showing an example of manufacturing the metal post of FIG.

[0070] First, a substrate is prepared, and multiple via portions V1 and V2 may be formed. The multiple via portions V1 and V2 may have different opening sizes in the protective layer 191. For example, the second via portion V2 may have a larger opening size in the protective layer 191 than the first via portion V1. Next, multiple gap portions G1 and G2 may be formed at the boundary between the protective layer 191 and the insulating layer 141, penetrating a portion of the insulating layer 141 from each side of the multiple via portions V1 and V2 in a direction substantially perpendicular to the thickness direction. The multiple gap portions G1 and G2 may have different sizes. For example, the second gap portion G2 may have a larger area than the first gap portion G1 in a cross section, but is not limited to this. Next, a seed layer S and a metal layer M may be formed. Next, portions of the seed layer S and the metal layer M may be removed. Next, the protective layer 191 may be removed. Through a series of processes, a plurality of metal posts 150'-1, 150'-2 can be formed, and other details can be substantially the same as those described above.

[0071] FIG. 27 is a cross-sectional view schematically showing yet another example of a printed circuit board, and FIG. 28 is a plan view schematically showing a top view of the printed circuit board of FIG.

[0072] Referring to the drawings, in a printed circuit board 100I according to yet another example, compared to the printed circuit board 100G according to yet another example described above, the top surface of at least one 150'-3 of the plurality of metal posts 150'-1, 150'-3 may be positioned higher than the top surface of the at least one other 150'-1. For example, the height of some 150'-3 of the plurality of metal posts 150'-1, 150'-3 may be increased as needed. For example, at least one metal post 150'-3 may further include an additional conductor portion 153'-3. The additional conductor portion 153'-3 may have a structure and material similar to that of the second conductor portion of the at least one other metal post 150'-1. For example, the top surface of the additional conductor portion 153'-3 may include a central region r3 and a corner region r4 that surrounds the central region r3 and at least a portion of which protrudes above the central region r3. The additional conductor portion 153'-3 may include a second seed layer S2 and a second metal layer M2 separate from the first seed layer S1 and the first metal layer M1. The remaining components of the at least one metal post 150'-3, such as the first to third conductor portions 151-3, 152'-3, and 156-3, may have substantially similar structures and materials to the first to third conductor portions of the other at least one metal post 150-1. Other descriptions may be substantially the same as those described above.

[0073] FIG. 29 is a process diagram schematically showing an example of manufacturing the metal post of FIG.

[0074] First, a substrate is prepared, and multiple via portions V and multiple gap portions G are formed. Next, a first seed layer S1 and a first metal layer M1 are formed. Next, a second protective layer 193 is attached on the first metal layer M1. The second protective layer 193 may be a protective film, such as, but not limited to, a polyethylene terephthalate film. Next, an additional via portion v is formed through the second protective layer 193, exposing at least a portion of the top surface of the first metal layer M1. The additional via portion v can be formed by CO2 laser processing or the like. Next, a second seed layer S2 can be formed on the bottom surface of the additional via portion v, for example, on the exposed top surface of the first metal layer M1, the wall surface of the additional via portion v, and the top surface of the second protective layer 193. The second seed layer S2 can be formed by electroless plating, for example, chemical copper. Next, a second metal layer M2 can be formed on the second seed layer S2, filling at least a portion of the additional via portion v. The second metal layer M2 may be formed by electrolytic plating, for example, electrolytic copper. Next, portions of the second seed layer S2 and the second metal layer M2 may be removed. For example, portions of the second seed layer S2 and the second metal layer M2 may be peeled off from the second protective layer 193. As a result, the second protective layer 193 may be exposed. At this time, a protruding or sharp shape may be formed on the upper surface of the remaining second metal layer M2. Next, the second protective layer 193 may be removed. The second protective layer 193 may be removed by peeling off the second protective layer 193. Next, portions of the first seed layer S1 and the first metal layer M1 may be removed. Next, the first protective layer 191 may be removed. Through a series of processes, a plurality of metal posts 150′-1 and 150′-3 may be formed, and other descriptions may be substantially the same as those described above.

[0075] FIG. 30 is a cross-sectional view schematically showing yet another example of a printed circuit board, and FIG. 31 is a plan view schematically showing a top view of the printed circuit board of FIG.

[0076] Referring to the drawings, a printed circuit board 100J according to another example may further include a first metal pattern 160' disposed on the insulating layer 141, compared to the printed circuit board 100G according to the above-described another example. The first metal pattern 160' may include a trace pattern and / or a pad pattern. The first metal pattern 160' may include a 4-1 conductor portion 161 disposed below the imaginary line L, a 5-1 conductor portion 162' disposed above the imaginary line L1, and a 6-1 conductor portion 166 having at least a portion protruding from a side surface of the 4-1 conductor portion 161 below the imaginary line L1 and at least another portion protruding from a side surface of the 5-1 conductor portion 162' above the imaginary line L1. The 5-1 conductor portion 162' and the 6-1 conductor portion 166 of the first metal pattern 160' may have a structure, material, etc. similar to the second conductor portion and the third conductor portion of the metal post 150', respectively. The upper surface of the first metal pattern 160' may be disposed at substantially the same level as the upper surface of the metal post 150', and the lower surface of the first metal pattern 160' may be disposed higher than the lower surface of the metal post 150'. The 4-1 conductor portion 161 of the first metal pattern 160' may have a smaller cross-sectional area, thickness, and / or depth than the first conductor portion of the metal post 150'. The 4-1 conductor portion 161 of the first metal pattern 160' may be, for example, dish-shaped in cross section. The first metal pattern 160' may also include a seed layer S and a metal layer M. For example, the 4-1, 5-1, and 6-1 conductor portions 161, 162', and 166 may each include a seed layer S and / or a metal layer M. Other descriptions may be substantially the same as those described above.

[0077] FIG. 32 is a process diagram schematically showing an example of manufacturing the metal post of FIG.

[0078] First, a substrate is prepared, and a via portion V may be formed. Then, another via portion V' may be formed, penetrating the protective layer 191 in the thickness direction and exposing at least a portion of the top surface of the insulating layer 141. Next, a gap G may be formed. Then, a groove W may be formed below the other via portion V', penetrating a portion of each of the protective layer 191 and the insulating layer 141 in the thickness direction and having a substantially tapered side in cross section. The gap G and the groove W may be formed by a desmear process. Next, a seed layer S may be formed. The seed layer S may fill at least a portion of the gap G and the groove W. Next, a metal layer M may be formed. The metal layer M may fill at least a portion of the via portion V and another via portion V'. Next, portions of the seed layer S and the metal layer M may be removed. Next, the protective layer 191 may be removed. Through a series of processes, a metal post 150' and a first metal pattern 160' may be formed, and other descriptions may be substantially the same as those described above.

[0079] FIG. 33 is a cross-sectional view schematically showing yet another example of a printed circuit board, and FIG. 34 is a plan view schematically showing a top view of the printed circuit board of FIG.

[0080] Referring to the drawings, in a printed circuit board 100K according to yet another example, compared to the printed circuit board 100J according to yet another example described above, the 4-2 conductor portion 171 of the second metal pattern 170' may be formed thicker and / or deeper than the 4-1 conductor portion of the first metal pattern described above. The 5-2 conductor portion 172', 6-2 conductor portion 176, etc. of the second metal pattern 170' may have a cross-sectional structure similar to the second conductor portion, the third conductor portion, etc. of the metal post 150' described above. The second metal pattern 170' may also include a seed layer S and a metal layer M. For example, the 4-2, 5-2, and 6-2 conductor portions 171, 172', and 176 may each include a seed layer S and / or a metal layer M. Other details may be substantially the same as those described above.

[0081] FIG. 35 is a process diagram schematically showing an example of manufacturing the metal post of FIG.

[0082] First, a substrate is prepared, and a via portion V may be formed. A trench portion T may be formed that penetrates a portion of the protective layer 191 and the insulating layer 141 in the thickness direction and exposes at least a portion of the insulating layer 141. The depth of the via portion V may be deeper than the depth of the trench portion T. Next, a gap portion G may be formed. Another gap portion J may be formed from the side of the trench portion T in a direction substantially perpendicular to the thickness direction, penetrating a portion of each of the protective layer 191 and the insulating layer 141. The gap portion G and the other gap portion J may be formed by a desmear process. Next, a seed layer S may be formed. The seed layer S may be further disposed on the bottom surface of the trench portion T, the wall surface of the trench portion T, and the upper surface of the protective layer 191, and may further fill at least a portion of the other gap portion J. Next, a metal layer M may be formed. The metal layer M may further fill at least a portion of the trench portion T. Next, portions of the seed layer S and the metal layer M may be removed. Next, the protective layer 191 may be removed. Through a series of processes, the metal posts 150' and the second metal pattern 170' can be formed, and other details may be substantially the same as those described above.

[0083] FIG. 36 is a cross-sectional view schematically showing yet another example of a printed circuit board, and FIG. 37 is a plan view schematically showing a top view of the printed circuit board of FIG.

[0084] Referring to the drawings, a printed circuit board 100L according to another example differs from the printed circuit board 100G according to the above-described another example in that the insulating layer 141 may include a first insulating material 141a and a second insulating material 141b disposed on the first insulating material 141a. The first insulating material 141a and the second insulating material 141b may include different insulating materials, for example, but not limited to, ABF and SR, respectively. Furthermore, based on an imaginary line L3 that is substantially at the same level as the boundary surface between the first and second insulating materials 141a and 141b, the metal post 150'-4 may further include another third conductor portion 156-5, at least a portion of which protrudes from a side surface of the first conductor portion 151 below the imaginary line L3 and at least another portion of which protrudes from a side surface of the first conductor portion 151 above the imaginary line L3. The other third conductor portion 156-5 may be substantially identical to the third conductor portion 156, but is not limited thereto. Meanwhile, the reliability of the metal post 150'-4 can be further improved. The other explanations can be substantially the same as those described above.

[0085] FIG. 38 is a process diagram schematically showing an example of manufacturing the metal post of FIG.

[0086] First, a substrate may be prepared. The insulating layer 141 of the substrate may include a first insulating material 141a covering at least a portion of the pad 123P and a second insulating material 141b disposed on an upper surface of the first insulating material 141a. A protective layer 191 may be disposed on an upper surface of the second insulating material 141b. Next, a via portion V'' may be formed to penetrate the protective layer 191 and the first and second insulating materials 141a and 141b in the thickness direction and expose at least a portion of the upper surface of the pad 123P. Next, a gap portion G may be formed to penetrate a portion of each of the second insulating material 141b and the protective layer 191 in a direction substantially perpendicular to the thickness direction from a side portion of the via portion V'' at the boundary between the second insulating material 141b and the protective layer 191. Furthermore, another gap G-5 may be formed penetrating a portion of each of the first and second insulating materials 141a, 141b in a direction substantially perpendicular to the thickness direction from a side of the via portion V'' at the boundary between the first and second insulating materials 141a, 141b. Next, a seed layer S may be formed. The seed layer S may fill at least a portion of each of the gap G and the other gap G-5. Next, a metal layer M may be formed. Next, portions of the seed layer S and the metal layer M may be removed. Next, the protective layer 191 may be removed. Through a series of processes, the metal post 150'-4 may be formed, and other descriptions may be substantially the same as those described above.

[0087] FIG. 39 is a cross-sectional view schematically showing yet another example of a printed circuit board, and FIG. 40 is a plan view schematically showing a top view of the printed circuit board of FIG.

[0088] Referring to the drawings, a printed circuit board 100M according to another example may further include a surface treatment layer Q disposed on an upper surface of a metal post 150′, as compared to the printed circuit board 100G according to the above-described another example. The surface treatment layer Q may include, but is not limited to, one or more of a tin (Sn) layer and a gold (Au) layer. The surface treatment layer Q may cover an upper surface of the metal post 150′, for example, an upper surface of the second conductor portion 152′, and may be spaced apart from a side surface of the metal post 150′, for example, a side surface of the second conductor portion 152, but is not limited to this. The surface treatment layer Q may improve the bonding reliability with electronic components and / or a main board. Other details may be substantially the same as those described above.

[0089] FIG. 41 is a process diagram schematically showing an example of manufacturing the metal post of FIG.

[0090] First, a substrate is prepared, and a via portion V may be formed. Next, a gap portion G may be formed. Next, a seed layer S and a metal layer M may be formed. Next, a surface treatment layer Q may be formed on the metal layer M. The surface treatment layer Q may be formed by, for example, but not limited to, electrolytic gold plating, electroless gold plating, OSP (Organic Solderability Preservative) or electroless tin plating, electroless silver plating, electroless nickel plating / displacement gold plating, DIG (Direct Immersion Gold) plating, HASL (Hot Air Solder Leveling), etc. Next, portions of the seed layer S and the metal layer M may be removed. For example, portions of the seed layer S and the metal layer M may be peeled off from the protective layer 191. At this time, portions of the surface treatment layer Q may also be peeled off and removed. Furthermore, sharp protrusions may be formed on the upper surfaces of the metal layer M and the surface treatment layer Q. Next, the protective layer 191 may be removed. Through a series of processes, the above-described metal post 150′ and the surface treatment layer Q covering the same may be formed, and other descriptions may be substantially the same as those described above.

[0091] FIG. 42 is a cross-sectional view schematically showing yet another example of a printed circuit board.

[0092] Referring to the drawings, a printed circuit board 100N according to yet another example may have a structure in which a metal post 150′, a first metal pattern 160′, etc. are applied to a multilayer cavity substrate including a plurality of insulating layers 111, 112, and 113, a plurality of wiring layers 121, 122, 123, and 124, and a plurality of via layers 131, 132, and 133. For example, the printed circuit board 100N according to yet another example may have a blind cavity H penetrating a portion of a plurality of first build-up insulating layers 112 among the plurality of insulating layers 111, 112, and 113. A metal post 150′ may be disposed on the cavity H, and at least a portion of the metal post 150′ may be exposed through the cavity H. For example, the first core wiring layer 121, at least a portion of which is exposed through the cavity H, among the plurality of wiring layers 121, 122, 123, and 124, may include a pad 121P, and a portion of the first build-up insulating layer 112, among the plurality of insulating layers 111, 112, and 113, that provides the bottom surface of the cavity H, may provide the insulating layer 112. Metal posts 150' and / or first metal patterns 160' may also be disposed inside the plurality of insulating layers 111, 112, and 113, and their respective top surfaces may be disposed at substantially the same level. The structures of the metal posts 150', first metal patterns 160', etc. are not limited to those shown in the drawings, and the metal posts and / or metal patterns described in connection with the above-described printed circuit boards 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J, 100K, 100L, and 100M may also be applied. The other explanations may be substantially the same as those described above.

[0093] 43 and 44 are process diagrams that schematically show an example of a method for manufacturing the metal post of FIG.

[0094] First, first and second core wiring layers 121 and 122 and a first via layer 131 can be formed on the core insulating layer 111, first and second buildup insulating layers 112 and 113 can be formed on both sides of the core insulating layer 111, and a second buildup wiring layer 124 and a second buildup via layer 133 can be formed on the second buildup insulating layer 113. Furthermore, a protective layer 191 can be formed on the first buildup insulating layer 112, and after processing via portions V, other via portions V', gap portions G, groove portions W, etc., a seed layer S and a metal layer M can be formed. Then, a line l for forming the cavity H can be processed. Next, portions of the seed layer S and the metal layer M can be removed from the remaining regions except for the region where the cavity H is to be formed. For example, portions of the seed layer S and the metal layer M can be peeled off from the protective layer 191. Then, the protective layer 191 can be removed from the remaining regions except for the region where the cavity H is to be formed. Next, a required number of first and second build-up insulating layers 112 and 113, first and second build-up wiring layers 123 and 124, and first and second build-up via layers 132 and 133 may be formed in a build-up process. Then, a cavity H penetrating a portion of the first build-up insulating layer 112 may be processed. For example, laser processing or blasting may be used, and the metal layer M may be used as a stopper. Next, a portion of each of the seed layer S and the metal layer M in the cavity H region may be removed. For example, a portion of each of the seed layer S and the metal layer M may be peeled off from the protective layer 191. Then, the protective layer 191 in the cavity H region may be removed. Through this series of processes, a multilayer cavity substrate having a metal post 150′, a first metal pattern 160′, etc. may be formed, and other descriptions may be substantially the same as those described above.

[0095] In the present invention, the imaginary line is an imaginary line that does not actually have a thickness on the cross section and may simply be a reference line for defining the positional relationship of components. For example, a structure arranged above and a structure arranged below the imaginary line may be directly connected to each other as needed, or may be integrated with each other without a boundary.

[0096] In the present invention, the term "cover" can refer to not only completely covering but also at least partially covering, and can refer to not only directly covering but also indirectly covering. Furthermore, the term "fill" can refer not only to completely filling but also to at least partially filling, and can also refer to almost completely filling. For example, it can refer to the presence of some voids or gaps. Furthermore, the term "surround" can refer not only to completely surrounding but also to partially surrounding and almost surrounding. Furthermore, the term "expose" can refer not only to completely exposing but also to partially exposing, and "exposing" can refer to exposing a structure from being embedded. For example, exposing a pad through an opening means exposing the pad from the outermost insulating layer, and a surface treatment layer or the like can be further disposed on the exposed pad.

[0097] In the present invention, "substantially" can be determined by taking into account process errors, positional deviations, measurement errors, and the like that occur during the manufacturing process. For example, "disposed at substantially the same level" can include not only being disposed at the exact same position, but also being disposed at approximately the same position. Furthermore, "substantially tapered" can include not only a shape that has a completely tapered shape, but also a shape that has an approximately tapered shape. For example, it can be determined by the overall shape.

[0098] In the present invention, the term "same insulating material" refers not only to the case where the insulating material is completely the same, but also to the case where the insulating material is of the same type. Therefore, although the compositions of the insulating materials are substantially the same, the specific composition ratios thereof may differ slightly.

[0099] In the present invention, the term "on a cross section" can refer to the cross-sectional shape of an object cut vertically or the cross-sectional shape of an object when viewed from the side, and the term "on a plane" can refer to the planar shape of an object cut horizontally or the planar shape of an object when viewed from the top or bottom.

[0100] In the present invention, for convenience, terms such as "lower side, bottom part, lower surface" are used to mean the downward direction based on the cross section of the drawing, and terms such as "upper side, top part, upper surface" are used to mean the opposite direction. However, these are definitions of directions for convenience of explanation, and it goes without saying that the scope of the claims is not particularly limited by such directional descriptions, and the concepts of up / down can be changed at any time.

[0101] In the present invention, the term "connected" refers not only to direct connection but also to indirect connection via an adhesive layer or the like. Furthermore, the term "electrically connected" refers to both physical connection and non-physical connection. Furthermore, expressions such as "first" and "second" are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, a first component may be called a second component, and similarly, a second component may be called a first component, without departing from the scope of the right.

[0102] In the present invention, "thickness, width, length, depth, line width, spacing, pitch, separation distance, surface roughness," etc. can be measured using a scanning microscope, optical microscope, etc., based on a cross section obtained by polishing or cutting a printed circuit board. The cut section can be a vertical or horizontal section, and each value can be measured based on the required cut section. For example, the width of the upper and / or lower ends of a via can be measured on a cross section cut along the central axis of the via. In this case, if the value is not constant, the value can be determined by averaging values ​​measured at any five points.

[0103] The term "one example" used in the present invention does not mean the same embodiment as another example, but is provided to emphasize and describe each example's unique features. However, the example presented above does not exclude the example being realized in combination with features of another example. For example, even if a feature described in a particular example is not described in another example, it can be understood as a description related to the other example unless there is a description in the other example that contradicts or contradicts that feature.

[0104] The terms used in the present invention are merely used to describe an example and are not intended to limit the present invention. In this case, singular expressions include plural expressions unless the context clearly indicates a different meaning. [Explanation of symbols]

[0105] 1000:Electronic equipment 1010: Main board 1020: Chip related parts 1030: Network related parts 1040:Other parts 1050: Camera 1060: Antenna 1070:Display 1080: Battery 1090: Signal line 1100: Smartphone 1110: Motherboard 1120: Parts 1121: Parts package 1130: Camera module 1140:Speaker 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J, 100K, 100L, 100M, 100N: Printed circuit board 111, 112, 113: insulating layers 141a, 141b: Insulation material 121, 122, 123, 124: Wiring layer 131, 132, 133: via layers 141, 142: insulating layer 141a, 141b: Insulation material 150, 150-1, 150-2, 150-3, 150', 150'-1, 150'-2, 150'-3, 150'-4: Metal post 151, 151-1, 151-2, 151-3, 152, 152-2, 152-3, 152', 152'-2, 152'-3, 153'-3, 156, 156-3, 156-5: conductor parts 160, 160', 170, 170': Metal pattern 161, 162, 162', 163, 166: Conductor parts 191, 193: Protective layer 192: Dry film

Claims

1. Metal posts and an insulating layer covering a portion of the metal post; Based on an imaginary line at substantially the same level as the uppermost surface of the insulating layer, The metal post includes a first conductor portion arranged below the imaginary line, a second conductor portion arranged above the imaginary line, and a third conductor portion at least a portion of which protrudes from a side surface of the first conductor portion below the imaginary line.

2. The printed circuit board according to claim 1 , wherein at least another part of the third conductor portion protrudes from a side surface of the second conductor portion above the imaginary line.

3. 3. The printed circuit board according to claim 2, wherein the thickness of the at least one third conductor portion and the at least one other third conductor portion decreases substantially outward from the side surfaces of the first conductor portion and the second conductor portion, respectively.

4. The printed circuit board according to claim 2 , wherein the third conductor portion surrounds each of the side surfaces of the first conductor portion and the second conductor portion.

5. an upper surface of the second conductor portion provides an upper surface of the metal post; The printed circuit board according to claim 1 , wherein the upper surface of the second conductor portion is substantially flat overall.

6. an upper surface of the second conductor portion provides an upper surface of the metal post; The printed circuit board according to claim 1 , wherein the upper surface of the second conductor portion includes a central region and corner regions that surround the central region and at least partially protrude above the central region.

7. the central region is substantially flat; The printed circuit board of claim 6 , wherein the corner regions are substantially sharper upwardly.

8. the top surface of the second conductor portion includes a central region and corner regions surrounding the central region, Based on the virtual line, The printed circuit board of claim 1 , wherein the maximum height of the central region is less than the maximum height of the corner regions.

9. The printed circuit board according to claim 1 , wherein each side surface of the first conductor portion and the second conductor portion includes a tapered region.

10. The printed circuit board according to claim 9 , wherein the side surface of the second conductor portion includes a plurality of regions with different inclinations.

11. The printed circuit board according to claim 10 , wherein a side surface of the second conductor portion has a stepped structure.

12. further comprising a surface treatment layer covering an upper surface of the metal post; The printed circuit board according to claim 1 , wherein the surface treatment layer comprises at least one of a tin (Sn) layer and a gold (Au) layer.

13. A plurality of the metal posts are arranged, 2. The printed circuit board according to claim 1, wherein the upper surfaces of the plurality of metal posts are arranged at substantially the same level as each other.

14. A plurality of the metal posts are arranged, 2. The printed circuit board according to claim 1, wherein at least one of the plurality of metal posts has a maximum width in cross section greater than at least one other of the plurality of metal posts.

15. A plurality of the metal posts are arranged, The printed circuit board according to claim 1 , wherein an upper surface of at least one of the plurality of metal posts is disposed higher than an upper surface of at least one other of the plurality of metal posts.

16. the insulating layer includes a first insulating material and a second insulating material disposed on the first insulating material; With reference to another imaginary line at substantially the same level as the boundary surface between the first insulating material and the second insulating material, the metal post further includes another third conductor portion at least a portion of which protrudes from a side surface of the first conductor portion below the other imaginary line, The printed circuit board according to claim 1 , wherein at least another portion of the other third conductor portion protrudes from a side surface of the first conductor portion above the imaginary line.

17. Further comprising a pad, the insulating layer covers a portion of the pad; The printed circuit board according to claim 1 , wherein the metal post is connected to the upper surface of the pad exposed from the insulating layer.

18. a plurality of insulating layers; a plurality of wiring layers disposed on or within the plurality of insulating layers; a plurality of via layers each penetrating at least a portion of at least one of the plurality of insulating layers; the uppermost wiring layer of the plurality of wiring layers includes the pad; The printed circuit board of claim 17 , wherein the uppermost insulating layer of the plurality of insulating layers includes the insulating layer.

19. a plurality of insulating layers; a plurality of wiring layers disposed on or within the plurality of insulating layers; a plurality of via layers each penetrating at least a portion of at least one of the plurality of insulating layers; the plurality of insulating layers have a cavity that exposes at least a portion of at least one of the plurality of wiring layers; the wiring layer exposed through the cavity includes the pad; an insulating layer providing a bottom surface of the cavity includes the insulating layer; The printed circuit board of claim 17 , wherein at least a portion of the metal post is exposed through the cavity.

20. Further comprising a metal pattern; the insulating layer covers at least a portion of the metal pattern; the metal pattern includes a fourth conductor portion that is disposed below the imaginary line and has a thickness thinner than the first conductor portion, a fifth conductor portion that is disposed above the imaginary line, and a sixth conductor portion that is at least partially protruding from a side surface of the fourth conductor portion below the imaginary line; The printed circuit board according to claim 1 , wherein at least another part of the sixth conductor portion protrudes from a side surface of the fifth conductor portion above the imaginary line.

21. the upper surfaces of the metal posts and the upper surfaces of the metal patterns are disposed at substantially the same level; The printed circuit board according to claim 20 , wherein a lower surface of the metal pattern is located above a lower surface of the metal post.

22. the metal post includes a metal layer and a seed layer covering at least a portion of each of a bottom surface and a side surface of the metal layer; The printed circuit board of claim 1 , wherein each of the first to third conductor portions includes at least one of the metal layer and the seed layer.

23. 23. The printed circuit board of claim 22, wherein the seed layer contacts a side surface of the metal layer in a region located above the imaginary line and is spaced apart from a top surface of the metal layer.

24. 24. The printed circuit board of claim 23, wherein the seed layer contacts a portion of a side surface of the region of the metal layer that is positioned above the imaginary line and is spaced apart from another portion of a side surface of the region of the metal layer that is positioned above the imaginary line.

25. providing a substrate including an insulating layer and a protective layer disposed on the insulating layer; forming a via portion penetrating the protective layer in a thickness direction from an upper surface of the protective layer and further penetrating at least a portion of the insulating layer; forming a gap portion penetrating a portion of each of the insulating layer and the protective layer from a side portion of the via portion in a direction substantially perpendicular to the thickness direction at a boundary between the insulating layer and the protective layer; forming a seed layer disposed on a bottom surface of the via portion, a wall surface of the via portion, and an upper surface of the protective layer, the seed layer filling at least a portion of the gap; forming a metal layer disposed on the seed layer and filling at least a portion of the via; removing a portion of each of the seed layer and the metal layer to expose at least a portion of a top surface of the protective layer; and removing the protective layer.

26. The method of claim 25, wherein the forming of the gap includes a desmear process.

27. removing a portion of each of the seed layer and the metal layer includes removing a portion of each of the seed layer and the metal layer by etching; 26. The method of claim 25, wherein the step of etching away a portion of each of the seed layer and the metal layer is performed such that an upper surface of the metal layer and an upper surface of the protection layer are substantially coplanar with each other.

28. removing the portions of the seed layer and the metal layer includes peeling the portions of the seed layer and the metal layer from the protective layer; Based on yet another imaginary line at substantially the same level as the uppermost surface of the protective layer, The method for manufacturing a printed circuit board according to claim 25 , wherein in the step of peeling the metal layer from the protective layer, another part of the metal layer remains above the still another imaginary line.

29. 29. The method for manufacturing a printed circuit board according to claim 28, wherein in the step of peeling the metal layer from the protective layer, at least a part of a corner region surrounding a central region of the upper surface of the metal layer protrudes above the central region.

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