Gate control type diode and electronic circuit

Abstract

To provide a gate control type diode in which an allowable range of the gate pulse width is increased while an adverse influence on other main electric characteristics is suppressed.SOLUTION: A gate control type diode 110 includes a diode gate electrode embedded in a plurality of first trenches 51 in a first active region RA1 through an oxide film 6, an anode electrode embedded in a plurality of second trenches 52 in a second active region RA2 through the oxide film 6, a P-type channel layer 2 formed in a surface layer of an N-type semiconductor substrate 1 between the two adjacent first trenches 51 and between the two adjacent second trenches 52 and electrically connected to the anode electrode, and an N+ type layer 4 formed in a surface layer of the P-type channel layer 2 in the first active region RA1. The area of the first active region RA1 is 20% or more and 80% or less of the total of the area of the first active region RA1 and the area of the second active region RA2.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to gated diodes. [Background technology]

[0002] 7A and 7B of Patent Document 1 show a gate-controlled diode including an N-type cathode drift layer, a P-type anode layer vertically adjacent to the N-type cathode drift layer, and an N+ type cathode layer vertically adjacent to the N-type cathode drift layer on the side opposite to the P-type anode layer.

[0003] In such gate-controlled diodes, the carrier concentration on the anode side is controlled by turning on / off the gate provided on the anode side. For example, if the MOSFET is an n-channel, when the diode is in a conducting state, a negative voltage is applied to the gate, turning it off, and holes accumulate in the MOSFET channel and are injected into the N-type semiconductor substrate 1, reducing conduction loss.

[0004] Before the diode begins recovery operation, a positive voltage is applied to the gate to turn it on, and electrons accumulate in the MOSFET channel, short-circuiting the anode PN junction or injecting electrons into the N-type semiconductor substrate 1, thereby reducing recovery loss.

[0005] On the other hand, if the gate on time, represented by the gate pulse width, becomes long before the diode recovery operation, the depletion layer extends toward the anode, causing an increase in conduction loss.If the gate pulse width becomes short, the effect of reducing recovery loss is suppressed, resulting in a narrow tolerance range for the gate pulse width. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent Publication No. 2021-90026 Summary of the Invention [Problem to be solved by the invention]

[0007] The present disclosure has been made to solve the above-mentioned problems, and aims to expand the allowable range of gate pulse width in a gate-controlled diode while suppressing adverse effects on other main electrical characteristics. [Means for solving the problem]

[0008] A gate-controlled diode according to the present disclosure comprises a semiconductor substrate of a first conductivity type, an active region formed on a first main surface of the semiconductor substrate, a cathode layer of the first conductivity type formed on a second main surface of the semiconductor substrate, which is the main surface opposite to the first main surface, and a buffer layer of the first conductivity type formed between the cathode layer and the semiconductor substrate, wherein the active region is divided into a first active region and a second active region in a plan view, and the gate-controlled diode comprises a plurality of first trenches periodically formed on the first main surface of the semiconductor substrate in the first active region, diode gate electrodes embedded in the plurality of first trenches via an oxide film, and a semiconductor layer in the second active region. The semiconductor device comprises: a plurality of second trenches periodically formed on a first main surface of a conductive substrate; an anode electrode embedded in the plurality of second trenches via an oxide film; a second conductivity type channel layer formed on a surface layer of the semiconductor substrate between two adjacent first trenches of the plurality of first trenches and between two adjacent second trenches of the plurality of second trenches and electrically connected to the anode electrode; and a first conductivity type layer formed on a surface layer of the channel layer in a first active region, wherein the area of ​​the first active region is 20% or more and 80% or less of the sum of the area of ​​the first active region and the area of ​​the second active region. [Effects of the Invention]

[0009] The gate-controlled diode of the present disclosure can widen the tolerance range of the gate pulse width while suppressing adverse effects on other main electrical characteristics. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a cross-sectional view of a gate-controlled diode according to a prerequisite technique. [Figure 2] FIG. 1 is a circuit diagram of an electronic circuit including a gate-controlled diode according to the base technology. [Figure 3] 10A and 10B are diagrams showing waveforms of gate signals of a pair of IGBTs and a diode gate signal in the base technology. [Figure 4] 1 is a plan view of a gate-controlled diode according to a first embodiment. [Figure 5] FIG. 5 is a cross-sectional view of the gate-controlled diode taken along line ZZ′ in FIG. 4. [Figure 6] FIG. 10 is a circuit diagram of a gate-controlled diode used in the first sequence and its peripheral configuration. [Figure 7] FIG. 10 is a diagram showing waveforms of a diode gate signal and a pair of IGBTs in a first sequence. [Figure 8] FIG. 10 is a circuit diagram of a gate-controlled diode used in the second sequence and its peripheral configuration. [Figure 9] FIG. 2 is a diagram showing a specific configuration of a control circuit. [Figure 10] FIG. 10 is a diagram showing waveforms of a gate signal, a diode gate signal, and a diode gate control signal of a pair of IGBTs in a second sequence. [Figure 11] 10A and 10B are diagrams showing waveforms of gate signals of a pair of IGBTs and a diode gate control signal. [Figure 12] 1 is a diagram showing the forward current of a gate-controlled diode, the cathode-anode voltage, and the waveform of a diode gate control signal. [Figure 13] FIG. 10 is a diagram showing the relationship between normalized Erec and Tw for each area ratio of the first active region. [Figure 14] FIG. 10 shows waveforms of forward current and cathode-anode voltage. [Figure 15] FIG. 15 is an enlarged view of a part of FIG. [Figure 16] FIG. 10 is a diagram showing a waveform of recovery power. [Figure 17]It is a diagram showing the analysis result of the electron distribution during the recovery operation of the gate-controlled diode according to Embodiment 1. [Figure 18] It is a diagram showing the electron distribution during the recovery operation of the gate-controlled diode according to the prior art. [Figure 19] It is an enlarged view of the dotted line portion in FIG. 17. [Figure 20] It is an enlarged view of the dotted line portion in FIG. 18. [Figure 21] It is a diagram showing the current distribution during the recovery operation of the gate-controlled diode of this embodiment. [Figure 22] It is a diagram showing the current distribution during the recovery operation of the gate-controlled diode of the prior art. [Figure 23] It is a diagram showing the dt dependence of Erec. [Figure 24] It is a cross-sectional view of the gate-controlled diode according to the first modification of Embodiment 1. [Figure 25] It is a cross-sectional view of the gate-controlled diode according to the second modification of Embodiment 1. [Figure 26] It is a cross-sectional view of the gate-controlled diode according to the third modification of Embodiment 1.

Mode for Carrying Out the Invention

[0011] <A. Prior Art> FIG. 1 is a cross-sectional view of a gate-controlled diode 100 according to the prerequisite technology. As shown in FIG. 1, the gate-controlled diode 100 includes an N-type semiconductor substrate 1, a P-type channel layer 2 formed on the surface layer of the N-type semiconductor substrate 1 on the first main surface S1 side, and a P+ type layer 3 and an N+ type layer 4 formed on the surface layer of the P-type channel layer 2. The upper surfaces of the P+ type layer 3 and the N+ type layer 4 form the first main surface S1 of the N-type semiconductor substrate 1. A plurality of trenches 5 are periodically formed, extending from the upper surface of the N+ type layer 4 through the N+ type layer 4 and the P-type channel layer 2 to reach the N-type semiconductor substrate 1. Polysilicon 7 is buried in each trench 5 via an oxide film 6. The polysilicon 7 functions as a gate electrode of the gate-controlled diode 100, and a diode gate control signal GD is input to the polysilicon 7. An anode signal A is input to the P+ type layer 3.

[0012] An N-type buffer layer 8 and an N+ type cathode layer 9 are formed on the second main surface S2 side of the N- type semiconductor substrate 1. The lower surface of the N+ type cathode layer 9 constitutes the second main surface of the N- type semiconductor substrate 1. The N-type buffer layer 8 is formed between the N+ type cathode layer 9 and the N- type semiconductor substrate 1.

[0013] 2 is a circuit diagram of an electronic circuit including a gate-controlled diode 100. A power supply Vcc is connected to the cathode of the gate-controlled diode 100. A load inductance is connected between the cathode and anode of the gate-controlled diode 100.

[0014] An IGBT is connected between the anode of the gate-controlled diode 100 and GND. This IGBT is referred to as a paired IGBT 201. The collector electrode of the paired IGBT 201 is connected to the anode of the gate-controlled diode 100, and the emitter of the paired IGBT 201 is connected to GND. A first signal source A1 that outputs a gate signal Gi of the paired IGBT 201 is connected to the gate terminal of the paired IGBT 201 via a resistor R.

[0015] The primary side of the choke coil M1 is connected to the gate of the gate-controlled diode 100. A second signal source A2 that outputs a diode gate signal D is connected to the secondary side of the choke coil M1. The first signal source A1 and the second signal source A2 are independent signal sources. The diode gate signal D output from the second signal source A2 is input to the choke coil M1 as a diode gate control signal GD. In the underlying technology, the diode gate signal D is equal to the diode gate control signal GD. The diode gate control signal GD, which has been voltage-converted by the choke coil M1, is input to the gate of the gate-controlled diode 100.

[0016] 3 shows the waveforms of the gate signal Gi and the diode gate signal D of the paired IGBT 201. As shown in Fig. 3, before the gate signal Gi of the paired IGBT 201 goes to a high level, that is, before the gate of the paired IGBT 201 is turned on, a high-level diode gate signal D, i.e., a turn-on pulse, is applied to the gate of the gate-controlled diode 100.

[0017] In gate-controlled diode 100, the carrier concentration on the anode side is controlled by the on / off operation of the gate provided on the anode side. For example, if the MOSFET is an n-channel, when the diode is in a conducting state, a negative voltage is applied to the gate to turn it off, and holes accumulate in the MOSFET channel and are injected into N-type semiconductor substrate 1, reducing conduction loss.

[0018] Before the diode begins recovery operation, a positive voltage is applied to the gate to turn it on, and electrons accumulate in the MOSFET channel, short-circuiting the anode PN junction or injecting electrons into the N-type semiconductor substrate 1, thereby reducing recovery loss.

[0019] On the one hand, before the recovery operation of the diode, if the on-time of the gate represented by the gate pulse width Tw becomes long, the depletion layer extends to the anode side, resulting in a problem of increased conduction loss. If the gate pulse width Tw becomes short, the effect of reducing the recovery loss is suppressed, so there is a problem that the allowable range of the gate pulse width Tw is narrow.

[0020] Therefore, in the following embodiments, a configuration for expanding the allowable range of the gate pulse width Tw of the gate-controlled diode while suppressing adverse effects on other major electrical characteristics will be described.

[0021] <B. Embodiment 1> In the following embodiments, the N-type is used as the first conductivity type of the semiconductor, and the P-type is used as the second conductivity type. N+ type means that the N-type impurity concentration is higher than that of the N-type, and N- type means that the N-type impurity concentration is lower than that of the N-type. Similarly, P+ type means that the P-type impurity concentration is higher than that of the P-type, and P- type means that the P-type impurity concentration is lower than that of the P-type. Note that the conductivity types of the semiconductors may be opposite. That is, the N-type may be used as the second conductivity type, and the P-type may be used as the first conductivity type.

[0022] <B-1. Structure> FIG. 4 is a plan view of the gate-controlled diode 111 according to Embodiment 1. In FIG. 4, only the active region RA of the gate-controlled diode 111 is shown, and structures such as any breakdown voltage holding structure or gate wiring arranged surrounding the active region RA are not shown. FIG. 5 is a cross-sectional view of the gate-controlled diode 111 along the Z-Z' line of FIG. 4.

[0023] Hereinafter, the configuration of the gate-controlled diode 111 will be described with reference to FIGS. 4 and 5. The gate-controlled diode 111 includes an N-type semiconductor substrate 1. An active region RA is provided on the first main surface S1 of the N-type semiconductor substrate 1. The active region RA includes a first active region RA1 and a second active region RA2. The active region RA is divided into a first active region RA1 and a second active region RA2 in a plan view.

[0024] In the first active region RA1 and the second active region RA2, an N-type layer 11, a P-type channel layer 2, and an N+-type layer 4 are provided on the first main surface S1 side of the N- type semiconductor substrate 1. The N-type layer 11 is formed between the N- type semiconductor substrate 1 and the P-type channel layer 2, and the N+-type layer 4 is formed in a part of the surface layer of the N- type layer 11. The upper surfaces of the N+-type layer 4 and the N-type layer 11 form the first main surface S1 of the N- type semiconductor substrate 1.

[0025] A plurality of trenches are periodically formed, extending from the first main surface S1 of the N-type semiconductor substrate 1 through the P-type channel layer 2 and the N-type layer 11 to reach the N-type semiconductor substrate 1. Of these trenches, the trench formed in the first active region RA1 is referred to as a first trench 51, and the trench formed in the second active region RA2 is referred to as a second trench 52. First polysilicon 71 is buried in the first trench 51 with an oxide film 6 interposed therebetween. Second polysilicon 72 is buried in the second trench 52 with the oxide film 6 interposed therebetween.

[0026] The first polysilicon 71 functions as the gate electrode of the gate-controlled diode 111, and receives a diode gate control signal GD. The gate electrode of the gate-controlled diode is also referred to as a diode gate electrode. On the other hand, an anode signal is input to the P-type channel layer 2 in the first active region RA1 and the second active region RA2 and to the second polysilicon 72. That is, the second polysilicon 72 functions as the anode electrode of the gate-controlled diode.

[0027] An N-type buffer layer 8 and an N+ type cathode layer 9 are formed on the second main surface S2 side of the N- type semiconductor substrate 1. The lower surface of the N+ type cathode layer 9 constitutes the second main surface S2 of the N- type semiconductor substrate 1. The N-type buffer layer 8 is formed between the N+ type cathode layer 9 and the N- type semiconductor substrate 1. The area of ​​the first active region RA1 is 20% or more and 80% or less of the total area of ​​the first active region RA1 and the second active region RA2, i.e., the area of ​​the active region RA.

[0028] <B-2.シーケンス> As the sequences of the diode gate control signal GD input to the gate-controlled diode 111, a first sequence and a second sequence will be described below.

[0029] 6 is a circuit diagram of a gate-controlled diode 111 used in the first sequence and its peripheral configuration. In other words, FIG. 6 is a circuit diagram of an electronic circuit including the gate-controlled diode 111. In FIG. 6, the gate-controlled diode 100 in the circuit diagram of FIG. 2 is replaced with the gate-controlled diode 111. That is, the diode gate control signal GD is equal to the diode gate signal D output from the second signal source A2, which is an independent signal source.

[0030] Fig. 7 shows the waveforms of the diode gate signal D and the paired IGBT 201 in the first sequence. In Fig. 7, the time from when the diode gate signal D turns off until the gate signal Gi turns on is defined as delay time dt. Here, delay time dt is 0 seconds or more.

[0031] Fig. 8 is a circuit diagram of the gate-controlled diode 111 and its peripheral circuitry used in the second sequence. In other words, Fig. 8 is a circuit diagram of an electronic circuit including the gate-controlled diode 111. In the circuit of Fig. 8, a control circuit 301 is provided between the second signal source A2 and the choke coil M1. The control circuit 301 receives a diode gate signal D from the second signal source A2, receives a gate signal Gi for the paired IGBTs 201 from the first signal source A1, and outputs a diode gate control signal GD.

[0032] 9 shows a specific configuration of the control circuit 301. The control circuit 301 is configured to include a NOT gate 31 and an AND gate 32. The gate signal Gi of the paired IGBT 201 is input to an input terminal of the NOT gate 31. The output terminal of the NOT gate 31 is connected to one input terminal of the AND gate 32. The diode gate signal D is input to the other input terminal of the AND gate 32. The output of the AND gate 32 becomes a diode gate control signal GD.

[0033] FIG. 10 shows waveforms of the gate signal Gi, the diode gate signal D, and the diode gate control signal GD of the pair IGBT 201 in the second sequence. In the second sequence, even when the fall of the diode gate signal D is delayed with respect to the rise of the gate signal Gi of the pair IGBT 201, the diode gate control signal GD falls simultaneously with the rise of the gate signal Gi.

[0034] <B-3. Peak Concentration> The allowable range of the peak concentration of each layer of the gate-controlled diode 111 is shown. The allowable range of the peak concentration of the N-type semiconductor substrate 1 is 1.0×10 12 cm -3 or more and 1.0×10 14 cm -3 or less. If the peak concentration of the N-type semiconductor substrate 1 deviates from this allowable range, there is a risk of causing a decrease in withstand voltage or the like. The allowable range of the peak concentration of the P-type channel layer 2 is 1.0×10 15 cm -3 or more and 1.0×10 17 cm -3 or less. If the peak concentration of the P-type channel layer 2 exceeds the upper limit, there is a risk of a decrease in the recovery blocking ability. If the peak concentration of the P-type channel layer 2 exceeds the lower limit, there is a risk of becoming non-conductive. The lower limit of the peak concentration of the P+ type layer 3 is 1.0×10 17 cm -3 . The peak concentration of the N+ type layer 4 needs to be higher than the peak concentration of the P-type channel layer 2. The lower limit of the peak concentration of the N-type buffer layer 8 is 1.0×10 15 cm -3 . If the peak concentration of the N-type buffer layer 8 exceeds the lower limit, there is a risk of causing a decrease in withstand voltage or the like. The lower limit of the peak concentration of the N+ type cathode layer 9 is 1.0×10 17 cm -3 . If the peak concentration of the N+ type cathode layer 9 exceeds the lower limit, there is a risk of becoming non-conductive. The peak concentration of the N-type layer 11 needs to be higher than the peak concentration of the N-type semiconductor substrate 1 and lower than the peak concentration of the P-type channel layer 2. If the peak concentration of the N-type layer 11 exceeds the upper limit, there is a risk of becoming non-conductive.

[0035] <B-4. Effect> <B-4-1. Effect of expanding the allowable range of the gate pulse width Tw> Figures 11 and 12 show representative examples of the recovery waveform. In Figure 11, the solid line indicates the gate signal Gi of the pair IGBT 201, and the dashed line indicates the waveform of the diode gate control signal GD. In Figure 11, the period during which the diode gate control signal GD is input is illustrated as the gate pulse width Tw.

[0036] In Figure 12, the dash-dotted line indicates the forward current If of the gate-controlled diode 111, the solid line indicates the cathode-anode voltage Vka, and the dashed line indicates the waveform of the diode gate control signal GD. The cathode-anode voltage Vka is obtained by subtracting the anode voltage from the cathode voltage. The loss of the gate-controlled diode 111 occurring from the turn-on of the diode gate control signal GD to the turn-off of the forward current If is defined as Erec. Specifically, Erec indicates the energy loss generated when the gate-controlled diode 111 performs the recovery operation. In Figure 12, the occurrence period of Erec is indicated by an arrow.

[0037] Figure 13 shows the relationship between the normalized Erec and Tw for each area ratio of the first active region RA1. The area ratio of the first active region RA1 is the area ratio of the first active region RA1 to the first active region RA1 and the second active region RA2. Since the prior art gate-controlled diode 100 does not have the second active region RA2, the area ratio of the first active region RA1 is 100%.

[0038] As shown in FIG. 13, in the gate-controlled diode 100 of the prior art, Erec decreases while the gate pulse width Tw is small, but Erec increases when the gate pulse width Tw becomes 20 μs or more. On the other hand, in the gate-controlled diode 111 according to Embodiment 1, even when the gate pulse width Tw increases, the increase amount of Erec is suppressed, and the effect of reducing the recovery loss is remarkably obtained. That is, in the gate-controlled diode 111, the allowable range of the gate pulse width Tw is expanded compared with the gate-controlled diode 100 of the prior art. There is no effect of reducing the recovery loss when the gate pulse width Tw = 0 s, and there is a tendency that the recovery loss remarkably increases when the gate pulse width Tw ≧ 50 μs. Therefore, it is desirable that the gate pulse width Tw is 0 μs or more and less than 50 μs.

[0039] Under the same condition of the gate pulse width Tw, as the area ratio of the first active region RA1 increases from 20% to �0%, the reduction rate of the recovery loss is large. When the area ratio of the first active region RA1 is less than 20%, no remarkable effect of reducing the recovery loss can be obtained. Further, when the area ratio of the first active region RA1 exceeds 80%, the effect of reducing the recovery loss deteriorates dramatically. Therefore, it is desirable that the area ratio of the first active region RA1 is 20% or more and 80% or less.

[0040] <B-4-2. Mechanism for Expanding the Allowable Range of the Gate Pulse Width Tw> FIGS. 14 to 16 show the recovery waveforms of the gate-controlled diode 111 when the gate pulse width Tw is 30 μs. In these figures, the dotted line indicates the case where the area ratio of the first active region RA1 is 100%, and the solid lines indicate the cases where the area ratio of the first active region RA1 is 0%, 20%, and 80%. FIG. 14 shows the waveforms of the forward current If and the cathode-anode voltage Vka, and FIG. 15 is an enlarged view of a part of FIG. 14. FIG. 16 shows the waveform of the recovery power Prr.

[0041] It was found that as the area ratio of the first active region RA1 increases from 0% to 80%, the maximum reverse recovery current Irr decreases, and Erec loss also decreases. On the other hand, in the case of the base technology structure where the area ratio of the first active region RA1 is 100%, the maximum reverse recovery current Irr decreases, but when the diode gate control signal GD is turned on, the cathode-anode voltage Vka increases in the negative direction. In other words, it was found that the conduction voltage, which is the anode voltage minus the cathode voltage, increases, and conduction loss increases.

[0042] 17 to 22 show the results of 2D internal analysis of the gate-controlled diode 111 of this embodiment and the gate-controlled diode 100 according to the prerequisite technology. FIGS. 17, 19, and 21 show the analysis results for the gate-controlled diode 111, where the area ratio of the first active region RA1 in the gate-controlled diode 111 is 80%. FIGS. 18, 20, and 22 show the analysis results for the gate-controlled diode 100 according to the prerequisite technology. FIGS. 17 and 18 show the electron distribution during recovery operation. FIGS. 19 and 20 are enlarged views of the dotted line areas in FIGS. 17 and 18, respectively. FIGS. 21 and 22 show the current distribution during recovery operation. The time of the internal analysis was t=2.0×10 s as shown in FIG. 14. -4 It is s.

[0043] 17 to 20 show that in both the gate-controlled diode 111 of this embodiment and the gate-controlled diode 100 according to the prerequisite technology, when the diode gate control signal GD is turned on, electrons accumulate on the P-type channel layer 2 side of the oxide film 6 in the MOSFET portion on the anode side. The electron accumulation layer short-circuits the N+ type layer 4, the N- type layer 11, and the N- type semiconductor substrate 1, and the PN junction between the P-type channel layer 2 and the N- type semiconductor substrate 1 is also short-circuited and becomes non-conductive. As a result, holes are no longer injected from the P-type channel layer 2, and a depletion layer extends from the anode side of the first active region RA1.

[0044] In the gate control type diode 111 of the present embodiment, since the PN junction conducts normally in the second active region RA2, the depletion layer does not extend, and the low conduction voltage of the diode can be maintained. Therefore, there is no increase in conduction loss.

[0045] On the other hand, in the gate control type diode 100 of the prior art, when the gate turns on, as shown in FIG. 18, the depletion layer extends from the entire region on the anode side, and a high-resistance region occurs in the entire region. Since the current flows through the high-resistance region, the conduction loss increases. Actually, as shown by the dotted line in FIG. 16, the conduction loss of the gate control type diode 100 of the prior art is large. Therefore, in the gate control type diode 100 of the prior art, the reduction of the recovery loss and the increase of the conduction loss cancel each other out, and the effect of improving the characteristics cannot be obtained.

[0046] <B-4-3. Allowable range of delay time dt> In the first sequence shown in FIGS. 6 and 7, the gate signal Gi of the pair IGBT201 and the diode gate signal D are also independent signal sources. In order to prevent malfunction, the delay time dt from when the diode gate signal D turns off to when the gate signal Gi turns on needs to be set to 0 s or more.

[0047] Referring to FIG. 8, when the gate control type diode 111 is in the recovery operation, the pair IGBT201 is in the on operation. When the pair IGBT201 turns off, since there is no electrical path between the power supply Vcc and GND, the current flows between the gate control type diode 111 and the load inductance Lm. When the pair IGBT201 turns on, an electrical path is formed between the power supply Vcc and GND, and the current flows through the load inductance Lm and the pair IGBT201.

[0048] When the gate of the pair IGBT 201 is on and the gate of the gate-controlled diode 111 is off, as described above, current does not flow from the power supply Vcc through the gate-controlled diode 111. When the gate of the pair IGBT 201 is on and the gate of the gate-controlled diode 111 is also on, the N+ layer 4, the N layer 11, and the N- type semiconductor substrate 1 are short-circuited via the electron accumulation layer, so current from the power supply Vcc flows from the cathode side to the anode side, causing the circuit to malfunction. To prevent this malfunction, it is necessary to set the delay time dt to 0 s or more.

[0049] Figure 23 shows the dt-dependency of Erec. It can be seen that as dt increases, holes are injected again from the PN junction on the anode side, weakening the recovery loss reduction effect of the gate-controlled diode 111. Therefore, in order to obtain the recovery loss reduction effect, it is desirable for dt to be as close to 0 s as possible.

[0050] In the second sequence shown in FIGS. 8 to 10, the gate of the gate-controlled diode 111 is not controlled by an independent signal source, but is controlled by both the gate signal Gi of the pair IGBT 201 and the diode gate signal D. When the gate signal Gi of the pair IGBT 201 is on, the diode gate control signal GD is always off by the control circuit 301. As a result, while preventing malfunction, the recovery loss reduction effect can be exhibited.

[0051] <B-5. Modified Example> The characteristic structure of the gate-controlled diode 111 described in Embodiment 1 is applicable to a p-i-n diode having a MOSFET gate structure in the anode type, for example, an RC-IGBT, and the same effect can be obtained.

[0052] The gate-controlled diode 111 is, for example, of a high breakdown voltage class of 3300V, but may be of other breakdown voltage classes.

[0053] 24 is a cross-sectional view of a gate-controlled diode 111 according to a first modification of the first embodiment. The gate-controlled diode 111 differs from the gate-controlled diode 110 of the first embodiment in that it does not include an N-type layer 11. Since the gate-controlled diode 111 does not include an N-type layer 11, holes are more easily injected from the anode PN junction, and the characteristics of the diode are shifted to the slower side. Note that the N-type layer 11 may be partially formed.

[0054] 25 is a cross-sectional view of a gate-controlled diode 112 according to a second modification of the first embodiment. The gate-controlled diode 112 differs from the gate-controlled diode 110 in that a portion of the N+ type cathode layer 9 serves as a P-type cathode layer 10, and the N+ type cathode layers 9 and the P-type cathode layers 10 are alternately arranged in a plane direction perpendicular to the thickness direction of the gate-controlled diode 112. The P-type cathode layer 10 provides a recovery oscillation suppression effect. Note that the P-type impurity concentration of the P-type cathode layer 10 is desirably higher than the N-type impurity concentration of the N-type buffer layer 8.

[0055] 26 is a cross-sectional view of a gate-controlled diode 113 according to a third modification of the first embodiment. The gate-controlled diode 113 differs from the gate-controlled diode 110 in that a P+ type layer 3 is provided on the surface of the P-type channel layer 2 in the first active region RA1 and the second active region RA2. The upper surface of the P+ type layer 3 forms the first main surface S1 of the N- type semiconductor substrate 1. The P+ type layer 3 improves the ohmic contact of the anode-side contact. The P+ type layer 3 may be formed partially, or the impurity concentration may be different between the first active region RA1 and the second active region RA2.

[0056] In the first embodiment and its modifications, the P-type channel layer 2 may be formed partially, or the impurity concentration may be different between the first active region RA1 and the second active region RA2.

[0057] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above embodiments, and various modifications and substitutions can be made to the above embodiments without departing from the scope of the claims. [Explanation of symbols]

[0058] 1 N-type semiconductor substrate, 2 P-type channel layer, 4 N+ type layer, 6 oxide film, 7 polysilicon, 8 N-type buffer layer, 9 N+ type cathode layer, 51 first trench, 52 second trench, 71 first polysilicon, 72 second polysilicon, 100, 110, 111, 112, 113 gate-controlled diode.

Claims

1. a semiconductor substrate of a first conductivity type; an active region formed on a first main surface of the semiconductor substrate; a cathode layer of a first conductivity type formed on a second main surface of the semiconductor substrate, the second main surface being a main surface opposite to the first main surface; a buffer layer of a first conductivity type formed between the cathode layer and the semiconductor substrate, the active region is divided into a first active region and a second active region in a plan view, a plurality of first trenches periodically formed in the first main surface of the semiconductor substrate in the first active region; a diode gate electrode embedded in each of the first trenches via an oxide film; a plurality of second trenches periodically formed in the first main surface of the semiconductor substrate in the second active region; an anode electrode embedded in the plurality of second trenches via an oxide film; a second conductivity type channel layer formed in a surface layer of the semiconductor substrate between two adjacent first trenches of the plurality of first trenches and between two adjacent second trenches of the plurality of second trenches, the second conductivity type channel layer being electrically connected to the anode electrode; a first conductivity type layer formed on a surface layer of the channel layer in the first active region, an area of ​​the first active region is 20% or more and 80% or less of a total area of ​​the first active region and the second active region; Gate-controlled diode.

2. the anode electrode is connected to the collector electrode of the paired IGBT; a delay time from when a diode gate control signal input to the diode gate electrode is turned off until a gate signal input to the gate electrodes of the paired IGBTs is turned on is equal to or greater than zero; 2. The gate-controlled diode of claim 1.

3. The pulse width of the diode gate control signal is equal to or greater than 0 μs and less than 50 μs.

3. The gate-controlled diode of claim 2.

4. A gate-controlled diode according to claim 2 or 3; a pair of IGBTs connected to an anode electrode of the gate-controlled diode; a first signal source that supplies a gate signal to the gate electrodes of the pair of IGBTs; a second signal source that outputs a diode gate signal independently of the first signal source; a control circuit that generates the diode gate control signal based on the gate signal and the diode gate signal, The control circuit a NOT gate to which the gate signal is input; an AND gate having the output of the NOT gate as one input and the diode gate signal as the other input, the output of the AND gate is the diode gate control signal; electronic circuit.

5. the pulse width of the diode gate signal is equal to or greater than 0 μs and less than 50 μs; 5. The electronic circuit of claim 4.

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