Display device

Abstract

To improve display quality.SOLUTION: A display panel 11 comprises: a connection wire 37 connected to a first wire 27α; a first switch wire 38; a first switching element 40; a second switch wire 39; a second switching element 41; and a signal supply section connected to the connection wire 37, the first switch wire 38, and the second switch wire 39. The signal supply section supplies an image signal to the connection wire 37, and supplies a switch signal to the first switch wire 38 and the second switch wire 39 at different timings, and the first wire 27α is disposed while being sandwiched by a second wire 27β and a third wire 27γ.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a display device with improved display quality. [Background technology]

[0002] A known example of a conventional display device is a liquid crystal display device described in Patent Document 1. In the liquid crystal display device described in Patent Document 1, a plurality of pixel electrodes are arranged in a group in a predetermined direction, and only specific image signal lines among the image signal lines electrically connected to each of the pixel electrodes are electrically connected to a drive circuit unit, and a pixel electrode selection circuit overlapping the frame unit in a plan view is disposed on the first substrate on the side facing the liquid crystal, facing the drive circuit unit across the display area, and the pixel electrode selection circuit supplies image signals from the drive circuit unit to each of the plurality of pixel electrodes constituting the group via the specific image signal line in a time-division manner. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-218330 Summary of the Invention [Problem to be solved by the invention]

[0004] In the liquid crystal display device described in Patent Document 1, three pixel electrodes form one group. Three image signal lines connected to these three pixel electrodes are connected to a pixel electrode selection circuit, while a specific image signal line among the three image signal lines is connected to a drive circuit. The pixel electrode selection circuit supplies an image signal from the drive circuit via the specific image signal line to the three image signal lines forming one group in a time-division manner. However, the specific image signal line is located at the end of the three image signal lines forming one group. This tends to complicate the routing of the specific image signal line to connect it to multiple CMOS transfer gate elements in the pixel electrode selection circuit, and the specific image signal line crosses multiple time-division signal input lines in the pixel electrode selection circuit. This raises concerns about parasitic capacitance between the specific image signal line and multiple time-division signal input lines, which could result in an increased load on the specific image signal line. An increased load on the specific image signal line could cause distortion of the transmitted image signal, resulting in a decrease in display quality.

[0005] The technology described in this specification was developed based on the above circumstances, and aims to improve display quality. [Means for solving the problem]

[0006] (1) A display device according to the technology described in this specification includes a display area where an image is displayed, a non-display area where the image is not displayed, a first wiring arranged in the display area, a second wiring arranged in the display area, a third wiring arranged in the display area, a connection wiring arranged in the non-display area and connected to the first wiring, a first switch wiring arranged in the non-display area, a first gate electrode arranged in the non-display area and connected to the first switch wiring, a first source electrode connected to the first wiring or the connection wiring, and a first drain electrode connected to the second wiring, a second switch wiring arranged in the non-display area, and a first switching element arranged in the non-display area, a second switching element having a second gate electrode connected to the second switch wiring, a second source electrode connected to the first wiring or the connecting wiring, and a second drain electrode connected to the third wiring; and a signal supply unit arranged in the non-display area and connected to the connecting wiring, the first switch wiring, and the second switch wiring, wherein the signal supply unit supplies an image signal to the connecting wiring and supplies switch signals of voltages higher than threshold voltages of the first switching element and the second switching element to the first switch wiring and the second switch wiring at different timings, and the first wiring is arranged sandwiched between the second wiring and the third wiring.

[0007] (2) Furthermore, in addition to (1), the display device may further include a display panel having a main surface including the display area and the non-display area, the display panel being provided with the first wiring, the second wiring, the third wiring, the connection wiring, the first switch wiring, the second switch wiring, the first switching element, and the second switching element, the signal supply unit including at least a first signal supply unit provided on the display panel and connected to the connection wiring, which supplies the image signal to the connection wiring, the first wiring, the second wiring, and the third wiring all extending along a first direction, the first signal supply unit, the first switching element, and the second switching element being arranged on either side of the display area in the first direction on the display panel, and the first wiring being connected to the first source electrode and the second source electrode.

[0008] (3) In addition to (2), the display device may be arranged such that the first switch wiring and the second switch wiring sandwich the first switching element and the second switching element between them and the display area in the first direction.

[0009] (4) In addition to (2) or (3), the display device may be arranged such that the first switching element and the second switching element are arranged on either side of the first wiring in a second direction intersecting the first direction.

[0010] (5) In addition to the above (1), the display device further includes a display panel having a main surface including the display region and the non-display region, the display panel is provided with the first wiring, the second wiring, the third wiring, the connection wiring, the first switch wiring, the second switch wiring, the first switching element, and the second switching element, the signal supply unit includes at least a first signal supply unit that is provided on the display panel and connected to the connection wiring and supplies the image signal to the connection wiring, the first wiring, the second wiring, and the third wiring all extend along a first direction, and the first switching element and the second switching element are arranged in a direction parallel to the display region of the display panel in the first direction. The first signal supply unit may be arranged in pairs on either side of the display area of ​​the display panel, the first signal supply unit being positioned on the side of one of the first switching elements and the second switching element with respect to the display area in the first direction, the connection wiring being connected to the first source electrode and the second source electrode of one of the first switching elements and the second switching element arranged on the same side of the display area as the first signal supply unit with respect to the first direction, and the first wiring being connected to the first source electrode and the second source electrode of the other of the first switching elements and the second switching element arranged on the opposite side of the display area from the first signal supply unit with respect to the first direction.

[0011] (6) In addition to the above (1), the display device further comprises: a display panel having a main surface including the display area and the non-display area; and a first switch circuit including a plurality of unit switch circuits each formed of the first switching element and the second switching element, and including the first switch wiring and the second switch wiring, wherein the display panel is provided with the first wiring, the second wiring, the third wiring, the connection wiring, and the first switch circuit; the signal supply unit includes at least a first signal supply unit that is provided on the display panel, connected to the connection wiring, and supplies the image signal to the connection wiring; the first wiring, the second wiring, and the third wiring all extend along a first direction; the display area includes a first region whose outer dimensions in a second direction intersecting with the first direction change depending on a position in the first direction, and a second region whose outer dimensions in the second direction are constant depending on a position in the first direction; and the first wiring, the second wiring, and the third wiring are provided between the first region and the second region. the connection wiring includes a first connection wiring connected to the first wiring arranged in the first region and a second connection wiring connected to the first wiring arranged in the second region, the first signal supply unit is arranged on one side of the display region in the first direction on the display panel, the plurality of unit switch circuits include a first unit switch circuit including the first switching element and the second switching element having the first source electrode and the second source electrode, respectively, connected to the first wiring connected to the first connection wiring, and a second unit switch circuit including the first switching element and the second switching element having the first source electrode and the second source electrode, respectively, connected to the second connection wiring, the first unit switch circuit is arranged on the opposite side of the display panel from the first signal supply unit in the first direction, and the second unit switch circuit is arranged on the same side of the display panel as the first signal supply unit in the first direction.

[0012] (7) In addition to the above (1), the display device further includes: a first region whose outer dimensions in a second direction intersecting with the first direction change depending on a position in the first direction; and a second region whose outer dimensions in the second direction are constant depending on a position in the first direction; the first wiring, the second wiring, and the third wiring are arranged in the first region; a fourth wiring arranged in the second region; a fifth wiring arranged in the second region; a sixth wiring arranged in the second region; a distribution wiring arranged in the non-display region and connected to the signal supply unit; and a fourth wiring arranged in the non-display region. The display device may include a third switch wiring, a third switching element arranged in the non-display area and having a third gate electrode connected to the first switch wiring, a third source electrode connected to the distribution wiring, and a third drain electrode connected to the fourth wiring, a fourth switching element arranged in the non-display area and having a fourth gate electrode connected to the second switch wiring, a fourth source electrode connected to the distribution wiring, and a fourth drain electrode connected to the fifth wiring, and a fifth switching element arranged in the non-display area and having a fifth gate electrode connected to the third switch wiring, a fifth source electrode connected to the distribution wiring, and a fifth drain electrode connected to the sixth wiring.

[0013] (8) In addition to the above (7), the display device may be configured such that the first wiring, the second wiring, and the third wiring have shorter wiring lengths than the fourth wiring, the fifth wiring, and the sixth wiring.

[0014] (9) In addition to any one of (1) to (8), the display device may be configured such that the first wiring is composed of a first wiring component made of a first conductive film and a second wiring component made of a second conductive film arranged above the first conductive film via a first insulating film and overlapping with the first wiring component, and the first wiring component and the second wiring component are connected through a first contact hole formed in the first insulating film.

[0015] (10) In addition to (9), the display device may be configured such that the second wiring is composed of a third wiring component consisting of a portion of the first conductive film that is different from the first wiring component, and a fourth wiring component consisting of a portion of the second conductive film that is different from the second wiring component and overlaps with the third wiring component; the third wiring is composed of a fifth wiring component consisting of a portion of the first conductive film that is different from the first wiring component and the third wiring component, and a sixth wiring component consisting of a portion of the second conductive film that is different from the second wiring component and the fourth wiring component and overlaps with the fifth wiring component; the third wiring component and the fourth wiring component are connected through a second contact hole formed in the first insulating film; and the fifth wiring component and the sixth wiring component are connected through a third contact hole formed in the first insulating film.

[0016] (11) In addition to the above (9), the display device may further include a first position detection wiring arranged in the display area and connected to the signal supply unit, a second position detection wiring arranged in the display area and connected to the signal supply unit, and a position detection electrode arranged in the display area, forming a capacitance with a position input body that performs position input and connected to at least one of the first position detection wiring and the second position detection wiring, wherein the signal supply unit supplies position detection signals to the first position detection wiring and the second position detection wiring, the second wiring consisting of a portion of the first conductive film different from the first wiring configuration unit, the third wiring consisting of a portion of the first conductive film different from the first wiring configuration unit and the second wiring, the first position detection wiring consisting of a portion of the second conductive film different from the second wiring configuration unit and arranged to overlap with the second wiring, and the second position detection wiring consisting of a portion of the second conductive film different from the second wiring configuration unit and the first position detection wiring and arranged to overlap with the third wiring.

[0017] (12) In addition to (9), the display device may further include a common electrode disposed in the display area, a first common wiring disposed in the display area and connected to the common electrode and the signal supply unit, and a second common wiring disposed in the display area and connected to the common electrode and the signal supply unit, wherein the signal supply unit supplies a common potential signal to the first common wiring and the second common wiring, the second wiring being made up of a portion of the first conductive film different from the first wiring configuration unit, the third wiring being made up of a portion of the first conductive film different from the first wiring configuration unit and the second wiring, the first common wiring being made up of a portion of the second conductive film different from the second wiring configuration unit and arranged to overlap with the second wiring, and the second common wiring being made up of a portion of the second conductive film different from the second wiring configuration unit and the first common wiring and arranged to overlap with the third wiring.

[0018] (13) Furthermore, in addition to any one of (1) to (12) above, the display device may be configured such that the signal supply unit supplies the image signal to the connection wiring and the switch signal to the first switch wiring, and after supplying the image signal to the connection wiring and the switch signal to the second switch wiring, supplies the image signal to the connection wiring without supplying the switch signal to either the first switch wiring or the second switch wiring.

[0019] (14) Furthermore, in addition to any one of (1) to (13), the display device may further include a display panel on which the first wiring, the second wiring, the third wiring, the connection wiring, the first switch wiring, the second switch wiring, the first switching element, and the second switching element are provided, and a flexible substrate connected to the display panel, wherein the signal supply unit includes a first signal supply unit provided on the display panel and a second signal supply unit connected to the flexible substrate, and the first signal supply unit supplies the image signal to the connection wiring, and the second signal supply unit supplies the switch signal to the first switch wiring and the second switch wiring via the flexible substrate at different timings. [Effects of the Invention]

[0020] According to the technology described in this specification, it is possible to improve the display quality. [Brief explanation of the drawings]

[0021] [Figure 1] 1 is a plan view of a liquid crystal panel, a driver, a flexible substrate, and a control substrate that constitute a liquid crystal display device according to Embodiment 1. [Figure 2] 1 is a cross-sectional view of a liquid crystal panel, a driver, and a flexible substrate according to Embodiment 1. [Figure 3] FIG. 1 is a plan view showing a pixel arrangement on an array substrate that constitutes a liquid crystal panel according to a first embodiment; [Figure 4] 4 is a cross-sectional view of the liquid crystal panel according to the first embodiment taken along line iv-iv in FIG. 3. [Figure 5] 4 is a cross-sectional view of the liquid crystal panel according to the first embodiment taken along line vv in FIG. 3. [Figure 6] 1 is a circuit diagram showing the electrical configuration of a liquid crystal panel according to a first embodiment; [Figure 7] 1 is a timing chart showing the operation of the gate drive circuit and the first switch circuit according to the first embodiment; [Figure 8] 10 is a plan view of a liquid crystal panel and a driver according to a second embodiment. [Figure 9] 1 is a circuit diagram showing the electrical configuration of a liquid crystal panel according to a second embodiment. [Figure 10] 10 is a circuit diagram showing the electrical configuration of a liquid crystal panel according to a third embodiment. [Figure 11] FIG. 10 is a circuit diagram showing the electrical configuration of a liquid crystal panel according to a fourth embodiment. [Figure 12] 10 is a timing chart showing the operation of the gate drive circuit and the first switch circuit according to the fourth embodiment. [Figure 13] 10 is a plan view of a liquid crystal panel, a driver, a flexible substrate, and a control substrate according to a fifth embodiment. [Figure 14] 10 is a circuit diagram showing the electrical configuration of a liquid crystal panel according to a fifth embodiment. [Figure 15]10 is a cross-sectional view of a liquid crystal panel according to a fifth embodiment taken along the same line as FIG. 5; [Figure 16] 10 is a plan view of a liquid crystal panel, a driver, a flexible substrate, and a control substrate according to a sixth embodiment. [Figure 17] 10 is a circuit diagram showing the electrical configuration of a liquid crystal panel according to a sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0022] <Embodiment 1> Embodiment 1 will be described with reference to Figs. 1 to 7. In this embodiment, a liquid crystal display device (display device) 10 will be illustrated. Note that X-axis, Y-axis, and Z-axis are shown in parts of each drawing, and each axis direction is depicted as being in the direction shown in each drawing. Also, the upper side of Figs. 2, 4, and 5 is the front side, and the lower side of each drawing is the back side.

[0023] As shown in Fig. 1, a liquid crystal display device 10 includes at least a horizontally elongated rectangular liquid crystal panel (display panel) 11 capable of displaying images, and a backlight device (illumination device) that irradiates the liquid crystal panel 11 with light for display. The backlight device is disposed on the rear side (back surface) of the liquid crystal panel 11 and includes a light source (e.g., an LED) that emits white light and optical components that convert the light from the light source into planar light by applying an optical effect. The central portion of the main surface 11S of the liquid crystal panel 11 is a display area AA where an image is displayed. In contrast, the outer peripheral portion of a frame-shaped (picture frame-shaped) portion of the main surface 11S of the liquid crystal panel 11 that surrounds the display area AA is a non-display area NAA where no image is displayed.

[0024] The liquid crystal panel 11 will be described with reference to FIG. 1 and FIG. 2. As shown in FIGS. 1 and 2, the liquid crystal panel 11 is formed by bonding a pair of substrates 20 and 21 together. The front side of the pair of substrates 20 and 21 is the counter substrate 20, and the back side is the array substrate 21. The counter substrate 20 and the array substrate 21 are both formed by laminating various films on the inner surface of a glass substrate. A liquid crystal layer 22 containing liquid crystal molecules, which are a substance whose optical properties change when an electric field is applied, is disposed between the pair of substrates 20 and 21. A seal portion 23 that seals the liquid crystal layer 22 is disposed between the outer peripheral edges of the pair of substrates 20 and 21. The seal portion 23 is formed in a rectangular frame shape so as to surround the liquid crystal layer 22. A polarizing plate 17 is attached to the outer surface of each of the substrates 20 and 21.

[0025] 1 and 2, the short side dimension of the counter substrate 20 is shorter than the short side dimension of the array substrate 21. The counter substrate 20 is attached to the array substrate 21 so that one end in the short side direction (Y-axis direction) is aligned with the array substrate 21. Therefore, the other end in the short side direction of the array substrate 21 is an exposed portion 21A that protrudes laterally from the counter substrate 20 and is exposed. The entire exposed portion 21A is a non-display area NAA, and a driver (first signal supply unit) 12 and a flexible substrate 13 for supplying various signals are mounted on the exposed portion 21A.

[0026] As shown in FIGS. 1 and 2, the driver 12 is mounted on the exposed portion 21A of the array substrate 21 by COG (Chip On Glass). The driver 12 is composed of an LSI chip having a drive circuit inside. The driver 12 processes various signals transmitted by the flexible substrate 13. The driver 12 is arranged adjacent to one side of the display area AA in the Y-axis direction in the exposed portion 21A, and is sandwiched between the flexible substrate 13 (described below) and the display area AA. Two drivers 12 are arranged in the exposed portion 21A at positions spaced apart in the X-axis direction. The driver 12 has a horizontally elongated rectangular shape in plan view. The long side of the driver 12 is smaller than the long side of the display area AA.

[0027] The flexible substrate 13 is configured by forming multiple wiring patterns on a base material made of an insulating and flexible synthetic resin material (e.g., polyimide resin). As shown in FIGS. 1 and 2, one end of the flexible substrate 13 is connected to the exposed portion 21A of the array substrate 21, and the other end is connected to a control substrate (second signal supply unit) 14. The flexible substrate 13 is connected to the end of the exposed portion 21A opposite the display area AA side in the Y-axis direction with respect to the driver 12. In other words, the flexible substrate 13 is attached to the exposed portion 21A at a position where the driver 12 is sandwiched between the flexible substrate 13 and the display area AA. The control substrate 14 is configured by mounting multiple circuit components on a rigid substrate made of synthetic resin (e.g., paper phenol or glass epoxy resin). The multiple circuit components include a power supply IC (Integrated Circuit) for outputting power, a timing controller for generating various signals to be supplied to the driver 12, and a level shifter IC for controlling (stepping down or stepping up) voltage levels. The control substrate 14 has a connector portion to which the flexible substrate 13 and the like are connected. The control substrate 14 is arranged so as to overlap the back side of the backlight device by bending the flexible substrate 13 in a folded shape. Since neither the flexible substrate 13 nor the control substrate 14 overlaps the front side (display side) of the display area AA of the liquid crystal panel 11, it can be said that they are arranged in the non-display area NAA. In this embodiment, the driver 12 and the control substrate 14 described above constitute a signal supply unit SS that supplies signals to each wiring and the like provided in the liquid crystal panel 11.

[0028] 1, a gate drive circuit 15 and a first switch circuit 16 are provided in the non-display area NAA of the array substrate 21. A pair of gate drive circuits 15 are provided to sandwich the display area AA from both sides in the X-axis direction. The gate drive circuit 15 is provided in a vertically long strip-shaped range extending along the short side direction (Y-axis direction) of the array substrate 21. The gate drive circuit 15 is for supplying scanning signals to gate wiring 26, which will be described later, and is provided monolithically on the array substrate 21.

[0029] As shown in FIG. 1 , the first switch circuit 16 is disposed in the non-display area NAA of the array substrate 21 at a position sandwiching the display area AA between it and the driver 12 in the Y-axis direction. That is, the first switch circuit 16 is disposed on one of the four sides of the frame-shaped non-display area NAA of the array substrate 21, on the side opposite the driver 12. The first switch circuit 16 is provided in a horizontally elongated band-shaped range extending along the long side (X-axis direction) of the array substrate 21. The first switch circuit 16 has a switching function of distributing image signals supplied from the driver 12 to source lines 27 (described later), and is a so-called SSD (Source Shared Driving) circuit. The specific circuit configuration of the first switch circuit 16 will be described in detail later.

[0030] The pixel arrangement in the display area AA of the array substrate 21 will be described with reference to FIG. 3. In FIG. 3, the components of the counter substrate 20 are indicated by dashed double-dashed lines. The above-described films of the array substrate 21 will be described in detail later. As shown in FIG. 3, on the inner surface of the display area AA of the array substrate 21, a plurality of pixel TFTs (pixel switching elements) 24 and pixel electrodes 25 are arranged side by side at intervals within the main surface of the array substrate 21. The plurality of pixel TFTs 24 and pixel electrodes 25 are arranged in a matrix (row and column pattern) at intervals in the X-axis and Y-axis directions. A grid of gate wiring (scanning wiring) 26 and source wiring (image wiring, signal wiring) 27 is arranged around the pixel TFTs 24 and pixel electrodes 25. The gate wiring 26 extends along the X-axis direction, and a plurality of gate wirings 26 are arranged side by side at intervals along the Y-axis, sandwiching the pixel electrodes 25. One end of each of the plurality of gate wirings 26 in the X-axis direction is connected to the gate drive circuit 15. The source wirings 27 extend along the Y-axis direction (first direction), and a plurality of source wirings 27 are arranged side by side at intervals in the X-axis direction (second direction intersecting with the first direction) so as to sandwich the pixel electrode 25 therebetween. The source wirings 27 intersect with the gate wirings 26. One end of each of the plurality of source wirings 27 in the Y-axis direction is connected to the first switch circuit 16.

[0031] As shown in Fig. 3, the pixel electrode 25 has a pixel electrode body 25A that has a vertically elongated, approximately rectangular shape in plan view. The pixel electrode 25 also has a contact portion 25B that protrudes to one side along the Y-axis direction from the pixel electrode body 25A. The contact portion 25B protrudes from the pixel electrode body 25A toward the pixel TFT 24 to be connected (downward in Fig. 3), and is disposed so as to overlap most of the pixel drain electrode 24C provided in the pixel TFT 24. The contact portion 25B is the portion of the pixel electrode 25 that is connected to the pixel drain electrode 24C (see Fig. 5).

[0032] The cross-sectional configuration of the pixel electrodes 25 of the liquid crystal panel 11 near the center in the Y-axis direction will be described with reference to Figure 4 and other figures. As shown in Figure 4, a common electrode 28 is formed above all of the pixel electrodes 25 on the inner surface of the display area AA of the array substrate 21, overlapping all of the pixel electrodes 25. The common electrode 28 has a plurality of first openings 28A at positions overlapping each pixel electrode 25. The first openings 28A extend parallel to the long sides (outer shapes) of each pixel electrode 25, and a plurality of first openings 28A are arranged side by side at intervals in the X-axis direction at positions overlapping each pixel electrode 25. A common potential signal (reference potential signal) of a common potential (reference potential) is supplied to the common electrode 28 from the control substrate 14 via the flexible substrate 13, and the common electrode 28 extends in a planar manner across almost the entire display area AA. When a potential difference occurs between the overlapping pixel electrode 25 and common electrode 28 as the pixel electrode 25 is charged, a fringe electric field (oblique electric field) including a component normal to the surface of the array substrate 21 in addition to a component along the main surface of the array substrate 21 is generated between the opening edge of the first opening 28A in the common electrode 28 and the pixel electrode 25. Therefore, by utilizing this fringe electric field, the orientation state of the liquid crystal molecules contained in the liquid crystal layer 22 can be controlled. In other words, the liquid crystal panel 11 according to this embodiment operates in FFS (Fringe Field Switching) mode.

[0033] 4, a plurality of second openings 28B are formed in the common electrode 28 in portions that overlap most of the plurality of source lines 27 (portions other than those that intersect with the gate lines 26). The second openings 28B have the shape of vertically long slits that extend along the source lines 27. The length of the second openings 28B is slightly smaller than the distance between the two gate lines 26 that sandwich the pixel electrode 25 in the Y-axis direction. The second openings 28B reduce parasitic capacitance that may occur between the source lines 27 and the common electrode 28.

[0034] As shown in FIG. 4, a display area AA on the inner surface of the counter substrate 20 constituting the liquid crystal panel 11 is provided with color filters 29 of three colors: blue (B), green (G), and red (R). The color filters 29 of different colors are arranged side by side in the extension direction (X-axis direction) of the gate lines 26. The color filters 29 of different colors extend along the extension direction (roughly the Y-axis direction) of the source lines 27. In this manner, the color filters 29 of different colors are arranged in a striped pattern as a whole. These color filters 29 are arranged to overlap with the pixel electrodes 25 on the array substrate 21 in a plan view, and together with the pixel electrodes 25, form pixels, which are display units. The color filters 29 of different colors are arranged such that their boundaries (color boundaries) overlap with the source lines 27. A light-shielding portion (inter-pixel light-shielding portion, black matrix) 30 is provided on the inner surface of the counter substrate 20, positioned below the color filters 29. The light-shielding portion 30 is made of a light-shielding material with excellent light-shielding properties. The light-shielding portion 30 can block light emitted from a backlight device or the like. In the display area AA, the light-shielding portion 30 has a generally lattice-like planar shape and separates adjacent pixel electrodes 25 (pixels). The light-shielding portion 30 is arranged to overlap at least the gate lines 26 and source lines 27 on the array substrate 21 side in a planar view. An overcoat film 31 is provided on the upper layer side (liquid crystal layer 22 side) of the color filter 29, and is disposed solidly across almost the entire counter substrate 20 for planarization. A conductive film 32 is provided on the outer surface of the counter substrate 20, at least in the display area AA. The conductive film 32 is made of a transparent electrode material and extends planarly across almost the entire display area AA. On the innermost surfaces (uppermost layers) of both substrates 20 and 21 that are in contact with the liquid crystal layer 22, alignment films for aligning the liquid crystal molecules contained in the liquid crystal layer 22 are formed.

[0035] Here, various films laminated on the inner surface of the array substrate 21 will be described with reference to FIG. 5. FIG. 5 is a cross-sectional view of the array substrate 21 near the pixel TFT 24. As shown in FIG. 5, the array substrate 21 is laminated with, from the lower layer (glass substrate side), a first metal film, a gate insulating film 33, a semiconductor film, a second metal film (first conductive film), a first interlayer insulating film (first insulating film) 34, a third metal film (second conductive film), a planarization film 35, a first transparent electrode film, a second interlayer insulating film 36, a second transparent electrode film, and an alignment film. The first metal film, the second metal film, and the third metal film are each a single layer film made of one type of metal material selected from copper, titanium, aluminum, molybdenum, tungsten, etc., or a laminate film or alloy made of different types of metal materials, thereby providing electrical conductivity and light-blocking properties. The first metal film constitutes the gate wiring 26, the pixel gate electrode 24A of the pixel TFT 24, etc. The second metal film constitutes part of the source wiring 27, the pixel source electrode 24B and the pixel drain electrode 24C of the pixel TFT 24, etc. The third metal film constitutes part of the source wiring 27, etc. The semiconductor film is made of a thin film using a material such as an oxide semiconductor or amorphous silicon, and constitutes the pixel semiconductor portion 24D of the pixel TFT 24, etc. The first transparent electrode film and the second transparent electrode film are made of a transparent electrode material (such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide)). The first transparent electrode film constitutes the pixel electrode 25, etc. The second transparent electrode film constitutes the common electrode 28, etc. The alignment film is as described above.

[0036] The gate insulating film 33, the first interlayer insulating film 34, and the second interlayer insulating film 36 are each made of silicon nitride (SiN xThe planarization film 35 is made of an inorganic material such as silicon dioxide (SiO2). The planarization film 35 is made of an organic material such as PMMA (acrylic resin). The planarization film 35 is much thicker than the gate insulating film 33, the first interlayer insulating film 34, and the second interlayer insulating film 36. The planarization film 35 flattens the inner surface of the array substrate 21 (the surface facing the liquid crystal layer 22). The gate insulating film 33 keeps the first metal film on the lower side insulated from the semiconductor film and second metal film on the upper side. For example, the intersection of the gate wiring 26 made of the first metal film and the source wiring 27 made of the second metal film is kept insulated by the gate insulating film 33. Furthermore, in the pixel TFT 24, the overlapping portion of the pixel gate electrode 24A made of the first metal film and the pixel semiconductor portion 24D made of the semiconductor film is kept insulated by the gate insulating film 33. The first interlayer insulating film 34 keeps the semiconductor film and second metal film on the lower layer side insulated from the third metal film on the upper layer side. The planarizing film 35 keeps the third metal film on the lower layer side insulated from the first transparent electrode film on the upper layer side. The second interlayer insulating film 36 keeps the first transparent electrode film on the lower layer side insulated from the second transparent electrode film on the upper layer side. For example, the overlapping portion of the pixel electrode 25 made of the first transparent electrode film and the common electrode 28 made of the second transparent electrode film is kept insulated by the second interlayer insulating film 36.

[0037] Next, the cross-sectional structure of the pixel TFT 24 will be described. As shown in FIG. 5, the pixel TFT 24 has a pixel gate electrode 24A made of a first metal film. The pixel gate electrode 24A is formed by locally widening a portion of the gate line 26 near its intersection with the source line 27 (see FIG. 3). The pixel gate electrode 24A drives the pixel TFT 24 based on a scanning signal supplied to the gate line 26. The pixel TFT 24 has a pixel source electrode 24B made of a second metal film. The pixel source electrode 24B is formed by locally widening a portion of the source line 27 near its intersection with the gate line 26 (see FIG. 3). The pixel source electrode 24B is disposed at one end of the pixel TFT 24 in the X-axis direction (the left end in FIG. 5). The pixel source electrode 24B overlaps a portion of the pixel gate electrode 24A and is connected to the pixel semiconductor portion 24D.

[0038] As shown in FIG. 5, the pixel TFT 24 has a pixel drain electrode 24C made of a second metal film. The pixel drain electrode 24C is disposed at a position spaced apart from the pixel source electrode 24B in the X-axis direction, i.e., at the other end of the pixel TFT 24 in the X-axis direction (the right end in FIG. 5). The end of the pixel drain electrode 24C on the pixel source electrode 24B side is disposed so as to overlap with a portion of the pixel gate electrode 24A and is connected to the pixel semiconductor portion 24D. The end of the pixel drain electrode 24C opposite the pixel source electrode 24B side is disposed so as to overlap with the contact portion 25B of the pixel electrode 25. Pixel contact holes CHPX are opened and provided in the first interlayer insulating film 34 and the planarizing film 35 at positions overlapping both the pixel drain electrode 24C and the contact portion 25B of the pixel electrode 25. The pixel drain electrode 24C and the contact portion 25B of the pixel electrode 25 are connected to each other through the pixel contact hole CHPX.

[0039] As shown in FIG. 5, the pixel TFT 24 has an island-shaped pixel semiconductor portion 24D including a channel portion. The pixel semiconductor portion 24D has a horizontally elongated shape extending along the X-axis direction. The pixel semiconductor portion 24D overlaps the pixel gate electrode 24A via a gate insulating film 33. One end of the pixel semiconductor portion 24D is connected to the pixel source electrode 24B. The other end of the pixel semiconductor portion 24D is connected to the pixel drain electrode 24C. The portion of the pixel semiconductor portion 24D that overlaps with the pixel gate electrode 24A but does not overlap with the pixel source electrode 24B and the pixel drain electrode 24C is a channel portion that functions as a channel (current path). When the pixel TFT 24 is turned on based on a scanning signal supplied to the pixel gate electrode 24A, the image signal (data signal) supplied to the source line 27 is supplied from the pixel source electrode 24B to the pixel drain electrode 24C via the pixel semiconductor portion 24D. As a result, the pixel electrode 25 is charged to a potential based on the image signal.

[0040] Next, the configuration of the source line 27 will be described. As shown in FIGS. 4 and 5, the source line 27 includes a lower layer 27A made of a second metal film and an upper layer 27B made of a third metal film. The lower layer 27A and the upper layer 27B overlap each other, with a first interlayer insulating film 34 interposed therebetween. As shown in FIGS. 3 and 5, a source line contact hole CHS is formed in the first interlayer insulating film 34 at a position where the first interlayer insulating film 34 overlaps both the lower layer 27A and the upper layer 27B. The lower layer 27A and the upper layer 27B are connected to each other through the source line contact hole CHS. The source line contact hole CHS is located adjacent to the pixel source electrode 24B of the pixel TFT 24 in the X-axis direction. The lower layer 27A made of the second metal film is directly connected to the pixel source electrode 24B of the pixel TFT 24, which is also made of the second metal film.

[0041] As shown in FIG. 6, the non-display area NAA of the array substrate 21 is provided with connection wiring 37 that connects a specific source wiring 27 (first source wiring 27α) among the multiple source wirings 27 to the driver 12. The connection wiring 37 is arranged on one of the four sides of the frame-shaped non-display area NAA of the array substrate 21, on the side closest to the driver 12, and is routed from the mounting area of ​​the driver 12 to the display area AA. An image signal is supplied to the connection wiring 37 from the driver 12, which serves as a signal supply unit SS. Hereinafter, the source wiring 27 among the multiple source wirings 27 that is connected to the connection wiring 37 will be referred to as the "first source wiring (first wiring) 27α," the source wiring 27 adjacent to the first source wiring 27α on the left side of FIG. 6 with a gap therebetween will be referred to as the "second source wiring (second wiring) 27β," and the source wiring 27 adjacent to the first source wiring 27α on the right side of FIG. 6 with a gap therebetween will be referred to as the "third source wiring (third wiring) 27γ."

[0042] In this embodiment, as shown in FIG. 6 , the connection wiring 37 is connected to the first source wiring 27α but is not connected to the second source wiring 27β and the third source wiring 27γ. Therefore, the number of connection wirings 37 is less than the number of source wirings 27, for example, about one-third. The first source wiring 27α, the second source wiring 27β, and the third source wiring 27γ are all connected to the first switch circuit 16 described above. An image signal supplied from the driver 12 to the connection wiring 37 is supplied to the first switch circuit 16 via the first source wiring 27α. In other words, the first source wiring 27α has a function of transmitting the image signal from the connection wiring 37 to the first switch circuit 16 (the second source wiring 27β and the third source wiring 27γ). The image signal supplied from the connection wiring 37 to the first source wiring 27α is distributed by the first switch circuit 16 to the second source wiring 27β and the third source wiring 27γ, which are not connected to the connection wiring 37. The configuration of the first switch circuit 16 will be described in detail below.

[0043] As shown in FIG. 6, the first switch circuit 16 has a plurality of unit switch circuits 16U and a plurality of switch wirings 38 and 39. The plurality of unit switch circuits 16U are arranged side by side along the extension direction of the first switch circuit 16 (the X-axis direction). The formation range of the first switch circuit 16 indicated by the dashed line in FIG. 1 represents the range in which the plurality of unit switch circuits 16U are arranged. The number of unit switch circuits 16U installed matches the number of connection wirings 37 installed, and is set to about one-third the number of source wirings 27 installed. The plurality of switch wirings 38 and 39 includes two wirings: a first switch wiring 38 and a second switch wiring 39. The first switch wiring 38 and the second switch wiring 39 extend along the X-axis direction within the range in which the plurality of unit switch circuits 16U are arranged. The first switch wiring 38 and the second switch wiring 39 are drawn out to outside the range in which the plurality of unit switch circuits 16U are arranged in the non-display area NAA of the array substrate 21, extend along the gate drive circuit 15 (in the Y-axis direction), and are then connected to the flexible substrate 13. A switch signal is supplied to the first switch wiring 38 and the second switch wiring 39 from a control substrate 14, which serves as a signal supply unit SS, via the flexible substrate 13. The control substrate 14 outputs a switch signal to the first switch wiring 38 and a switch signal to the second switch wiring 39 at different timings. This switch signal has a voltage higher than the threshold voltages of a first switch TFT 40 and a second switch TFT 41, which will be described later.

[0044] 6, the unit switch circuit 16U has a first switch TFT (first switching element) 40 connected to a first switch wiring 38, a first source wiring 27α, and a second source wiring 27β, and a second switch TFT (second switching element) 41 connected to a second switch wiring 39, a first source wiring 27α, and a third source wiring 27γ. The first switch TFT 40 has a first gate electrode 40A connected to the first switch wiring 38, a first source electrode 40B connected to the first source wiring 27α, a first drain electrode 40C connected to the second source wiring 27β, and a first semiconductor portion 40D connected to the first source electrode 40B and the first drain electrode 40C. The second switch TFT 41 has a second gate electrode 41A connected to the second switch wiring 39, a second source electrode 41B connected to the first source wiring 27α, a second drain electrode 41C connected to the third source wiring 27γ, and a second semiconductor portion 41D connected to the second source electrode 41B and the second drain electrode 41C. The first switch TFT 40 and the second switch TFT 41 have the same configuration as the pixel TFT 24 (see FIG. 5). Specifically, the first gate electrode 40A and the second gate electrode 41A are both made of the same first metal film as the pixel gate electrode 24A. The first source electrode 40B, the first drain electrode 40C, the second source electrode 41B, and the second drain electrode 41C are all made of the same second metal film as the pixel source electrode 24B and the pixel drain electrode 24C. The first semiconductor portion 40D and the second semiconductor portion 41D are both made of the same semiconductor film as the pixel semiconductor portion 24D. The ends of the source lines 27α, 27β, and 27γ on the opposite side to the driver 12 in the Y-axis direction are extended to the non-display area NAA and connected to the switch TFTs 40 and 41, respectively.

[0045] The operation of the first switch circuit 16 will be described. A switch signal is supplied from the control substrate 14, which serves as the signal supply unit SS, to the first switch wiring 38 via the flexible substrate 13. The first switch TFT 40 is then driven by the switch signal being supplied from the first switch wiring 38 to the first gate electrode 40A. At this time, when an image signal is supplied from the driver 12, which serves as the signal supply unit SS, to the connection wiring 37, the image signal is supplied from the first source electrode 40B of the first switch TFT 40 via the first source wiring 27α, the first semiconductor portion 40D, and the first drain electrode 40C to the second source wiring 27β. The image signal supplied to the second source wiring 27β is supplied from the pixel source electrode 24B of the pixel TFT 24 connected to the gate wiring 26, to which the scanning signal is supplied by the gate drive circuit 15, via the pixel semiconductor portion 24D and the pixel drain electrode 24C, to a predetermined pixel electrode 25 (the pixel electrode 25 belonging to the column connected to the second source wiring 27β), and the pixel electrode 25 is charged to a potential based on the image signal.

[0046] A switch signal is supplied from the control substrate 14, which serves as a signal supply unit SS, to the second switch wiring 39 via the flexible substrate 13 at a timing different from that of the first switch wiring 38. The second switch TFT 41 is then driven by the switch signal being supplied from the second switch wiring 39 to the second gate electrode 41A. At this time, when an image signal is supplied from the driver 12, which serves as the signal supply unit SS, to the connection wiring 37, the image signal is supplied from the second source electrode 41B of the second switch TFT 41 via the first source wiring 27α, the second semiconductor portion 41D, and the second drain electrode 41C to the third source wiring 27γ. The image signal supplied to the third source wiring 27γ is supplied from the pixel source electrode 24B of the pixel TFT 24 connected to the gate wiring 26 to which the scanning signal is supplied by the gate drive circuit 15, via the pixel semiconductor portion 24D and the pixel drain electrode 24C, to a predetermined pixel electrode 25 (the pixel electrode 25 belonging to the column connected to the third source wiring 27γ), and the pixel electrode 25 is charged to a potential based on the image signal.

[0047] At a timing when the control substrate 14, which serves as the signal supply unit SS, does not supply a switch signal to either the first switch wiring 38 or the second switch wiring 39, an image signal is supplied from the signal supply unit SS to the connection wiring 37. Then, although the image signal is supplied from the connection wiring 37 to the first source wiring 27α, because neither the first switch TFT 40 nor the second switch TFT 41 is driven, the image signal is not supplied to the second source wiring 27β or the third source wiring 27γ. The image signal supplied to the first source wiring 27α is supplied from the pixel source electrode 24B of the pixel TFT 24 connected to the gate wiring 26 to which the scanning signal is supplied by the gate drive circuit 15 via the pixel semiconductor portion 24D and the pixel drain electrode 24C to a predetermined pixel electrode 25 (the pixel electrode 25 belonging to the column connected to the first source wiring 27α), and the pixel electrode 25 is charged to a potential based on the image signal.

[0048] In this way, by controlling the driving of the first switch TFT 40 and the second switch TFT 41, it is possible to supply image signals to the first source wiring 27α, the second source wiring 27β, and the third source wiring 27γ, respectively. If a switch TFT were connected individually to each of the first source wiring 27α, the second source wiring 27β, and the third source wiring 27γ, three switch TFTs would be required for one unit switch circuit. However, in comparison, only two switch TFTs 40 and 41 are required for one unit switch circuit 16U, and the number of switch TFTs 40 and 41 installed can be reduced. This is advantageous in terms of narrowing the frame of the liquid crystal panel 11 and increasing the size of the first switch TFT 40 and the second switch TFT 41 to improve their performance.

[0049] In this embodiment, the first source wiring 27α connected to the connection wiring 37 is arranged to be sandwiched between the second source wiring 27β and the third source wiring 27γ in the X-axis direction, as shown in FIG. 6 . Because the first source wiring 27α is connected to both the first switch TFT 40 and the second switch TFT 41, the arrangement of the first source wiring 27α sandwiched between the second source wiring 27β and the third source wiring 27γ facilitates routing for connecting the first source wiring 27α to the source electrodes 40B, 41B of the first switch TFT 40 and the second switch TFT 41. This reduces parasitic capacitance that may occur between the first source wiring 27α and other wiring, thereby reducing the load on the first source wiring 27α. Reducing the load on the first source wiring 27α reduces distortion in transmitted image signals, which is advantageous for improving display quality.

[0050] In this embodiment, the driver 12, the first switch TFT 40, and the second switch TFT 41 are arranged on either side of the display area AA in the Y-axis direction on the liquid crystal panel 11, as shown in FIG. 6 . Since the driver 12, the first switch TFT 40, and the second switch TFT 41 are arranged on both sides of the liquid crystal panel 11 in the Y-axis direction, this arrangement is preferable for narrowing the frame of the liquid crystal panel 11 compared to a case in which the first switch TFT 40 and the second switch TFT 41 are arranged on the same side of the liquid crystal panel 11 as the driver 12 in the Y-axis direction. The first source wiring 27α has an end on the driver 12 side in the Y-axis direction connected to the connection wiring 37, and an end on the opposite side from the driver 12 connected to the source electrodes 40B, 41B of the first switch TFT 40 and the second switch TFT 41. The second source wiring 27β has an end on the opposite side from the driver 12 connected to the first drain electrode 40C of the first switch TFT 40. The third source line 27γ has an end opposite to the driver 12 side connected to the second drain electrode 41C of the second switch TFT41.

[0051] 6, the first switch wiring 38 and the second switch wiring 39 are arranged to sandwich the first switch TFT 40 and the second switch TFT 41 between them and the display area AA in the Y-axis direction. Thus, the first switch wiring 38 and the second switch wiring 39 are located on the opposite side of the display area AA in the Y-axis direction from the first switch TFT 40 having the first source electrode 40B connected to the first source wiring 27α and the second switch TFT 41 having the second source electrode 41B connected to the first source wiring 27α. This prevents the first source wiring 27α from intersecting the first switch wiring 38 and the second switch wiring 39. This reduces parasitic capacitance that may occur between the first source wiring 27α and the first switch wiring 38 and the second switch wiring 39, thereby reducing the load on the first source wiring 27α.

[0052] 6, the first switch TFT 40 and the second switch TFT 41 are arranged to sandwich the first source line 27α in the X-axis direction. The first switch TFT 40 is arranged on the left side of the first source line 27α in FIG. 6, i.e., on the second source line 27β side in the X-axis direction. The first switch TFT 40 has its first source electrode 40B located on the right side of the first gate electrode 40A in FIG. 6, i.e., on the first source line 27α side, and its first drain electrode 40C located on the left side of the first gate electrode 40A in FIG. 6, i.e., on the second source line 27β side. The second switch TFT 41 is arranged on the right side of the first source line 27α in FIG. 6, i.e., on the third source line 27γ side in the X-axis direction. 6, i.e., on the side of the first source line 27α, and the second drain electrode 41C is located on the right side of the second gate electrode 41A in FIG. 6, i.e., on the side of the third source line 27γ. In this way, the first source line 27α is sandwiched between the first switch TFT 40 and the second switch TFT 41 in the X-axis direction, so that the first source line 27α can be easily connected to the first source electrode 40B of the first switch TFT 40 and the second source electrode 41B of the second switch TFT 41.

[0053] As shown in FIGS. 4 and 5, the first source wiring 27α includes a lower-layer portion 27A, a first wiring portion 27Aα, and an upper-layer portion 27B, a second wiring portion 27Bα. The first wiring portion 27Aα and the second wiring portion 27Bα overlap each other, with a first interlayer insulating film 34 interposed therebetween. As shown in FIGS. 3 and 5, a first contact hole CHS1, which serves as a source wiring contact hole CHS, is formed in the first interlayer insulating film 34 at a position overlapping both the first wiring portion 27Aα and the second wiring portion 27Bα. The first wiring portion 27Aα and the second wiring portion 27Bα are connected to each other through the first contact hole CHS1. The first wiring portion 27Aα, which is made of the second metal film, is directly connected to the source electrodes 40B and 41B of the switch TFTs 40 and 41, which are made of the second metal film. In this way, the wiring resistance of the first source wiring 27α can be reduced compared to when the first source wiring 27α is composed of only the first wiring configuration portion 27Aα or the second wiring configuration portion 27Bα. This reduces distortion that may occur in the image signal transmitted by the first source wiring 27α. In particular, since the image signal is supplied to the second source wiring 27β and the third source wiring 27γ via the first source wiring 27α, distortion of the image signal transmitted by the second source wiring 27β and the third source wiring 27γ can also be reduced.

[0054] As shown in FIG. 4, the second source wiring 27β includes a third wiring portion 27Aβ in the lower layer 27A, which is made of the second metal film, and a fourth wiring portion 27Bβ in the upper layer 27B, which is made of the third metal film. The third wiring portion 27Aβ and the fourth wiring portion 27Bβ overlap each other, with a first interlayer insulating film 34 interposed therebetween. As shown in FIG. 3, a second contact hole CHS2, which is a source wiring contact hole CHS, is opened in the first interlayer insulating film 34 at a position overlapping both the third wiring portion 27Aβ and the fourth wiring portion 27Bβ. The third wiring portion 27Aβ and the fourth wiring portion 27Bβ are connected to each other through the second contact hole CHS2. The third wiring portion 27Aβ, made of the second metal film, is directly connected to the first drain electrode 40C of the first switch TFT 40, made of the second metal film. In this way, the wiring resistance of the second source wiring 27β can be reduced compared to when the second source wiring 27β is composed of only the third wiring configuration portion 27Aβ or the fourth wiring configuration portion 27Bβ, thereby reducing distortion that may occur in the image signal transmitted by the second source wiring 27β.

[0055] As shown in FIGS. 4 and 5 , the third source wiring 27γ includes a fifth wiring component 27Aγ in the lower layer 27A, which is made of the second metal film, and a sixth wiring component 27Bγ in the upper layer 27B, which is made of the third metal film. The fifth wiring component 27Aγ and the sixth wiring component 27Bγ overlap each other, with the first interlayer insulating film 34 interposed therebetween. As shown in FIGS. 3 and 5 , a third contact hole CHS3, which is a source wiring contact hole CHS, is opened in the first interlayer insulating film 34 at a position overlapping both the fifth wiring component 27Aγ and the sixth wiring component 27Bγ. The fifth wiring component 27Aγ and the sixth wiring component 27Bγ are connected to each other through the third contact hole CHS3. The fifth wiring component 27Aγ, made of the second metal film, is directly connected to the second drain electrode 41C of the second switch TFT 41, made of the second metal film. This reduces the wiring resistance of the third source wiring 27γ compared to when the third source wiring 27γ is composed of only the fifth wiring component 27Aγ or the sixth wiring component 27Bγ, thereby reducing distortion that may occur in the image signal transmitted by the third source wiring 27γ.

[0056] Next, detailed operation of the first switch circuit 16 will be described with reference to FIG. 7. FIG. 7 is a timing chart relating to the operation of the first switch circuit 16. FIG. 7 shows signal waveforms in the gate wiring 26, the first switch wiring 38, and the second switch wiring 39. FIG. 7 also includes a scale for each unit period (one horizontal period) H. Specifically, FIG. 7 shows, from top to bottom, a first scanning signal G(i) transmitted by the ith gate wiring 26 (hereinafter, i is an integer equal to or greater than 1) counting from the top of FIG. 6, a second scanning signal G(i+1) transmitted by the i+1th gate wiring 26 counting from the top of FIG. 6, a first switch signal SW1 transmitted by the first switch wiring 38, and a second switch signal SW2 transmitted by the second switch wiring 39.

[0057] 7, the high-level potential (hereinafter referred to as the high potential) of the first scanning signal G(i), the second scanning signal G(i+1), the first switch signal SW1, and the second switch signal SW2 is "Vgh," which is a potential higher than the threshold voltage of each of the switch TFTs 40 and 41. The low-level potential (hereinafter referred to as the low potential) of the first scanning signal G(i), the second scanning signal G(i+1), the first switch signal SW1, and the second switch signal SW2 is "Vgl," which is a potential lower than the threshold voltage of each of the switch TFTs 40 and 41. The first switch signal SW1 and the second switch signal SW2 are both substantially rectangular waves, and have signal waveforms that periodically repeat one unit period H of high potential Vgh and two consecutive unit periods H of low potential Vgl. The timing at which the first switch signal SW1 falls from high potential Vgh to low potential Vgl and the timing at which the second switch signal SW2 rises from low potential Vgl to high potential Vgh are synchronized so that they coincide with each other. In this way, the control board 14, which is the signal supply unit SS, applies high potential Vgh to the first switch wiring 38 and the second switch wiring 39 at different times.

[0058] As shown in FIG. 7, the first scanning signal G(i) and the second scanning signal G(i+1) have signal waveforms that are at a high potential Vgh during three consecutive unit periods H within one frame display period and at a low potential Vgl during the remaining unit periods H. The first scanning signal G(i) is synchronized so that the timing at which the first scanning signal G(i) falls from a high potential Vgh to a low potential Vgl coincides with the timing at which the second scanning signal G(i+1) rises from a low potential Vgl to a high potential Vgh. The timing at which each scanning signal G(i) and G(i+1) rises from a low potential Vgl to a high potential Vgh coincides with the timing at which the first switch signal SW1 rises from a low potential Vgl to a high potential Vgh. The timing at which each scanning signal G(i) and G(i+1) falls from a high potential Vgh to a low potential Vgl coincides with the timing at which the first switch signal SW1 rises from a low potential Vgl to a high potential Vgh.

[0059] The specific operation of the first switch circuit 16 will be described. As shown in FIG. 7, when the gate drive circuit 15 outputs a high potential Vgh in the first scanning signal G(i) to the ith gate line 26 (time t1), the control substrate 14 outputs a high potential Vgh in the first switch signal SW1 to the first switch line 38. The first switch TFT 40 is driven during the period from time t1 to when the first switch signal SW1 falls from the high potential Vgh to the low potential Vgl (time t2). While the first switch TFT 40 is driven, the image signal supplied from the driver 12 to the connection line 37 is supplied to the second source line 27β via the first source line 27α. Therefore, the pixel TFT 24 connected to the ith gate line 26 and the second source line 27β is driven, and the pixel electrode 25 connected to that pixel TFT 24 is charged to a potential based on the image signal supplied to the second source line 27β. In addition, the pixel TFT 24 connected to the i-th gate line 26 and the first source line 27α is also driven, and the pixel electrode 25 connected to that pixel TFT 24 is charged to a potential based on the image signal supplied to the first source line 27α.

[0060] At time t2, the first scanning signal G(i) is maintained at high potential Vgh, and the control substrate 14 outputs high potential Vgh in the second switch signal SW2 to the second switch wiring 39. The second switch TFT 41 is driven from time t2 until the second switch signal SW2 falls from high potential Vgh to low potential Vgl (time t3). While the second switch TFT 41 is driven, the image signal supplied from the driver 12 to the connection wiring 37 is supplied to the third source wiring 27γ via the first source wiring 27α. Therefore, the pixel TFT 24 connected to the i-th gate wiring 26 and the third source wiring 27γ is driven, and the pixel electrode 25 connected to that pixel TFT 24 is charged to a potential based on the image signal supplied to the third source wiring 27γ. In addition, the pixel TFT 24 connected to the i-th gate line 26 and the first source line 27α is also driven, and the pixel electrode 25 connected to that pixel TFT 24 is charged to a potential based on the image signal supplied to the first source line 27α.

[0061] During the period from time t3 until the first scanning signal G(i) falls from high potential Vgh to low potential Vgl (time t4), the first scanning signal G(i) is maintained at high potential Vgh, while the switch signals SW1 and SW2 are maintained at low potential Vgl, and neither switch TFT 40 nor 41 is driven. Therefore, during this period, the image signal supplied from the driver 12 to the connection wiring 37 is selectively supplied to the first source wiring 27α, and is not supplied to the second source wiring 27β or the third source wiring 27γ. Therefore, the pixel TFT 24 connected to the i-th gate wiring 26 and the first source wiring 27α is selectively driven, and the pixel electrode 25 connected to that pixel TFT 24 is charged to a potential based on the image signal selectively supplied to the first source wiring 27α.

[0062] As described above, the pixel TFT 24 connected to the i-th gate line 26 and the first source line 27α is turned on during the period when the first scanning signal G(i) is maintained at the high potential Vgh (the period from time t1 to time t4). Therefore, the pixel electrode 25 connected to this pixel TFT 24 maintains a potential based on the image signal supplied to the second source line 27β during the period from time t1 to time t2, a potential based on the image signal supplied to the third source line 27γ during the period from time t2 to time t3, and a potential based on the image signal supplied only to the first source line 27α during the period from time t3 to time t4. This ensures that the display gradation of the pixel including the pixel electrode 25 to which the image signal is supplied via the first source line 27α is appropriate, resulting in a satisfactory display. Note that even when the gate drive circuit 15 outputs the high potential Vgh of the second scanning signal G(i+1) to the (i+1)-th gate line 26, the image signal is distributed to each of the source lines 27α to 27γ in the same manner as described above.

[0063] As described above, the liquid crystal display device (display device) 10 of this embodiment includes the display area AA where an image is displayed, the non-display area NAA where an image is not displayed, the first source wiring (first wiring) 27α arranged in the display area AA, the second source wiring (second wiring) 27β arranged in the display area AA, the third source wiring (third wiring) 27γ arranged in the display area AA, the connection wiring 37 arranged in the non-display area NAA and connected to the first source wiring 27α, the first switch wiring 38 arranged in the non-display area NAA, the first switch TFT (first switching element) 40 arranged in the non-display area NAA and having the first gate electrode 40A arranged in the non-display area NAA and connected to the first switch wiring 38, the first source electrode 40B connected to the first source wiring 27α, and the first drain electrode 40C connected to the second source wiring 27β. the signal supply unit SS is arranged in the non-display area NAA and connected to the connecting wiring 37, the first switch wiring 38, and the second switch wiring 39; the signal supply unit SS supplies an image signal to the connecting wiring 37, and supplies switch signals having voltages higher than the threshold voltages of the first switch TFT 40 and the second switch TFT 41 to the first switch wiring 38 and the second switch wiring 39 at different times; and the first source wiring 27α is arranged between the second source wiring 27β and the third source wiring 27γ.

[0064] When a switch signal is supplied from the signal supply unit SS to the first switch wiring 38, the first switch TFT 40, whose first gate electrode 40A is connected to the first switch wiring 38, is driven. At this time, when an image signal is supplied from the signal supply unit SS to the connection wiring 37, the image signal is supplied from the first source electrode 40B of the first switch TFT 40 to the first drain electrode 40C of the first switch TFT 40 via the first source wiring 27α and to the second source wiring 27β. When a switch signal is supplied from the signal supply unit SS to the second switch wiring 39, the second switch TFT 41, whose second gate electrode 41A is connected to the second switch wiring 39, is driven. At this time, when an image signal is supplied from the signal supply unit SS to the connection wiring 37, the image signal is supplied from the second source electrode 41B of the second switch TFT 41 to the third source wiring 27γ via the first source wiring 27α and the second drain electrode 41C of the second switch TFT 41. When an image signal is supplied from the signal supply unit SS to the connection line 37 at a timing when the signal supply unit SS does not supply a switch signal to either the first switch line 38 or the second switch line 39, the image signal is supplied from the connection line 37 to the first source line 27α. In this manner, by controlling the driving of the first switch TFT 40 and the second switch TFT 41, the image signal can be supplied to the first source line 27α, the second source line 27β, and the third source line 27γ, respectively. Compared to a case where a switch TFT is individually connected to each of the first source line 27α, the second source line 27β, and the third source line 27γ, the number of switch TFTs 40 and 41 can be reduced. This is advantageous for narrowing the frame and increasing the size of the first switch TFT 40 and the second switch TFT 41 to improve their performance.

[0065] Furthermore, the first source wiring 27α connected to the connection wiring 37 is disposed between the second source wiring 27β and the third source wiring 27γ, which facilitates routing of the first source wiring 27α to connect it to the first switch TFT 40 and the second switch TFT 41. This reduces parasitic capacitance that may occur between the first source wiring 27α and other wiring, thereby reducing the load on the first source wiring 27α. Reducing the load on the first source wiring 27α reduces the risk of distortion in the transmitted image signal, which is advantageous for improving display quality.

[0066] The liquid crystal panel 11 also includes a liquid crystal panel (display panel) 11 having a main surface 11S including a display area AA and a non-display area NAA. The liquid crystal panel 11 is provided with a first source wiring 27α, a second source wiring 27β, a third source wiring 27γ, a connection wiring 37, a first switch wiring 38, a second switch wiring 39, a first switch TFT 40, and a second switch TFT 41. The signal supply unit SS includes at least a driver (first signal supply unit) 12 that is provided in the liquid crystal panel 11 and connected to the connection wiring 37 and supplies an image signal to the connection wiring 37. The first source wiring 27α, the second source wiring 27β, and the third source wiring 27γ all extend along a first direction. The driver 12, the first switch TFT 40, and the second switch TFT 41 are arranged on either side of the display area AA in the first direction on the liquid crystal panel 11. The first source wiring 27α is connected to a first source electrode 40B and a second source electrode 41B. The image signal supplied from the driver 12 to the connection wiring 37 is supplied via the first source wiring 27α to the first source electrode 40B of the first switch TFT 40 and the second source electrode 41B of the second switch TFT 41. In this way, the driver 12 and the first switch TFT 40 and the second switch TFT 41 are distributed and arranged on both sides of the liquid crystal panel 11 in the first direction, which is preferable in terms of narrowing the frame of the liquid crystal panel 11 compared to a case where the first switch TFT 40 and the second switch TFT 41 are arranged on the same side of the liquid crystal panel 11 as the driver 12 in the first direction.

[0067] The first switch wiring 38 and the second switch wiring 39 are arranged to sandwich the first switch TFT 40 and the second switch TFT 41 between them and the display area AA in the first direction. The first switch wiring 38 and the second switch wiring 39 are located on the opposite side of the display area AA in the first direction from the first switch TFT 40 having the first source electrode 40B connected to the first source wiring 27α and the second switch TFT 41 having the second source electrode 41B connected to the first source wiring 27α. This prevents the first source wiring 27α from crossing the first switch wiring 38 and the second switch wiring 39. This reduces parasitic capacitance that may occur between the first source wiring 27α and the first switch wiring 38 and the second switch wiring 39, thereby reducing the load on the first source wiring 27α.

[0068] Furthermore, the first switch TFT40 and the second switch TFT41 are arranged to sandwich the first source line 27α in a second direction intersecting the first direction. Because the first source line 27α is sandwiched between the first switch TFT40 and the second switch TFT41 in the second direction, the first source line 27α can be easily connected to the first switch TFT40 and the second switch TFT41.

[0069] The first source wiring 27α is composed of a first wiring portion 27Aα made of a second metal film (first conductive film) and a second wiring portion 27Bα made of a third metal film (second conductive film) disposed above the second metal film via a first interlayer insulating film (first insulating film) 34, and overlapping with the first wiring portion 27Aα. The first wiring portion 27Aα and the second wiring portion 27Bα are connected through a first contact hole CHS1 formed in the first interlayer insulating film 34. This reduces the wiring resistance of the first source wiring 27α compared to when the first source wiring 27α is composed of only the first wiring portion 27Aα or the second wiring portion 27Bα. This reduces distortion that may occur in an image signal transmitted by the first source wiring 27α. In particular, since image signals are supplied to the second source wiring 27β and the third source wiring 27γ via the first source wiring 27α, distortion of the image signals transmitted by the second source wiring 27β and the third source wiring 27γ can also be reduced.

[0070] The second source wiring 27β is composed of a third wiring configuration portion 27Aβ consisting of a portion of the second metal film different from the first wiring configuration portion 27Aα, and a fourth wiring configuration portion 27Bβ consisting of a portion of the third metal film different from the second wiring configuration portion 27Bα and overlapping with the third wiring configuration portion 27Aβ. The third source wiring 27γ is composed of a fifth wiring configuration portion 27Aγ consisting of a portion of the second metal film different from the first wiring configuration portion 27Aα and the third wiring configuration portion 27Aβ, and a fourth wiring configuration portion 27Bβ consisting of a portion of the third metal film different from the second wiring configuration portion 27Bα and overlapping with the third wiring configuration portion 27Aβ. The second source wiring 27β is composed of a sixth wiring component 27Bγ that overlaps with the fifth wiring component 27Aγ and is composed of a portion different from the second wiring component 27Bα and the fourth wiring component 27Bβ. The third wiring component 27Aβ and the fourth wiring component 27Bβ are connected through a second contact hole CHS2 formed in the first interlayer insulating film 34, and the fifth wiring component 27Aγ and the sixth wiring component 27Bγ are connected through a third contact hole CHS3 formed in the first interlayer insulating film 34. This reduces the wiring resistance of the second source wiring 27β compared to when the second source wiring 27β is composed only of the third wiring component 27Aβ or the fourth wiring component 27Bβ. This reduces distortion that may occur in the image signal transmitted by the second source wiring 27β. Furthermore, compared to the case where the third source wiring 27γ is composed of only the fifth wiring component 27Aγ or the sixth wiring component 27Bγ, the wiring resistance of the third source wiring 27γ can be reduced, thereby reducing distortion that may occur in the image signal transmitted by the third source wiring 27γ.

[0071] Furthermore, the signal supply unit SS supplies an image signal to the connection wiring 37 and a switch signal to the first switch wiring 38, supplies an image signal to the connection wiring 37 and a switch signal to the second switch wiring 39, and then supplies the image signal to the connection wiring 37 without supplying a switch signal to either the first switch wiring 38 or the second switch wiring 39. When the signal supply unit SS supplies the image signal to the connection wiring 37 and the switch signal to the first switch wiring 38, the first switch TFT 40 is driven and the image signal is supplied to the second source wiring 27β. At this time, the image signal is also supplied to the first source wiring 27α. When the signal supply unit SS supplies the image signal to the connection wiring 37 and the switch signal to the second switch wiring 39, the second switch TFT 41 is driven and the image signal is supplied to the third source wiring 27γ. At this time, the image signal is also supplied to the first source wiring 27α. Thereafter, the signal supply unit SS supplies an image signal to the connection wiring 37 without supplying a switch signal to either the first switch wiring 38 or the second switch wiring 39, and therefore the image signal is supplied to the first source wiring 27α without being supplied to the second source wiring 27β and the third source wiring 27γ. In this way, even if the image signals supplied to the second source wiring 27β and the third source wiring 27γ are supplied to the first source wiring 27α, the image signal to be subsequently supplied to the first source wiring 27α can be supplied only to the first source wiring 27α, thereby obtaining a good display.

[0072] The display device also includes a liquid crystal panel 11 provided with first source wiring 27α, second source wiring 27β, third source wiring 27γ, connection wiring 37, first switch wiring 38, second switch wiring 39, first switch TFT 40, and second switch TFT 41, and a flexible substrate 13 connected to the liquid crystal panel 11. The signal supply unit SS includes a driver 12 provided in the liquid crystal panel 11 and a control substrate (second signal supply unit) 14 connected to the flexible substrate 13. The driver 12 supplies an image signal to the connection wiring 37, and the control substrate 14 supplies switch signals at different times to the first switch wiring 38 and the second switch wiring 39 via the flexible substrate 13. In this way, the driver 12 supplies an image signal to the connection wiring 37, and the control substrate 14 supplies switch signals at different times to the first switch wiring 38 and the second switch wiring 39 via the flexible substrate 13. Compared to the case where the driver 12 supplies both the image signal and the switch signal, the driver 12 is required to have fewer functions, which makes it possible to miniaturize the driver 12. If the driver 12 provided in the non-display area NAA of the liquid crystal panel 11 is miniaturized, it is preferable for achieving a narrower frame of the liquid crystal panel 11.

[0073] <Embodiment 2> A second embodiment will be described with reference to Fig. 8 or 9. In this second embodiment, the outer shape of the liquid crystal panel 111 and the configuration of the first switch circuit 116 are changed. Note that a redundant description of the structure, action, and effects similar to those of the first embodiment will be omitted.

[0074] As shown in FIG. 8 , the liquid crystal panel 111 according to this embodiment has a non-rectangular shape in a plan view, specifically, a horizontally elongated, approximately oval shape. In FIG. 8 , the areas where the main portions of the gate drive circuit 115 and the first switch circuit 116 are formed are shown with different hatching patterns. The outer peripheral edge of the liquid crystal panel 111 includes two linear portions 111L that are approximately linear along the X-axis direction in a plan view, and two arc-shaped portions (curved portions) 111R that are approximately arc-shaped (curved) in a plan view. Of the non-display area NAA of the array substrate 121, the side on which the driver 112 is mounted and the side opposite thereto in the Y-axis direction each include the linear portion 111L. Of the non-display area NAA of the array substrate 121, the two sides including the two gate drive circuits 115 each include the arc-shaped portion 111R. The display area AA has a shape similar to the outline of the liquid crystal panel 111 in a plan view. The display area AA includes a first area AA1 having an approximately arc-shaped outline following the arc-shaped portion 111R described above, and a second area AA2 having an approximately linear outline following the linear portion 111L described above. The display area AA includes two first areas AA1, one on either side of the second area AA2 in the X-axis direction. The outer dimensions of the first area AA1 in the X-axis direction vary depending on the position in the Y-axis direction. Specifically, the outer dimensions of the first area AA1 in the X-axis direction are smallest at both ends of the first area AA1 in the Y-axis direction and largest at the center in the Y-axis direction. In other words, the first area AA1 has an approximately arch-shaped outline in a plan view. The second area AA2 is disposed in the center of the display area AA in the X-axis direction. The second region AA2 is positioned adjacent to and spaced apart from the driver 112 in the Y-axis direction. The second region AA2 has constant outer dimensions in the X-axis direction depending on its position in the Y-axis direction. That is, the second region AA2 has a substantially rectangular shape in a plan view.

[0075] As shown in FIG. 8, the gate drive circuit 115 has a strip shape that extends in a substantially arc-like (curved) shape following the arc-shaped portion 111R of the outer peripheral edge of the liquid crystal panel 111. The gate drive circuit 115 is disposed between the arc-shaped portion 111R and the first area AA1 of the display area AA. The central portion of the first switch circuit 116 in the X-axis direction has a strip shape that extends linearly following the linear portion 111L of the outer peripheral edge of the liquid crystal panel 111. The first switch circuit 116 has both end portions in the X-axis direction that have a strip shape that extends in a substantially arc-like (curved) shape following the arc-shaped portion 111R of the outer peripheral edge of the liquid crystal panel 111, and is adjacent to the end portions of the gate drive circuit 115 in the length direction. Note that in FIG. 8, adjacent portions of the gate drive circuit 115 and the first switch circuit 116 are shown with different overlapping hatches.

[0076] In this embodiment, as shown in FIGS. 8 and 9 , the first switch circuits 116 are arranged in pairs on either side of the display area AA in the Y-axis direction. That is, one first switch circuit 116 is arranged on the driver 112 side of the display area AA in the Y-axis direction, and the other first switch circuit 116 is arranged on the opposite side of the display area AA from the driver 112 side in the Y-axis direction. Each of the source lines 127α to 127γ arranged in a first area AA1 of the display area AA is connected to both one first switch circuit 116 and the other first switch circuit 116. Similarly, each of the source lines 127α to 127γ arranged in a second area AA2 is connected to both one first switch circuit 116 and the other first switch circuit 116. Each of the switch lines 138 and 139 includes a portion extending along the X-axis direction to cross one first switch circuit 116 and a portion extending along the X-axis direction to cross the other first switch circuit 116. In FIG. 9, the configuration of the first area AA1 of the display area AA is shown on the left side, and the configuration of the second area AA2 is shown on the right side.

[0077] As shown in FIG. 9 , one of the first switch TFTs 140 and the second switch TFT 141 constituting one unit switch circuit 116U receives an image signal from a connection wiring 137. That is, the connection wiring 137 is connected to a first source electrode 140B and a second source electrode 141B of one of the first switch TFTs 140 and the second switch TFT 141, which are arranged on the same side as the driver 112 in the Y-axis direction with respect to the display area AA. A first drain electrode 140C of one of the first switch TFTs 140 is connected to an end of the second source wiring 127β that is closer to the driver 112 in the Y-axis direction. A second drain electrode 141C of one of the second switch TFTs 141 is connected to an end of the third source wiring 127γ that is closer to the driver 112 in the Y-axis direction. A first gate electrode 140A of one of the first switch TFTs 140 is connected to a portion of the first switch wiring 138 that is arranged on the driver 112 side with respect to the display area AA in the Y-axis direction. One second gate electrode 141A of the second switch TFT 141 is connected to a portion of the second switch wiring 139 that is disposed on the driver 112 side with respect to the display area AA in the Y-axis direction.

[0078] 9, the other first switch TFT 140 and second switch TFT 141 constituting the other unit switch circuit 116U are supplied with image signals from a first source wiring 127. That is, the first source wiring 127 is connected to a first source electrode 140B and a second source electrode 141B provided in the other first switch TFT 140 and second switch TFT 141 arranged on the opposite side of the display area AA from the driver 112 in the Y-axis direction. A first drain electrode 140C of the other first switch TFT 140 is connected to an end of the second source wiring 127β on the opposite side of the driver 112 in the Y-axis direction. A second drain electrode 141C of the other second switch TFT 141 is connected to an end of the third source wiring 127γ on the opposite side of the driver 112 in the Y-axis direction. The first gate electrode 140A of the other first switch TFT 140 is connected to a portion of the first switch wiring 138 that is located on the opposite side of the display area AA from the driver 112 in the Y-axis direction. The second gate electrode 141A of the other second switch TFT 141 is connected to a portion of the second switch wiring 139 that is located on the opposite side of the display area AA from the driver 112 in the Y-axis direction.

[0079] The image signal supplied from the driver 112 to the connection wiring 137 is directly supplied from the connection wiring 137 to the first source electrode 140B and the second source electrode 141B of one of the first switch TFT 140 and the second switch TFT 141. The image signal supplied from the driver 112 to the connection wiring 137 is supplied to the first source electrode 140B and the second source electrode 141B of the other of the first switch TFT 140 and the second switch TFT 141 via the first source wiring 127α. The one first switch TFT 140 and the other first switch TFT 140 are driven at the same timing based on the first switch signal SW1 (see FIG. 7 ) supplied to the first switch wiring 138, so that the same image signal is supplied to the second source wiring 127β from the end on the driver 112 side and the end on the opposite side in the Y-axis direction. Because the one second switch TFT 141 and the other second switch TFT 141 are driven at the same timing based on the second switch signal SW2 (see FIG. 7) supplied to the second switch line 139, the same image signal is supplied to the third source line 127γ from the end on the driver 112 side and the opposite end in the Y-axis direction. The image signals supplied to the source lines 127β, 127γ via the one first switch TFT 140 and the second switch TFT 141 are less likely to be dulled than the image signals supplied to the source lines 127β, 127γ via the other first switch TFT 140 and the second switch TFT 141 because they do not pass through the first source line 127α. Therefore, image signals with less dullness can be supplied to the source lines 127β, 127γ, improving display quality.

[0080] As described above, in this embodiment, the first switch TFT 140 and the second switch TFT 141 are arranged in pairs on either side of the display area AA in the Y-axis direction. This allows each of the first switch TFTs 140 and the second switch TFTs 141 to be made smaller than when the first switch TFT 140 and the second switch TFT 141 are arranged on only one side of the display area AA in the Y-axis direction, as in the first embodiment described above. This reduces the space required for arranging each of the first switch TFTs 140 and the second switch TFTs 141, which is suitable for narrowing the frame of the liquid crystal panel 111. In particular, in a configuration in which the display area AA includes the first area AA1 and the gate drive circuit 115 and the first switch circuit 116 have adjacent portions, as in this embodiment, it is difficult to secure space for arranging both circuits 115 and 116. In this regard, if the arrangement space for each first switch TFT 140 and each second switch TFT 141 is reduced as described above, it becomes less likely that the frame will become thick in the area where the gate drive circuit 115 and the first switch circuit 116 are adjacent to each other, which is effective in narrowing the frame.

[0081] As described above, according to this embodiment, a liquid crystal panel 111 having a main surface 111S including a display area AA and a non-display area NAA is provided, and the liquid crystal panel 111 is provided with a first source wiring 127α, a second source wiring 127β, a third source wiring 127γ, a connection wiring 137, a first switch wiring 138, a second switch wiring 139, a first switch TFT 140, and a second switch TFT 141, and the signal supply unit SS includes at least a driver 112 that is provided in the liquid crystal panel 111 and connected to the connection wiring 137 and supplies an image signal to the connection wiring 137, and the first source wiring 127α, the second source wiring 127β, and the third source wiring 127γ all extend along the first direction, and the first switch TFT 140 and the second switch TFT 141 are provided on the liquid crystal panel 111. In the liquid crystal panel 111, the driver 112 is arranged on the side of the first switch TFT 140 and the second switch TFT 141 with respect to the display area AA in the first direction, the connection wiring 137 is connected to the first source electrode 140B and the second source electrode 141B of the first switch TFT 140 and the second switch TFT 141 arranged on the same side as the driver 112 with respect to the display area AA in the first direction, and the first source wiring 127α is connected to the first source electrode 140B and the second source electrode 141B of the other first switch TFT 140 and the second switch TFT 141 arranged on the opposite side of the driver 112 with respect to the display area AA in the first direction. The image signal supplied from the driver 112 to the connection wiring 137 is supplied to the first source electrode 140B and the second source electrode 141B provided in one of the first switch TFT 140 and the second switch TFT 141 arranged on the same side as the driver 112 with respect to the display area AA in the first direction. The image signal supplied from the driver 112 to the connection wiring 137 is supplied via the first source wiring 127α to the first source electrode 140B and the second source electrode 141B provided in the other of the first switch TFT 140 and the second switch TFT 141 arranged on the opposite side of the driver 112 with respect to the display area AA in the first direction.In this way, the first switch TFT 140 and the second switch TFT 141 are arranged in pairs to sandwich the display area AA in the first direction, which makes it possible to reduce the size of each of the first switch TFTs 140 and second switch TFTs 141 compared to a case in which the first switch TFTs 140 and the second switch TFTs 141 are arranged on only one side of the display area AA in the first direction. This reduces the arrangement space for each of the first switch TFTs 140 and each of the second switch TFTs 141, which is suitable for narrowing the frame of the liquid crystal panel 111.

[0082] <Embodiment 3> A third embodiment will be described with reference to Fig. 10. In this third embodiment, the configuration of the first switch circuit 216 is changed from that of the second embodiment. Note that redundant descriptions of the structure, operation, and effects similar to those of the second embodiment will be omitted.

[0083] 10, the first switch circuit 216 according to this embodiment includes a unit switch circuit 216U (hereinafter referred to as a first unit switch circuit 216Uα) arranged on the opposite side of the driver 212 in the Y-axis direction with respect to a first region AA1 of the display region AA, and a unit switch circuit 216U (hereinafter referred to as a second unit switch circuit 216Uβ) arranged on the same side of the driver 212 in the Y-axis direction with respect to a second region AA2. That is, in this embodiment, the unit switch circuit 216U is not arranged on the driver 212 side with respect to the Y-axis direction with respect to the first region AA1, and the unit switch circuit 216U is not arranged on the opposite side of the driver 212 side with respect to the Y-axis direction with respect to the second region AA2.

[0084] In the following, of the multiple connection wirings 237, the connection wiring 237 connected to the first source wiring 227α arranged in the first area AA1 of the display area AA will be referred to as the ``first connection wiring 237α,'' and the connection wiring 237 connected to the first source wiring 227α arranged in the second area AA2 will be referred to as the ``second connection wiring 237β.''

[0085] The first switch TFT240 and the second switch TFT241 constituting the first unit switch circuit 216Uα have a first source electrode 240B and a second source electrode 241B respectively connected to the first source wiring 227α which is connected to the first connection wiring 237α. Therefore, an image signal supplied from the driver 212 to the first connection wiring 237α is supplied to the first source wiring 227α arranged in the first area AA1, and is also supplied to the first source electrode 240B and the second source electrode 241B of the first switch TFT240 and the second switch TFT241, respectively, via the first source wiring 227α arranged in the first area AA1.

[0086] The first switch TFT240 and the second switch TFT241 constituting the second unit switch circuit 216Uβ have a first source electrode 240B and a second source electrode 241B, respectively, connected to the second connection wiring 237β. Therefore, the image signal supplied from the driver 212 to the second connection wiring 237β is supplied to the first source electrode 240B and the second source electrode 241B of the first switch TFT240 and the second switch TFT241, respectively, and is also supplied to the first source wiring 227α arranged in the second area AA2.

[0087] Here, in the non-display area NAA of the liquid crystal panel 211, it is difficult to secure space for arranging wiring and the like in a portion adjacent to the first area AA1 (more specifically, the portion sandwiched between the substantially arc-shaped outer portion of the first area AA1 and the arc-shaped portion 111R (see FIG. 8)). In particular, in a configuration in which the display area AA has the first area AA1 and the gate drive circuit 115 and the first switch circuit 216 have portions adjacent to each other, it is difficult to secure space for arranging both circuits 115, 216 (see FIG. 8). In this regard, in this embodiment, the driver 212 and the first unit switch circuit 216Uα are arranged in a dispersed manner on the liquid crystal panel 211 so as to sandwich the first area AA1 in the Y-axis direction. Therefore, compared to the case where the first unit switch circuit 216Uα is arranged on the same side of the liquid crystal panel 211 as the driver 212 in the Y-axis direction, it is possible to narrow the frame of that part of the non-display area NAA of the liquid crystal panel 211 adjacent to the first area AA1 while ensuring space for arranging wiring etc. (including the gate drive circuit 15).

[0088] As described above, according to this embodiment, the liquid crystal panel 211 has a main surface 11S including a display area AA and a non-display area NAA, and a first switch circuit 216 including a plurality of unit switch circuits 216U each composed of a first switch TFT 240 and a second switch TFT 241, and including a first switch wiring 238 and a second switch wiring 239. The liquid crystal panel 211 is provided with a first source wiring 227α, a second source wiring 227β, a third source wiring 227γ, a connection wiring 237, and the first switch circuit 216. The signal supply unit SS is provided with a first switch wiring 227α, a second source wiring 227β, a third source wiring 227γ, a connection wiring 237, and the first switch circuit 216. 211, and includes at least a driver 212 that is connected to the connection wiring 237 and supplies an image signal to the connection wiring 237, the first source wiring 227α, the second source wiring 227β, and the third source wiring 227γ all extend along a first direction, the display area AA includes a first area AA1 whose outer dimensions in a second direction intersecting with the first direction change depending on the position in the first direction, and a second area AA2 whose outer dimensions in the second direction are constant depending on the position in the first direction, and the first source wiring 227α, the second source wiring 227β, and The three source wirings 227γ are respectively arranged in the first area AA1 and the second area AA2, the connection wiring 237 includes a first connection wiring 237α connected to the first source wiring 227α arranged in the first area AA1 and a second connection wiring 237β connected to the first source wiring 227α arranged in the second area AA2, the driver 212 is arranged on one side of the display area AA in the first direction in the liquid crystal panel 211, and the plurality of unit switch circuits 216U includes a first source electrode 237β connected to the first source wiring 227α connected to the first connection wiring 237α. a first unit switch circuit 216Uα including a first switch TFT240 and a second switch TFT241 having a first source electrode 240B and a second source electrode 241B connected to a second connection wiring 237β, respectively; and a second unit switch circuit 216Uβ including a first switch TFT240 and a second switch TFT241 having a first source electrode 240B and a second source electrode 241B connected to a second connection wiring 237β, the first unit switch circuit 216Uα is disposed on the opposite side of the liquid crystal panel 211 from the driver 212 in the first direction, and the second unit switch circuit 216Uβ isThe first unit switch circuit 216Uα is located on the same side of the liquid crystal panel 211 as the driver 212 in the first direction. In this way, the first unit switch circuit 216Uα is located on the opposite side of the liquid crystal panel 211 from the driver 212 in the first direction, and the first source wiring 227α located in the first area AA1 is connected to the first source electrode 240B and the second source electrode 241B of the first switch TFT 240 and the second switch TFT 241, respectively. Therefore, the image signal supplied from the driver 212 to the first connection wiring 237α is supplied to the first source electrode 240B and the second source electrode 241B of the first switch TFT 240 and the second switch TFT 241 constituting the first unit switch circuit 216Uα, respectively, via the first source wiring 227α located in the first area AA1. On the other hand, the second unit switch circuit 216Uβ is arranged on the same side of the liquid crystal panel 211 as the driver 212 in the first direction, and a second connection wiring 237β is connected to the first source electrode 240B and the second source electrode 241B of the first switch TFT 240 and the second switch TFT 241, respectively. Therefore, the image signal supplied from the driver 212 to the second connection wiring 237β is supplied to the first source wiring 227α arranged in the second area AA2, and is also supplied to the first source electrode 240B and the second source electrode 241B of the first switch TFT 240 and the second switch TFT 241, respectively, which constitute the second unit switch circuit 216Uβ. Here, it is difficult to secure space for arranging wiring and the like in the portion of the non-display area NAA of the liquid crystal panel 211 adjacent to the first area AA1. In this regard, since the driver 212 and the first unit switch circuit 216Uα are disposed in a dispersed manner on either side of the first area AA1 in the first direction on the liquid crystal panel 211, it is possible to narrow the frame of that portion while ensuring space for arranging wiring and the like in the portion of the non-display area NAA of the liquid crystal panel 211 adjacent to the first area AA1, compared to the case where the first unit switch circuit 216Uα is disposed on the same side of the liquid crystal panel 211 as the driver 212 in the first direction.

[0089] <Embodiment 4> A fourth embodiment will be described with reference to Fig. 11 or 12. In this fourth embodiment, the configuration of the first switch circuit 316 is changed from that of the second embodiment, and a second switch circuit 42 and the like are added. Note that a redundant description of the structure, operation, and effects similar to those of the second embodiment will be omitted.

[0090] 11 , the first switch circuit 316 according to this embodiment includes a unit switch circuit 316U arranged on the same side of the display area AA1 as the driver 312 in the Y-axis direction. The first switch TFT 340 and the second switch TFT 341 constituting the unit switch circuit 316U each have a first source electrode 340B and a second source electrode 341B connected to a connection wiring 337. Therefore, an image signal supplied from the driver 312 to the connection wiring 337 is supplied to the first source electrode 340B and the second source electrode 341B of the first switch TFT 340 and the second switch TFT 341, respectively, and is also supplied to a first source wiring 327α arranged in the first area AA1. The number of connection wirings 337 is set to about one-third the number of source wirings 327 arranged in the first area AA1.

[0091] 11 , the liquid crystal panel 311 according to this embodiment is provided with a second switch circuit 42 arranged on the same side of the second area AA2 as the driver 312 in the Y-axis direction, and distribution wiring 43 connected to the second switch circuit 42 and the driver 312. The distribution wiring 43 is arranged on one of the four sides of the frame-shaped non-display area NAA of the liquid crystal panel 311, on the side closest to the driver 312, and is routed from the mounting area of ​​the driver 312 to the second switch circuit 42. An image signal is supplied to the distribution wiring 43 from the driver 312, which serves as the signal supply unit SS. The number of distribution wirings 43 installed is approximately one-third the number of source wirings 327 installed in the second area AA2.

[0092] 11, the second switch circuit 42 is arranged on one of the four sides of the frame-shaped non-display area NAA of the liquid crystal panel 311, on the same side as the driver 312. The second switch circuit 42 is provided in a horizontally long band-shaped range extending along the X-axis direction, and its range is approximately the same as the formation range in the X-axis direction of the second area AA2. Like the first switch circuit 316, the second switch circuit 42 has a switch function that distributes the image signals supplied from the driver 312 to the source lines 327, and is a so-called SSD circuit.

[0093] 11, the second switch circuit 42 has a plurality of unit switch circuits 42U and a plurality of switch wirings 44, 338, and 339. The plurality of unit switch circuits 42U are arranged side by side along the extension direction (X-axis direction) of the second switch circuit 42. The number of unit switch circuits 42U is the same as the number of distribution wirings 43, and is approximately one-third of the number of source wirings 327 arranged in the second area AA2. The plurality of switch wirings 44, 338, and 339 constituting the second switch circuit 42 include a third switch wiring 44 in addition to the first switch wiring 338 and second switch wiring 339 described in the first embodiment. That is, the first switch wiring 338 and second switch wiring 339 are shared by the first switch circuit 316 and the second switch circuit 42. Here, the third switch wiring 44 will be described. The third switch wiring 44 extends along the X-axis direction within the range in which the plurality of unit switch circuits 42U are arranged. The third switch wiring 44 is drawn out to outside the area in which the plurality of unit switch circuits 42U are arranged in the non-display area NAA, and is connected to the flexible substrate 13 (see FIG. 1). A switch signal is supplied to the third switch wiring 44 from the control substrate 14, which is a signal supply unit SS, via the flexible substrate 313 (see FIG. 1). The control substrate 14 outputs the switch signal to the third switch wiring 44 at a timing different from that of the switch signals to the first switch wiring 338 and the second switch wiring 339. This switch signal has a voltage higher than the threshold voltages of the first switch TFT 340 and the second switch TFT 341, and the threshold voltages of the third switch TFT 45, the fourth switch TFT 46, and the fifth switch TFT 47, which will be described later.

[0094] As shown in FIG. 11, the unit switch circuit 42U has a third switch TFT (third switching element) 45 connected to the first switch wiring 338, a predetermined source wiring 327 (fourth source wiring 327δ) arranged in the second area AA2, and the distribution wiring 43, a fourth switch TFT (fourth switching element) 46 connected to the second switch wiring 339, a predetermined source wiring 327 (fifth source wiring 327ε) arranged in the second area AA2, and the distribution wiring 43, and a fifth switch TFT (fifth switching element) 47 connected to the third switch wiring 44, a predetermined source wiring 327 (sixth source wiring 327ζ) arranged in the second area AA2, and the distribution wiring 43. In the following, of the multiple source wirings 327 arranged in the second area AA2, the source wiring 327 connected to the third switch TFT 45 will be referred to as the "fourth source wiring (fourth wiring) 327δ", the source wiring 327 connected to the fourth switch TFT 46 will be referred to as the "fifth source wiring (fifth wiring) 327ε", and the source wiring 327 connected to the fifth switch TFT 47 will be referred to as the "sixth source wiring (sixth wiring) 327ζ".

[0095] 11, the third switch TFT 45 has a third gate electrode 45A connected to the first switch wiring 338, a third source electrode 45B connected to the distribution wiring 43, a third drain electrode 45C connected to the fourth source wiring 327δ, and a third semiconductor portion 45D connected to the third source electrode 45B and the third drain electrode 45C. The fourth switch TFT 46 has a fourth gate electrode 46A connected to the second switch wiring 339, a fourth source electrode 46B connected to the distribution wiring 43, a fourth drain electrode 46C connected to the fifth source wiring 327ε, and a fourth semiconductor portion 46D connected to the fourth source electrode 46B and the fourth drain electrode 46C. The fifth switch TFT 47 has a fifth gate electrode 47A connected to the third switch wiring 44, a fifth source electrode 47B connected to the distribution wiring 43, a fifth drain electrode 47C connected to the sixth source wiring 327ζ, and a fifth semiconductor portion 47D connected to the fifth source electrode 47B and the fifth drain electrode 47C. The third switch TFT 45, the fourth switch TFT 46, and the fifth switch TFT 47 have the same configuration as the pixel TFT 324, the first switch TFT 340, and the second switch TFT 341 (see FIG. 5). Specifically, the third gate electrode 45A, the fourth gate electrode 46A, and the fifth gate electrode 47A are all made of the same first metal film as the pixel gate electrode 324A, etc. The third source electrode 45B, the third drain electrode 45C, the fourth source electrode 46B, the fourth drain electrode 46C, the fifth source electrode 47B, and the fifth drain electrode 47C are all made of the same second metal film as the pixel source electrode 324B, the pixel drain electrode 324C, etc. The third semiconductor portion 45D, the fourth semiconductor portion 46D, and the fifth semiconductor portion 47D are all made of the same semiconductor film as the pixel semiconductor portion 324D, etc. Note that the ends of the source lines 327δ, 327ε, and 327ζ arranged in the second area AA2 on the driver 312 side in the Y-axis direction are extended to the non-display area NAA and connected to the switch TFTs 45 to 47.

[0096] Next, detailed operation of the second switch circuit 42 will be described with reference to FIG. 12. FIG. 12 is a timing chart relating to the operation of the second switch circuit 42. FIG. 12 shows signal waveforms in the gate wiring 326, the first switch wiring 338, the second switch wiring 339, and the third switch wiring 44. FIG. 12 also shows a scale for each unit period (one horizontal period) H. Specifically, FIG. 12 shows, from top to bottom, a first scanning signal G(i) transmitted by the ith gate wiring 326 (hereinafter, i is an integer equal to or greater than 1) counting from the top of FIG. 11, a second scanning signal G(i+1) transmitted by the i+1th gate wiring 326 counting from the top of FIG. 11, a first switch signal SW1 transmitted by the first switch wiring 338, a second switch signal SW2 transmitted by the second switch wiring 339, and a third switch signal SW3 transmitted by the third switch wiring 44.

[0097] The first scanning signal G(i), the second scanning signal G(i+1), the first switch signal SW1, the second switch signal SW2, and the third switch signal SW3 each include a high potential Vgh and a low potential Vgl, as described in the first embodiment. The first switch signal SW1, the second switch signal SW2, and the third switch signal SW3 are all generally rectangular waves, with signal waveforms that periodically repeat one unit period H of the high potential Vgh and two consecutive unit periods H of the low potential Vgl. The timing at which the first switch signal SW1 falls from the high potential Vgh to the low potential Vgl and the timing at which the second switch signal SW2 rises from the low potential Vgl to the high potential Vgh are synchronized to coincide with each other, and the timing at which the second switch signal SW2 falls from the high potential Vgh to the low potential Vgl and the timing at which the third switch signal SW3 rises from the low potential Vgl to the high potential Vgh are synchronized to coincide with each other. In this way, the control board 14, which is the signal supply unit SS, applies the high potential Vgh at different timings to the first switch wiring 338, the second switch wiring 339, and the third switch wiring 44. Note that the first scanning signal G(i) and the second scanning signal G(i+1) are as described in the first embodiment above.

[0098] Specific operation of the second switch circuit 42 will be described. As shown in FIG. 12, when the gate drive circuit 15 outputs a high potential Vgh in the first scanning signal G(i) to the ith gate wiring 326 (time t1), the control board 14 outputs a high potential Vgh in the first switch signal SW1 to the first switch wiring 338. The third switch TFT 45 is driven during the period from time t1 to when the first switch signal SW1 falls from the high potential Vgh to the low potential Vgl (time t2). At this time, the first switch TFT 340 of the first switch circuit 316 is also driven. During the period when the third switch TFT 45 is driven, the image signal supplied from the driver 312 to the distribution wiring 43 is supplied to the fourth source wiring 327δ via the third source electrode 45B, the third semiconductor portion 45D, and the third drain electrode 45C of the third switch TFT 45. Therefore, the pixel TFT 324 connected to the i-th gate line 326 and the fourth source line 327δ is driven, and the pixel electrode 325 connected to that pixel TFT 324 is charged to a potential based on the image signal supplied to the fourth source line 327δ.

[0099] At time t2, the first scanning signal G(i) is maintained at high potential Vgh, and the control substrate 14 outputs high potential Vgh of the second switch signal SW2 to the second switch wiring 339. During the period from time t2 to when the second switch signal SW2 falls from high potential Vgh to low potential Vgl (time t3), the fourth switch TFT 46 is driven. At this time, the second switch TFT 341 of the first switch circuit 316 is also driven. During the period in which the fourth switch TFT 46 is driven, the image signal supplied from the driver 312 to the distribution wiring 43 is supplied to the fifth source wiring 327ε via the fourth source electrode 46B, the fourth semiconductor portion 46D, and the fourth drain electrode 46C of the fourth switch TFT 46. Therefore, the pixel TFT 324 connected to the i-th gate line 326 and the fifth source line 327ε is driven, and the pixel electrode 325 connected to that pixel TFT 324 is charged to a potential based on the image signal supplied to the fifth source line 327ε.

[0100] At time t3, the first scanning signal G(i) is maintained at high potential Vgh, and the control substrate 14 outputs the high potential Vgh of the third switch signal SW3 to the third switch wiring 44. During the period from time t3 to when the third switch signal SW3 falls from high potential Vgh to low potential Vgl (time t4), the fifth switch TFT 47 is driven. At this time, neither the first switch TFT 340 nor the second switch TFT 341 of the first switch circuit 316 is driven. During the period when the fifth switch TFT 47 is driven, the image signal supplied from the driver 312 to the distribution wiring 43 is supplied to the sixth source wiring 327ζ via the fifth source electrode 47B, the fifth semiconductor portion 47D, and the fifth drain electrode 47C of the fifth switch TFT 47. Therefore, the pixel TFT 324 connected to the i-th gate line 326 and the sixth source line 327ζ is driven, and the pixel electrode 325 connected to that pixel TFT 324 is charged to a potential based on the image signal supplied to the sixth source line 327ζ.

[0101] As described above, the second switch circuit 42 controls the driving of the third switch TFT 45, the fourth switch TFT 46, and the fifth switch TFT 47, thereby distributing the image signal supplied from the driver 312 to the distribution wiring 43 to each of the source wirings 327δ to 327ζ arranged in the second area AA2 in a time-division manner. Note that even when the high potential Vgh of the second scanning signal G(i+1) is output from the gate drive circuit 15 to the (i+1)-th gate wiring 326, the image signal is distributed to each of the source wirings 327δ to 327ζ in the same manner as described above.

[0102] Here, it is difficult to secure space for arranging wiring and the like in a portion of the non-display area NAA of the liquid crystal panel 311 adjacent to the first area AA1. In particular, in a configuration in which the display area AA has the first area AA1 and the gate drive circuit 115 and the first switch circuit 316 have portions adjacent to each other, it is difficult to secure space for arranging both circuits 115 and 316 (see FIG. 8 ). In this regard, in this embodiment, the first switch TFT 340 and the second switch TFT 341 are connected to the first source wiring 327α, the second source wiring 327β, and the third source wiring 327γ arranged in the first area AA1. This reduces the number of switch TFTs installed in the portion of the non-display area NAA adjacent to the first area AA1, compared to a configuration in which the third switch TFT 45, the fourth switch TFT 46, and the fifth switch TFT 47 are connected to the fourth source wiring 327δ, the fifth source wiring 327ε, and the sixth source wiring 327ζ arranged in the second area AA2. This allows a narrower frame in the portion of the non-display area NAA adjacent to the first area AA1 of the liquid crystal panel 311 while ensuring space for arranging wiring and the like. Furthermore, since the first switch wiring 338 is connected to the first gate electrode 340A and the third gate electrode 45A of the first switch TFT 340 and the third switch TFT 45, and the second switch wiring 339 is connected to the second gate electrode 341A and the fourth gate electrode 46A of the second switch TFT 341 and the fourth switch TFT 46, the number of switch wirings 44, 338, and 339 can be reduced compared to a case in which separate switch wirings are connected to the first gate electrode 340A and the third gate electrode 45A, and separate switch wirings are connected to the second gate electrode 341A and the fourth gate electrode 46A. This is advantageous for narrowing the frame in the portion of the non-display area NAA adjacent to the first area AA1 of the liquid crystal panel 311.

[0103] In this embodiment, the first source wiring 327α, the second source wiring 327β, and the third source wiring 327γ arranged in the first region AA1 have shorter wiring lengths than the fourth source wiring 327δ, the fifth source wiring 327ε, and the sixth source wiring 327ζ arranged in the second region AA2, as shown in FIG. 11. This is because the range in the Y-axis direction of the first region AA1, which has a non-rectangular planar shape, is narrower than the range in the Y-axis direction of the second region AA2, which has a rectangular planar shape (see FIG. 8). Here, in the first region AA1, the image signals supplied to the second source wiring 327β and the third source wiring 327γ are also supplied to the first source wiring 327α, and are therefore susceptible to parasitic capacitance between the first source wiring 327α and other wirings, resulting in a tendency for signal distortion to occur. In this regard, the first source wiring 327α, the second source wiring 327β, and the third source wiring 327γ are shorter in length than the fourth source wiring 327δ, the fifth source wiring 327ε, and the sixth source wiring 327ζ, and therefore the wiring resistance of the first source wiring 327α, the second source wiring 327β, and the third source wiring 327γ is reduced, and as a result, signal distortion is less likely to occur in the image signals supplied to the second source wiring 327β and the third source wiring 327γ via the first source wiring 327α.On the other hand, the fourth source wiring 327δ, the fifth source wiring 327ε, and the sixth source wiring 327ζ are longer in length than the first source wiring 327α, the second source wiring 327β, and the third source wiring 327γ. In this regard, the image signal supplied to the fourth source wiring 327δ is not supplied to the fifth source wiring 327ε and the sixth source wiring 327ζ, the image signal supplied to the fifth source wiring 327ε is not supplied to the fourth source wiring 327δ and the sixth source wiring 327ζ, and the image signal supplied to the sixth source wiring 327ζ is not supplied to the fourth source wiring 327δ and the fifth source wiring 327ε, so signal dulling is unlikely to occur in any of the image signals.

[0104] As described above, according to this embodiment, the first source wiring 327α, the second source wiring 327β, and the third source wiring 327γ all extend along the first direction, and the display area AA includes a first area AA1 in which the outer dimensions in a second direction intersecting with the first direction change depending on the position in the first direction, and a second area AA2 in which the outer dimensions in the second direction are constant depending on the position in the first direction. The first source wiring 327α, the second source wiring 327β, and the third source wiring 327γ are arranged in the first area AA1, and the fourth source wiring (fourth wiring) 327δ arranged in the second area AA2, the fifth source wiring (fifth wiring) 327ε arranged in the second area AA2, the sixth source wiring (sixth wiring) 327ζ arranged in the second area AA2, the distribution wiring 43 arranged in the non-display area NAA and connected to the signal supply unit SS, and the third switch wiring 327ζ arranged in the non-display area NAA. 44, a third switch TFT (third switching element) 45 arranged in the non-display area NAA and having a third gate electrode 45A connected to the first switch wiring 338, a third source electrode 45B connected to the distribution wiring 43, and a third drain electrode 45C connected to the fourth source wiring 327δ, a fourth switch TFT (fourth switching element) 46 arranged in the non-display area NAA and having a fourth gate electrode 46A connected to the second switch wiring 339, a fourth source electrode 46B connected to the distribution wiring 43, and a fourth drain electrode 46C connected to the fifth source wiring 327ε, and a fifth switch TFT (fifth switching element) 47 arranged in the non-display area NAA and having a fifth gate electrode 47A connected to the third switch wiring 44, a fifth source electrode 47B connected to the distribution wiring 43, and a fifth drain electrode 47C connected to the sixth source wiring 327ζ. When a switch signal is supplied from the signal supply unit SS to the first switch wiring 338, the third switch TFT 45, whose third gate electrode 45A is connected to the first switch wiring 338, is driven. At this time, when an image signal is supplied from the signal supply unit SS to the distribution wiring 43, the image signal is supplied to the fourth source wiring 327δ via the third source electrode 45B and the third drain electrode 45C of the third switch TFT 45.When a switch signal is supplied from the signal supply unit SS to the second switch wiring 339, the fourth switch TFT 46, whose fourth gate electrode 46A is connected to the second switch wiring 339, is driven. At this time, when an image signal is supplied from the signal supply unit SS to the distribution wiring 43, the image signal is supplied to the fifth source wiring 327ε via the fourth source electrode 46B to the fourth drain electrode 46C of the fourth switch TFT 46. When a switch signal is supplied from the signal supply unit SS to the third switch wiring 44, the fifth switch TFT 47, whose fifth gate electrode 47A is connected to the third switch wiring 44, is driven. At this time, when an image signal is supplied from the signal supply unit SS to the distribution wiring 43, the image signal is supplied to the sixth source wiring 327ζ via the fifth source electrode 47B to the fifth drain electrode 47C of the fifth switch TFT 47. In this way, by controlling the driving of the third switch TFT 45, the fourth switch TFT 46, and the fifth switch TFT 47, it is possible to supply image signals to the fourth source wiring 327δ, the fifth source wiring 327ε, and the sixth source wiring 327ζ, respectively. Here, it is difficult to secure space for arranging wiring and the like in the portion of the non-display area NAA of the liquid crystal panel 311 adjacent to the first area AA1. In this regard, the first switch TFT 340 and the second switch TFT 341 are connected to the first source wiring 327α, the second source wiring 327β, and the third source wiring 327γ arranged in the first area AA1. This reduces the number of switch TFTs installed in the portion of the non-display area NAA adjacent to the first area AA1, compared to when the third switch TFT 45, the fourth switch TFT 46, and the fifth switch TFT 47 are connected to the fourth source wiring 327δ, the fifth source wiring 327ε, and the sixth source wiring 327ζ arranged in the second area AA2. This makes it possible to ensure space for arranging wiring and the like in the portion of the non-display area NAA of the liquid crystal panel 311 adjacent to the first area AA1 while also narrowing the frame of that portion.Furthermore, the first switch wiring 338 is connected to the first gate electrode 340A and the third gate electrode 45A of the first switch TFT 340 and the third switch TFT 45, and the second switch wiring 339 is connected to the second gate electrode 341A and the fourth gate electrode 46A of the second switch TFT 341 and the fourth switch TFT 46. This makes it possible to reduce the number of switch wirings 44, 338, and 339 installed, compared to the case where another switch wiring is connected to the first gate electrode 340A and the third gate electrode 45A, and another switch wiring is connected to the second gate electrode 341A and the fourth gate electrode 46A. This is advantageous in narrowing the frame of the portion of the non-display area NAA of the liquid crystal panel 311 adjacent to the first area AA1.

[0105] Furthermore, the first source wiring 327α, the second source wiring 327β, and the third source wiring 327γ have shorter wiring lengths than the fourth source wiring 327δ, the fifth source wiring 327ε, and the sixth source wiring 327ζ. The image signals supplied to the second source wiring 327β and the third source wiring 327γ are also supplied to the first source wiring 327α, which tends to cause signal distortion. In this regard, because the first source wiring 327α, the second source wiring 327β, and the third source wiring 327γ have shorter wiring lengths than the fourth source wiring 327δ, the fifth source wiring 327ε, and the sixth source wiring 327ζ, the wiring resistances of the first source wiring 327α, the second source wiring 327β, and the third source wiring 327γ are reduced, which makes it less likely that the image signals supplied to the second source wiring 327β and the third source wiring 327γ will be distorted. On the other hand, the fourth source wiring 327δ, the fifth source wiring 327ε, and the sixth source wiring 327ζ are longer than the first source wiring 327α, the second source wiring 327β, and the third source wiring 327γ. In this regard, the image signal supplied to the fourth source wiring 327δ is not supplied to the fifth source wiring 327ε and the sixth source wiring 327ζ, the image signal supplied to the fifth source wiring 327ε is not supplied to the fourth source wiring 327δ and the sixth source wiring 327ζ, and the image signal supplied to the sixth source wiring 327ζ is not supplied to the fourth source wiring 327δ and the fifth source wiring 327ε, so signal distortion is unlikely to occur in any of the image signals.

[0106] <Embodiment 5> A fifth embodiment will be described with reference to Figures 13 to 15. In this fifth embodiment, a touch panel function is added to the liquid crystal panel 411 of the first embodiment. Note that a redundant description of the structure, operation, and effects similar to those of the first embodiment will be omitted.

[0107] The liquid crystal panel 411 according to this embodiment has both a display function for displaying images and a touch panel function for detecting a position (input position) at which a user inputs based on the displayed image. A touch panel pattern for achieving the touch panel function is integrated (in-cell) into the liquid crystal panel 411. This touch panel pattern is a so-called projected capacitive type, and its detection method is a self-capacitive type. As shown in FIG. 13 , the touch panel pattern is composed of a plurality of touch electrodes (position detection electrodes) 48 arranged in a matrix on the main surface 411S of the liquid crystal panel 411. The touch electrodes 48 are arranged in a display area AA of the liquid crystal panel 411. Therefore, the display area AA of the liquid crystal panel 411 substantially coincides with a touch area (position input area) where an input position can be detected, and the non-display area NAA substantially coincides with a non-touch area (non-position input area) where an input position cannot be detected. When a user approaches a conductive finger (position input object) to the surface of the liquid crystal panel 411 to input a position based on the image in the display area AA of the liquid crystal panel 411, a capacitance is formed between the finger and the touch electrode 48. As a result, the capacitance detected at the touch electrode 48 closest to the finger changes as the finger approaches, and becomes different from that of the touch electrode 48 farther away from the finger, making it possible to detect the input position based on this. The touch electrode 48 has a substantially rectangular shape in a plan view, with each side measuring approximately several millimeters. Therefore, the size of the touch electrode 48 in a plan view is much larger than the pixel (described later) and is arranged in an area spanning multiple pixels in the X-axis and Y-axis directions. The touch electrode 48 configured in this way is composed of a common electrode 428. The common electrode 428 has lattice-shaped partition slits that separate adjacent touch electrodes 48. The partition slits divide the common electrode 428 into a grid pattern, forming multiple touch electrodes 48 that are electrically independent from each other. In addition to the illustration in FIG. 13, the specific number of touch electrodes 48 to be installed and their planar shapes can be changed as appropriate.

[0108] As shown in FIG. 13 , a plurality of touch wirings (position detection wirings) 49 connected to a plurality of touch electrodes 48 are provided on the inner surface of the display area AA of the array substrate 421. The touch wirings 49 extend along the Y-axis direction to cross the display area AA and are parallel to the source wirings 427. A plurality of touch wirings 49 are arranged in the display area AA at intervals along the X-axis direction. At least one touch wiring 49 is connected to the touch electrode 48. A common potential signal related to the display function and a touch signal (position detection signal) related to the touch function are supplied to the touch wiring 49 at different timings (time-division). The timing when the common potential signal is supplied to the touch wiring 49 is the display period, and the timing when the touch signal is supplied to the touch wiring 49 is the sensing period (position detection period). During the display period, the common potential signal is supplied to all the touch wirings 49, so that all the touch electrodes 48 have a common potential and function as the common electrode 428. The touch wiring 49 is connected to a driver 412. The touch signal and the common potential signal are supplied from a driver 412, which is a signal supply unit SS, to the touch wiring 49. The touch wiring 49 may be connected to a flexible substrate 413. In this case, the touch signal and the common potential signal are supplied to the touch wiring 49 from a control substrate 414, which is a signal supply unit SS, via the flexible substrate 413.

[0109] In this embodiment, the above-described touch wiring 49 is arranged to overlap some of the source wirings 427, as shown in FIGS. 14 and 15 . Specifically, the plurality of touch wirings 49 are arranged to overlap the second source wiring 427β and the third source wiring 427γ of the plurality of source wirings 427, respectively, but do not overlap the first source wiring 427α. Therefore, in this embodiment, the number of installed touch wirings 49 is approximately two-thirds of the number of installed source wirings 427. Hereinafter, of the plurality of touch wirings 49, the touch wiring 49 overlapping the second source wiring 427β will be referred to as the first touch wiring (first position detection wiring) 49α, and the touch wiring 49 overlapping the third source wiring 427γ will be referred to as the second touch wiring (second position detection wiring) 49β. In Figure 14, the first touch wiring 49α and the second source wiring 427β, which overlap each other, are shown side by side, the second touch wiring 49β and the third source wiring 427γ, which overlap each other, are shown side by side, and the first wiring configuration portion 427Aα and the second wiring configuration portion 427Bα that constitute the first source wiring 427α are shown side by side.

[0110] As shown in FIG. 14, the first source wiring 427α according to this embodiment has the same configuration as the first source wiring 27α described in the first embodiment, and has a stacked structure in which a first wiring configuration portion 427Aα and a second wiring configuration portion 427Bα are interconnected. On the other hand, as shown in FIG. 15, the second source wiring 427β and the third source wiring 427γ each have a single-layer structure made of only the second metal film. In contrast, the first touch wiring 49α and the second touch wiring 49β each have a single-layer structure made of only the third metal film. The first touch wiring 49α made of the third metal film is disposed so as to overlap the second source wiring 427β made of the second metal film with the first interlayer insulating film 434 interposed therebetween. The second touch wiring 49β made of the third metal film is disposed so as to overlap the third source wiring 427γ made of the second metal film with the first interlayer insulating film 434 interposed therebetween. Each touch wiring 49 is connected to the touch electrode 48 to be connected thereto through a touch contact hole CHTP formed in the intervening planarization film 435 and second interlayer insulating film 436. The planar arrangement of the touch contact hole CHTP may be the same as the planar arrangement of the contact holes CHS2 and CHS3 described in the first embodiment above (see FIG. 3).

[0111] 15 , the first touch wiring 49α is prevented from being short-circuited with the second source wiring 427β by the first interlayer insulating film 434 being interposed between the first touch wiring 49α and the overlapping second source wiring 427β. The second touch wiring 49β is prevented from being short-circuited with the third source wiring 427γ by the first interlayer insulating film 434 being interposed between the second touch wiring 49β and the overlapping third source wiring 427γ. Since the first touch wiring 49α overlaps the second source wiring 427β and the second touch wiring 49β is arranged so as to overlap the third source wiring 427γ, a decrease in aperture ratio caused by the first touch wiring 49α and the second touch wiring 49β is suppressed.

[0112] As described above, according to this embodiment, the display device includes a first touch wiring (first position detection wiring) 49α arranged in the display area AA and connected to the signal supply unit SS, a second touch wiring (second position detection wiring) 49β arranged in the display area AA and connected to the signal supply unit SS, and a touch electrode (position detection electrode) 48 arranged in the display area AA, which forms a capacitance with a position input body that performs a position input, and which is connected to at least one of the first touch wiring 49α and the second touch wiring 49β, and the signal supply unit SS outputs a touch signal (position detection signal) to the first touch wiring 49α and the second touch wiring 49β. The second source wiring 427β is made of a portion of the second metal film different from the first wiring configuration portion 427Aα, the third source wiring 427γ is made of a portion of the second metal film different from the first wiring configuration portion 427Aα and the second source wiring 427β, the first touch wiring 49α is made of a portion of the third metal film different from the second wiring configuration portion 427Bα and is arranged overlapping with the second source wiring 427β, and the second touch wiring 49β is made of a portion of the third metal film different from the second wiring configuration portion 427Bα and the first touch wiring 49α and is arranged overlapping with the third source wiring 427γ. The touch electrode 48 forms a capacitance with a position input object that performs a position input, and can detect an input position by the position input object using a touch signal supplied from the signal supply unit SS via at least one of the first touch wiring 49α and the second touch wiring 49β. The first touch wiring 49α is prevented from shorting with the second source wiring 427β by the first interlayer insulating film 434 being interposed between the first touch wiring 49α and the overlapping second source wiring 427β. The second touch wiring 49β is prevented from shorting with the third source wiring 427γ by the first interlayer insulating film 434 being interposed between the second touch wiring 49β and the overlapping third source wiring 427γ. Because the first touch wiring 49α overlaps the second source wiring 427β and the second touch wiring 49β is arranged to overlap the third source wiring 427γ, a decrease in aperture ratio caused by the first touch wiring 49α and the second touch wiring 49β is suppressed.

[0113] <Embodiment 6> A sixth embodiment will be described with reference to Fig. 16 or 17. This sixth embodiment shows a case where a common wiring 51 is added to the first embodiment in order to reduce the resistance distribution of the common electrode 528. Note that a redundant description of the structure, action, and effect similar to those of the first embodiment will be omitted.

[0114] 16, a liquid crystal panel 511 according to this embodiment is provided with a common trunk wiring 50 connected to a common electrode 528 and a flexible substrate 513. The common trunk wiring 50 is made up of a frame-shaped portion 50A that surrounds the entire periphery of the display area AA, and an extraction portion 50B that is extracted from the frame portion 50A and routed to the flexible substrate 513. The frame portion 50A is disposed so as to overlap the outer peripheral edge of the common electrode 528, and is connected to the common electrode 528. A common potential signal is supplied to the common trunk wiring 50 from a control substrate 514, which serves as a signal supply unit SS, via the flexible substrate 513.

[0115] As shown in FIG. 16 , a plurality of common wirings 51 connected to the common electrode 528 and the common trunk wiring 50 are provided on the inner surface of the display area AA of the array substrate 521. The common wirings 51 extend along the Y-axis direction to transversely cross the display area AA and are parallel to the source wirings 527. A plurality of common wirings 51 are arranged side by side in the display area AA at intervals in the X-axis direction. Both ends of each common wiring 51 in the Y-axis direction are connected to the frame-shaped portion 50A of the common trunk wiring 50, and a central portion located closer to the center than both ends is connected to the common electrode 528 at multiple points. The common wiring 51 is connected to the control substrate 514, which serves as a signal supply unit SS, via the common trunk wiring 50 and the flexible substrate 513, so that a common potential signal is supplied from the control substrate 514. The connection structure between the common wirings 51 and the common electrode 528 is the same as the connection structure between the touch wiring 49 and the touch electrode 48 described in the fifth embodiment (see FIG. 15 ). Specifically, the common wiring 51 is connected to the common electrode 528 through a common contact hole CHCM formed in the planarizing film 35 and the second interlayer insulating film 36 interposed therebetween.

[0116] In this embodiment, the above-described common wiring 51 is arranged to overlap some of the source wirings 527, as shown in FIG. 17 . Specifically, the multiple common wirings 51 are arranged to overlap the second source wiring 527β and the third source wiring 527γ of the multiple source wirings 527, respectively, but do not overlap the first source wiring 527α. Therefore, in this embodiment, the number of installed common wirings 51 is approximately two-thirds of the number of installed source wirings 527. Hereinafter, of the multiple common wirings 51, the common wiring 51 overlapping the second source wiring 527β will be referred to as a first common electrode 51α, and the common wiring 51 overlapping the third source wiring 527γ will be referred to as a second common wiring 51β. In Figure 17, the first common wiring 51α and the second source wiring 527β, which overlap each other, are shown side by side, the second common wiring 51β and the third source wiring 527γ, which overlap each other, are shown side by side, and the first wiring component 527Aα and the second wiring component 527Bα that constitute the first source wiring 527α are shown side by side.

[0117] As shown in FIG. 17 , the first source wiring 527α according to this embodiment has the same configuration as the first source wiring 27α described in the first embodiment, and has a stacked structure in which a first wiring portion 527Aα and a second wiring portion 527Bα are interconnected. Meanwhile, the second source wiring 527β and the third source wiring 527γ each have a single-layer structure made of only the second metal film. In contrast, the first common wiring 51α and the second common wiring 51β each have a single-layer structure made of only the third metal film. The first common wiring 51α made of the third metal film is arranged to overlap the second source wiring 527β made of the second metal film via the first interlayer insulating film 34, and has the same relationship as the first touch wiring 49α and the second source wiring 427β described in the fifth embodiment (see FIG. 15 ). The second common wiring 51β made of a third metal film is arranged to overlap the third source wiring 527γ made of a second metal film via the first interlayer insulating film 34, and has the same relationship as the second touch wiring 49β and the third source wiring 427γ described in the above-mentioned embodiment 5 (see Figure 15).

[0118] According to this embodiment, a common potential signal is supplied to the common electrode 528 from the control substrate 514, which serves as the signal supply unit SS, via the flexible substrate 513, the common main wiring 50, and the common wiring 51, which is suitable for reducing the resistance distribution of the common electrode 528. The first common wiring 51α is prevented from shorting with the second source wiring 527β by the first interlayer insulating film 34 interposed between the first common wiring 51α and the overlapping second source wiring 527β. The second common wiring 51β is prevented from shorting with the third source wiring 527γ by the first interlayer insulating film 34 interposed between the second common wiring 51β and the overlapping third source wiring 527γ. Since the first common wiring 51α overlaps the second source wiring 527β and the second common wiring 51β overlaps the third source wiring 527γ, a decrease in aperture ratio due to the first common wiring 51α and the second common wiring 51β is suppressed.

[0119] As described above, according to this embodiment, the display device includes the common electrode 528 arranged in the display area AA, the first common wiring 51α arranged in the display area AA and connected to the common electrode 528 and the signal supply section SS, and the second common wiring 51β arranged in the display area AA and connected to the common electrode 528 and the signal supply section SS, and the signal supply section SS supplies a common potential signal to the first common wiring 51α and the second common wiring 51β, and the second source wiring 527β is connected to the first wiring component 527Aα of the second metal film. The third source wiring 527γ is composed of a different portion of the second metal film from the first wiring component 527Aα and the second source wiring 527β. The first common wiring 51α is composed of a different portion of the third metal film from the second wiring component 527Bα and is arranged overlapping the second source wiring 527β. The second common wiring 51β is composed of a different portion of the third metal film from the second wiring component 527Bα and the first common wiring 51α and is arranged overlapping the third source wiring 527γ. A common potential signal is supplied to the common electrode 528 from the signal supply unit SS via the first common wiring 51α and the second common wiring 51β, which is advantageous in reducing the resistance distribution of the common electrode 528. The first common wiring 51α is prevented from shorting with the second source wiring 527β by the first interlayer insulating film 34 interposed between the first common wiring 51α and the overlapping second source wiring 527β. The second common wiring 51β is prevented from short-circuiting with the third source wiring 527γ by the first interlayer insulating film 34 interposed between the second common wiring 51β and the overlapping third source wiring 527γ. Since the first common wiring 51β overlaps the second source wiring 527β and the second common wiring 51β overlaps the third source wiring 527γ, a decrease in aperture ratio caused by the first common wiring 51α and the second common wiring 51β is suppressed.

[0120] <Other embodiments> The technology disclosed in this specification is not limited to the embodiments described above and illustrated in the drawings, and the following embodiments, for example, are also included in the technical scope.

[0121] (1) Each of the switch wirings 38, 39, 44, 138, 238, 139, and 239 may have a laminated structure similar to that of the first source wirings 27α, 127α, 227α, 327α, 427α, and 527α (a ​​structure in which a lower layer portion made of the second metal film and an upper layer portion made of the third metal film are superimposed and connected to each other). In this way, the wiring resistance of each of the switch wirings 38, 39, 44, 138, 238, 139, and 239 can be reduced, and distortion of the switch signal is less likely to occur.

[0122] (2) Each of the switch wirings 38, 39, 44, 138, 238, 139, and 239 may be connected to a driver 12, 112, 212, 312, 412, or 512, which is a signal supply unit SS. In this case, the driver 12, 112, 212, 312, 412, or 512 supplies an image signal to the connection wirings 37, 137, 237, and 337 (source wirings 27, 127, 327, 427, and 527), and also supplies a switch signal to each of the switch wirings 38, 39, 44, 138, 238, 139, and 239.

[0123] (3) In the configurations described in the first to fourth embodiments, each of the source wirings 27α, 127α, 227α, 327α, 27β, 127β, 227β, 327β, 27γ, 127γ, 227γ, and 327γ may have a single-layer structure made of only the second metal film.

[0124] (4) In the configurations described in the fifth and sixth embodiments, the first source wirings 427α and 527α may have a single-layer structure made of only the second metal film. In this case, the touch wiring 49 and the common wiring 51 made of the third metal film may be arranged to overlap the first source wirings 427α and 527α.

[0125] (5) In the configurations described in embodiments 1 to 4, the source wiring contact hole CHS, which is arranged at a position overlapping both the lower layer 27A made of the second metal film and the upper layer 27B made of the third metal film, may be arranged in the non-display area NAA.

[0126] (6) In the configurations described in the first, fifth, and sixth embodiments, the first switch circuit 16 may be arranged on the same side as the drivers 12, 412, and 512 in the Y-axis direction with respect to the display area AA.

[0127] (7) In the configuration described in embodiment 2, the first switch circuit 116 connected to the source wiring 127 arranged in the second region AA2 may be arranged on only one side of the second region AA2 in the Y-axis direction (the same side as the driver 112 or the opposite side from the driver 112).

[0128] (8) In the configuration described in embodiment 3, the second unit switch circuits 216Uβ may be arranged on the opposite side of the second area AA2 in the Y-axis direction from the driver 212. Furthermore, the second unit switch circuits 216Uβ may be arranged in pairs on both sides of the second area AA2 in the Y-axis direction.

[0129] (9) In the configuration described in the fourth embodiment, the first switch circuit 316 may be arranged on the opposite side of the first area AA1 from the driver 312 in the Y-axis direction. Also, the second switch circuit 42 may be arranged on the opposite side of the second area AA2 from the driver 312 in the Y-axis direction.

[0130] (10) In the configuration described in the fourth embodiment, the first switch circuits 316 may be arranged in pairs on both sides of the first area AA1 in the Y-axis direction. Also, the second switch circuits 42 may be arranged in pairs on both sides of the second area AA2 in the Y-axis direction.

[0131] (11) In the configuration described in the sixth embodiment, the common main line 50 may be connected to a driver 512 .

[0132] (12) In the configuration described in the sixth embodiment, the common wiring 51 may be disconnected from the common main wiring 50 and connected to the flexible substrate 513. Also, the common wiring 51 may be disconnected from the common main wiring 50 and connected to the driver 512.

[0133] (13) The common main wiring 50 described in the sixth embodiment can be appropriately applied to the configurations described in the first to fifth embodiments.

[0134] (14) The configurations described in the second to fourth embodiments may be combined with the configurations described in the fifth and sixth embodiments as appropriate.

[0135] (15) In the array substrate 21, 121, 421, 521, the third metal film may be disposed above the planarization film 35, 436. In this case, an interlayer insulating film may be added between the third metal film and the first transparent electrode film. In this case, the first interlayer insulating film 34, 434 may be omitted.

[0136] (16) The number and arrangement of the drivers 12, 112, 212, 312, 412, and 512 can be changed as appropriate to other than those shown in the drawings.

[0137] (17) The material of the semiconductor film provided on the array substrate 21, 121, 421, 521 may be any of amorphous silicon material, oxide semiconductor material, polycrystalline polysilicon material, etc. When polycrystalline polysilicon material is used as the material of the semiconductor film, the semiconductor film may be provided below the first metal film.

[0138] (18) Each of the TFTs 24, 324, 40, 140, 240, 340, 41, 141, 241, 341, 45, 46, and 47 may be a bottom gate type, a top gate type, or a double gate type.

[0139] (19) Instead of the gate drive circuit 15, 115, a gate driver may be mounted on the array substrate 21, 121, 421, 521.

[0140] (20) The drivers 12, 112, 212, 312, 412, and 512 may be mounted on the flexible substrates 13, 313, 413, and 513 by COF (Chip On Film) mounting, which are mounted on the array substrates 21, 121, 421, and 521 by FOG (Film On Glass) mounting.

[0141] (21) The planar shape of the liquid crystal panels 11, 111, 211, 311, 411, and 511 may be a vertically long rectangle, a square, a circle, a semicircle, a vertically long oval, an ellipse, a trapezoid, or the like.

[0142] (22) The liquid crystal panels 11, 111, 211, 311, 411, and 511 may be of a reflective or semi-transmissive type in addition to a transmissive type.

[0143] (23) The display mode of the liquid crystal panels 11, 111, 211, 311, 411, and 511 may be a multi-domain vertical alignment (MVA) mode, an in-plane switching (IPS) mode, a twisted nematic (TN) mode, or the like.

[0144] (24) The display device may be other than the liquid crystal panels 11, 111, 211, 311, 411, and 511 (such as an organic EL (Electro Luminescence) display panel) or an EPD (microcapsule electrophoretic display panel). [Explanation of symbols]

[0145] 10... liquid crystal display device (display device), 11,111,211,311,411,511... liquid crystal panel (display panel), 11S, 111S, 411S... main surface, 12,112,212,312,412,512... driver (first signal supply unit), 13,313,413,513... flexible substrate, 14,414,514... control substrate (second signal supply unit), 16,116,216,316... first switch circuit, 16U, 116U, 216U, 316U...unit switch circuit, 27α, 127α, 227α, 327α, 427α, 527α...first source wiring (first wiring), 27Aα, 427Aα, 527Aα...first wiring configuration section, 27Bα, 427Bα, 527Bα...second wiring configuration section, 27β, 127β, 227β, 327β, 427β, 527β...second source wiring (second wiring), 27Aβ...third wiring configuration section, 27Bβ...fourth Wiring configuration section, 27γ, 127γ, 227γ, 327γ, 427γ, 527γ... third source wiring (third wiring), 27Aγ... fifth wiring configuration section, 27Bγ... sixth wiring configuration section, 28, 428, 528... common electrode, 34, 434... first interlayer insulating film (first insulating film), 37, 137, 237, 337... connection wiring, 38, 138, 238... first switch wiring, 39, 139, 239... second switch wiring, 40, 140, 240 , 340...first switch TFT (first switching element), 40A, 140A, 340A...first gate electrode, 40B, 140B, 240B, 340B...first source electrode, 40C, 140C...first drain electrode, 41, 141, 241, 341...second switch TFT (second switching element), 41A, 141A, 341A...second gate electrode, 41B, 141B, 241B, 341B...second source electrode, 41C,141C...second drain electrode, 43...distribution wiring, 44...third switch wiring, 45...third switch TFT (third switching element), 45A...third gate electrode, 45B...third source electrode, 45C...third drain electrode, 46...fourth switch TFT (fourth switching element), 46A...fourth gate electrode, 46B...fourth source electrode, 46C...fourth drain electrode, 47...fifth switch TFT (fifth switching element), 47A...fifth gate electrode, 47B...fifth source electrode, 47C...fifth drain electrode, 48...touch electrode (position detection electrode), 49α...first touch wiring (first position detection wiring), 49β...second touch wiring (second position detection wiring), 51α...first common wiring, 51β...second common wiring, 216Uα...first unit switch circuit, 216Uβ...second unit switch circuit, 237α...first connection wiring, 237β...second connection wiring, 327δ...fourth source wiring (fourth wiring), 327ε...fifth source wiring (fifth wiring), 327ζ...sixth source wiring (sixth wiring), AA...display area, AA1...first area, AA2...second area, CHS1...first contact hole, CHS2...second contact hole, CHS3...third contact hole, NAA...non-display area, SS...signal supply unit,

Claims

1. a display area in which an image is displayed; a non-display area in which the image is not displayed; a first wiring arranged in the display area; a second wiring arranged in the display area; a third wiring arranged in the display area; a connection wiring arranged in the non-display area and connected to the first wiring; a first switch wiring arranged in the non-display area; a first switching element disposed in the non-display area and having a first gate electrode connected to the first switch wiring, a first source electrode connected to the first wiring or the connection wiring, and a first drain electrode connected to the second wiring; a second switch wiring arranged in the non-display area; a second switching element disposed in the non-display area, the second switching element having a second gate electrode connected to the second switch wiring, a second source electrode connected to the first wiring or the connecting wiring, and a second drain electrode connected to the third wiring; a signal supply unit that is arranged in the non-display area and is connected to the connection wiring, the first switch wiring, and the second switch wiring; the signal supply unit supplies an image signal to the connection wiring, and supplies switch signals having voltages higher than threshold voltages of the first switching element and the second switching element to the first switch wiring and the second switch wiring at different timings; The display device, wherein the first wiring is disposed between the second wiring and the third wiring.

2. a display panel having a main surface including the display area and the non-display area; the display panel is provided with the first wiring, the second wiring, the third wiring, the connection wiring, the first switch wiring, the second switch wiring, the first switching element, and the second switching element; the signal supply unit includes at least a first signal supply unit that is provided on the display panel, connected to the connection wiring, and supplies the image signal to the connection wiring; the first wiring, the second wiring, and the third wiring all extend along a first direction; the first signal supply unit, the first switching element, and the second switching element are arranged on the display panel so as to sandwich the display area in the first direction; The display device according to claim 1 , wherein the first wiring is connected to the first source electrode and the second source electrode.

3. The display device according to claim 2 , wherein the first switch wiring and the second switch wiring are arranged so as to sandwich the first switching element and the second switching element between the first switch wiring and the display area in the first direction.

4. 4. The display device according to claim 2, wherein the first switching element and the second switching element are arranged to sandwich the first wiring in a second direction intersecting the first direction.

5. a display panel having a main surface including the display area and the non-display area; the display panel is provided with the first wiring, the second wiring, the third wiring, the connection wiring, the first switch wiring, the second switch wiring, the first switching element, and the second switching element; the signal supply unit includes at least a first signal supply unit that is provided on the display panel, connected to the connection wiring, and supplies the image signal to the connection wiring; the first wiring, the second wiring, and the third wiring all extend along a first direction; the first switching element and the second switching element are arranged in pairs on the display panel so as to sandwich the display area in the first direction, the first signal supply unit is disposed on the display panel at a side of one of the first switching elements and the second switching element with respect to the display area in the first direction, the connection wiring is connected to the first source electrode and the second source electrode provided in one of the first switching element and the second switching element arranged on the same side as the first signal supply unit in the first direction with respect to the display area, 2. The display device according to claim 1, wherein the first wiring is connected to the first source electrode and the second source electrode of the other of the first switching elements and the second switching elements arranged on the opposite side of the display area from the first signal supply unit in the first direction.

6. a display panel having a main surface including the display area and the non-display area; a first switch circuit including a plurality of unit switch circuits each formed by the first switching element and the second switching element, and including the first switch wiring and the second switch wiring; the display panel is provided with the first wiring, the second wiring, the third wiring, the connection wiring, and the first switch circuit; the signal supply unit includes at least a first signal supply unit that is provided on the display panel, connected to the connection wiring, and supplies the image signal to the connection wiring; the first wiring, the second wiring, and the third wiring all extend along a first direction; the display area includes a first area whose outer dimensions in a second direction intersecting with the first direction change depending on a position in the first direction, and a second area whose outer dimensions in the second direction are constant depending on a position in the first direction, the first wiring, the second wiring, and the third wiring are arranged in the first region and the second region, respectively; the connection wiring includes a first connection wiring connected to the first wiring arranged in the first region, and a second connection wiring connected to the first wiring arranged in the second region; the first signal supply unit is disposed on one side of the display area in the first direction on the display panel; the plurality of unit switch circuits include a first unit switch circuit including the first switching element and the second switching element, each having the first source electrode and the second source electrode connected to the first wiring connected to the first connection wiring, and a second unit switch circuit including the first switching element and the second switching element, each having the first source electrode and the second source electrode connected to the second connection wiring, the first unit switch circuit is disposed on the display panel on an opposite side to the first signal supply unit in the first direction, 2. The display device according to claim 1, wherein the second unit switch circuit is disposed on the same side of the display panel as the first signal supply unit in the first direction.

7. the first wiring, the second wiring, and the third wiring all extend along a first direction, the display area includes a first area whose outer dimensions in a second direction intersecting with the first direction change depending on a position in the first direction, and a second area whose outer dimensions in the second direction are constant depending on a position in the first direction, the first wiring, the second wiring, and the third wiring are arranged in the first region, a fourth wiring disposed in the second region; a fifth wiring arranged in the second region; a sixth wiring arranged in the second region; a distribution wiring arranged in the non-display area and connected to the signal supply unit; and a third switch wiring arranged in the non-display area. a third switching element disposed in the non-display area, the third switching element having a third gate electrode connected to the first switch wiring, a third source electrode connected to the distribution wiring, and a third drain electrode connected to the fourth wiring; a fourth switching element disposed in the non-display area, the fourth switching element having a fourth gate electrode connected to the second switch wiring, a fourth source electrode connected to the distribution wiring, and a fourth drain electrode connected to the fifth wiring; 2. The display device according to claim 1, further comprising: a fifth switching element arranged in the non-display area and having a fifth gate electrode connected to the third switch wiring, a fifth source electrode connected to the distribution wiring, and a fifth drain electrode connected to the sixth wiring.

8. 8. The display device according to claim 7, wherein the first wiring, the second wiring, and the third wiring have lengths shorter than the fourth wiring, the fifth wiring, and the sixth wiring.

9. the first wiring is composed of a first wiring component made of a first conductive film, and a second wiring component made of a second conductive film arranged on an upper layer side of the first conductive film with a first insulating film interposed therebetween, the second wiring component overlapping the first wiring component; 9. The display device according to claim 1, wherein the first wiring configuration and the second wiring configuration are connected through a first contact hole formed in the first insulating film.

10. the second wiring is composed of a third wiring component made of a portion of the first conductive film different from the first wiring component, and a fourth wiring component made of a portion of the second conductive film different from the second wiring component and overlapping with the third wiring component, the third wiring is composed of a fifth wiring component consisting of a portion of the first conductive film that is different from the first wiring component and the third wiring component, and a sixth wiring component consisting of a portion of the second conductive film that is different from the second wiring component and the fourth wiring component and that overlaps with the fifth wiring component, the third wiring component and the fourth wiring component are connected through a second contact hole formed in the first insulating film, 10. The display device according to claim 9, wherein the fifth wiring portion and the sixth wiring portion are connected to each other through a third contact hole formed in the first insulating film.

11. a first position detection wiring line that is arranged in the display area and connected to the signal supply unit; a second position detection wiring that is arranged in the display area and connected to the signal supply unit; a position detection electrode that is arranged in the display area, forms a capacitance with a position input body that performs a position input, and is connected to at least one of the first position detection wiring and the second position detection wiring; the signal supply unit supplies a position detection signal to the first position detection wiring and the second position detection wiring; the second wiring is made of a portion of the first conductive film that is different from the first wiring component, the third wiring is made of a portion of the first conductive film that is different from the first wiring component and the second wiring, the first position detection wiring is made of a portion of the second conductive film that is different from the second wiring component, and is arranged to overlap the second wiring; 10. The display device according to claim 9, wherein the second position detection wiring is made of a portion of the second conductive film that is different from the second wiring component and the first position detection wiring, and is arranged so as to overlap the third wiring.

12. a common electrode disposed in the display area; a first common wiring arranged in the display area and connected to the common electrode and the signal supply unit; a second common wiring disposed in the display area and connected to the common electrode and the signal supply unit; the signal supply unit supplies a common potential signal to the first common wiring and the second common wiring; the second wiring is made of a portion of the first conductive film that is different from the first wiring component, the third wiring is made of a portion of the first conductive film that is different from the first wiring component and the second wiring, the first common wiring is made of a portion of the second conductive film that is different from the second wiring component, and is arranged to overlap the second wiring; 10. The display device according to claim 9, wherein the second common wiring is made of a portion of the second conductive film that is different from the second wiring component and the first common wiring, and is arranged so as to overlap the third wiring.

13. 9. The display device according to claim 1, wherein the signal supply unit supplies the image signal to the connection wiring and the switch signal to the first switch wiring, supplies the image signal to the connection wiring and the switch signal to the second switch wiring, and then supplies the image signal to the connection wiring without supplying the switch signal to either the first switch wiring or the second switch wiring.

14. a display panel provided with the first wiring, the second wiring, the third wiring, the connection wiring, the first switch wiring, the second switch wiring, the first switching element, and the second switching element; a flexible substrate connected to the display panel, the signal supply unit includes a first signal supply unit provided on the display panel and a second signal supply unit connected to the flexible substrate; the first signal supplying unit supplies the image signal to the connection wiring; 9. The display device according to claim 1, wherein the second signal supply unit supplies the switch signal to the first switch wiring and the second switch wiring via the flexible substrate at different timings.

Images