Package substrate

Abstract

To provide a package substrate with a new structure, a package substrate that is easy to adapt to fine pitches, and a manufacturing method thereof.SOLUTION: A package substrate 100 includes a first outer circuit pattern 120 arranged on the upper surface of an insulating layer 110, a second outer circuit pattern 125 arranged on the lower surface of the insulating layer, a first connecting portion 170 arranged on the upper surface of the 1-1 circuit pattern of the first outer circuit pattern, a first connection portion 180 arranged on the first connecting portion, a first element 200 arranged on the first connecting portion via the first connection portion, a second connection portion 185 arranged on the lower surface of the 2-1 circuit pattern of the second outer circuit pattern, a second element 300 attached to the 2-1 circuit pattern via the second connection portion, and a second connecting portion 175 arranged on the lower surface of the 2-2 circuit pattern of the second outer circuit pattern, and the first connecting portion has a first width and a first spacing, and the second connecting portion has a second width greater than the first width and a second spacing greater than the first spacing.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The embodiment relates to a package substrate. [Background technology]

[0002] As electronic components become smaller, lighter, and more integrated, the line width of circuits becomes finer. As semiconductor chip design rules become more integrated on a nanometer scale, The circuit line width of the package substrate or circuit board on which the body chip is mounted is several micrometers or less. It has been miniaturized to.

[0003] In order to increase the circuit integration of circuit boards, i.e., to reduce the circuit line width, various methods are used. In the step of etching to form a pattern after copper plating, To prevent loss of circuit line width, SAP (semi-additive process) cess) method and MSAP (modified semi-additive process) ess) etc. were proposed.

[0004] In order to realize finer circuit patterns, copper foil was embedded in the insulating layer. Embedded Trace Substrate (hereinafter referred to as "ETS") The ETS method is used in the industry. Instead of forming a copper foil circuit on the surface of an insulating layer, Furthermore, since it is manufactured in a form that is embedded in the insulating layer, there is no circuit loss due to etching, and the circuit This is advantageous for making the pitch finer.

[0005] Meanwhile, recently, improved 5G (5th generation) has been developed to meet the demand for wireless data traffic. Efforts to develop 5G or pre-5G communication systems Here, the 5G communication system requires ultra-high-speed data transmission to achieve high data rates. High frequency (mmWave) band (sub6Giga (6GHz), 28Giga (28GHz), 3 Uses a frequency of 8 gigahertz (38 GHz) or higher.

[0006] This reduces the path loss of radio waves in the ultra-high frequency band and increases the transmission distance of radio waves. To achieve this, 5G communication systems will use beamforming, Massive MIMO, array antenna In this frequency band, several hundred wavelengths of active light can be obtained. Considering the number of antennas that can be configured, the antenna system becomes relatively large.

[0007] Such antennas and AP modules are patterned or mounted on a circuit board. Low loss in the circuit board is very important because it is used to form an active antenna system. The antenna board, the antenna power supply board, the transceiver The er board and the baseband board are integrated into a single compact device. This means that the sensors must be integrated into a single compact unit. Summary of the Invention [Problem to be solved by the invention]

[0008] In the embodiments, a package substrate with a new structure and a manufacturing method thereof are provided.

[0009] In addition, in the embodiment, a package substrate that can easily accommodate fine pitches and a manufacturing method thereof are provided. I try to provide.

[0010] In addition, in the embodiment, the balance between both sides of the circuit board is maintained to minimize the occurrence of warping. To provide a package substrate and a manufacturing method thereof that can minimize the number of parts required.

[0011] Furthermore, the embodiment provides a package substrate and a method for manufacturing the same that can improve the reliability of the connection portion. The present invention aims to provide a manufacturing method for the above.

[0012] In the embodiment, post bumps directly connected to the elements embedded inside the insulating layer are used. The present invention provides a circuit board including the same and a package substrate including the same.

[0013] In addition, in the embodiment, a circuit board that can easily accommodate fine pitches and a package substrate including the same are provided. Provide the board.

[0014] Furthermore, the embodiment minimizes the occurrence of warpage by maintaining the balance between the upper and lower parts. The present invention provides a circuit board that can be mounted on a package substrate and a package substrate that includes the circuit board.

[0015] In the proposed embodiment, the technical problem to be solved is the technical problem mentioned above. The present invention is not limited to the above-mentioned technical problems, but other technical problems not mentioned are also included in the implementation proposed in the following description. The examples will be clearly understood by those skilled in the art. [Means for solving the problem]

[0016] The package substrate according to the embodiment includes an insulating layer and a first outer circumferential wall disposed on the insulating layer. a second outer circuit pattern disposed on the lower surface of the insulating layer; and a second outer circuit pattern disposed on the lower surface of the insulating layer. a first connecting portion disposed on the upper surface of the first-first circuit pattern of the circuit pattern; a first connecting portion disposed on the first coupling portion via the first connecting portion; the second connection element and the second outer circuit pattern disposed on the lower surface of the second-1 circuit pattern; a second element attached to the second-1 circuit pattern via the second connection part; a second connecting portion disposed on the lower surface of the second-2 circuit pattern of the second outer circuit pattern; The first connecting portion is disposed with a first width and a first interval, and the second connecting portion is disposed with the The electrodes are arranged with a second width greater than the first width and a second spacing greater than the first spacing.

[0017] A first insulating layer is disposed on the upper surface of the insulating layer and includes a first opening that exposes the first connecting portion. a solder resist and a second connecting portion and a second connecting portion disposed on the lower surface of the insulating layer; a second solder resist exposing a portion of the first circuit pattern, The first and second circuit patterns are covered with a photoresist.

[0018] Also, a seed metal layer disposed between the first circuit pattern and the first connection portion the seed metal layer is disposed between the first circuit pattern and the first connection portion. a first portion disposed between the first-second circuit pattern and the first solder resist; and a second portion.

[0019] The seed metal layer includes the first circuit pattern, the second circuit pattern, and a seed layer of the first connecting portion.

[0020] Also, a first molding element is disposed on the insulating layer and molds the first element. a molding layer disposed under the insulating layer, molding the second element, and the second connecting portion; and a second molding layer including an opening exposing the underside of the

[0021] The second connection portion is spaced apart from the first post bump, and and a second post bump having a width different from that of the first post bump.

[0022] The upper surface of the first outer circuit pattern is flush with the upper surface of the insulating layer. The first outer circuit pattern is located lower than the upper surface of the insulating layer, and the side surface of the first outer circuit pattern is located lower than the upper surface of the insulating layer. covered with a layer.

[0023] The first molding layer also includes an open area, and the open area includes the The first element is exposed.

[0024] The first outer circuit pattern protrudes above the upper surface of the insulating layer, and the first molding the first opening of the first molding layer is exposed through the open area of ​​the first molding layer. The bottom surface of the open area is located higher than the lower surface of the first outer circuit pattern.

[0025] The first open area of ​​the first molding layer is also formed by the first outer circuit pattern. The first portion has a height of: The height of the second portion is different. [Effects of the Invention]

[0026] According to the embodiment, the first connection portion is formed by a UBM (Under Bump Metal) of the first element. ) is formed on the first circuit pattern of the circuit board. At this time, the first connecting portion is The seed metal layer formed for electroplating the first circuit pattern is used as a seed layer. According to this, in the embodiment, the first circuit pattern can be formed by electroplating. The first connection portion is formed using a seed metal layer, The bonding strength between the first circuit pattern and the first connecting portion can be improved. In the embodiment, the first connecting portion is formed on the first circuit pattern, thereby A first circuit pattern having an embedded trace substrate structure In the embodiment, there is an advantage that it is not necessary to control the embedding depth of the first element and the circuit board. When assembling the board, the embedding depth of the first circuit pattern in the comparative example changes. Non-contact or non-wet issues caused by (non-wet issue) problem can be solved.

[0027] In addition, in the embodiment, there is no need to control the embedding depth of the first circuit pattern. The spacing between the connecting portions or the spacing between the first circuit patterns can be reduced, resulting in fine pitch In addition, in the embodiment, the size width and spacing of the first connecting portion can be reduced. It can be used for fine bump products, and this allows for greater design freedom through space savings. It can be secured.

[0028] In the embodiment, the first connecting portion is disposed on the upper side of the insulating layer, and the second connecting portion is disposed on the lower side of the insulating layer. This allows the balance between the top and bottom of the package board to be the same. This can improve the warpage characteristics of the package substrate.

[0029] In the embodiment, the attachment of the element and the main board is performed by the first connecting portion and the second connecting portion. This ensures a higher collapse height for the solder balls than the solder ball bonding method. Since there is no need for solder balls, the volume of the product can be reduced. The first and second connecting parts have higher thermal conductivity than the conventional ones, allowing for easier attachment of the elements and main board. This improves the heat transfer characteristics of the heat generated in the device and the motherboard in the embodiment. This can improve the heat dissipation characteristics.

[0030] In the embodiment, a first post bump constituting a second connection portion is formed on the circuit board, and By using post bumps to attach the main board to the package substrate, It can accommodate fine pitches, thereby maximizing productivity for manufacturers. do.

[0031] In the embodiment, elements are mounted on both sides of the circuit board, and the mounted elements are used as a module. By placing a molding part to be attached, the existing cross-section molding structure can be Compared to the conventional structure, it is possible to maintain the balance between the upper and lower parts of the printed circuit board. This can minimize the occurrence of warping.

[0032] Furthermore, according to the embodiment, by mounting elements on both sides of the circuit board, All active and passive elements that are currently mounted in the upper package are mounted on the circuit board. This allows the overall thickness of the package substrate to be reduced.

[0033] In addition, according to this embodiment, the lower surface of the lower molding part to which the main board is attached is , by placing it on the same plane as the lower surface of the element mounted on the lower part of the circuit board. This can improve the connection reliability between the main board and the circuit board.

[0034] In the embodiment, the second post bumps constituting the second connecting portions are embedded in the circuit board. The embedded device is connected to the main board. By using a plurality of second post bumps corresponding to the pitch of the terminals of the attached element, In the embodiment, the second post bumps are connected to the front end of the wiring board via the second post bumps. The device is connected to the main board, which improves heat dissipation. In the embodiment, the embedded element and the main bump are connected via the second post bump. By connecting the embedded device to the main board, the signal transmission distance between the embedded device and the main board can be increased. This can reduce noise and improve transmission speed. can.

[0035] Furthermore, according to this embodiment, the height of the first post bump can be adjusted by the height of the element. This makes it easy to design the package.

[0036] According to the embodiment, the first and second post bumps constituting the second connecting portion are electrically plated. The post bump is formed using the seed layer of the pad without forming a separate seed layer for the bump. This allows forming a separate seed layer for forming the post bumps. Since there is no need to form a seed layer for the post bump, the manufacturing process can be simplified. This solves the problem of cracks occurring between the parts, thereby improving the reliability and durability of the product. can be improved. [Brief explanation of the drawings]

[0037] [Figure 1] FIG. 10 is a diagram showing a package substrate according to a comparative example. [Figure 2] FIG. 2 is a diagram showing a package substrate of a first form according to the first embodiment. [Figure 3] FIG. 10 is a diagram showing a package substrate of a second type according to the first embodiment. [Figure 4] FIG. 10 is a diagram showing a package substrate of a third form according to the first embodiment. [Figure 5] 5A to 5C are diagrams showing a method for manufacturing the substrate shown in FIG. 4 in the order of steps. [Figure 6] 5A to 5C are diagrams showing a method for manufacturing the substrate shown in FIG. 4 in the order of steps. [Figure 7] 5A to 5C are diagrams showing a method for manufacturing the substrate shown in FIG. 4 in the order of steps. [Figure 8] 5A to 5C are diagrams showing a method for manufacturing the substrate shown in FIG. 4 in the order of steps. [Figure 9] 5A to 5C are diagrams showing a method for manufacturing the substrate shown in FIG. 4 in the order of steps. [Figure 10] 5A to 5C are diagrams showing a method for manufacturing the substrate shown in FIG. 4 in the order of steps. [Figure 11] 5A to 5C are diagrams showing a method for manufacturing the substrate shown in FIG. 4 in the order of steps. [Figure 12] 5A to 5C are diagrams showing a method for manufacturing the substrate shown in FIG. 4 in the order of steps. [Figure 13] 5A to 5C are diagrams showing a method for manufacturing the substrate shown in FIG. 4 in the order of steps. [Figure 14] 5A to 5C are diagrams showing a method for manufacturing the substrate shown in FIG. 4 in the order of steps. [Figure 15] 5A to 5C are diagrams showing a method for manufacturing the substrate shown in FIG. 4 in the order of steps. [Figure 16] FIG. 10 is a diagram showing a printed circuit board according to a second embodiment. [Figure 17a] FIG. 17 shows an open area of ​​the first molding layer of FIG. 16 according to the first embodiment. [Figure 17b] FIG. 17 shows an open area of ​​the first molding layer of FIG. 16 according to the first embodiment. [Figure 18] FIG. 17 shows an open area of ​​the first molding layer of FIG. 16 according to the second embodiment. [Figure 19]2A to 2C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 1 in the order of steps. [Figure 20] 2A to 2C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 1 in the order of steps. [Figure 21] 2A to 2C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 1 in the order of steps. [Figure 22] 2A to 2C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 1 in the order of steps. [Figure 23] 2A to 2C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 1 in the order of steps. [Figure 24] 2A to 2C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 1 in the order of steps. [Figure 25] 2A to 2C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 1 in the order of steps. [Figure 26] 2A to 2C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 1 in the order of steps. [Figure 27] 2A to 2C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 1 in the order of steps. [Figure 28] 2A to 2C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 1 in the order of steps. [Figure 29] 2A to 2C are diagrams showing a method for manufacturing the printed circuit board shown in FIG. 1 in the order of steps. [Figure 30] FIG. 10 is a diagram showing a package substrate according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0038] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0039] However, the technical idea of ​​the present invention is not limited to the embodiments described. The present invention may be embodied in various different forms, and within the scope of the present invention. One or more of the components may be used in combination or substitution.

[0040] Furthermore, the terms used in the examples of the present invention (including technical and scientific terms) are for clarity. Unless otherwise clearly defined and described, a person having ordinary skill in the art to which the present invention pertains It is interpreted as meaning that is commonly understood by the The terms used can be interpreted in light of the contextual meaning of the relevant art. In addition, the terms used in the examples of the present invention are intended to explain the examples. and is not intended to limit the invention.

[0041] In this specification, the singular can also include the plural unless the context clearly dictates otherwise. In the case where it is stated as "A and (and) at least one (or more) of B and C" If the condition is met, it can contain one or more of all combinations of A, B, and C. In addition, in describing the components of the embodiment of the present invention, first, second, A, B, (a), Terms such as (b) can be used.

[0042] Such terms are used only to distinguish one component from another, The terms do not limit the nature, order, or procedure of the components. When an element is described as being "coupled," "coupled," or "connected" to another element, The components of the invention are not only directly connected to or connected with other components, but also to the components of the invention. "Connected," "coupled," or "bonded" between or by other components This may also include cases where the device is "connected."

[0043] It is also described as being formed or arranged "above (upper) or below (lower)" each component. If a component is in direct contact with another component, then the term upper (top) or lower (bottom) is used. However, if one or more other components are formed or disposed between the two components, In addition, when it is expressed as "upper (upper part) or lower (lower part)", it means that one component is the basis. As a criterion, it can include not only the upward direction but also the downward direction.

[0044] Hereinafter, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. .

[0045] FIG. 1 is a diagram showing a package substrate of a comparative example.

[0046] Referring to FIG. 1, the package substrate of the comparative example includes an insulating layer 10, a first circuit pattern 20, Second circuit pattern 25, via 30, first solder resist 40, second solder resist 4 5, first connection part 50, second connection part 55, element 60, UBM (Under Bump Meter) tal) 65, and a connecting portion 70.

[0047] The comparative example package substrate includes a circuit board manufactured by the ETS method.

[0048] Therefore, the paging substrate is made up of an insulating layer 10 and two insulating layers 10a and 10b arranged on both sides of the insulating layer 10. and a circuit pattern.

[0049] At this time, the circuit pattern is a first circuit pattern 20 disposed on one surface of the insulating layer 10. and a second circuit pattern 25 disposed on the other surface of the insulating layer 10. One of the pattern 20 and the second circuit pattern 25 has a structure embedded in the insulating layer 10. Has.

[0050] In the insulating layer 10, the first circuit pattern 20 and the second circuit pattern 25 are electrically connected. A via 30 is formed to connect to the

[0051] The upper and lower surfaces of the insulating layer 10 are provided with the surface of the insulating layer 10 and the first circuit pattern 20 or The first solder resist 40 and the second solder resist 42 protect the surface of the second circuit pattern 25. A resist 45 is placed.

[0052] The first solder resist 40 has an opening that exposes the upper surface of the first circuit pattern 20. The second solder resist 45 includes a hole (not shown) and covers the lower surface of the second circuit pattern 25. It includes an opening (not shown) through which it is exposed.

[0053] On the other hand, the package substrate of the comparative example has the element 60 mounted on the first circuit pattern 20. At this time, the lower surface of the element 60 is provided with an UBM (Under Bump Metal). ) 65 is formed. Also, under the UBM (Under Bump Metal) 65 The connecting portion 70 is generally made of copper filler. r).

[0054] In the package substrate of the comparative example, the element 60 is mounted by connecting the connecting portion 70 to the element 60, a first connection portion is formed between the first circuit pattern 20 and the connecting portion 70. This is done by forming 50.

[0055] That is, the device mounting in the package substrate of the comparative example is not on the circuit board but on the UB of the device 60. A connection part 70 is formed on the M (Under Bump Metal) 65, and the element is attached. Then, the connecting portion 70 of the element 60 and the first circuit pattern 20 of the circuit board are soldered. This is done by interconnecting them.

[0056] However, the structure of the connection portion included in the package substrate of the comparative example is Although it is possible to reduce the thickness, there are many restrictions on the device mounting space during design. The problem is that the warpage characteristics are weak.

[0057] Specifically, in the package substrate of the comparative example, a connecting portion 70 is formed on the element 60. In this case, the above-described connecting portion 70 is formed only on one side of the package substrate, and In other words, the package substrate of the comparative example does not have a corresponding connecting portion. The plate has an asymmetric structure in which the connecting portion is arranged only on one side of the insulating layer 10. However, the problem of poor warpage due to the imbalance between the top and bottom of the package substrate is a problem.

[0058] In addition, in the package substrate of the comparative example, when soldering to the element, the first circuit pattern The contact area between the first connecting portion 20 is reduced depending on the degree of embedding. There may be problems with the reliability of the connection with 50.

[0059] In addition, in the package substrate of the comparative example, the connection between the first circuit pattern 20 and the first connection portion 50 If the contact area is small, the possibility of cracks occurring due to thermal stress or physical damage increases. This can cause reliability problems.

[0060] As a result, the embodiment solves the reliability problem of the package substrate of the comparative example. This will enable the provision of a package substrate with a new structure that can

[0061] FIG. 2 is a diagram showing a package substrate of a first type according to an embodiment.

[0062] Referring to FIG. 2, the first type of package substrate 100 includes an insulating layer 110, a first circuit pattern, and a The first solder layer 120, the second circuit pattern 125, the via 130, the seed metal layer 140, the first solder layer 140, the second solder layer 150, the second solder layer 160, the second solder layer 170, the first solder layer 180, the second solder layer 190, the second solder layer 190, the second solder layer 190, the first solder layer 190, the second solder layer 190, the second solder The solder resist 160, the second solder resist 165, the first connecting portion 170, and the second connecting portion 17 5, a first connecting portion 180, and a second connecting portion 185.

[0063] In addition, the package substrate 100 of the first embodiment has a UBM (Under Bump Mount) on the bottom surface. The device includes a first element 200 and a second element 300 on which a dielectric film 210 is formed.

[0064] Before explaining FIG. 2, the package substrate according to the embodiment has a multi-layer structure based on the insulating layer of the circuit board. That is, the circuit board in FIG. 2 is shown to include a single insulating layer. For example, the package substrate in the embodiment may be made of a plurality of insulating layers. For example, the package substrate 100 may include a circuit board having a laminated structure. The insulating layer 110 can have a multi-layer structure. If the first circuit pattern 120 is provided, the first circuit pattern 120 is formed on the upper surface of the uppermost insulating layer of the insulating layers of the multi-layer structure. The second circuit pattern 125 may be disposed on the bottom layer of the insulating layer of the multi-layer structure. For example, the first circuit pattern 120 may be disposed on the uppermost side of the circuit board. It can also be said that the second circuit pattern is a first outer circuit pattern arranged on the first outermost side. The pattern 125 is a second outer circuit pattern disposed on the bottom or second outermost side of the circuit board. It can also be said that.

[0065] For the sake of convenience, the following description will be given assuming that the insulating layer 110 is formed as a single layer.

[0066] A circuit pattern may be disposed on the surface of the insulating layer 110 .

[0067] For example, a first circuit pattern 120 may be formed on the upper surface of the insulating layer 110. A second circuit pattern 125 may be formed on the lower surface of the edge layer 110 .

[0068] The first circuit pattern 120 may be embedded in the insulating layer 110. For example, the first circuit pattern 120 may be an ETS (Embedded Trace Substrate). For example, the side of the first circuit pattern 120 may have a front (or rear) structure. The first circuit pattern 120 may be surrounded by the insulating layer 110. For example, the upper surface of the first circuit pattern 120 may be It may be disposed on the same plane as the upper surface of the insulating layer 110, or may be lower than the upper surface of the insulating layer 110. For example, the lower surface of the first circuit pattern 120 may be disposed on the upper surface of the insulating layer 110. It can be positioned lower than the surface.

[0069] The second circuit pattern 125 may be disposed to protrude below the lower surface of the insulating layer 110. The upper surface of the second circuit pattern 125 may be in direct contact with the lower surface of the insulating layer 110. However, the embodiment is not limited thereto, and the upper surface of the second circuit pattern 125 and the insulating layer A seed metal layer (not shown) of the second circuit pattern 125 is disposed between the lower surface of the second circuit pattern 110 and the lower surface of the second circuit pattern 125. It can be placed.

[0070] That is, the package substrate in the embodiment is manufactured by the ETS method, and as a result, The first circuit pattern 120 may have a structure embedded in the insulating layer 110, and the second The circuit pattern 125 may have a protruding structure on the surface of the insulating layer 110 .

[0071] The first circuit pattern 120 and the second circuit pattern 125 transmit electrical signals. The wiring may be made of a metal material having high conductivity. The pattern 120 and the second circuit pattern 125 are made of gold (Au), silver (Ag), platinum (Pt), or titanium. (Ti), tin (Sn), copper (Cu), and zinc (Zn). The first circuit pattern 120 and the second circuit pattern 121 may be made of at least one metal material. The second circuit pattern 125 is made of gold (Au), silver (Ag), platinum (Pt), or the like, which have excellent bonding strength. Pt), titanium (Ti), tin (Sn), copper (Cu), zinc (Zn) The paste or solder paste may comprise at least one metallic substance. Preferably, the first circuit pattern 120 and the second circuit pattern 125 are electrically It can be made of copper (Cu), which has high conductivity and is relatively inexpensive.

[0072] On the other hand, the first circuit pattern 120 and the second circuit pattern 125 are each configured as a plurality of patterns. For example, the first circuit pattern 120 is connected to the first connection portion 170 through a first-1 circuit. The first circuit pattern 120 is formed on the first solder resist 160. For example, the second circuit pattern 1 may be covered by the first circuit pattern 2. 25 is a 2-1 circuit pattern on which the second connection portion 185 is arranged and the second element 300 is mounted. For example, the second circuit pattern 125 may include a second connecting portion 175. The second-2 circuit pattern may be included.

[0073] A via 130 may be disposed within the insulating layer 110. The via 130 may be disposed within the insulating layer 110. 0, which allows the circuit patterns arranged on different layers to be electrically connected to each other. They can be linked together.

[0074] That is, the via 130 is disposed in the insulating layer 110 and has an upper surface facing the first circuit pattern 120. The lower surface of the second circuit pattern 125 may be connected to the upper surface of the second circuit pattern 125 .

[0075] The via 130 is a via hole (not shown) formed in the insulating layer 110 . It may be formed by filling it with a material.

[0076] The metal material forming the via 130 is copper (Cu), silver (Ag), tin (Sn), gold ( One selected from the group consisting of Au, nickel (Ni), and palladium (Pd). The conductive material may be filled by electroless plating, electrolytic plating, screen printing, or the like. Screen Printing, Sputtering, Steaming Evaporation, Ink-Jet Printing, and Disfencing Any one of these methods or a combination thereof can be used.

[0077] A seed metal layer 140 is disposed on top of the insulating layer 110 .

[0078] The seed metal layer 140 is formed by electroplating the first circuit pattern 120. The seed metal layer 140 may be a seed layer used in the first connection step described later. This may be a seed layer used to form the portion 170 by electroplating. The seed metal layer 140 is a seed layer for the first circuit pattern 120 and is connected to the first connecting portion 17. 0 seed layer.

[0079] That is, the seed metal layer 140 is formed between the first circuit pattern 120 and the first connecting portion 170. The first circuit pattern 120 may be formed by using the seed metal layer 140. The first connection portion 170 may be formed by electroplating the first circuit panel. Electroplating was performed using the seed metal layer 140, which is the same seed layer as the turn 120. It can be formed by

[0080] The seed metal layer 140 may be formed by a chemical copper plating process. The insulating layer 110 may have a thin film shape and may be formed on the upper surface of the insulating layer 110. However, the embodiment is not limited thereto. The seed metal layer 140 is not formed on the carrier board (not shown) used in the manufacture of the circuit board. The copper foil layer (not shown) may be included in the printed wiring board.

[0081] At this time, the seed metal layer 140 is connected to the first circuit pattern 120 and the first connection portion 170. The first portion of the seed metal layer 140 includes a lower surface and a first portion disposed between the lower surface and the second portion. For example, the bottom and top surfaces of the first portion of the seed metal layer 140 may have the same width. The surface may have the same width as the top surface of the first circuit pattern 120. For example, The top surface of the first portion of the seed metal layer 140 has the same width as the bottom surface of the first connection portion 170. As a result, the first circuit pattern 120 and the seed metal layer 140 The first portion of the insulating layer 110 and the first circuit pattern 120 have a pillar shape. The projection 12 may be formed to protrude outward from the projection 12.

[0082] On the other hand, the seed metal layer 140 is formed by the first circuit pattern 120 and the first solder resist 160. and a second portion disposed between the seed metal layer and the second portion. The seed metal layer has the same width as the circuit pattern. The circuit pattern is formed by plating, and the electroplating process is completed. That is, the circuit pattern is disposed on the seed metal layer, and the above-mentioned When the formation of the circuit pattern is completed, the seed metal in the area where the circuit pattern is not formed is removed. The metal layer is removed so that the circuit pattern and the seed metal layer have the same width.

[0083] In contrast, in the embodiment, after the first solder resist 160 is formed, the seed The first connecting part 170 is formed using the metal layer 140. After the first solder resist 160 and the first connecting portion 170 are formed, The seed metal layer is removed in the uncovered areas. The second portion of the metal layer 140 may have a different width than the second circuit pattern 125. That is, the lower surface of the second portion of the seed metal layer 140 is directly in contact with the first circuit pattern 120. The upper surface of the second portion of the seed metal layer 140 is in contact with the first solder resist. 160. At this time, the second portion of the seed metal layer 140 is in direct contact with the The width of the first circuit pattern 120 may be larger than the width of the first circuit pattern 120. The second portion of the solder metal layer 140 has the same width as the first solder resist 160 that it contacts. For example, the seed metal layer 14 may have a width of 100 nm or less. The second portion of the 0 is larger than the width of the contacting first circuit pattern 120, and the contacting The width of the first solder resist 160 can be made smaller than the width of the first solder resist 160.

[0084] Thus, in the embodiment, the seed metal layer 140 is used to form the first circuit pattern 120 and The first connecting portion 170 is formed. This eliminates the need for a separate seed layer formation and removal process for the purpose of reducing the manufacturing process. It can be simplified.

[0085] In the embodiment, the seed metal layer 140 is used to form the first connecting portion 170. Therefore, the bonding strength between the first circuit pattern 120 and the first connecting portion 170 can be improved. That is, in the embodiment, after the seed metal layer 140 is formed, an electroplating process is performed. The first circuit pattern 120 is formed by dividing the first connecting portion 170. The seed metal layer 140 is used as a seed layer as it is. Then, a chemical copper plating process is performed on the first circuit pattern to form an additional seed metal layer. In this case, the bonding strength of the seed metal layer formed by the additional step is This is lower than the bonding strength between the first circuit pattern 120 and the seed metal layer 140. In the example, after the seed metal layer 140 is formed, a first circuit pattern having a thickness greater than that of the seed metal layer 140 is formed. The turn 120 is formed, whereas in the comparative example, after the circuit pattern is formed, This is because a seed metal layer having a small thickness is formed.

[0086] A first connection part 170 is formed on the top surface of the first portion of the seed metal layer 140 . The first connection portion 170 is formed in plurality on the seed metal layer 140 at regular intervals. The first connection part 170 may be a copper pillar. The first connection portion 170 is a UBM (Under Bump Metal) 2 of the first element 200. 10. Thus, the first connection part 170 may be connected to the seed metal layer 140. The first circuit pattern 1 may be formed to have a first width and a first interval. For example, the width and spacing of the first connecting portion 170 may be equal to or less than 10 μm. and a first spacing of 10 μm or less, and disposed on the top surface of the seed metal layer 140. It is possible.

[0087] The second connection portion 175 may be formed below the lower surface of the second circuit pattern 125. The second connecting portion 175 is formed on the lower surface of the insulating layer 110. The second connecting portion 175 may be disposed in an opening (not shown). The lower surface of the resist 165 may be formed with a protruding structure below it.

[0088] The second connecting portion 175 may be formed in a plurality of portions spaced apart from each other at regular intervals.

[0089] The second connecting portions 175 may be arranged to have a second width and a second interval. The second width may be larger than the first width of the first connecting portion 170. The spacing may be larger than the first spacing of the first connecting portion 170 .

[0090] A first connecting portion 180 may be disposed on an upper surface of the first connecting portion 170. A second connection portion 185 may be disposed on the lower surface of the connector 125 .

[0091] The first connecting portion 180 and the second connecting portion 185 have a circular or elliptical shape. It can be, but is not limited to, these.

[0092] The first connecting portion 180 and the second connecting portion 185 are made of silver copper (Cu), tin (Sn), or aluminum. Aluminum (Al), zinc (Zn), indium (In), lead (Pb), antimony (S b) ), bismuth (Bi), silver (Ag), nickel (Ni) containing at least one of For example, the first connecting portion 180 and the second connecting portion 185 may be made of solder. For example, the first connecting portion 180 and the second connecting portion 185 may be solder bumps. The adhesive layer may be a thicker ball, which will melt at the temperature of the reflow process.

[0093] The first element 200 may be attached on the first connection part 180. Below the portion 185, a second element 300 may be attached.

[0094] At this time, a UBM ( That is, the first element 200 may be formed with an Under Bump Metal 210. On the underside of the substrate, a UBM (Under Bump Metal) 210 is formed. The first element 200 is located at the position of the UBM (Under Bump Metal) 210. The soldering process is performed while the device is aligned on the first connecting portion 180. The adhesive layer 170 may be attached to the surface of the adhesive layer 170 .

[0095] According to the embodiment, the first connection part is a UBM (Under Bump Metal) of the first element. l), the first connecting portion is formed on the first circuit pattern of the circuit board. a seed metal layer formed for electroplating the first circuit pattern as a seed layer; According to this, in the embodiment, the first circuit pattern can be formed by electroplating. The first connection portion is formed using the seed metal layer. The bonding strength between the first circuit pattern and the first connecting portion can be improved. In the embodiment, the first connecting portion is formed on the first circuit pattern, thereby A first circuit pattern having an embedded trace substrate structure In the embodiment, there is an advantage that it is not necessary to control the embedding depth of the first element and the second element. When assembling the circuit board, the embedding depth of the first circuit pattern in the comparative example changes. Non-contact or non-wet contact occurs when This can solve the problem of shoe (non-wet issue).

[0096] In addition, in the embodiment, there is no need to control the embedding depth of the first circuit pattern. The spacing between the connecting portions or the spacing between the first circuit patterns can be reduced, resulting in fine pitch In addition, in the embodiment, the size width and spacing of the first connecting portion can be reduced. It can be used for fine bump products, which allows for greater freedom of design through space conservation. can be secured.

[0097] In the embodiment, the first connecting portion is disposed on the upper side of the insulating layer, and the second connecting portion is disposed on the lower side of the insulating layer. This allows the balance between the top and bottom of the package board to be the same. This can improve the warpage characteristics of the package substrate.

[0098] In the embodiment, the attachment of the element and the main board is performed by the first connecting portion and the second connecting portion. This ensures a higher collapse height for the solder balls than the solder ball bonding method. Since there is no need for solder balls, the volume of the product can be reduced. The first and second connecting parts have higher thermal conductivity than the conventional ones, allowing for easier attachment of the elements and main board. This improves the heat transfer characteristics of the heat generated in the device and the motherboard in the embodiment. This makes it possible to improve the heat dissipation characteristics.

[0099] FIG. 3 is a diagram showing a package substrate of a second type according to the embodiment.

[0100] Referring to FIG. 3, the package substrate further includes a molding layer compared to FIG. 2. It is possible.

[0101] That is, the second type package substrate 100B has a first molding layer 190 and a second It includes a molding layer 195 .

[0102] The first molding layer 190 is formed on the top surface of the insulating layer 110 and the first solder resist 16. 0.

[0103] The first molding layer 190 is disposed over the insulating layer 110. That is, the first molding layer 190 may be disposed on the top surface of the insulating layer 110. The seed metal layer 140, the first solder resist 160, the first connecting portion 170, the first connecting portion 1 80, the first element 200, and the UBM (Under Bump Metal) 210 are buried. It can be formed by inlaying.

[0104] As described above, the first molding layer 190 is formed by embedding the first solder resist 160. It can be formed by

[0105] A second molding layer 195 is disposed over the structure disposed below the insulating layer 110. That is, second molding layer 195 may be disposed below the lower surface of insulating layer 110. The second coupling portion 175, the second connecting portion 185, and the second element 300 may be embedded. However, the second molding layer 195 exposes the lower surface of the second connecting portion 175. It may include an opening (not shown).

[0106] FIG. 4 is a diagram showing a package substrate of a third embodiment according to the present invention.

[0107] Referring to FIG. 4, the package substrate may further include a lower substrate compared to FIG. Cut.

[0108] That is, the package substrate 100C of the third embodiment has a third connection portion 410 and a lower substrate 400. may include:

[0109] The third connecting portion 410 may be a solder ball. The second connecting portion 175 may be formed below the lower surface of the second connecting portion 175 exposed through the opening in the sealing layer 195 .

[0110] A lower substrate 400 may be attached below the third connection portion 410. The lower substrate 400 can be, but is not limited to, a main board.

[0111] For example, the lower substrate 400 may be used to configure an active antenna system in a 5G package substrate. The antenna board, the antenna power supply board, the transceiver (transceiver) ver) board and baseband board do.

[0112] The method for manufacturing a package substrate according to the embodiment will be described below in the order of steps.

[0113] 5 to 15 are diagrams showing the manufacturing method of the manufacturing substrate shown in FIG. 4 in the order of steps.

[0114] Referring to FIG. 5, the embodiment is preferably made of a ceramic substrate, which is a base material for the manufacture of a circuit board. A rear board CB is prepared. The carrier board CB includes a carrier insulating layer CB1 and the carrier insulating layer CB2. The carrier insulating layer CB1 may include a carrier metal layer CB2 disposed on one side of the carrier insulating layer CB1. In this case, the carrier metal layer CB2 is disposed on only one side of the carrier insulating layer CB1. However, the present invention is not limited to this. That is, the carrier metal layer is a carrier insulating layer CB 1, and the upper and lower surfaces of the carrier 1 may be formed, respectively, so that, in the embodiment, Multiple circuit boards could be fabricated simultaneously on both sides of the insulating layer CB1.

[0115] Next, referring to FIG. 6, in the embodiment, a seed metal layer 14 is formed under the carrier metal layer CB2. The seed metal layer 140 may be formed by a chemical copper plating process. Not limited to.

[0116] After the seed metal layer 140 is formed, in the embodiment, a second metal layer is formed on the seed metal layer 140. In this embodiment, the first mask M1 is exposed and developed. The first mask M1 is then subjected to a masking process to form an opening (not shown) in the first mask M1. The lower surface of the seed metal layer 140 is exposed at a position where the first circuit pattern 120 is to be formed. It can be formed by extruding.

[0117] After the first mask M1 is formed, in an embodiment, the seed metal layer 140 is Electroplating is performed as the first mask M1 to form a first circuit pattern 1 that fills the open portions of the first mask M1. Form 20.

[0118] Next, referring to FIG. 7, in an embodiment, the first mask M1 is removed, thereby An insulating layer 110 is formed under the seed metal layer 140 to cover the first circuit pattern 120 .

[0119] Once the insulating layer 110 is formed, in an embodiment, a via 130 is formed in the insulating layer 110. In addition, in the embodiment, a second circuit connected to the via 130 is formed on the lower surface of the insulating layer 110. A pattern 125 is formed.

[0120] The second circuit pattern 125 may be disposed to protrude below the lower surface of the insulating layer 110. The upper surface of the second circuit pattern 125 can be in direct contact with the lower surface of the insulating layer 110. However, the embodiment is not limited thereto, and the upper surface of the second circuit pattern 125 and the insulating Between the lower surface of the layer 110 and the seed metal layer (not shown) of the second circuit pattern 125 It can be arranged.

[0121] That is, the package substrate in the embodiment is manufactured by the ETS method, and as a result, The first circuit pattern 120 may have a structure embedded in the insulating layer 110, and the second The circuit pattern 125 may have a protruding structure on the surface of the insulating layer 110 .

[0122] That is, the via 130 is disposed in the insulating layer 110 and has an upper surface facing the first circuit pattern 120. The via may be connected to the bottom surface of the second circuit pattern 125, and the bottom surface may be connected to the top surface of the second circuit pattern 125. 130 is a via hole (not shown) formed in the insulating layer 110 filled with a metal material. It can be formed by:

[0123] Next, referring to FIG. 8, in an embodiment, a second solder layer is formed below the lower surface of the insulating layer 110. The second solder resist 165 is formed on the second circuit pattern 125. The insulating film may have an opening that opens the portion of the lower surface that should be exposed.

[0124] Next, referring to FIG. 9, a second mask M is formed under the lower surface of the second solder resist 165. The second mask M2 forms the second connecting portion 175 through an exposure and development process. An opening (not shown) exposes the lower surface of the second circuit pattern 125 at the position where the may contain (but not limited to)

[0125] When the openings of the second mask M2 are formed, the exposed portions are A second connection part 175 is formed under the lower surface of the second circuit pattern 125 .

[0126] Next, referring to FIG. 10, in the embodiment, the step of removing the second mask M2 and the step of A step of removing the carrier board CB can be performed. After the process is completed, the seed layer used as the seed layer of the first circuit pattern 120 is The top surface of the metal layer 140 may be exposed.

[0127] Next, referring to FIG. 11, in an embodiment, a first solder layer is formed on the seed metal layer 140. The first solder resist 160 may be formed by An opening (not shown) is formed on the upper surface of the seed metal layer 140 to expose the area. may contain (but not limited to)

[0128] Next, referring to FIG. 12, in the embodiment, the first solder resist 160 and the A process of forming a third mask M3 on the seed metal layer 140 may be performed. The third mask M3 is formed by exposing and developing the first connecting portion 170. 1. The seed metal layer 140 may include an opening (not shown) exposing the top surface of the seed metal layer 140. do.

[0129] Then, when the openings of the third mask M3 are formed, the exposed portions are exposed through the openings. Electroplating is performed on the upper surface of the exposed seed metal layer 140 to form the first connecting portion 170. At this time, the first connection part 170 can be formed by using the seed metal layer 140 as a seed layer. The seed metal layer 140 can be formed by electroplating the first metal layer 140 as described above. It is also used as a seed layer for the wiring pattern 120. In the embodiment, the seed metal layer 140 is The first circuit pattern 120 and the first connecting portion 170 are formed on both sides of the first circuit pattern 120. To do so.

[0130] Next, referring to FIG. 13, in an embodiment, the third mask M3 is removed, thereby 1. The solder resist 160 and the first connecting portion 170 are not formed in the region. A step of removing the metal layer 140 can be performed.

[0131] Next, referring to FIG. 14, in the embodiment, a first connecting portion 180 is provided on the first connecting portion 170. In the embodiment, a step of attaching the first element 200 can be performed by placing the second element 200. Under the lower surface of the second circuit pattern 125 exposed through the opening of the solder resist 165 A process of disposing the second connection portion 185 and attaching the second element 300 can be performed.

[0132] Referring now to FIG. 15, in an embodiment, a first molding layer 190 and a second molding layer 191 are provided. A step of forming a bonding layer 195 can be performed.

[0133] The first molding layer 190 is formed on the top surface of the insulating layer 110 and the first solder resist 16. The first molding layer 190 may be formed on the upper surface of the insulating layer 110. That is, the first molding layer 190 may be disposed over the insulating layer 190. The seed metal layer 140, the first solder resist 160, and the first The coupling portion 170, the first connection portion 180, the first element 200, and the UBM (Under Bum As described above, the first molding The layer 190 may be formed by embedding the first solder resist 160 .

[0134] A second molding layer 195 is disposed over the structure disposed below the insulating layer 110. That is, second molding layer 195 may be disposed below the lower surface of insulating layer 110. The second coupling portion 175, the second connecting portion 185, and the second element 300 may be embedded. However, the second molding layer 195 exposes the lower surface of the second connecting portion 175. It may include an opening (not shown).

[0135] In this embodiment, a third connection portion 410 is formed below the lower surface of the second connection portion 175. This can be used to perform the process of attaching the lower substrate 400 .

[0136] FIG. 16 is a diagram showing a circuit board according to the second embodiment.

[0137] The circuit board in the first embodiment was manufactured using the ETS method. The circuit board according to the second embodiment of No. 6 is a MSAP (Modified Semi-Additive ive Process) and SAP (Semi-Additive Process) ) can be manufactured by using one of the methods. In this case, each of the circuit patterns arranged on the outermost side has a structure protruding above the surface of the insulating layer. can have:

[0138] Referring to FIG. 16, the circuit board according to the embodiment includes a first insulating layer 1101, a second insulating layer 1102, and a second insulating layer 1103. 02, a third insulating layer 1103, a first circuit pattern 1111, a second circuit pattern 1112, 3 circuit pattern 1113, fourth circuit pattern 1114, first via 1121, second via 11 22, third via 1123, first element C1, second element C2, third element C3, first post band 1150, a second post bump 1160, a first connecting portion 1141, a second connecting portion 1142, a The first molding layer 1131 and the second molding layer 1133 are included. The stop bump 1150 and the second post bump 1160 are the same as the second connecting portion 175 of the first embodiment. For example, according to the second embodiment, the The second connecting portion may include a plurality of post bumps having different widths.

[0139] In the circuit board of the second embodiment, the first insulating layer 1101 may be a core substrate. The second insulating layer 1102 and the third insulating layer 1103 are respectively formed above and below the first insulating layer 1101. In this case, in the second embodiment, the number of insulating layers is three. However, the number of insulating layers in the second embodiment is not limited to one. It may consist of two or four layers, or alternatively, it may have four or more layers. Cut.

[0140] The surfaces of the first insulating layer 1101, the second insulating layer 1102, and the third insulating layer 1103 are covered with a circuit. The circuit pattern may be a first circuit pattern 1111, a second circuit pattern 1112, a a first circuit pattern 1112, a third circuit pattern 1113, and a fourth circuit pattern 1114; can be done.

[0141] The first circuit pattern 1111 may be disposed on the top surface of the first insulating layer 1101. The third circuit pattern 1113 may be disposed on the lower surface of the first insulating layer 1101. The fourth circuit pattern 1114 may be disposed on the top surface of the third insulating layer 1102. The third circuit pattern 1113 may be disposed on the bottom surface of the insulating layer 1103 of the circuit board. In the laminated structure, it can mean a circuit pattern arranged on the top surface of the uppermost insulating layer. For example, the third circuit pattern 1113 can also be referred to as a first outer circuit pattern. The fourth circuit pattern 1114 is the lowest insulating layer in the laminated structure of the insulating layers of the circuit board. For example, the fourth circuit pattern may refer to a circuit pattern disposed on the lower surface of the edge layer. The turns 1114 may also be referred to as a second outer circuit pattern disposed on the bottom insulating layer.

[0142] The third circuit pattern 1113 corresponding to the first outer circuit pattern is a second element C2 The fourth circuit pattern 1114 includes a first pad 1113a on which the The fourth circuit may include a second pad (not shown) on which the third element C3 is mounted. The pattern 1114 is arranged so as to overlap the first terminal T1 of the first element C1 in the vertical direction. It can include the 4-1 pattern and the 4-2 pattern other than this. The first post bump 1150 is formed on the fourth circuit pattern 1114. The second post bump 1160 is disposed under the lower surface of the fourth circuit pattern 11 It can be placed under pattern 4-1 out of 14.

[0143] At this time, the first pad 1113a is the first pad on which an element is mounted on the circuit board of the first embodiment. For example, the first circuit pattern 120 in the second embodiment can be The upper surface of the pad 1113a is provided with the first circuit pattern 120 in the first embodiment. A first connecting portion 170 can be arranged.

[0144] Vias are arranged in each of the insulating layers. Vias are formed in and through the second insulating layer 1102 and the third insulating layer 1103. It is possible.

[0145] Specifically, a first via 1121 is disposed in the first insulating layer 1101. A 1121 is a first circuit pattern 1111 disposed on the upper surface of the first insulating layer 1101. The first insulating layer 1101 is electrically connected to a second circuit pattern 1112 disposed on the lower surface thereof. To connect.

[0146] A second via 1122 is disposed in the second insulating layer 1102. The second via 1122 is a third circuit pattern 1113 disposed on the upper surface of the second insulating layer 1102; The first circuit pattern 1111 is electrically connected to the edge layer 1101 .

[0147] A third via 1123 is disposed in the third insulating layer 1103. The third via 1123 is a second circuit pattern 1112 disposed on the lower surface of the first insulating layer 1101; The fourth circuit pattern 1114 is electrically connected to the lower surface of the edge layer 1103 .

[0148] A first element C1 is embedded in the first insulating layer 1101. The first element C1 is embedded in the insulating layer 1101 and at least a portion of which is below the lower surface of the first insulating layer 1101 For example, the first element C1 includes a first terminal T1. The first terminal T1 of the terminal C1 may be disposed to protrude below the lower surface of the first insulating layer 1101. As a result, at least a part of the first terminal T1 of the first element C1 is connected to the third insulating layer 1103. It may be covered by

[0149] For example, the upper surface of the first terminal T1 of the first element C1 is It can be flush with the top surface.

[0150] As a result, the first terminal T1 of the first element C1 is disposed within the third insulating layer 1103. As described above, the first terminal T1 of the first element C1 can be directly connected to the third via 1123. The third via is directly connected to the first terminal T1 of the first element C1 without any additional connecting pad. 1123 is connected to the first element C1 in this embodiment. The wiring length of the transmitted electrical signal can be minimized, thereby improving transmission speed. Also, noise characteristics can be improved.

[0151] The first element C1 may be an electronic component such as a chip, which may be divided into active elements and passive elements. An active element is an element that actively uses a nonlinear part, and a passive element is an element that actively uses a nonlinear part. It means an element that has both linear and nonlinear characteristics but does not use nonlinear characteristics. The active element may include a transistor, an IC semiconductor chip, etc. The passive elements may include capacitors, resistors, and the inductors. Active elements are used to increase the signal processing speed of semiconductor chips or to provide filtering functions. etc. can be done.

[0152] The second element C2 is mounted on the second insulating layer 1102. On the first pad 1113a of the third circuit pattern 1113 arranged on the upper surface of O2, The second element C2 is mounted on the second insulating layer 1102. The second insulating layer 1102 is the first outermost insulating layer among the plurality of insulating layers. The second element C2 is also referred to as the first outer insulating layer arranged on the uppermost side. It may be disposed on the first outer insulating layer.

[0153] Specifically, the first pad 1113a of the third circuit pattern 1113 has a first connection portion 1113b. The second element C2 is connected to the first connecting portion 1141 via the first connecting portion 1141. The first connection portion 1141 is electrically connected to the first pad 1113a. The first connecting portion 1141 may include a material of a different component in the solder. The solder is at least one of SnCu, SnPb, and SnAgCu. The heterogeneous material may be Al, Sb, Bi, Cu, Ni , In, Pb, Ag, Sn, Zn, Ga, Cd, and Fe. can.

[0154] A first molding layer 1131 is disposed on the second insulating layer 1102. A first molding layer 1131 is disposed on the top surface of the second insulating layer 1102. Preferably, the first molding layer 1131 covers the entire upper surface of the second insulating layer 1102. For example, a part of the upper surface of the second insulating layer 1102 is disposed over the third circuit pattern. The remaining part of the upper surface of the second insulating layer 1102 is in contact with the 1 contacts molding layer 1131.

[0155] The first molding layer 1131 is made of EMC (Epoxy molding compound). The range may be, but is not limited to, a sphere.

[0156] The first molding layer 1131 includes an open area 1132. The first molding layer 1131 is formed on the second insulating layer 1102 in an upper region thereof. The element C2 is disposed in an open area 1132. The second element C2 is located in the open area 1132 of the first molding layer 1131. 3 may be mounted on the first pad 1113 a of the circuit pattern 1113 .

[0157] The third element C3 is mounted under the third insulating layer 1103. Specifically, On the second pad (not shown) of the fourth circuit pattern 1114 arranged on the lower surface of 103 The third element C3 is mounted.

[0158] Specifically, a second connection portion 1142 is provided under the second pad of the fourth circuit pattern 1114. The third element C3 is connected to the second pad 1142 via the second connecting portion 1142. The second connection portion 1142 may be a solder ball. The two connection portions 1142 may contain materials of different components in the solder.

[0159] A second molding layer 1133 is disposed under the third insulating layer 1103. A second molding layer 1133 is disposed over the lower surface of the third insulating layer 1103 . The second molding layer 1133 is made of EMC (Epoxy molding compound). nd), but is not limited to this.

[0160] The second molding layer 1133 may be formed to expose the bottom surface of the third element C3. That is, the second molding layer 1133 covers the side and top surfaces of the third element C3. In this case, the terminal (not shown) of the third element C3 is disposed on the upper surface, As a result, the second connection portion 1142 and the terminal of the third element C3 are connected to the second mold The substrate may be covered by a coating layer 1133 .

[0161] The second molding layer 1133 is formed under the third insulating layer 1103 to a predetermined thickness. In this case, the lower surface of the second molding layer 1133 may be The lower surface of the third element C3 can be positioned on the same plane. The bottom surface of the third element C3 may be exposed to the outside. The gas can be released to the outside through the hole.

[0162] Meanwhile, the lower surface of the second molding layer 1133 is provided with the first post bumps 1150 and The second post bump 1160 may be positioned lower than the lower surface of the second post bump 1160. The bonding layer 1133 is connected to the first post bump 1150 and the second post bump 116. 0 is formed so that the bottom surface of the first post bump 1150 and the second post bump 1151 are exposed. The lower surface of the post bump 1160 is formed in the open area of ​​the second molding layer 1133. A mounting point may be formed, which will then be used for connection to the main board. The solder balls can be placed in precise positions, improving reliability. Cut.

[0163] A first post bump 1150 and a second post bump 1151 are formed under the lower surface of the fourth circuit pattern 1114. A post bump 1160 is disposed. The first post bump 1150 and the second post bump The amplifier 1160 may be a connector for connecting to an external main board.

[0164] The first post bump 1150 and the second post bump 1160 are Formed using a plating seed layer (not shown) used to form pattern 1114 As a result, in the embodiment, the first post bump 1150 and the second post bump The separate seed layer for forming the first post 1160 may be omitted. The top bump 1150 and the second post bump 1160 are formed on the lower surface of the third insulating layer 1103. It may be placed in direct contact with the fourth circuit pattern 1114 placed thereon.

[0165] That is, in the embodiment, the first and second post bumps 150, 160 and the fourth circuit pattern 1 114, a seed layer for electroplating is not formed between the fourth circuit pattern 1114. The first post bump 1114 is formed on the fourth circuit pattern 1114 using the seed layer formed thereon. 150 and the second post bump 1160 are formed. This allows for the omission of a separate seed layer for the post bump shape, thereby improving the manufacturing process. In the embodiment, a separate process for electroplating the post bumps can be used. When forming the seed layer, the cladding between the separate seed layer and the post bump is This solves the problem of crack generation, thereby improving the reliability and durability of the product. It is possible.

[0166] That is, in the circuit board of the first embodiment, the second connecting portion includes only one post bump. In contrast, the second connecting portions in the circuit board of the second embodiment have different widths. A first post bump 1150 and a second post bump 1160 may be included.

[0167] The first post bump 1150 may have a first width W1. The first width W1 of the one-post bump 1150 is in the range of 150 μm to 300 μm. For example, the first width W1 of the first post bump 1150 is 170 μm. For example, the first post bump 1150 can satisfy the range of 100 μm to 280 μm. The first width W1 can be in the range of 200 μm to 250 μm. If the width of the stop bump 1150 is smaller than 150 μm, the main board 1200 will not function properly. In addition, if the width of the first post bump 1150 is 300 μm, the support may become impossible. If it is larger than , the volume of the circuit board in the longitudinal direction may increase.

[0168] The second post bump 1160 may have a second width W2. The second width W2 of the stop bump 1160 may be in the range of 50 μm to 120 μm. For example, the second width W2 of the second post bump 1160 is 70 μm to 110 μm. For example, the second post bump 1160 may have a thickness of 0 μm. The width W2 of the second post bump can be in the range of 80 μm to 100 μm. If the width of 1160 is smaller than 50 μm, the adjacent second post bumps In addition, the second post bump 1160 may not be able to stably support the board. If the width is greater than 120 μm, the volume of the circuit board in the longitudinal direction may increase.

[0169] In the embodiment, as described above, the second connecting portion connected to the main board is provided with different A first post bump 1150 and a second post bump 1160 having different widths are formed. That is, in the comparative example, the second connecting portion includes only the first post bump. The thickness of the circuit board in the longitudinal direction is increased. In addition, the second post bump is also formed together with the first post bump, This allows the support of different main boards, thereby reducing the length of the circuit board. This allows the volume to be reduced.

[0170] The second post bump 1160 is a first element embedded in the first insulating layer 1101. It may be a bump connected to C1.

[0171] For example, the second post bump 1160 is connected to the fourth circuit pattern 1114 and the third via 1115. 23 may be a bump directly connected to the first terminal T1 of the first element C1. For example, the second post bump 1160 is arranged so as to overlap the first element C1 in the vertical direction. For example, the second post bump 1160 may be a bump positioned forward in the vertical direction. It may be disposed so as to overlap the first terminal T1 of the first element C1.

[0172] As described above, in the embodiment, the second post bumps 1160 are used to connect the first element C1 and the metal In this case, the comparative example uses solder balls. The first element and the main board are connected by the solder balls. Due to its characteristics, there is a limit to how fine pitches can be accommodated, so additional interconnect wiring is used to connect the solder. -We had to create space for the ball to form.

[0173] Alternatively, in this embodiment, a second post bump 1160 is used to connect the first element and the main In this embodiment, the first terminal T1 of the first element C1 is connected to the board. By using a plurality of second post bumps 1160 corresponding to the pitch of In the embodiment, the second post bump 1160 can be used to The first element C1 is connected to the main board, which improves heat dissipation characteristics compared to the comparative example. In the embodiment, the first element is connected to the second post bump via the second post bump. Since the first element C1 is connected to the main board, the signal between the first element C1 and the main board is This reduces the signal transmission distance, thereby improving the characteristics and increasing the transmission speed. It is possible.

[0174] The open area 1132 of the first molding layer 1131 according to the embodiment will be described below. This will be explained in detail.

[0175] FIG. 17 is a diagram illustrating an open area of ​​the first molding layer of FIG. 2 according to the first embodiment. 18 is a diagram showing an open area of ​​the first molding layer of FIG. 2 according to a second embodiment. be.

[0176] At this time, the structure of the first molding layer described below is the same as that of the first molding layer shown in FIG. The same would be applicable to the coating layer 190.

[0177] The open area 1132 of the first molding layer 1131 is in contact with the second insulating layer 110. 2, the region where the second element C2 is disposed can be opened.

[0178] At this time, the open area 1132 of the first molding layer 1131 is The first pad 1113a may be formed to cover the upper surface of the edge layer 1102 and expose the first pad 1113a.

[0179] As a result, even in the open region 1132, the upper surface of the second insulating layer 1102 That is, in a general cavity, the upper surface of the second insulating layer is also exposed. In contrast to this, in the embodiment, the open area 1132 is The upper surface of the second insulating layer 1102 is covered while the first pad 1113a is selectively exposed. In this way, reliability can be improved.

[0180] That is, the first molding layer 1131 is a first molding layer that forms the open region 1132. The first portion includes a first part and a second part other than the first part.

[0181] The first portion exposes a first pad 1113a on which the second element C2 is mounted. It can be formed as follows.

[0182] The upper surface of the first portion may have a step. The first portion of the layer 1131 may form steps having different heights depending on the position. For example, the upper surface of the first portion of the first molding layer 1131 may have a certain surface roughness. In this case, the first portion of the first molding layer 1131 may have a thickness of 1 / 2 mm. The surface roughness of the surface is not obtained by processing the surface through an additional process. The first molding layer 1131 is formed with the jig in place. The upper surface of the first portion can have a certain surface roughness.

[0183] The first portion of the first molding layer 1131 is a portion 1-1 corresponding to an edge region. and a first and second portion corresponding to the inner region.

[0184] At this time, the upper surface S1 of the first molding layer 1131 is in contact with the first The upper surface S2 of the first and second portions of the molding layer 1131 may have different heights. can.

[0185] For example, the upper surface of the first portion of the first molding layer 1131 is For example, the first molding layer may have a thickness that varies from the first molding layer to the first-second portion. The upper surface of the first portion of 1131 decreases in height as it moves away from the inner wall of the open area 1132. This may happen.

[0186] For example, the depth of the open area 1132 of the first molding layer 1131 is It may increase as you go up.

[0187] In this embodiment, a square jig is used to form the open area 1132. 1132, the inner wall of the open area 1132 is in contact with the upper surface of the second insulating layer 1102. Preferably, the upper and lower widths of the open area 1132 are equal to each other. It may be identical to.

[0188] The first molding layer 1131 may have a second height H2. In addition, the first molding layer 1131 has a first-second portion that is higher than the second height H2. The third height H3 may be smaller than the first height H1.

[0189] That is, the first pad 1113a is formed on the upper surface of the second insulating layer 1102 at a first height H1. The first molding layer 1131 may have a first portion 1-1. The top surface of the first pad 1113a must be exposed, so that the first pad 1113a The second height H2 may be smaller than the first height H1 of the first portion 113a.

[0190] The first molding layer 1131 has a first-second portion 1-2 that is larger than the second height H2. The third height H3 may be small. The 1-2 portion is closer to the first pad 111 than the 1-1 portion having the second height H2. It may be arranged adjacent to 3a.

[0191] Meanwhile, as shown in FIG. 17, the first molding layer 1131 and the first The upper surfaces S1 and S2 of the two sections may have the same height over the entire area. For example, the upper surface S1 of the 1-1 portion of the first molding layer 1131 may be flat. For example, the upper surface S1 of the 1-1 portion of the first element C1 has the same height as each other throughout the entire area. For example, the upper surface S2 of the first molding layer 1131 at the first-2 portion may be For example, the upper surface S2 of the first element C1 in the first-2 portion may be can have the same height.

[0192] 18, the first molding layer 1131 has a first-1 portion. The height of each of the upper surfaces S1 and S2 of the first and second portions changes from the outside to the inside. This may happen.

[0193] Meanwhile, the second height H2 may have a level equal to or less than 95% of the first height H1. At this time, the first upper surface S1 of the first molding layer 1131 and the second upper surface S2 of the first-1 portion of the first molding layer 1131 are in contact with each other. The second upper surface S2 of the 1-2 portion may have different heights at different positions. Therefore, the second height H2 may refer to the average height of the first upper surface S1. In addition, differently from this, the second height H2 is the maximum height among the heights at each position of the first upper surface S1. can also mean a large height value.

[0194] The upper surface S1 of the 1-1 portion may become lower from the outside to the inside. The upper surface S1 of the first-1 portion has the maximum height at the portion closest to the inner wall. For example, the upper surface S1 of the 1-1 portion is adjacent to the upper surface S2 of the 1-2 portion. The contact portion may have a minimum height.

[0195] The upper surface S2 of the 1-2 portion has a height smaller than the upper surface S1 of the 1-1 portion. 1113a and may be located between the first pads 1113a.

[0196] At this time, the upper surface S2 of the 1-2 portion is smaller than the upper surface S1 of the 1-1 portion. Furthermore, the upper surfaces S2 of the first and second portions may be different from each other depending on the position. That is, the upper surface S2 of the first-second portion may have a third height. The height H3 may have different values ​​depending on the position.

[0197] Preferably, the height of the upper surface S2 of the first-second portion becomes lower from the outside to the inside. For example, the upper surface S2 of the 1-2 portion is located inside the first pad 1113a. The adjacent portion (or the portion adjacent to the upper surface of the first portion) has the maximum height. The upper surface S2 of the first-second portion has a minimum height at the center. That is, the upper surface S2 cross section of the first-second portion has a height that increases from the outside to the inside. The upper surface S1 of the first-1 portion may have a V-shape in which the upper surface S1 is gradually lowered. The surface may also have a V-shape that decreases in height from the outside to the inside. In this embodiment, when the second element C2 is mounted, the surface of the first pad 1113a is not exposed. Therefore, the connection failure of the second element C2 can be resolved, and the first pad 1 This can improve the reliability of the electrical connection between 113a and the second element C2.

[0198] 19 to 29 are diagrams showing the manufacturing method of the circuit board shown in FIG. 16 in the order of steps.

[0199] Referring to FIG. 19, in the embodiment, a process for manufacturing an inner layer substrate can be performed preferentially. do.

[0200] To manufacture the inner layer substrate, in this embodiment, a first insulating layer 1101 is prepared. In this example, a first circuit pattern 1111 is formed on the upper surface of the first insulating layer 1101. A process of forming a second circuit pattern 1112 on the lower surface of the edge layer 1101 may be performed. In the embodiment, the first circuit pattern 1111 and the second circuit pattern 1112 are formed in the first insulating layer 1101. A step of forming a first via 1121 connecting to the pattern 1112 can be performed.

[0201] Next, referring to FIG. 20, in the embodiment, a carrier ball is formed under the first insulating layer 1101. In the embodiment, a step of forming a CB can be performed. 1, a step of forming a cavity 1101a in the substrate 1 can be performed.

[0202] Next, referring to FIG. 21, in the embodiment, the cavity formed in the first insulating layer 1101 A step of embedding the first element C1 in the tee 1101a can be performed. is embedded in the first insulating layer 1101 and at least a part of the first insulating layer 1101 For example, the first element C1 includes a first terminal T1. The first terminal T1 of the first element C1 is disposed so as to protrude below the lower surface of the first insulating layer 1101. For example, the first terminal T1 of the first element C1 may be disposed within the carrier board CB. For example, the upper surface of the first terminal T1 of the first element C1 may be located on the second circuit pattern 1. It can be flush with the top surface of 112.

[0203] Next, referring to FIG. 22, in the embodiment, the second insulating layer 1101 is formed on the upper surface of the first insulating layer 1101. A step of forming an edge layer 1102 can be performed. The insulating layer 1102 may be covered by a second insulating layer 1102 .

[0204] Next, referring to FIG. 23, in this embodiment, a metal film is disposed on the lower surface of the first insulating layer 1101. For example, in the embodiment, the first The second circuit pattern 1112 protruding below the lower surface of the insulating layer 1101 and the first element C1 A step of removing the carrier board CB can be performed to expose the first terminal T1. do.

[0205] Next, referring to FIG. 24, in an embodiment, a third circuit pattern is formed on the upper surface of the second insulating layer 1102. In the embodiment, a step of forming a turn 1113 can be performed. 1102, the first circuit pattern 1111 and the third circuit pattern 1113 are connected to each other. At this time, a step of forming a second via 1122 through the second insulating layer 11 can be performed. The third circuit pattern 1113 formed on the upper surface of the second element C2 is a first circuit pattern for mounting the second element C2. Pad 1113a may be included.

[0206] In the embodiment, a fourth circuit pattern 1114 is formed on the lower surface of the third insulating layer 1103. In the embodiment, the second insulating layer 1103 may be formed in the second insulating layer 1103. A third via 1123 connecting the circuit pattern 1112 and the fourth circuit pattern 1114 is formed. At this time, the third via 1123 may be formed in the first insulating layer 1124. 1101 includes a via directly connected to the first terminal T1 of the first element C1 embedded in the The fourth circuit pattern 1114 can be used as a second pattern for mounting the third element C3. The device may include a head (not shown).

[0207] Next, referring to FIG. 25, in an embodiment, a mold chain is formed on the second insulating layer 1102. A process of placing a mold chase (MC) can be performed. The mold chase (MC) is a second insulating layer (1102) disposed on the upper surface of the second insulating layer (1102). 3. The first pad 1113a of the circuit pattern 1113 is connected to the second element C2. That is, the mold chase MC (mo The protrusions of the first pads 1113a of the third circuit pattern 1113 are It can be placed on top.

[0208] Next, referring to FIG. 26, in an embodiment, the front of the upper region of the second insulating layer 1102 The remaining area excluding the protruding part of the mold chase MC is filled. While this is happening, a process of forming the first molding layer 1131 can be performed.

[0209] The first molding layer 1131 includes the mold chase MC. The open area 1132 corresponds to the protrusion of the The first molding layer 1131 in the region 1132 is formed on the second insulating layer 11 of the protrusion. The upper surface of the insulating film 02 may be formed by filling a part of the space between the upper surfaces of the insulating film 02.

[0210] Next, referring to FIG. 27, in an embodiment, the opening of the first molding layer 1131 The first connecting portion 1141 is disposed on the first pad 1113a exposed through the contact region 1132. In this embodiment, the first connecting portion 1141 is used to connect to the first pad 1113a. A step of mounting the second element C2 can be performed.

[0211] In the embodiment, the fourth circuit pattern 11 disposed on the lower surface of the third insulating layer 1103 A second connecting portion 1142 is disposed under the second pad of the first and second connecting portions 1142. Then, a step of mounting the third element C3 can be performed.

[0212] Specifically, the open area 1132 of the first molding layer 1131 is The region above the insulating layer 1102 where the second element C2 is to be disposed can be opened. At this time, the open area 1132 of the first molding layer 1131 is The second insulating layer 1102 may be formed to cover the upper surface of the second insulating layer 1102 and expose the first pad 1113a. .

[0213] As a result, the upper surface of the second insulating layer 1102 is also covered with the insulating film 1102 in the open region 1132. That is, in a general cavity, the upper surface of the second insulating layer is also exposed. In contrast to this, in the embodiment, the open area 1132 is The upper surface of the second insulating layer 1102 is covered while the first pad 1113a is selectively exposed. In this way, reliability can be improved.

[0214] Next, referring to FIG. 28 and FIG. 29, in the embodiment, the fourth circuit pattern 1114 The first post bump 1150 and the second post bump 1151 form the second connection portion below the lower surface of the In the embodiment, a step of forming the third insulating layer 1103 can be performed. The lower surface of the first post bump 1150 and the lower surface of the second post bump 1160 are forming a second molding layer 1133 covering the third element C3 while exposing the third element C3; It can be done.

[0215] FIG. 30 is a diagram illustrating a package substrate according to an embodiment.

[0216] Referring to FIG. 30, the package substrate in the embodiment is the first circuit board shown in FIG. The third connection portion 1220 is disposed below the post bump 1150 and the second post bump 1160. It can be done.

[0217] Further, a main board 1200 is connected below the circuit board via the third connection part 1220. At this time, the first post bumps 1100 may be attached to the top surface of the main board 1200. 150 and a pad directly connected to the second post bump 1160. Each of the above may include a code and a code.

[0218] The second post bumps 1160 are embedded in the first insulating layer 1101 of the circuit board. The second post bump 1160 is disposed so as to overlap the first element C1 in the vertical direction. The third via 1123 and the fourth circuit pattern 1114 are directly connected to the first element C1. Here, the direct connection means that the signal line connected to the terminal T1 of the first element C1 is directly connected to the terminal T2 of the first element C1. The third via 1123 and the fourth circuit pattern 1114 are not provided in the horizontal direction, but are provided in the vertical direction. It may mean that the second post bump 1160 is directly connected to the second post bump 1160 via the

[0219] The features, structures, effects, etc. described in the above embodiments may be included in at least one embodiment. The present invention is not necessarily limited to one embodiment. The advantages and effects of the present invention will be apparent to those skilled in the art from the perspective of the present invention. Therefore, the present invention is not limited to the above. The amount should be construed as being included in the scope of the examples.

[0220] Although the above description has been centered on the examples, these are merely examples and are not intended to limit the scope of the invention. The present invention is not intended to be limited to the above embodiments, and a person having ordinary skill in the art to which the present invention pertains can easily understand the present invention. Various modifications and applications not exemplified above are possible within the scope of the qualitative characteristics. For example, it will be understood that each component specifically shown in the embodiment may be modified. The differences between these modifications and applications are as follows: It should be construed as falling within the scope of the embodiments defined in the appended claims.

Claims

1. an insulating layer; a first outer circuit pattern disposed on the upper surface of the insulating layer; a second outer circuit pattern disposed on the lower surface of the insulating layer; a first connection portion disposed on an upper surface of the first-1 circuit pattern of the first outer circuit pattern; a first connection portion disposed on the first coupling portion; a first element disposed on the first coupling portion via the first connection portion; a second connection portion disposed on a lower surface of the 2-1 circuit pattern of the second outer circuit pattern; a second element attached to the second-1 circuit pattern via the second connection portion; a second connecting portion disposed on the lower surface of the second-2 circuit pattern of the second outer circuit pattern; Including, The first connecting portion is disposed with a first width and a first spacing; The second connecting portion has a second width greater than the first width and a second spacing greater than the first spacing. A package substrate is arranged with a gap therebetween.

2. a first solder layer disposed on the insulating layer and including a first opening exposing the first connecting portion; Resist and a second solder disposed on the lower surface of the insulating layer, the second solder joint and the second connecting portion being exposed; a photoresist; The first circuit pattern is a first-2 circuit pattern covered by the first solder resist. The package substrate of claim 1 , comprising a line.

3. a seed metal layer disposed between the first-1 circuit pattern and the first connection portion; The seed metal layer comprises: a first portion disposed between the first-1 circuit pattern and the first connecting portion; a second portion disposed between the first-second circuit pattern and the first solder resist; The package substrate of claim 2 , comprising:

4. The seed metal layer comprises: The first-1 circuit pattern, the first-2 circuit pattern, and the seed of the first connection portion The package substrate of claim 3 , wherein the package substrate is a layer.

5. a first molding layer disposed on the insulating layer and molding the first element; 、 a second element disposed under the insulating layer, the second element being molded, and a lower surface of the second connecting portion being a second molding layer including an opening for exposing the first molding layer; Board.

6. a third element embedded within the insulating layer; The second-2 circuit pattern is a first pattern portion overlapping the third element in a thickness direction; a second pattern portion other than the first pattern portion, The second connecting portion is a first post bump disposed below the first pattern portion; A second post bump is disposed under the second pattern portion and has a width different from that of the first post bump. and a strip bump.

7. The upper surface of the first outer circuit pattern is The insulating layer is located on the same plane as the upper surface of the insulating layer or is located lower than the upper surface of the insulating layer; The side surface of the first outer circuit pattern is The package substrate of claim 1 covered with the insulating layer.

8. the first molding layer includes an open area; The package substrate of claim 5 , wherein the open area exposes the first element.

9. The first outer circuit pattern protrudes above the upper surface of the insulating layer and is connected to the first molding die. exposed through the open area of ​​the sealing layer; The bottom surface of the first open area of ​​the first molding layer is The package substrate according to claim 8 , wherein the first outer circuit pattern is positioned higher than the lower surface of the first outer circuit pattern. 。

10. The first open area of ​​the first molding layer comprises: a first portion adjacent to the first outer circuit pattern; a second portion other than the first portion, 10. The package substrate of claim 9, wherein the height of the first portion is different from the height of the second portion. Board.

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