Ceramic wiring board, ceramic wiring board for probe card, and probe card

Abstract

To provide a ceramic wiring board capable of improving yield regarding insulation properties, a ceramic wiring board for a probe card, and a probe card.SOLUTION: A ceramic wiring board comprises an insulating base that consists mainly of mullite and the grain boundary phase of which contains Mn and Ti, and a conductor layer that is positioned within the insulating base. The insulating base includes a Ti crystal phase positioned between mullite particles and containing MnTiO3. With the exception of the Ti crystal phase with an area less than 1.1 μm2 on a surface of the insulating base, an area ratio of the Ti crystal phase in a region of 0.01 mm2, in which the Ti crystal phase is most densely positioned, on the surface of the insulating base is 2% or less.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a ceramic wiring substrate, a ceramic wiring substrate for a probe card, and a probe card. [Background technology]

[0002] Patent Document 1 describes a probe card that uses a ceramic wiring substrate for a probe card that has an insulating base made of a mullite sintered body. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-047579 Summary of the Invention [Problem to be solved by the invention]

[0004] Ceramic wiring substrates and probe cards are required to have insulating substrates. An object of the present disclosure is to provide a ceramic wiring substrate, a ceramic wiring substrate for a probe card, and a probe card that can improve yield in terms of insulating properties. [Means for solving the problem]

[0005] The ceramic wiring substrate according to the present disclosure comprises: an insulating substrate whose main component is mullite and whose grain boundary phase contains Mn and Ti; a conductor layer located within the insulating base; Equipped with the insulating substrate includes a Ti crystalline phase located between mullite grains and containing MnTiO3; The area of ​​the surface of the insulating substrate is 1.1 μm 2 The Ti crystalline phase is most densely located on the surface, excluding the Ti crystalline phase less than 0.01 mm 2 The area ratio of the Ti crystalline phase in this region is 2% or less.

[0006] The ceramic wiring substrate for a probe card according to the present disclosure comprises: The ceramic wiring substrate is provided.

[0007] The probe card according to the present disclosure comprises: The ceramic wiring substrate; a plurality of probe pins; Equipped with. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to provide a ceramic wiring substrate, a ceramic wiring substrate for a probe card, and a probe card that can improve yield in terms of insulation. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic cross-sectional view of a ceramic wiring substrate for a probe card according to an embodiment of the present disclosure. [Figure 2] 1 is an explanatory diagram of a semiconductor element evaluation device using a probe card according to an embodiment of the present disclosure. [Figure 3] 1A and 1B are schematic cross-sectional views showing an insulating substrate included in a ceramic wiring substrate for a probe card according to the present embodiment, in which (A) shows an example of a surface that satisfies the conditions of the present embodiment, (B) shows an enlarged view of a portion B1, and (C) shows an example of a surface that does not meet the conditions of the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings.

[0011] Fig. 1 is a schematic cross-sectional view of a ceramic wiring substrate for a probe card according to an embodiment of the present disclosure. The ceramic wiring substrate for a probe card 1 shown in Fig. 1 may include an insulating base 11 made of a ceramic sintered body, an internal wiring layer 12 formed inside the insulating base 11, and a surface wiring layer 13 formed on the surface of the insulating base 11. Via-hole conductors 14 may be located inside the insulating base 11 to electrically connect the internal wiring layers 12 to each other or to the internal wiring layer 12 and the surface wiring layer 13. The internal wiring layer 12 and the surface wiring layer 13 correspond to examples of wiring layers according to the present disclosure.

[0012] The insulating base 11 may have a plurality of laminated ceramic insulating layers 11a, 11b, 11c, and 11d. Each of the plurality of ceramic insulating layers 11a, 11b, 11c, and 11d may be a ceramic sintered body whose main component is mullite (3Al2O3·2SiO2) powder. "Main component" refers to a component that accounts for 80% or more by mass. Hereinafter, a ceramic sintered body whose main component is mullite will be referred to as a "mullite-based sintered body." By using a mullite-based sintered body, the thermal expansion coefficient of the insulating base 11 can be reduced.

[0013] The insulating base 11 may further contain Mn (manganese) and Ti (titanium). Typically, sintering a compact material primarily composed of mullite requires a firing temperature of at least 1,450°C. However, when the insulating base 11 contains at least Mn and Ti, a dense mullite sintered body with few large pores can be obtained even at a lower firing temperature. The insulating base 11 may further contain Mg (magnesium). By further containing Mg, a denser mullite sintered body can be obtained even at a lower firing temperature. The presence of Mn, Ti, and Mg in the insulating base 11 can be confirmed by atomic absorption spectrometry or ICP (inductively coupled plasma) analysis. The term "dense" as used herein refers to an insulating base 11 having a water absorption rate of 0.1% or less. The water absorption rate of the insulating base 11 is measured in accordance with JIS C2141.

[0014] Mullite may exist as particulate or columnar crystals in the insulating substrate 11. The average particle size of mullite may be 1.0 to 5.0 μm, or 1.7 to 2.5 μm. This average particle size allows for high thermal conductivity and high strength.

[0015] (probe card) FIG. 2 is an explanatory diagram of a semiconductor device evaluation device using a probe card according to an embodiment of the present disclosure. The above-described ceramic wiring substrate 1 for a probe card can be used, for example, in a probe card 2 as shown in FIG. 2. The probe card 2 includes the ceramic wiring substrate 1 for a probe card and a plurality of probe pins 21. The ceramic wiring substrate 1 for a probe card has, on one main surface thereof, a surface wiring layer (not shown) connected to the internal wiring layer 12, and the probe pins 21 for measuring the electrical characteristics of the semiconductor device may be connected to the surface wiring layer. The probe pins 21 may be connected directly to the ceramic wiring substrate 1 for a probe card or may be connected via a separate conductor.

[0016] The evaluation device may include a probe card 2, an external circuit board 4 electrically connected to the probe card 2, a tester 5 that inspects semiconductor elements based on signals transmitted through the external circuit board 4, a stage 6 on which a semiconductor wafer 7 including the semiconductor elements is mounted, and an elevator device 8 that raises and lowers the probe card 2 and the external circuit board 4. The probe card 2 may have a surface wiring layer (not shown) on the other main surface, and the surface wiring layer may be joined to the external circuit board 4 via connection terminals 3.

[0017] According to this configuration, the lifting device 8 can be driven to bring the probe pins 21 of the probe card 2 into contact with the electrodes of the semiconductor element included in the semiconductor wafer 7. This contact enables transmission of electrical signals and voltages between the external circuit board 4 and the semiconductor element through the internal wiring layer 12, via-hole conductors 14, and surface wiring layer 13 of the ceramic wiring substrate 1 for the probe card. Then, the tester 5 can test the semiconductor element based on the electrical signals and voltages.

[0018] (Details of insulating base) 3A and 3B are schematic cross-sectional views of an insulating substrate included in a ceramic wiring substrate for a probe card according to this embodiment, in which (A) shows an example of a surface that satisfies the conditions of this embodiment, (B) shows an enlarged view of a portion B1, and (C) shows an example of a surface that does not meet the conditions of this embodiment. In Fig. 3, to avoid complexity, only a portion of the Ti crystalline phase 112 is labeled with a symbol.

[0019] As described above, the insulating substrate 11 is a mullite crystalline body containing Mn and Ti. As shown in FIGS. 3(A) and 3(C), Ti crystalline phases 112 containing MnTiO3 are located on the surface or cross section of the insulating substrate 11. As shown in FIG. 3(A), the Ti crystalline phases 112 may be small and dispersed. Furthermore, as shown in FIG. 3(C), the Ti crystalline phases 112 may be concentrated together to form a large Ti crystalline phase 112, or the faces of multiple Ti crystalline phases 112 may be concentrated in one area to form a group 114. Furthermore, as shown in FIG. 3(B), extremely small Ti crystalline phases 112 are distributed throughout the multiple small Ti crystalline phases 112 and the multiple large Ti crystalline phases 112.

[0020] Since MnTiO2 has low insulating properties, the distribution of the Ti crystal phase 112 can be a factor in reducing the insulating performance of the insulating substrate 11.

[0021] The distribution of the Ti crystalline phase 112 generally does not differ significantly between the surface and the interior of the insulating base 11. Therefore, if a cross section is taken and measured inside the insulating base 11, a distribution of the Ti crystalline phase 112 that is almost the same as that on the surface will be observed. Therefore, the following describes the conditions related to the size and distribution of the Ti crystalline phase 112 on the surface of the insulating base 11, but a cross section of the insulating base 11 cut out from the ceramic wiring substrate 1 for a probe card may be applied instead of the surface. The cross section may be a polished surface.

[0022] The Ti crystal phase 112 has a different contrast from other components in the image obtained by the backscattered electron images of SEM (scanning electron microscope). For example, by using the image processing software "Image_J" to extract and analyze the region with the above contrast, the area or the maximum width can be counted.

[0023] <Condition 1 of Ti crystal phase> Excluding the Ti crystal phase 112 with an area less than 1.1 μm on the surface of the insulating substrate 11, the area ratio of the Ti crystal phase 112 in the region of 0.01 mm where the Ti crystal phase 112 is most densely located on the above surface may be 2% or less. 2 2 2 of the region may be 2% or less.

[0024] As in the case of the extremely small Ti crystal phase 112 shown in Fig. 3(B), when the Ti crystal phase 112 with an area less than 1.1 μm is dispersed, the insulating performance of the insulating substrate 11 can be maintained. Therefore, in the above condition 1, the Ti crystal phase 112 with an area less than 1.1 μm (= area S2) is excluded from the area counting target. Area S2 is shown in Fig. 3(B). 2 2 2 (= area S2) is excluded from the area counting target. Area S2 is shown in Fig. 3(B).

[0025] On the other hand, when the Ti crystal phase 112 with an area of 1.1 μm or more is located mostly between the two wiring conductors on the insulating substrate 11, it acts to reduce the insulation resistance between the two wiring conductors and becomes a factor for reducing the insulating performance of the insulating substrate 11. Furthermore, the larger the Ti crystal phase 112 is, and the more densely the large Ti crystal phases 112 gather, the greater the effect of reducing the above insulation resistance. From the results of the leakage test described later, it was derived that the above area ratio for maintaining the insulating performance of the insulating substrate 11 is within 2%. 2 2

[0026] From the above, it is derived that by satisfying the area ratio of the above condition 1, the factors for reducing the insulation resistance of the insulating substrate 11 are reduced, and the yield regarding the insulation of the ceramic wiring board 1 for the probe card can be improved.

[0027] When measuring the above area ratio of the Ti crystal phase 112, it is difficult to measure the entire surface of the insulating substrate 11. Also, when the Ti crystal phase 112 with a size of 1.1 μm 2 or more is deposited, the Ti crystal phase 112 is sparsely dispersed and the distribution pattern varies. On the other hand, in a region larger than 1 mm 2 or more, the Ti crystal phase 112 with a size of 1.1 μm 2 or more is included in any region at the same ratio, and in a region of about 100 mm 2 or more, a distribution in which the Ti crystal phase 112 gathers densely also appears. Furthermore, in SEM, by reducing the magnification, the surface of a sample of about 100 mm 2 can be roughly observed, and by increasing the magnification, the surface of about 0.01 mm 2 (a rectangular region of 96 μm × 128 μm) can be observed in detail. Therefore, the area ratio of the above Ti crystal phase 112 can be measured as follows. That is, first, for example, by roughly observing the surface of a sample of about 100 mm 2 or more, a region of 0.01 mm 2 where the Ti crystal phase 112 gathers most densely is extracted. Subsequently, the region of 0.01 mm 2 is observed in detail, and the area of the Ti crystal phase 112 is measured. As a result, the area ratio of the Ti crystal phase 112 in the region can be obtained.

[0028] <Condition 2 of the Ti crystal phase> When observing a continuous region of 100 mm 2 on the surface of the insulating substrate 11, the area of the largest Ti crystal phase 112 included in the region may be less than 20 μm 2 even.

[0029] Even if the area ratio of the Ti crystal phase 112 satisfies the above-mentioned Condition 1, there remains a possibility that a large Ti crystal phase 112 is formed. The large Ti crystal phase 112 is located between two wiring conductors and is close to each wiring conductor, which becomes a major factor in reducing the insulation resistance between the two wiring conductors. However, like the above Condition 2, the largest Ti crystal phase 112 has a surface area of 20 μm 2If it is less than this size, it is possible to reduce the situation where both of the two wiring conductors (for example, the internal wiring layer 12, the surface wiring layer 13, and the via hole conductor 14) located on the surface or inside of the insulating substrate 11 come close to each other. Therefore, by satisfying the above condition 2, the high insulating performance of the insulating substrate 11 can be maintained, and the yield regarding the insulation of the ceramic wiring board 1 for a probe card can be improved.

[0030] In SEM, by reducing the magnification, the surface of a sample of about 100 mm 2 can be roughly observed. And if a Ti crystal phase 112 with an area of about 20 μm 2 is located on the surface, the Ti crystal phase 112 can be found in a rough observation. Therefore, by extracting the largest one from the Ti crystal phases 112 and observing the largest Ti crystal phase 112 at a high magnification using SEM, the area of the largest Ti crystal phase 112 can be accurately measured.

[0031] <Condition 3 for Ti crystal phase> When observing a continuous 100 mm 2 region on the surface of the insulating substrate 11, the maximum area of one or more Ti crystal phases 112 included in the region, as well as a group 114 or a plurality of groups 114 of Ti crystal phases 112 included in the region, may be less than 20 μm 2 .

[0032] The above-mentioned "group 114 of Ti crystal phases 112" means a collection of a plurality of Ti crystal phases 112 that are close to each other on the surface of the insulating substrate 11 as shown in Fig. 3(C). However, the extremely small Ti crystal phases 112 with an area of 1.1 μm 2 or more are excluded from the "plurality of Ti crystal phases 112". Furthermore, the above-mentioned "close to each other" means that one Ti crystal phase 112 included in the collection is located at a distance within 10 μm from at least one other Ti crystal phase 112 included in the collection. The area of the group 114 of Ti crystal phases 112 means the sum of the areas of the plurality of Ti crystal phases 112 included in the group 114, and the area of the region between two Ti crystal phases 112 is not included.

[0033] Even if there are two separated Ti crystal phases 112 on the surface, those that are close to each other may be connected inside the insulating substrate 11. Also, if two Ti crystal phases 112 are close to each other, discharge may occur between them. Therefore, when the group 114 of Ti crystal phases 112 exists, as in the above condition 3, by setting the condition considering the size of the group 114 of Ti crystal phases 112, the insulation performance of the insulating substrate 11 can be more accurately determined. Thus, when the Ti crystal phase 112 satisfies the above condition 3, higher insulation performance of the insulating substrate 11 can be maintained, and the yield regarding the insulation of the ceramic wiring board 1 for the probe card can be further improved.

[0034] <Condition 4 of Ti crystal phase> When observing a continuous 100 mm 2 region on the surface of the insulating substrate 11, even if the largest maximum width among the maximum widths of one or more Ti crystal phases 112 included in the region is less than 20 μm. The maximum width means the distance of the line segment that becomes the maximum when the Ti crystal phase 112 is sandwiched from various directions by two parallel line segments. In FIG. 3(C), the maximum width Lmax1 of the large Ti crystal phase 112 is shown.

[0035] As described above, even if the area ratio of the Ti crystal phase 112 satisfies the above-described condition 1, there remains a possibility that a large Ti crystal phase 112 is formed. The large Ti crystal phase 112 is located between two wiring conductors and is in proximity to each wiring conductor, which becomes a major factor in reducing the insulation resistance between the two wiring conductors. Further, even if the area is small, if any one-dimensional dimension is large, there is a possibility of coming close to each of the two wiring conductors, similar to the case where the area is large. However, as in the above condition 4, if the largest maximum width among the maximum widths of the plurality of Ti crystal phases 112 is less than 20 μm, among the wiring conductors (for example, the internal wiring layer 12, the surface wiring layer 13, and the via hole conductor 14) located on the surface or inside of the insulating substrate 11, a situation where it comes close to both of the two wiring conductors can be reduced. Therefore, by satisfying the above condition 4, the high insulation performance of the insulating substrate 11 can be maintained, and the yield regarding the insulation of the ceramic wiring substrate 1 for a probe card can be improved.

[0036] In SEM, by reducing the magnification, the surface of a sample of about 100 mm 2 can be roughly observed. And if a Ti crystal phase 112 having a maximum width of about 20 μm is located on the surface, the Ti crystal phase 112 can be found in a rough observation. Therefore, by extracting the largest one from the Ti crystal phases 112 and observing the largest Ti crystal phase 112 at a high magnification using SEM, the largest maximum width of the Ti crystal phase 112 can be accurately measured.

[0037] <Condition 5 of Ti crystal phase> 100 mm continuous on the surface of the insulating substrate 11 2When observing the region, the maximum width of one or more Ti crystal phases 112 contained in the region, and among the maximum widths of a group 114 or a plurality of groups 114 of Ti crystal phases 112, the largest maximum width may be less than 20 μm. The group 114 of Ti crystal phases 112 and the maximum width are as described above. The maximum width of the Ti crystal phases 112 in the group 114 means the maximum width including the length of the region between two Ti crystal phases 112. In FIG. 3(C), the maximum width Lmax2 of a group 114 of Ti crystal phases 112 is shown.

[0038] Even for two Ti crystal phases 112 separated on the surface, those close to each other may be connected inside the insulating substrate 11. Also, if two Ti crystal phases 112 are close to each other, discharge may occur between them. Therefore, when there is a group 114 of Ti crystal phases 112, as in condition 5 above, by setting the condition considering the size of the group 114 of Ti crystal phases 112, the insulation performance of the insulating substrate 11 can be more accurately determined. Thus, when the Ti crystal phase 112 satisfies the above condition 5, higher insulation performance of the insulating substrate 11 can be maintained, and the yield regarding the insulation of the ceramic wiring board 1 for the probe card can be further improved.

[0039] <Condition 6 of Ti crystal phase> On the surface of the insulating substrate 11, the average area of Ti crystal phases 112 of 1.1 μm 2 or more may be 7 μm 2 or less. When a large Ti crystal phase 112 is formed, the ratio of small Ti crystal phases 112 gathering together increases. Therefore, as the size of the largest Ti crystal phase 112 increases, the average area of the Ti crystal phases 112 increases. The size of the largest Ti crystal phase 112 and the average area of the Ti crystal phases 112 are correlated. The average area of 7 μm 2is a value between the average area of ​​lots for which the results of the leak test described below are good (few products in one lot fail) and the average area of ​​lots for which the results are fair (a small number of products in one lot fail). By satisfying the above condition 6, the high insulating performance of the insulating base 11 can be maintained, and the yield of the insulating properties of the ceramic wiring substrate 1 for a probe card can be improved.

[0040] The average area of ​​the Ti crystalline phase 112 is 1 mm 2 Therefore, the average area of ​​the Ti crystalline phase 112 is defined as the area of ​​1 mm2 on the surface of the insulating substrate 11. 2 It may be considered as the average area measured over the above continuous regions.

[0041] <Manufacturing method> Next, an example of a method for manufacturing the ceramic wiring substrate 1 for a probe card of this embodiment will be described. The manufacturing method that follows is a specific example, and the ceramic wiring substrate for a probe card according to the present disclosure can also be manufactured by applying other methods.

[0042] First, mullite (3Al2O3·2SiO2) powder with a purity of 99% or more and an average particle size of 0.5 to 2.5 μm is used to form the insulating base 11. By setting the average particle size of the mullite powder to 0.5 μm or more, sheet formability is improved, and by setting it to 2.5 μm or less, densification can be promoted even by firing at a low temperature.

[0043] Next, a mixed powder is prepared by adding at least 0 to 15 parts by weight of Al2O3 powder, 1 to 8 parts by weight of Mn2O3 powder, 1 to 10 parts by weight of TiO2 powder, 0.05 to 3 parts by weight of MgO powder, and 0 to 4 parts by weight of Na2O powder to 100 parts by weight of mullite powder. In this case, the Al2O3 powder used as additives should have an average particle size of 0.5 to 1.5 μm, the Mn2O3 powder should have an average particle size of 0.5 to 3 μm, the TiO2 powder should have an average particle size of 0.5 to 2 μm, the MgO powder should have an average particle size of 0.5 to 3 μm, and the Na2O powder should have an average particle size of 0.5 to 3 μm. The purity of the Al2O3 powder, Mn2O3 powder, TiO2 powder, MgO powder, and Na2O powder should all be 99% by weight or higher. This improves sheet formability, improves the diffusion of Mn, Ti, Mg, and Na, and enhances sinterability at low temperatures.

[0044] When manufacturing the ceramic wiring substrate 1 for a probe card of this embodiment, adding MgO powder to mullite powder along with Mn2O3 powder and TiO2 powder makes the mullite sintered body obtained after firing denser, and a sintered body with a water absorption rate of 0.1% or less can be obtained. Furthermore, by including predetermined amounts of Mn, Ti, and Mg, neck growth of mullite particles during firing is suppressed, thereby suppressing abnormal grain growth of mullite, and a mullite sintered body with a high Young's modulus can be obtained.

[0045] In the above case, by adding 1 to 7 parts by mass of Mn2O3 powder, 2 to 10 parts by mass of TiO2 powder, and 0.05 to 3 parts by mass of MgO powder to 100 parts by mass of mullite powder, a Ti crystalline phase 112 containing MnTiO3 can be formed between the mullite particles.

[0046] Furthermore, by adding 1 to 7 parts by mass of Mn2O3 powder, 2 to 10 parts by mass of TiO2 powder, and 0.05 to 1 part by mass of MgO powder to 100 parts by mass of mullite powder, it is possible to form a mullite sintered body having an amorphous phase between mullite particles and a Ti crystalline phase 112 containing MnTiO3 present around the amorphous phase.

[0047] Furthermore, by adding 3 to 7 parts by mass of Mn2O3 powder, 2 to 4 parts by mass of TiO2 powder, 1 to 3 parts by mass of MgO powder, and 0.5 to 3 parts by mass of Na2O powder to 100 parts by mass of mullite powder, a mullite sintered body having a Ti crystal phase 112 containing MnTiO3 between mullite particles can be obtained.

[0048] In addition to the oxide powders described above, Mn, Ti, Mg, and Na may be added as carbonates, nitrates, acetates, or the like that can form oxides upon firing. Furthermore, for the purposes of densifying the mullite sintered body and improving the simultaneous sintering property with the composite metal that forms the internal wiring layer 12, one or more oxide powders selected from the group consisting of Ca, Sr, B, and Cr (CaO powder, SrO powder, BO powder, CrO powder) or powders of carbonates, nitrates, and acetates that can form oxides upon firing may be added to 100 parts by mass of the mullite powder in a proportion that does not change the thermal expansion coefficient of the ceramic wiring substrate 1 for a probe card of this embodiment or deteriorate the chemical resistance.

[0049] Next, an organic binder and a solvent are added to this mixed powder to prepare a slurry, which is then formed into a green sheet by a molding method such as pressing, doctor blade, rolling, or injection molding. Alternatively, an organic binder is added to the mixed powder, and a green sheet of a predetermined thickness is produced by a method such as pressing or rolling. The thickness of the green sheet can be, for example, 50 to 300 μm, but is not particularly limited.

[0050] Then, through holes with a diameter of 50 to 250 μm are appropriately formed in this green sheet using a microdrill, a laser or the like.

[0051] Copper (Cu) powder and tungsten (W) powder are mixed with the green sheets produced in this manner to prepare a conductive paste, which is then filled into the through holes of each green sheet and printed using a method such as screen printing or gravure printing to form a wiring pattern.

[0052] In addition, in order to improve adhesion to the insulating base 11, this conductive paste may contain, in addition to the above metal powder, alumina powder or a mixed powder of the same composition as the insulating base 11, and further, active metals such as Ni (nickel) or their oxides may be added at a rate of 0.05 to 2 volume % relative to the entire conductive paste.

[0053] Thereafter, the green sheets coated with the conductive paste by printing are aligned, laminated and pressure-bonded, and then the laminate is fired. The firing atmosphere is preferably a non-oxidizing atmosphere containing hydrogen and nitrogen to suppress the diffusion of Cu in the internal wiring layer 12. If desired, an inert gas such as argon gas may be mixed into the firing atmosphere.

[0054] The firing temperature affects the rate at which large Ti crystalline phases 112 are formed. This correlation holds true even when the amounts of Mn and Ti, and other sintering aids, are different. Therefore, the firing temperature is determined to satisfy the necessary conditions 1 to 6 for the Ti crystalline phase 112, as follows. That is, once the amounts of Mn and Ti and other sintering aids are determined, several test substrates are fabricated using the necessary amounts and sintering aids at several firing temperatures. Next, the Ti crystalline phase 112 is observed for each test substrate, and the test substrates that satisfy the necessary conditions 1 to 6 are identified to determine the firing temperature range that satisfies the conditions. The firing temperature is then determined based on this temperature range.

[0055] Then, by the above-mentioned firing, the ceramic wiring substrate 1 for the probe card is manufactured. The manufactured ceramic wiring substrate 1 for the probe card contains Cu and W as its main components, has an internal wiring layer 12 with low wiring resistance, and has a thermal expansion coefficient close to that of the Si wafer to be inspected. Therefore, during a thermal load test, there is no misalignment between the probe pins 21 provided on the ceramic wiring substrate 1 for the probe card and the measurement pads formed on the surface of the semiconductor wafer 7, making it suitable for use in inspecting electrical characteristics.

[0056] Furthermore, the produced ceramic wiring substrate 1 for a probe card satisfies the necessary conditions among the above conditions 1 to 6 for the Ti crystalline phase 112 located between the mullite particles, and maintains high insulation resistance, thereby improving the yield of the ceramic wiring substrate 1 for a probe card in terms of insulation properties.

[0057] <Leak test> Several lots of probe card ceramic wiring substrates 1 for testing, A to F, were produced with different sizes of the Ti crystalline phases 112 (i.e., the degree of dispersion of the Ti crystalline phases 112) by varying the firing temperature, and the results of a leak test were carried out on each probe card ceramic wiring substrate 1. The leak test is a test on the insulation resistance between insulated wiring conductors.

[0058] [Table 1] A "○" next to a condition indicates that the condition is met, an "×" next to a condition indicates that the condition is not met, a test result of "good" indicates that all products in the production lot passed, a test result of "pass" indicates that the production lot contains some products that failed but more than 70% passed, and a test result of "fail" indicates that all products in the production lot failed.

[0059] As shown in the above leak test table, by satisfying the area ratio of condition 1, the high insulating performance of the insulating base 11 is maintained, and the yield related to the insulating performance of the ceramic wiring board 1 for a probe card is improved. Furthermore, by satisfying conditions 2 to 6, the high insulating performance of the insulating base 11 is maintained even more highly, and the yield related to the insulating performance of the ceramic wiring board 1 for a probe card is further improved.

[0060] The above describes the embodiments of the present disclosure. However, the ceramic wiring substrate, the ceramic wiring substrate for a probe card, and the probe card of the present disclosure are not limited to the ceramic wiring substrate for a probe card 1 and the probe card 2 of the embodiments. For example, the ceramic wiring substrate of the present disclosure may be used for substrates other than wiring substrates for probe cards, such as various circuit boards and various module substrates. In addition, the details shown in the embodiments can be modified as appropriate without departing from the spirit of the invention.

[0061] An embodiment of the present disclosure will be described below. (1) Ceramic wiring boards are an insulating substrate whose main component is mullite and whose grain boundary phase contains Mn and Ti; a conductor layer located within the insulating base; Equipped with the insulating substrate includes a Ti crystalline phase located between mullite grains and containing MnTiO3; The area of ​​the surface of the insulating substrate is 1.1 μm 2 The Ti crystalline phase is most densely located on the surface, excluding the Ti crystalline phase less than 0.01 mm 2 The area ratio of the Ti crystalline phase in this region is 2% or less.

[0062] (2) The ceramic wiring substrate of (1) above is A continuous 100 mm 2 When observing the area of The maximum area of ​​the Ti crystal phase is 20 μm 2 is less than.

[0063] (3) The ceramic wiring substrate of (1) or (2) above is 1.1 μm 2 A plurality of Ti crystalline phases, each of which is located at a distance of 10 μm or less from at least one other Ti crystalline phase, is called a group of Ti crystalline phases, and a group of Ti crystalline phases is defined as ... 2 When observing the area of The maximum area of ​​one or more of the Ti crystalline phases contained in the region and one or more groups of Ti crystalline phases contained in the region is 20 μm 2 is less than.

[0064] (4) Any of the ceramic wiring substrates (1) to (3) above is A continuous 100 mm 2 When observing the area of The largest maximum width among the maximum widths of the one or more Ti crystalline phases contained in the region is less than 20 μm.

[0065] (5) Any of the ceramic wiring substrates (1) to (4) above is 1.1 μm 2 A plurality of Ti crystalline phases, each of which is located at a distance of 10 μm or less from at least one other Ti crystalline phase, is called a group of Ti crystalline phases, and a group of Ti crystalline phases is defined as ... 2 When observing the area of The largest of the maximum widths of the one or more Ti crystalline phases contained in the region and the maximum widths of the group or groups of Ti crystalline phases contained in the region is less than 20 μm.

[0066] (6) Any of the ceramic wiring substrates (1) to (5) above is 1.1 μm on the surface of the insulating substrate 2 The average area of ​​the Ti crystalline phase is 7 μm 2 The following is the result.

[0067] In one embodiment, (7) Ceramic wiring substrate for probe card The ceramic wiring substrate is any one of (1) to (6).

[0068] In one embodiment, (8) The probe card is The ceramic wiring substrate for a probe card according to (7) above; a plurality of probe pins; Equipped with. [Explanation of symbols]

[0069] 1. Ceramic wiring board for probe card (ceramic wiring board) 2 probe cards 11 Insulating substrate 11a to 11d Ceramic insulating layer 12 Internal wiring layer (wiring layer) 13 Surface wiring layer (wiring layer) 14 Via hole conductor 21 probe pin

Claims

1. an insulating substrate whose main component is mullite and whose grain boundary phase contains Mn and Ti; a conductor layer located within the insulating base; Equipped with The insulating substrate is located between the mullite particles and is made of MnTiO ３ The Ti crystalline phase contains The area of ​​the surface of the insulating substrate is 1.1 μm ２ The Ti crystalline phase is most densely located on the surface, excluding the Ti crystalline phase less than 0.01 mm ２ the area ratio of the Ti crystalline phase in the region is 2% or less; Ceramic wiring board.

2. A continuous 100 mm ２ When observing the area of The maximum area of ​​the Ti crystal phase is 20 μm ２ is less than The ceramic wiring board according to claim 1.

3. 1.1 μm ２ A plurality of Ti crystalline phases, each of which is located at a distance of 10 μm or less from at least one other Ti crystalline phase, is called a group of Ti crystalline phases, and a continuous 100 mm ２ When observing the area of The maximum area of ​​one or more of the Ti crystalline phases contained in the region, and one or more groups of the Ti crystalline phases contained in the region, is 20 μm ２ is less than The ceramic wiring board according to claim 1.

4. A continuous 100 mm ２ When observing the area of the largest maximum width among the maximum widths of the one or more Ti crystalline phases contained in the region is less than 20 μm; The ceramic wiring board according to claim 1.

5. 1.1 μm ２ A plurality of Ti crystalline phases, each of which is located at a distance of 10 μm or less from at least one other Ti crystalline phase, is called a group of Ti crystalline phases, and a continuous 100 mm ２ When observing the area of the largest maximum width among the maximum width of the one or more Ti crystalline phases contained in the region and the maximum width of the group or groups of Ti crystalline phases contained in the region is less than 20 μm; The ceramic wiring board according to claim 1.

6. 1.1 μm on the surface of the insulating substrate ２ The average area of ​​the Ti crystalline phase is 7 μm ２ Below is the The ceramic wiring board according to claim 1.

7. A ceramic wiring substrate for a probe card, which is the ceramic wiring substrate according to any one of claims 1 to 6.

8. a ceramic wiring substrate for a probe card according to claim 7; a plurality of probe pins; A probe card comprising:

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