Burning hardware training acceleration

Abstract

The memory includes a link training circuit having a pseudo-random bit sequence (PRBS) generator and a burst error detection counter including a comparator, a first input coupled to the data input, a second input coupled to the PRBS generator, and a counter operable to increment an error count value by one in response to detecting any number of errors greater than zero in a sequence of symbols including a predetermined number of symbols.

Description

[Background technology]

[0001] Modern dynamic random-access memory (DRAM) provides high memory bandwidth by increasing the speed of data transmission on a bus that connects the DRAM to one or more data processors, such as a graphics processing unit (GPU) or central processing unit (CPU). DRAM is typically inexpensive and dense, which allows for large amounts of DRAM to be integrated per device. Most DRAM chips sold today conform to various double data rate (DDR) DRAM standards promoted by the Joint Electron Devices Engineering Council (JEDEC). Typically, several DDR DRAM chips are combined on a single printed circuit board to form a memory module that is relatively fast but also offers scalability.

[0002] DDR DRAM is synchronous because it operates according to a free-running clock signal that synchronizes the issuance of commands from the host processor to the memory and thus the exchange of data between the host processor and the memory. The DDR DRAM responds to the clock signal to synchronize the commands and may use the clock signal to generate a read data strobe signal. For example, the DDR DRAM receives write data using a center-aligned data strobe signal known as "DQS" provided by the host processor, and the memory captures data on both the rising and falling edges of the DQS. Similarly, the DDR DRAM provides read data synchronously with the edge-aligned DQS where the DDR DRAM provides the DQS signal. During a read cycle, the host processor internally delays the DQS signal to align it with the center portion of the DQ signal, typically by an amount determined at start-up by performing data eye training. Some DDR DRAMs, such as Graphics DDR, version 6 (GDDR6) DRAMs, receive both a main clock signal and a separate write clock signal, and programmably generate a read data strobe signal.

[0003] However, while these enhancements have improved the speed of DDR memory used for main memory in computer systems, further improvements are desired. [Brief description of the drawings]

[0004] [Figure 1] 1 is a block diagram illustrating a data processing system according to some embodiments. [Diagram 2] 2 is a block diagram of the GDDR memory of FIG. 1 according to some embodiments. [Diagram 3] 3 is a block diagram of a portion of a data training logic circuit suitable for use as the data training logic circuit of FIG. 2. [Figure 4] FIG. 13 is a block diagram of a data training logic circuit, according to some additional embodiments. [Diagram 5] FIG. 5 is a block diagram of a more detailed view of the Thermometer-to-Gray (T2G) and XOR circuit of FIG. [Figure 6] FIG. 2 illustrates the variation of the reference voltage of a PAM receiver in accordance with some embodiments. [Figure 7] 1 is an eye diagram illustrating an XOR eye margining process using self-referencing in accordance with some embodiments. [Figure 8] FIG. 8 is a block diagram of a data training logic circuit 800, according to some additional embodiments. [Figure 9] FIG. 9 is a block diagram of a more detailed view of the T2G and bypass circuitry of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] In the following description, the use of the same reference numbers in different figures indicates similar or identical items. Unless otherwise noted, the word "coupled" and its related verb forms include both direct and indirect electrical connections by means known in the art, and unless otherwise noted, any description of a direct connection also refers to alternative embodiments using a suitable form of indirect electrical connection.

[0006] The memory includes a data input circuit for coupling to a data bus having a multi-level pulse amplitude modulation (PAM) receiver for outputting multi-bit symbols based on receiving a data signal including three or more PAM levels. The memory includes a training circuit having a pseudo-random bit sequence (PRBS) generator and a burst error detection counter. The burst error detection counter includes a comparator, a first input coupled to the data input, a second input coupled to the PRBS generator, and a counter operable to increment an error count value by one in response to detecting any number of errors greater than zero in a sequence of symbols including a predetermined number of symbols.

[0007] A method for use by a memory includes receiving, in a write training mode in the memory, on a data line a pseudorandom bit sequence (PRBS) encoded into symbols in a multi-level pulse amplitude modulation (PAM) format including three or more PAM levels. The method generates an identical PRBS in the memory and compares the received PRBS to the identical PRBS to detect errors. The method increases an error count value by one in response to detecting any number of errors greater than zero in a sequence of symbols including a predetermined number of symbols.

[0008] The data processing system includes a data processor and a memory coupled to the data processor via a data bus. The memory includes a data input circuit and a training circuit. The data input circuit is for coupling to the data processor via the data bus and includes a multi-level pulse amplitude modulation (PAM) receiver for outputting multi-bit symbols based on receiving a data signal including three or more PAM levels. The training circuit includes a pseudo-random bit sequence (PRBS) generator and a burst error detection counter, the burst error detection counter including a comparator, a first input coupled to the data input, a second input coupled to the PRBS generator, and a counter operable to increment an error count value by one in response to detecting any number of errors greater than zero in a sequence of symbols including a predetermined number of symbols.

[0009] 1 is a block diagram illustrating a data processing system 100 in accordance with some embodiments. Data processing system 100 generally includes data processors in the form of a graphics processing unit (GPU) 110, a host central processing unit (CPU) 120, double data rate (DDR) memory 130, and graphics DDR (GDDR) memory 140.

[0010] GPU 110 is a discrete graphics processor that has very high performance for optimized graphics processing, rendering and display, but requires high memory bandwidth to perform these tasks. GPU 110 generally includes a set of command processors 111, a graphics single instruction multiple data (SIMD) core 112, a set of caches 113, a memory controller 114, a DDR physical interface circuit (PHY) 115, and a GDDR PHY 116.

[0011] Command processor 111 is used to interpret high-level graphics instructions, such as those specified in the OpenGL programming language. Command processor 111 has a bidirectional connection to memory controller 114 for receiving high-level graphics instructions, a bidirectional connection to cache 113, and a bidirectional connection to graphics SIMD core 112. In response to receiving the high-level instructions, command processor 111 issues SIMD instructions for rendering, geometric processing, shading, and rasterization of data, such as frame data, using cache 113 as temporary storage. In response to the graphics instructions, graphics SIMD core 112 executes low-level instructions on large data sets in a massively parallel manner. Command processor 111 and cache 113 are used for temporary storage of input data and output (e.g., rendered and rasterized) data. Cache 113 also has a bidirectional connection to graphics SIMD core 112 and a bidirectional connection to memory controller 114.

[0012] The memory controller 114 has a first upstream port connected to the command processor 111, a second upstream port connected to the cache 113, a first downstream bidirectional port, and a second downstream bidirectional port. As used herein, the "upstream" port is the side of the circuitry towards the data processor and away from the memory, and the "downstream" port is the side of the circuitry away from the data processor and towards the memory. The memory controller 114 controls the timing and ordering of data transfers to and from the DDR memory 130 and the GDDR memory 140. DDR and GDDR memories support asymmetric access, i.e., accesses to open pages in the memory are faster than accesses to closed pages. The memory controller 114 stores memory access commands and processes them out of order for efficiency, for example, by prioritizing accesses to open pages and deprioritizing frequent bus turnarounds from writes to reads and vice versa, while observing certain quality of service objectives.

[0013] The DDR PHY 115 has an upstream port connected to a first downstream port of the memory controller 114 and a downstream port bidirectionally connected to the DDR memory 130. The DDR PHY 115 meets all specified timing parameters of an implementation version of the DDR memory 130, such as DDR version 5 (DDR5), and performs training operations at the direction of the memory controller 114. Similarly, the GDDR PHY 116 has an upstream port connected to a second downstream port of the memory controller 114 and a downstream port bidirectionally connected to the GDDR memory 200. The GDDR PHY 116 meets all specified timing parameters of an implementation version of the GDDR memory 140, and performs training operations at the direction of the memory controller 114, including initial training of the various data and command lanes of the GDDR PHY 116 and retraining during operation.

[0014] Figure 2 is a block diagram of the GDDR memory 200 of Figure 1, according to some embodiments. The GDDR memory 200 generally includes a control circuit 210, an address path 220, a memory array and page buffer 230, a data read path 240, a set of bond pads 250, and a data write path.

[0015] The control circuit 210 includes a command decoder 211, a mode register 212, and a training control circuit 213. The command decoder 211 decodes commands received from command and address pins (not shown in FIG. 2) into one of several supported commands defined by the memory's command truth table. One type of command decoded by the command decoder 211 is a mode register set (MRS) command. The MRS command causes the command decoder to provide a setting to the indicated mode register whose address input contains the setting. The MRS command has been known in the context of DRAM for quite some time and differs between different GDDR DRAM versions. The mode register 212 stores the programmed settings and possibly outputs information about the GDDR DRAM. The training control circuit 213 has a first input connected to an output of the command decoder 211, a second input connected to a particular output of the mode register 212, and an output. As will be further described, the training control circuit 213 generally responds to commands from the memory controller 114 to place the GDDR memory 200 in a PHY training mode, instructing the training logic for the input and output buffers to perform link training steps.

[0016] The address path 220 receives multi-bit address signals and includes an input buffer 221 and an address latch 222 for each address signal, a set of row decoders 223, and a set of column decoders 224. The input buffer 221 receives and buffers a corresponding multi-bit address signal and provides a multi-bit buffered address signal in response. The address latch 222 has an input connected to the output of the input buffer 221, an output, and a clock input that receives a signal labeled "WCK". The address latch 222 latches the bits of the buffered address on a clock edge, e.g., a rising edge, and serves as a write clock during write commands as well as a main clock used to capture commands. The row decoder 223 has an input connected to the output of the address latch 222, and an output. The column decoder 224 has an input connected to the output of the address latch 222, and an output.

[0017] The memory arrays and page buffers 230 are organized into sets of individual memory arrays known as separately addressable banks. For example, the GDDR memory 200 may have a total of 16 banks. Each bank can have only one "open" page at a time, which has its contents read into the corresponding page buffer for faster read and write access. The row decoder 223 selects the row in the bank accessed during the activate command, and the contents of the indicated row are read into the page buffer and the row is ready for read and write access. The column decoder 224 selects a column of the row according to a column address.

[0018] The data read path 240 includes a read queue 241, a read latch 242, an output buffer 243, a delay locked loop (DLL) 244, and

[0019]

number

[0020]

number

[0021] Write data path 260 includes an input buffer 261, a write latch 262, and a write queue 263. Input buffer 261 has an input connected to a set of bond pads 250 labeled “DQ”, and an output. Write latch 262 has an input connected to the output of input buffer 261, and an output. Write queue 263 has an input connected to the output of write latch 262, and an output connected to the memory array and page buffer 230.

[0022] Data training logic 270 has an input connected to training control circuit 213, and inputs and outputs connected to input buffer 261 and output buffer 243 for performing the training function.

[0023] In operation, the GDDR memory 200 allows for simultaneous operations on memory banks, and in one embodiment, the GDDR memory 200 is compatible with any of the double data rate (DDR) standards published by the Joint Electron Device Engineering Council (JEDEC). To access data, a memory accessing agent, such as the GPU 110, activates a row in a memory bank by issuing an activate (ACT) command. In response to the ACT command, data from memory cells along the selected row are stored in a corresponding page buffer. In DRAM, data reads are destructive to the contents of the memory cells, but a copy of the data is stored in the page buffer. After the memory controller 114 has finished accessing the data in the selected row of the bank, it closes the row by issuing a precharge (PRE) command (or a write or read command with automatic precharge, or a precharge all command). The PRE command causes the data in the page buffer 124 to be rewritten to that row in the selected bank, and then allows another row to be activated. These operations are conventional in DDR memories, are described in various JEDEC standard documents, and will not be described further.

[0024] However, in accordance with various embodiments disclosed herein, the GDDR memory 200 includes a modified mode register set 212 that adds mode register fields and command decoder functions compared to existing standards such as GDDR6, which can be used to define the behavior of the training control circuit 213 and data training logic 270 to perform additional training functions as further described below.

[0025] 3 is a block diagram of a portion of a data training logic circuit 300 suitable for use as the data training logic circuit 270 of FIG. 2. This diagram shows only the relevant portions of the data training logic 300 to avoid obscuring the present invention. The data training logic 300 generally includes a burst error detection counter 310 and a reporting path 320. Generally, the burst error detection counter 310 detects errors associated with a single DQ input of the memory 200 and is repeated for each DQ lane, as indicated by the label "n." For example, in one embodiment, PAM3 signaling is used for the DQ lanes and each of the ten data lanes (DQ[0:7], DQX, DQY, and DQE) includes a burst error detection counter 310.

[0026] The burst error detection counter 310 includes a comparison logic circuit 312 and a burst error counter 314. The comparison logic circuit 312 has a first input for receiving a received data signal labeled "DATA[31:0]", a second input for receiving a pseudo-random bit sequence labeled "PRBS[31:0]", and an output. The burst error counter 314 has an input connected to the output of the comparison logic 312, a counter reset input labeled "CTR RST", and an output.

[0027] The reporting path 320 generally provides a signaling path for reporting error counts during link training and inserts error count data into an error detection code (EDC) data path. The reporting path 320 includes a multiplexer 322, a first-in-first-out (FIFO) buffer 324 labeled "EDC FIFO", and a multiplexer 326. The multiplexer 326 has a first input that receives the DRAM's EDC signal (for normal operation), a second input connected to the output of the burst error counter 314 for write training operations, a control input (not shown), and an output. The EDC FIFO 324 has an input connected to the output of the multiplexer 326, and an output. The multiplexer 322 has a first input connected to the output of the EDC FIFO 324, a second input labeled "DQ", a control input (not shown), and an output labeled "To PAM Encoder".

[0028] In operation, during a write training (WRTR) mode, a training pattern is received by a PAM receiver for the DQ lanes (e.g., 261 in FIG. 2) and decoded into symbols that are provided to the data[31:0] input of the comparison logic 312. A PRBS generator locally generates a training pattern for comparison and provides it to the PRBS[31:0] input of the comparison logic 312. The comparison logic detects errors by XOR comparison and outputs a HIGH signal to a burst error counter 314 each time an error is detected in a symbol. The burst error counter 314 is a 12-bit burst error counter operable to increment an error count value by 1 in response to detecting any number of errors greater than 0 in a sequence of symbols that includes a predetermined number of symbols. The counter value is then reported to the memory controller via the DQE lanes for the training pattern by controlling multiplexers 322 and 326. For example, in one embodiment, bursts of 16 symbols are used and the burst error counter 314 increments by 1 if there are any errors in the 16 symbol burst and does not increment if there are no errors. While this embodiment counts burst errors, other embodiments may include a configuration mode for the burst error detection counter 310 to count individual errors within a burst.

[0029] The illustrated configuration allows multiple read cycles of WRTR data, with a linear feedback shift register (LFSR) incremented to generate a different PRBS training pattern each cycle. This configuration improves accuracy while reducing write training time. Without the use of error counters, only pass / fail boundaries are detected during WRTR cycles. The error counters can be used by the host to determine leading and trailing edge failure density of the DQ lane data eye for phase alignment updates during training. The host can also measure failure rate gradients. Although a burst error counter is used in this embodiment, in some embodiments the counter can be operated in a normal error counter mode where each error in a burst increases the counter value. The use of error counters also allows an XOR logic mode to be performed without reference to the LFSR pattern, which can perform data eye margining without reference to write training, as described further below.

[0030] The illustrated configuration also has the advantage that the error count value for a burst can be transmitted by the PAM encoder in a single burst. Preferably, in WRTR mode, the PAM encoder of the DQ lane is operated using only two of the PAM levels to avoid errors and simplify the PAM encoding process. For example, in PAM3 encoding, only the +1 and -1 levels are used to transmit the error count.

[0031] 4 is a block diagram of a data training logic circuit 400 according to some additional embodiments. The data training logic circuit 400 is suitable for use as the data training logic circuit 270 of FIG. 2. In general, the data training logic circuit includes a symbol masking capability and an XOR logic mode that can perform data eye margining without reference to write training and can perform data eye margining without reference to an LFSR pattern.

[0032] The data training logic circuit 400 includes a PRBS generator 402, a maximum transition avoidance (MTA) encoder 404, a masking circuit 406, a burst error detection counter 410, a deserializer and FIFO circuit 412 labeled "DES+FIFO", a thermometer-to-Gray and XOR circuit 420 labeled "T2G&XOR", and three flip-flops 414, 416, 418.

[0033] The PRBS generator 402 has a control input (not shown) and an output, and generally includes at least one LFSR along with control logic for initializing the LFSR. The MTA encoder 404 has an input and an output connected to the output of the PRBS generator 402. The masking circuit 406 has a first mode input for receiving a mode signal labeled "MODE", a symbol mask input labeled "SYMBOL_MASK[7:0]", an eye mask input labeled "EYE_LEVEL_MASK[1:0]", two data inputs, a first output labeled "PRBS[31:0]", and a second output labeled "DATA[31:0]".

[0034] The burst error detection counter 410 has a first input connected to the PRBS[31:0] output of the masking circuit 406, a second input connected to the data[31:0] output of the masking circuit 406, a counter reset input labeled “CNT_RST”, a mode input, and a counter output.

[0035] Each of the flip-flops 414, 416, 418 has a "D" input, a clock input, and a "Q" output. Three reference voltages labeled "VRHIGH", "VRMID" and "VRLOW" are connected to the D inputs of the flip-flops 414, 416, 418, respectively. The T2G and XOR circuit 420 has a first input receiving a signal "D0" from the output of the flip-flop 418, a second input receiving a signal "D1" from the output of the flip-flop 416, a third input receiving a signal "D2" from the output of the flip-flop 414, a mode input, a first output labeled "DatH", and a second output labeled "DatL". Flip-flops 414, 416, 418 are dedicated flip-flop circuits that function as level detectors or comparators (also known as slicers) for the PAM receiver, with their clock inputs all connected to the DQ lane signal labeled "DQ[n]" and their three outputs indicating whether the DQ signal is higher than respective reference voltage inputs VRHIGH, VRMID, and VRLOW. T2G and XOR circuit 420 generally serves as a PAM decoder for the PAM receiver and operates in two different modes, either as a PAM level decoder or as an XOR comparator circuit to perform a self-referenced comparison, as further described below with respect to Figures 5-7.

[0036] The deserializer and FIFO circuit 412 has a first input that receives the DatH output from the T2G and XOR circuit 420, a second input that receives the DatL output from the T2G and XOR circuit 420, and an output connected to a data input of the masking circuit 406. The deserializer and FIFO circuit 812 is a FIFO buffer that converts the input serial data streams DatH and DatL to a 32-bit wide data signal at its output.

[0037] In operation, the data training logic circuit 400 can operate similarly to that of FIG. 3, comparing data received via DQ[n] with data generated by the PRBS 402, and includes masking and receiver XOR comparison capabilities. The masking circuit 406 can apply either eye level masking or symbol level masking, selectable by a mode input. Eye level masking generally involves remapping the PAM decoder output to isolate either the upper eye or the lower eye, as controlled by the EYE_LEVEL_MASK[1:0] input. Symbol level masking provides the ability to isolate selected symbols within a burst, as controlled by the SYMBOL_MASK[7:0] input. Symbol level masking is applied by forcing selected masked symbol bits to all zeros, in both the PRBS and the received data, thus leaving only the bits to be examined to be fed to the comparison logic for error checking and error counting. The symbol-level masking capability provides training improvements by allowing isolation of bits that may frequently have errors due to system noise and thus generally distort the overall eye training. For example, the first symbol in a burst may be masked to avoid the effects of power noise that may be present on the first symbol. Such a mask may be applied constantly during training. As another example, individual symbols may be masked off sequentially to capture data such as deviations.

[0038] Referring to the T2G and XOR circuit 420, shown in more detail in FIG. 5, it includes a thermometer-to-Gray encoder 502, two XOR gates 504 and 506, and two multiplexers 508 and 510. The T2G and XOR circuit 420 replaces the normal T2G encoder in a PAM receiver (such as a PAM3 or PAM4 receiver) to add self-comparison capability. The T2G encoder 502 has three inputs and two outputs. It receives three inputs D0, D1, and D2 and generates a 2-bit code on the output. Also, the XOR gate 504 receives inputs D1 and D2, and the XOR gate 506 receives inputs D0 and D1. The XOR gate 504 has an output labeled "XORH" and the XOR gate 506 has an output labeled "XORL". The XORL and XORH are fed to the respective inputs of both the multiplexer 508 and the multiplexer 510. In this embodiment a thermometer-to-Gray encoder is used, although other embodiments may use other suitable encoders, such as a thermometer-to-binary encoder, for example.

[0039] The multiplexer 508 has a first input connected to the first output of the T2G encoder 502, a second and third inputs receiving the outputs of the XOR gates 504 and 506, and a control input connected to the mode input. Similarly, the multiplexer 510 has a first input connected to the second output of the T2G encoder 502, a second and third inputs receiving the outputs of the XOR gates 504 and 506, and a control input connected to the mode input. In normal operation mode, the multiplexers 508 and 510 pass the T2G encoder output to DatH and DatL. In XOR comparison mode, the multiplexers 508 and 510 pass the result of the XOR comparison of either D0 and D1 or D1 and D2, as selected by the mode input. In this embodiment, the mode input is a 2-bit binary number that configures the multiplexer to pass the desired data. A "0" value passes the T2G encoder output to DatH and DatL. A value of "1" passes XORH only to both DatH and DatL. A value of "2" passes XORL only to both DatH and DatL. A value of "3" passes XORH to DatH and XORL to DatL. The XOR comparison data is used in conjunction with selectively varying VRHIGH, VRMID, and VRLOW to perform self-referenced training of the PAM receiver's data eye, as further described with respect to Figures 6-7 below.

[0040] 6 shows a diagram 600 illustrating the variation of reference voltages in a PAM receiver, according to some embodiments. A scale is shown to indicate the range of variation of the signal supply voltage VDDQ and the reference voltages VRMID, VRHIGH, and VRLOW during normal operation. (VDDQ may vary or be set to different levels, requiring different values ​​for the reference voltages.) The adjustable reference voltages that are part of a typical PAM receiver enable a new technique for eye training, as shown in FIG. 7.

[0041] 7 shows an eye diagram 700 illustrating the XOR eye margining process using self-referencing according to some embodiments. The vertical axis represents the voltage on DQ[n] and the horizontal axis represents time. Although a data eye for a PAM4 signal is shown, the same process may be used for other PAM signaling schemes, such as PAM3, PAM6, or PAM8.

[0042] Referring to both Figures 6 and 7, the eye diagram shown includes three data eyes 702, 704, 706 defined by overlapping multiple voltage transitions. The normal expected upper and lower boundaries of the eyes are shown at levels 710, 712, 714, 716. In normal operation of a PAM receiver, the reference voltages VRHIGH, VRMID, VRLOW go to three different slicers or comparators (such as flip-flops 414, 416, 418 used for this purpose in the circuit of Figure 4) to identify the voltage level of DQ[n]. In the XOR self-referencing mode, the reference voltages have a different role of finding the margin of the data eye for a single data eye at a time.

[0043] In this process, the two slicers have their reference voltages adjusted to make sample comparisons at the same eye. The third reference voltage and its slicer output are ignored in this process. In the illustrated exemplary scenario of FIG. 7, the data eye 704 is tested to train the phase delay of each DQ[n] driver. VRMID is set to the magnitude in the middle of the expected voltage range between levels 712 and 714. VRHIGH is adjusted up and down in value, and the slicer outputs (D1 and D2 in this case) are fed to the XOR gate 504 to determine if they detect the same value. For each sample of each bit period, the XOR output indicates whether D1 and D2 are equal or not. As VRHIGH is swept across the range from levels 712 to 714 over successive samples, eventually D1 and D2 change from equal to unequal, indicating that the eye envelope is at the current level of VRHIGH. The phase offset of the DQ[n] driver is adjusted forward and backward during this process to find the eye envelope edges or margins. Once these margins are identified, the phase offset is set to the center phase offset point (i.e., the point furthest from the identified envelope edges).

[0044] This XOR self-referencing process does not require a specific data pattern and does not compare the received D1 and D2 with anything other than the other value of the pair. Therefore, there is no need to adjust the initialization and timing of the data patterns from the DQ[n] driver and PRBS generator, which are not used in this process. Furthermore, this process can be used to detect the shape of the eye envelope at all four corners to detect anomalies. Finally, this process can be used with the different PAM signaling configurations mentioned above, such as PAM3, PAM6, or PAM8.

[0045] This process is then repeated for data eyes 702 and 706 to locate their envelope edges. As can be appreciated, it does not matter which pair of reference voltages is used, but in this embodiment, since XOR gates 504 and 506 each use D1, VRMID is whichever pair is used for each eye. In this embodiment, VRMID is held at a value in the center of data eye 704, but VRHIGH or VRLOW could also be used in this role, and VRMID is swept. Preferably, each reference voltage is adjustable over the full range of VDDQ, or at least over the full expected range of any slicer reference voltage. At a minimum, at least one reference voltage should be adjustable to the center of each eye, and at least one other reference voltage should be adjustable to sweep through the expected voltage range of the eye.

[0046] 4, the output of the XOR comparison is fed to a burst error detection counter 410 that counts the detection of different PAM levels by the XOR comparison as an error to detect the outer margin of the data eye of the PAM receiver. In this way, the same comparison logic used for training with the training sequence can be used for the XOR self-referencing process.

[0047] 8 is a block diagram of a data training logic circuit 800 according to some additional embodiments. The data training logic circuit 800 is suitable for use as the data training logic circuit 270 of FIG. 2. In general, the data training logic circuit 800 has the same symbol masking capabilities as the circuit of FIG. 4 and a similar XOR logic mode in which data eye margining can be performed, although the XOR logic mode is implemented differently in this embodiment.

[0048] The data training logic circuit 800 includes a PRBS generator 802, a maximum transition avoidance (MTA) encoder 804, a masking circuit 806, a burst error detection counter 810, a deserializer and FIFO circuit 812 labeled "DES+FIFO", a thermometer-to-Gray conversion and bypass circuit 820 labeled "T2G and bypass", and three flip-flops 814, 816, 818. Note that some embodiments use PAM3 signaling and do not require an MTA encoder.

[0049] The PRBS generator 802 has a control input (not shown) and an output, and generally includes at least one LFSR along with control logic for initializing the LFSR. The MTA encoder 804 has an input and an output connected to the output of the PRBS generator 802. The masking circuit 806 has a first mode input, a symbol mask input labeled "SYMBOL_MASK[7:0]", an eye mask input labeled "EYE_LEVEL_MASK[1:0]", a data input, a first output labeled "PRBS[31:0]", and a second output labeled "DATA[31:0]".

[0050] Each of the flip-flops 814, 816, 818 has a "D" input, a clock input, and a "Q" output. Three reference voltages labeled "VRHIGH", "VRMID", and "VRLOW" are connected to the D inputs of the flip-flops 814, 816, 818, respectively. The T2G and bypass circuit 820 has a first input receiving signal "D0" from the output of the flip-flop 818, a second input receiving signal "D1" from the output of the flip-flop 816, a third input receiving signal "D2" from the output of the mode input of the flip-flop 814, a first output labeled "DatH", and a second output labeled "DatL". Flip-flops 814, 816, and 818 generally function as level detectors or comparators for the PAM receiver, with their clock inputs all connected to the DQ lane signal labeled "DQ[n]" and their three outputs indicating whether the DQ signal is higher than the respective reference voltage inputs VRHIGH, VRMID, and VRLOW.

[0051] The deserializer and FIFO circuit 812 has a first input that receives the DatH output from the T2G and bypass circuit 820, a second input that receives the DatL output from the T2G and bypass circuit 820, and an output connected to the data input of the masking circuit 806. The deserializer and FIFO circuit 812 is a FIFO buffer that converts the input serial data streams DatH and DatL to a 32-bit wide data signal at its output.

[0052] The burst error detection circuit 810 has a first input connected to the PRBS[31:0] output of the masking circuit 806, a second input connected to the data[31:0] output of the masking circuit 806, a counter reset input labeled "CNT_RST", a mode input, and a counter output. In this embodiment, the burst error detection circuit 810 is similar to the circuit 310 of FIG. 3, but includes a multiplexer 811 between the data input and its comparison logic 813, allowing the circuit 810 to use the comparison logic 813 to compare PRBS[31:0] to data[31:0] in normal error counting mode, but to compare the two bit streams on DatH and DatL in XOR comparison mode. In this manner, the XOR self-reference comparison described above can be completed by setting the T2G and bypass circuit 820 in bypass mode and comparing the desired pair of signals D0, D1, D2 in the burst error detection circuit 810, as will be further described below.

[0053] In operation, the data training logic circuit 800 may operate similarly to the circuit of Figure 3, comparing data received via DQ[n] with data generated by PRBS 802, and including masking and receiver XOR comparison capabilities. The masking circuit 806 may apply either eye level masking or symbol level masking, selectable by a mode input, as described above with respect to Figure 4.

[0054] Figure 9 is a block diagram of a more detailed view of the T2G and bypass circuit 820 of Figure 8. The T2G and bypass circuit 820 includes a thermometer-to-Gray encoder 902 and two multiplexers 908 and 910. The T2G and bypass circuit 820 replaces a normal T2G encoder in a PAM receiver (such as a PAM3 or PAM4 receiver) to add bypass functionality. The T2G encoder 902 has three inputs and two outputs. It receives three inputs D0, D1, D2 and generates a 2-bit code on the output.

[0055] A multiplexer 908 has a first input connected to a first output of the T2G encoder 902, second and third inputs receiving the D2 and D0 inputs, a control input connected to the mode input, and an output. A multiplexer 910 has a first input connected to a second output of the T2G encoder 902, a second input receiving the D1 input, a control input connected to the mode input, and an output.

[0056] In normal operation mode, multiplexers 908 and 910 pass the T2G encoder output to DatH and DatL. The mode control input, a 2-bit signal, uses a "0" to set normal mode, a "1" to pass D2 to DatH and D1 to DatL for XOR comparison in burst error detection counter 810, and a "2" to pass D0 to DatH and D1 to DatL for XOR comparison in burst error detection counter 810.

[0057] The memory 200 of FIG. 2, such as the data training logic circuits 300, 400 and 800, may be described or represented by a computer accessible data structure in the form of a database or other data structure that may be read by a program and used directly or indirectly to manufacture an integrated circuit. For example, the data structure may be a behavioral level description or a register transfer level (RTL) description of the hardware functionality in a hardware description language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool that may synthesize the description to generate a netlist that includes a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware that comprises the integrated circuit. The netlist may then be placed and routed to generate a data set that describes the geometric shapes to be applied to a mask. The mask may then be used in various semiconductor manufacturing processes to manufacture the integrated circuit. Alternatively, the database on the computer accessible storage medium may be a netlist (with or without a synthesis library) or a data set, or Graphic Data System (GDS) II data, if desired.

[0058] Although specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, while GDDR memory has been described as using the techniques herein, other types of DRAM or other memory types may benefit from the link training techniques and circuits described above. As another example, the burst error detection counter herein may be configured to count individual errors within a burst. The length of the burst and the size of the data path may, of course, vary across different configurations of memory. Finally, the XOR self-referencing training technique described with respect to Figures 4-7 may be used to train a variety of communication links that use PAM signaling and do not necessarily require the burst error detection counter configuration herein. A variety of counter configurations may be used to count mismatches in the paired signals used in the processes of Figures 6-7. It is therefore intended that the appended claims cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. A memory, a data input circuit for coupling to a data bus, the data input circuit including a multi-level pulse amplitude modulation (PAM) receiver for outputting multi-bit symbols based on receiving a data signal including three or more PAM levels; A training circuit, The training circuit comprises: a pseudorandom bit sequence (PRBS) generator; A burst error detection counter; The burst error detection counter includes: a comparator, a first input coupled to said data input, a second input coupled to said PRBS generator, and a counter operable to increment an error count value by one in response to detecting any number of errors greater than zero in a symbol sequence comprising a predetermined number of symbols. Memory.

2. a plurality of data input circuits each having the training circuit of claim 1; a first-in-first-out buffer coupled to the burst error detection counter and operable to hold a value from the counter during a write training sequence and to provide the value to a host requester in response to a specified command to the memory. The memory of claim 1.

3. the predetermined number of symbols is 16 symbols, and the counter is a 12-bit counter. The memory of claim 2.

4. a masking circuit coupled between the PRBS generator and the second input of the burst error detection counter for selectively masking one or more selected bits of a symbol such that errors for the one or more selected bits are not detected by the burst error detection counter. The memory of claim 1.

5. the multi-level PAM receiver includes at least two reference voltage inputs for receiving respective reference voltages defining boundaries of the PAM levels; The multi-level PAM receiver can be configured to operate in an exclusive-or (XOR) self-referencing mode, where a first one of the reference voltages is set to a center level of a selected one of the PAM levels, and a second one of the reference voltages is adjusted within a selected PAM level during a training sequence, and an XOR comparison is performed within the multi-bit symbols output by the multi-level PAM receiver to detect when an adjustment of the second one of the reference voltages causes a different PAM level to be detected. The memory of claim 1.

6. an output of the XOR comparison is provided to the burst error detection counter, which counts detection of different PAM levels by the XOR comparison as an error to detect an outer margin of a data eye for a PAM receiver; The memory of claim 5.

7. A method for using a memory, comprising: (a) receiving, in a write training mode at the memory, on a data line, a pseudo-random bit sequence (PRBS) encoded into symbols in a multi-level pulse amplitude modulation (PAM) format including three or more PAM levels; (b) generating an identical PRBS in said memory; and (c) comparing the received PRBS with said identical PRBS to detect errors; (d) incrementing an error count value by one in response to detecting a number of errors greater than zero in a sequence of symbols comprising a predetermined number of symbols. method.

8. performing (a)-(d) simultaneously for a plurality of data lines in the memory for a write training sequence; loading the error count values ​​for the plurality of data lines for the write training sequence into a first-in, first-out (FIFO) buffer; transmitting the error count value from the memory to a host memory controller. The method of claim 7.

9. the predetermined number of symbols is 16 symbols, and the incrementing is performed using a 12-bit counter.

9. The method of claim 8.

10. selectively masking one or more selected bits of a symbol such that errors are not detected for the one or more selected bits to increase the error count value. The method of claim 7.

11. selectively operating the multi-level PAM receiver in an exclusive-or (XOR) self-referencing mode in which a reference voltage is set to a level centered on a selected PAM level and a second reference voltage is adjusted within the selected PAM level during a training sequence; and performing an XOR comparison within multi-bit symbols output by the multi-level PAM receiver to detect when adjustment of the second reference voltage causes detection of a different PAM level. The method of claim 7.

12. In the XOR self-referencing mode, detecting different PAM levels by the XOR comparison is counted as an error to detect an outer margin of a data eye for the data line.

12. The method of claim 11.

13. 1. A data processing system comprising: A data processor; a memory coupled to the data processor via a data bus; The memory includes: a data input circuit for coupling to the data processor via the data bus, the data input circuit including a multi-level pulse amplitude modulation (PAM) receiver for outputting multi-bit symbols based on receiving a data signal including three or more PAM levels; A training circuit, The training circuit comprises: a pseudorandom bit sequence (PRBS) generator; A burst error detection counter; The burst error detection counter includes: a comparator; a first input coupled to said data input; a second input coupled to said PRBS generator; and a counter operable to increment an error count value by one in response to detecting any number of errors greater than zero in a sequence of symbols comprising a predetermined number of symbols. Data processing system.

14. The memory includes: a plurality of data input circuits coupled to respective data lines of said data bus, each data input circuit having a training circuit of claim 13; a first-in-first-out buffer coupled to the burst error detection counter and operable to hold a value from the counter during a write training sequence and to provide the value to a host requester in response to a specified command to the memory.

14. The data processing system of claim 13.

15. the predetermined number of symbols is 16 symbols, and the counter is a 12-bit counter.

15. The data processing system of claim 14.

16. the data processor includes a memory controller operable to activate a training mode in which the training circuitry is activated and to instruct the memory to transmit a write sequence including the PRBS to the memory; 15. The data processing system of claim 14.

17. a masking circuit coupled between the PRBS generator and the second input of the burst error detection counter for selectively masking one or more selected bits of a symbol such that errors for the one or more selected bits are not detected by the burst error detection counter.

14. The data processing system of claim 13.

18. the multi-level PAM receiver includes at least two reference voltage inputs for receiving respective reference voltages defining boundaries of the PAM levels; The multi-level PAM receiver can be configured to operate in an exclusive-or (XOR) self-referencing mode, where a first one of the reference voltages is set to a center level of a selected one of the PAM levels, and a second one of the reference voltages is adjusted within a selected PAM level during a training sequence, and an XOR comparison is performed within the multi-bit symbols output by the multi-level PAM receiver to detect when an adjustment of the second one of the reference voltages causes a different PAM level to be detected.

14. The data processing system of claim 13.

19. an output of the XOR comparison is provided to the burst error detection counter, which counts detection of different PAM levels by the XOR comparison as an error to detect an outer margin of a data eye for the PAM receiver; 20. The data processing system of claim 18.

20. the data processor includes a memory controller that receives an error count indicative of an outer margin of a data eye of the data line and makes at least one adjustment to a multi-level PAM transmitter phase offset based on the received error count.

20. The data processing system of claim 19.

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