Timer-Based Fault Protection Circuit

Abstract

A timer-based fault protection circuit (100) is provided, the timer-based fault protection circuit (100) comprising a high voltage line (102) configured to be electrically coupled to a first terminal of an intrinsically safe load (ISL), a low voltage line (104) configured to be electrically coupled to a second terminal of the intrinsically safe load (ISL), a voltage limiter (110) and a delay / LIP enable circuit (120) coupled to the high voltage line (102) and the low voltage line (104) in electrical parallel to the intrinsically safe load (ISL), and a switchable low impedance path (130) electrically coupled to the high voltage line (102) and the low voltage line (104) in a shunt configuration relative to the intrinsically safe load (ISL). The voltage limiter (110) is communicatively coupled to the delay / LIP enable circuit (120) and configured to provide a signal to the delay / LIP enable circuit (120), which is communicatively coupled to the switchable low impedance path (130) and configured to provide a signal to the switchable low impedance path (130).

Description

[Technical field]

[0001] The embodiments described below relate to fault protection circuits, and more particularly, to timer-based fault protection circuits. [Background technology]

[0002] Some processing systems require more power to perform their intended functions in the intrinsically safe (IS) zone. This high power requirement can result, for example, from a high speed multi-core processor with an embedded FPGA. In some cases, the high power requirement can only be met by supplying a high current. However, the operation of the barrier is only considered under fault conditions, so the worst fault conditions must be considered when designing an IS barrier.

[0003] Under normal operating conditions, these barriers should be open circuit and may not be part of normal circuit operation. Traditional Zener barriers may not be suitable for such high current / high power applications due to their high power dissipation under fault conditions. Under fault conditions with high power dissipation, the temperature of the Zener leads and its case can easily exceed maximum threshold levels and the barrier can be damaged. If the IS barrier is damaged, the IS load may be exposed to fault conditions.

[0004] Traditional Zener diode barriers have been employed, but may require undesirably large form factors (e.g., board space, overhead space, heat dissipation hardware, etc.) to be effective in high current applications. Furthermore, Zener diodes may require undesirably high power consumption and therefore significant heat dissipation requirements. If the Zener diodes were time limited, a smaller form factor could be used without such undesirably high power consumption requirements. Thus, a timer-based fault protection circuit is needed. Summary of the Invention

[0005] A timer-based fault protection circuit is provided. In one embodiment, the timer-based fault protection circuit includes a high voltage line configured to electrically couple to a first terminal of an intrinsically safe load, a low voltage line configured to electrically couple to a second terminal of the intrinsically safe load, a voltage limiter and a delay / LIP enable circuit coupled to the high voltage line and the low voltage line in electrical parallel to the intrinsically safe load, and a switchable low impedance path electrically coupled to the high voltage line and the low voltage line in a shunt configuration to the intrinsically safe load. The voltage limiter is communicatively coupled to the delay / LIP enable circuit and configured to provide a signal to the delay / LIP enable circuit, and the delay / LIP enable circuit is communicatively coupled to the switchable low impedance path and configured to provide a signal to the switchable low impedance path.

[0006] A method of forming a timer-based fault protection circuit is provided, according to one embodiment, comprising the steps of: electrically coupling a high voltage line to a first terminal of an intrinsically safe load, electrically coupling a low voltage line to a second terminal of the intrinsically safe load, coupling a voltage limiter and a delay / LIP enable circuit to the high voltage line and the low voltage line in electrical parallel to the intrinsically safe load, electrically coupling a switchable low impedance path to the high voltage line and the low voltage line in a shunt configuration to the intrinsically safe load, communicatively coupling the voltage limiter to the delay / LIP enable circuit and configuring it to provide a signal to the delay / LIP enable circuit, communicatively coupling the delay / LIP enable circuit to the switchable low impedance path, and configuring the delay / LIP enable circuit to provide a signal to the switchable low impedance path.

[0007] [Aspects] According to one aspect, a timer-based fault protection circuit includes a high voltage line configured to electrically couple to a first terminal of an intrinsically safe load, a low voltage line configured to electrically couple to a second terminal of the intrinsically safe load, a voltage limiter and a delay / LIP enable circuit coupled to the high voltage line and the low voltage line in electrical parallel to the intrinsically safe load, and a switchable low impedance path electrically coupled to the high voltage line and the low voltage line in a shunt configuration to the intrinsically safe load, the voltage limiter is communicatively coupled to the delay / LIP enable circuit and configured to provide a signal to the delay / LIP enable circuit, and the delay / LIP enable circuit is communicatively coupled to the switchable low impedance path and configured to provide a signal to the switchable low impedance path.

[0008] Preferably, the timer-based fault protection circuit further comprises a transient voltage suppression diode having a first terminal electrically coupled to a high voltage line and a second terminal electrically coupled to a low voltage line, the transient voltage suppression diode configured to conduct current between the high voltage line and the low voltage line when a voltage on the high voltage line is greater than a breakdown voltage of the transient voltage suppression diode.

[0009] Preferably, upon receiving a signal from the delay / LIP enable circuit, the switchable low impedance path is configured to conduct forward conduction current between the high voltage line and the low voltage line at a voltage less than the breakdown voltage of the transient voltage suppression diode.

[0010] Preferably, the voltage limiter is configured to sense the voltage of the high voltage line relative to the voltage of the low voltage line and provide a signal to the delay / LIP enable circuit when the voltage of the high voltage line relative to the voltage of the low voltage line is greater than an overvoltage threshold.

[0011] Preferably, the voltage limiter comprises a voltage divider having a first terminal electrically coupled to the high voltage line and a second terminal electrically coupled to the low voltage line, and configured to provide a reference voltage based on a voltage of the high voltage line relative to a voltage of the low voltage line, and a first voltage adjustable shunt regulator having a first terminal electrically coupled to the high voltage line, a second terminal electrically coupled to the low voltage line, and a voltage reference terminal configured to receive the reference voltage, the first voltage adjustable shunt regulator configured to pass a current based on the reference voltage.

[0012] Preferably, the delay / LIP enable circuit is configured to receive a signal from the voltage limiter, initiate a timer function of the delay / LIP enable circuit upon receiving a signal from the voltage limiter, and provide a signal to the switchable low impedance path when the timer function reaches a delay threshold.

[0013] Preferably, the delay / LIP enable circuit comprises an RC network configured to receive a signal from the voltage limiter and to charge one or more capacitors in the RC network to a voltage using the signal from the voltage limiter, a second voltage adjustable shunt regulator electrically coupled to the RC network and configured to receive voltages of the one or more capacitors in the RC network and to conduct a current based on the voltages of the one or more capacitors in the RC network, and an SCR enable switch electrically coupled to the second voltage adjustable shunt regulator, the SCR enable switch configured to provide a signal to a switchable low impedance path when the second voltage adjustable shunt regulator conducts current.

[0014] Preferably, the second voltage adjustable shunt regulator comprises a first terminal electrically coupled to the high voltage line and to the base terminal of the SCR enable switch, a second terminal electrically coupled to the low voltage line, and a reference voltage terminal configured to receive a voltage across the one or more capacitors of the RC network, The second voltage adjustable shunt regulator is configured to direct a current from the high voltage line to the low voltage line in proportion to the voltage across the one or more capacitors of the RC network.

[0015] Preferably, the switchable low impedance path comprises an SCR having a first terminal electrically coupled to the high voltage line, a second terminal electrically coupled to the low voltage line, and a gate electrically coupled to the SCR enable switch to receive a signal from the delay / LIP enable circuit, the SCR being configured to conduct a forward conduction current between the high voltage line and the low voltage line when the signal from the delay / LIP enable circuit exceeds a gate threshold.

[0016] Preferably, the signal received from the delay / LIP enable circuit comprises a voltage value of the high voltage line that exceeds a gate threshold.

[0017] Preferably, the SCR is configured to pass a forward conduction current while the forward conduction current is greater than a holding current of the SCR.

[0018] According to one aspect, a method of forming a timer-based fault protection circuit includes configuring a high voltage line to be electrically coupled to a first terminal of an intrinsically safe load, configuring a low voltage line to be electrically coupled to a second terminal of the intrinsically safe load, coupling a voltage limiter and a delay / LIP enable circuit to the high voltage line and the low voltage line in electrical parallel to the intrinsically safe load, electrically coupling a switchable low impedance path to the high voltage line and the low voltage line in a shunt configuration to the intrinsically safe load, communicatively coupling the voltage limiter to the delay / LIP enable circuit and configuring it to provide a signal to the delay / LIP enable circuit, communicatively coupling the delay / LIP enable circuit to the switchable low impedance path, and configuring the delay / LIP enable circuit to provide a signal to the switchable low impedance path.

[0019] Preferably, the method further includes electrically coupling a first terminal to the high voltage line and a second terminal to the low voltage line of a transient voltage suppression diode, the transient voltage suppression diode being configured to conduct current between the high voltage line and the low voltage line when a voltage on the high voltage line is greater than a breakdown voltage of the transient voltage suppression diode.

[0020] Preferably, upon receiving a signal from the delay / LIP enable circuit, a switchable low impedance path is configured to conduct forward conduction current between the high voltage line and the low voltage line at a voltage less than the breakdown voltage of the transient voltage suppression diode.

[0021] Preferably, the method further comprises the step of sensing a voltage on the high voltage line relative to a voltage on the low voltage line and configuring the voltage limiter to provide the signal to the delay / LIP enable circuit when the voltage on the high voltage line relative to the voltage on the low voltage line is greater than an overvoltage threshold.

[0022] Preferably, the step of electrically coupling the voltage limiter to the high voltage line and the low voltage line includes electrically coupling a first terminal of a voltage divider to the high voltage line and a second terminal of the voltage divider to the low voltage line, configuring the voltage divider to provide a reference voltage based on a voltage on the high voltage line relative to a voltage on the low voltage line; electrically coupling a first terminal of a first voltage adjustable shunt regulator to the high voltage line and a second terminal of the first voltage adjustable shunt regulator to the low voltage line, receiving a reference voltage at a voltage reference terminal of the first voltage adjustable shunt regulator, and configuring the first voltage adjustable shunt regulator to conduct a current based on the reference voltage.

[0023] Preferably, the method further comprises configuring a delay / LIP enable circuit to receive a signal from a voltage limiter, to initiate a timer function of the delay / LIP enable circuit upon receiving a signal from the voltage limiter, and to provide a signal to a switchable low impedance path when the timer function reaches a delay threshold.

[0024] Preferably, the delay / LIP enable circuit comprises an RC network configured to receive a signal from the voltage limiter and to charge one or more capacitors in the RC network to a voltage using the signal from the voltage limiter, a second voltage adjustable shunt regulator electrically coupled to the RC network and configured to receive voltages of the one or more capacitors in the RC network and to conduct a current based on the voltages of the one or more capacitors in the RC network, and an SCR enable switch electrically coupled to the second voltage adjustable shunt regulator, the SCR enable switch configured to provide a signal to the switchable low impedance path when the second voltage adjustable shunt regulator conducts current.

[0025] Preferably, the second voltage adjustable shunt regulator includes a first terminal electrically coupled to the high voltage line and to the base terminal of the SCR enable switch, a second terminal electrically coupled to the low voltage line, and a reference voltage terminal configured to receive a voltage across the one or more capacitors of the RC network, and is configured to direct a current from the high voltage line to the low voltage line in proportion to the voltage across the one or more capacitors of the RC network.

[0026] Preferably, the switchable low impedance path comprises an SCR having a first terminal electrically coupled to the high voltage line, a second terminal electrically coupled to the low voltage line, and a gate electrically coupled to the SCR enable switch to receive a signal from the delay / LIP enable circuit, the SCR being configured to conduct a forward conduction current between the high voltage line and the low voltage line when the signal from the delay / LIP enable circuit exceeds a gate threshold.

[0027] Preferably, the signal received from the delay / LIP enable circuit comprises a voltage value of the high voltage line that exceeds a gate threshold.

[0028] Preferably, the SCR is configured to pass a forward conduction current while the forward conduction current is greater than a holding current of the SCR. [Brief description of the drawings]

[0029] Like reference numbers represent like elements in all drawings. It should be understood that the drawings are not necessarily to scale. [Figure 1] FIG. 1 shows a timer-based fault protection circuit 100. [Diagram 2] FIG. 2 shows a more detailed diagram of the timer-based fault protection circuit 100 described with reference to FIG. [Diagram 3] FIG. 3 illustrates another timer-based fault protection circuit 300. [Figure 4]FIG. 4 shows a timing diagram 400 illustrating the timing of a timer-based fault protection circuit, such as the timer-based fault protection circuits 100, 300 described above with reference to FIGS. 1-3. [Diagram 5] FIG. 5 illustrates a method 500 for forming a timer-based fault protection circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] 1-5 and the following description provide specific examples to teach those skilled in the art how to make and use the best modes of embodiments of the timer-based fault protection circuit. Some conventional aspects have been simplified or omitted for the purpose of teaching the principles of the invention. Those skilled in the art will appreciate variations from these examples that fall within the scope of the present disclosure. Those skilled in the art will appreciate that the features described below can be combined in various ways to form multiple variations of the timer-based fault protection circuit. As a result, the embodiments described below are not limited to the specific examples described below, but only by the claims and their equivalents.

[0031] FIG. 1 illustrates a timer-based fault protection circuit 100. As shown in FIG. 1, the timer-based fault protection circuit 100 includes an input 100i communicatively coupled to a high voltage line 102 and a low voltage line 104. The high voltage line 102 and the low voltage line 104 are electrically coupled to an intrinsically safe load ISL. More specifically, the high voltage line 102 is electrically coupled to a first terminal of the intrinsically safe load ISL, and the low voltage line 104 is electrically coupled to a second terminal of the intrinsically safe load ISL. The high voltage line 102, the low voltage line 104, and the intrinsically safe load ISL form a current loop CL, which is indicated by a dashed line having an arrow at one end indicating the direction of current in the current loop CL. As shown in FIG. 1, the high voltage line 102 and the low voltage line 104 can be referred to as high voltage terminals since they are composed only of conductors. Alternative high voltage lines may include elements such as lumped elements. For example, the alternative high voltage and / or low voltage lines may include resistive, capacitive, and / or inductive elements.

[0032] Also shown in FIG. 1 is a voltage limiter 110 electrically coupled to the high voltage line 102 and the low voltage line 104 in parallel with the input terminal. As shown in FIG. 1, the voltage limiter 110 includes a first terminal electrically coupled to the high voltage line 102 and a second terminal electrically coupled to the low voltage line 104. A delay / low impedance path ("LIP") enable circuit 120 is also electrically coupled to the high voltage line 102 and the low voltage line 104 in parallel with the input terminal. For example, as shown in FIG. 1, the delay and LIP enable circuit 120 includes a first terminal electrically coupled to the high voltage line 102 and a second terminal electrically coupled to the low voltage line 104. As shown in FIG. 1, the voltage limiter 110 is shown as being electrically coupled to the delay / LIP enable circuit 120. For example, as shown in FIG. 1, the voltage limiter 110 is communicatively coupled to the delay / LIP enable circuit 120 in the direction indicated by the arrow.

[0033] Also shown in FIG. 1 is a switchable low impedance path 130 electrically coupled to the high voltage line 102 and the low voltage line 104. The switchable low impedance path 130 is shown to include a first terminal electrically coupled to the high voltage line 102 and a second terminal electrically coupled to the low voltage line 104. The switchable low impedance path 130 includes an SCR 130D and a series resistor 130R. As used herein, the acronym "SCR" may refer to a silicon controlled rectifier, although alternative devices may be employed that are not referred to as silicon controlled rectifiers. For example, a thyristor may be employed in the switchable low impedance path 130.

[0034] The SCR 130D and the series resistor 130R are electrically coupled in series. More specifically, a first terminal of the SCR 130D is electrically coupled to the high voltage line 102 and a second terminal of the SCR 130D is electrically coupled to a first terminal of the series resistor 130R. A second terminal of the series resistor 130R is electrically coupled to the low voltage line 104. Thus, the second terminal of the SCR 130D is electrically coupled to the low voltage line 104 via the series resistor 130R, although the SCR 130D may be electrically coupled directly to the low voltage line 104. The SCR 130D and / or the series resistor 130R may be selected to ensure that a desired low power consumption level is achieved, although any suitable criteria may be employed.

[0035] 1 also shows a transient voltage shunt ("TVS") diode 140 electrically coupled to the high voltage line 102 and the low voltage line 104 in parallel with the input terminals. More specifically, a first terminal of the TVS diode 140 is electrically coupled to the high voltage line 102 and a second terminal of the TVS diode 140 is electrically coupled to the low voltage line 104. The TVS diode 140 may be any diode or diodes that may be reverse biased to conduct when a threshold voltage, such as a breakdown voltage of the diode, is exceeded.

[0036] When the input 100i is in a normal voltage state, no current flows through the TVS diode 140, the voltage limiter 110, and the switchable low impedance path 130. That is, current flows only from the positive terminal, through the high voltage line 102, through the intrinsically safe load ISL, and to the negative terminal via the low voltage line 104. This current flow is shown in FIG. 1 as the current loop CL.

[0037] When the input 100i is subjected to an overvoltage condition, such as a transient overvoltage condition, the TVS diode 140 is configured to clamp the voltage difference between the high voltage line 102 and the low voltage line 104 to a voltage clamp value Vclamp. At substantially the same time, the voltage limiter 110 is also configured to detect the overvoltage condition on the input 100i and provide a signal to the delay / LIP enable circuit 120 to initiate a timer function.

[0038] For example, the voltage limiter 110 may apply a voltage to the delay / LIP enable circuit 120, an example of which is described in more detail below with reference to FIG. 2. During this voltage condition, the delay / LIP enable circuit 120 may perform a timer function to determine whether the voltage has been applied for a period of time, which may be a predetermined delay time. After the delay / LIP enable circuit 120 has been energized for this period of time, the delay / LIP enable circuit 120 enables the switchable low impedance path 130 to conduct current between the high voltage line 102 and the low voltage line 104.

[0039] The delay / LIP enable circuit 120 may be subjected to a voltage due to an overvoltage condition on the input 100i. More specifically, the voltage limiter 110 may be configured to provide a voltage to the delay / LIP enable circuit 120 while the overvoltage condition on the input 100i exists. The voltage provided by the voltage limiter 110 may be proportional to the voltage of the overvoltage condition applied to the high voltage line 102. More specifically, the voltage applied to the delay / LIP enable circuit 120 may be used, for example, to charge a capacitor or capacitors, as described in more detail below, although any suitable signal may be used to initiate and power a timer function of the delay / LIP enable circuit.

[0040] As will be appreciated, the timer-based fault protection circuit 100 is scalable; that is, alternative component values, topologies, etc., can be used for higher or lower voltage applications. Thus, the principles and procedures associated with the timer-based fault protection circuit 100 can be used to scale the circuit to support higher power requirements. By way of example, scaling of the timer-based fault protection circuit 100 can be achieved, for example, by using a higher power SCR 130D and series resistor 130R. Exemplary principles and procedures of the timer-based fault protection circuit 100, as well as other timer-based fault protection circuits, are described in more detail below.

[0041] Detailed Example of a Timer-Based Fault Protection Circuit Figure 2 shows a more detailed diagram of the timer-based fault protection circuit 100 described with reference to Figure 1. As shown in Figure 2, the timer-based fault protection circuit 100 includes an input 100i, a high voltage line 102, an intrinsically safe load ISL, and a low voltage line 104. As also shown in Figure 2, the timer-based fault protection circuit 100 includes a voltage limiter 110, a delay / LIP enable circuit 120, a switchable low impedance path 130, and a TVS diode 140, which were described with reference to Figure 1.

[0042] As shown in Figure 2, the voltage limiter 110 includes a voltage divider 112, a first voltage adjustable shunt regulator 114, and a delay circuit switch 116. Also shown in Figure 2, the delay / LIP enable circuit 120 includes a resistor-capacitor (RC) network 123, a second voltage adjustable shunt regulator 124, and an SCR enable switch 126. The switchable low impedance path 130 is shown as including an SCR 130D and a series resistor 130R as described with reference to Figure 1. The TVS diodes 140 as described with reference to Figure 1 are shown in Figure 2 as including four TVS diodes, although more or less diodes and / or other elements may be used.

[0043] The voltage divider 112 comprises a first resistor R1 and a second resistor R2 electrically connected in series. A first terminal of the first resistor R1 is electrically coupled to the high voltage line 102 and a second terminal of the first resistor R1 is electrically coupled to a first terminal of the second resistor R2. A second terminal of the second resistor R2 is electrically coupled to the low voltage line 104. A first voltage reference V1 is between the first and second resistors R1, R2 of the voltage divider 112.

[0044] The first voltage adjustable shunt regulator 114 is shown as being electrically coupled to the high voltage line 102 and to the low voltage line 104 via a third resistor R3. That is, the first voltage adjustable shunt regulator 114 is electrically in parallel with the terminals of the input 100i. The first voltage adjustable shunt regulator 114 is also shown as being electrically coupled to a first voltage reference V1 between the first and second resistors R1, R2 of the voltage divider 112, a voltage reference V2. REF 1 is shown having terminals.

[0045] The delay circuit switch 116 is shown as a bipolar junction transistor (BJT). In particular, as shown in the figure, the delay circuit switch 116 may be a model BCX52, more specifically a model BCX52-16, 115, available from a variety of manufacturers, although any suitable switch may be used. The delay circuit switch 116 includes an emitter electrically coupled to the high voltage line 102, a base electrically coupled to a third resistor R3 and a fourth resistor R4, and a collector electrically coupled to a first terminal of a voltage dropping resistor 122. As shown in FIG. 2, a second terminal of the third resistor R3 and a first terminal of the fourth resistor R4 are electrically coupled to the base of the delay circuit switch 116, and a second terminal of the fourth resistor R4 is electrically coupled to a first terminal of the first voltage adjustable shunt regulator 114. A second terminal of the first voltage adjustable shunt regulator 114 is electrically coupled to the low voltage line 104.

[0046] 2, the voltage dropping resistor 122 includes a first terminal electrically coupled to the collector of the delay circuit switch 116. More specifically, the collector of the delay circuit switch 116 is electrically coupled to a first terminal of a fifth resistor R5. As shown in FIG. 2, the voltage dropping resistor 122 is illustrated as consisting of a fifth resistor R5, although alternative voltage dropping resistors may include multiple resistors.

[0047] A first terminal of the RC network 123 is electrically coupled to the second terminal of the voltage dropping resistor 122. A second terminal of the RC network 123 is electrically coupled to the low voltage line 104. The RC network 123 is shown in FIG. 2 as comprising a sixth resistor R6 and a capacitor C in parallel with each other. More specifically, a first terminal of the sixth resistor R6 and a first terminal of the capacitor C are electrically coupled to each other. Additionally, a second terminal of the sixth resistor R6 and a second terminal of the capacitor C are electrically coupled to the low voltage line 104.

[0048] The first terminal of the RC network 123 is also connected to the voltage reference terminal V of the second voltage adjustable shunt regulator 124. REF 2, the second terminal of second voltage adjustable shunt regulator 124 is directly coupled to low voltage line 104, although an indirect electrical coupling, such as a low resistance path, may also be employed.

[0049] A first terminal of the eighth resistor R8 is electrically coupled to the high voltage line 102. A second terminal of the eighth resistor R8 is electrically coupled to the emitter of the SCR enable switch 126. A first terminal of the seventh resistor R7 is electrically coupled to the base of the SCR enable switch 126. The SCR enable switch 126 includes an emitter electrically coupled to the high voltage line 102 via the eighth resistor R8 and a collector electrically coupled to a switchable low impedance path 130. The SCR enable switch 126 is shown as a BJT, although any suitable switch may be employed. The SCR enable switch 126 is shown in FIG. 2 as a BCX52 transistor available from a variety of manufacturers. For example, the SCR enable switch 126 may be a BCX52-16, 115 transistor.

[0050] A first terminal of the ninth resistor R9 is electrically coupled to the high voltage line 102. A second terminal of the ninth resistor R9 is electrically coupled to a first terminal of the seventh resistor R7. The seventh resistor R7 and the ninth resistor R9 electrically couple the second voltage adjustable shunt regulator 124 to the high voltage line 102. A second terminal of the ninth resistor R9 is also electrically coupled to a base of the SCR enable switch 126. As can be appreciated, the ninth resistor R9 provides a voltage to the base of the SCR enable switch 126. As can also be appreciated, this voltage can be reduced when the second voltage adjustable shunt regulator 124 conducts current, as will be described in more detail below.

[0051] As shown in FIG. 2, the switchable low impedance path 130 includes an SCR 130D and a series resistor 130R as described with reference to FIG. 1. The first and second terminals of the SCR 130D are electrically coupled to the high voltage line 102 and the low voltage line 104, respectively. As shown in FIG. 3, the second terminal of the SCR 130D is electrically coupled to the low voltage line 104 via the series resistor 130R, although the SCR 130D may be electrically coupled directly to the low voltage line 104. Note that the series resistor 130R is also referred to as a tenth resistor. The SCR 130D and the series resistor 130R are arranged in series as shown in FIG. 2. The SCR 130D is shown as an SJ6008D, such as the SJ6008D1RP manufactured by Littelfuse, but any suitable silicon controlled rectifier, thyristor, or the like may be employed. The SCR 130D includes a gate electrically coupled to the collector of the SCR enable switch 126.

[0052] As discussed above and shown in FIG. 2, TVS diode 140 is comprised of two transient voltage suppression diodes arranged in an electrically parallel configuration. In particular, TVS diode 140 is shown as being comprised of two Littelfuse 5.0 SMDJ diodes, although any suitable TVS diode may be used. TVS diode 140 is arranged as described with reference to FIG. 1. More particularly, a first terminal of TVS diode 140 is electrically coupled to high voltage line 102 and a second terminal of TVS diode 140 is electrically coupled to low voltage line 104. TVS diode 140 is electrically in parallel with intrinsically safe load ISL.

[0053] The first and second voltage adjustable shunt regulators 114, 124 may be TL431 shunt regulators manufactured by various manufacturers, although any suitable adjustable shunt regulator may be employed. As shown in FIG. 2, the first and second voltage adjustable shunt regulators 114, 124 are connected to a voltage reference terminal V REF The first and second voltage adjustable shunt regulators 114, 124 include a voltage reference terminal V REF is greater than the internal voltage references of the first and second voltage adjustable shunt regulators 114, 124. REF is less than the internal voltage references of the first and second voltage adjustable shunt regulators 114, 124, the first and second voltage adjustable shunt regulators 114, 124 may be prevented from conducting.

[0054] 2, when the voltage of the high voltage line 102 is greater than the voltage threshold and the first voltage reference V1 value is greater than the voltage reference value of the first voltage adjustable shunt regulator 114, the first voltage adjustable shunt regulator 114 can be conductive. As can be understood, the first voltage reference V1 can be determined from the resistance values ​​of the first and second resistors R1, R2 of the voltage limiter 110. In the delay / LIP enable circuit 120, the second voltage adjustable shunt regulator 124 can be conductive when the voltage of the first terminal of the RC network 123 is greater than the voltage reference value of the second voltage adjustable shunt regulator 124.

[0055] As can be seen, when the first voltage adjustable shunt regulator 114 conducts current, the voltage at the base of the delay circuit switch 116 drops to a relatively low state or value, thereby increasing the voltage difference between the base and emitter of the delay circuit switch 116. The increase in the voltage difference between the base and emitter of the delay circuit switch 116 allows the delay circuit switch 116 to conduct current between the emitter and collector of the delay circuit switch 116. This results in a voltage being applied to the first terminal of the RC network 123, thus beginning to charge the capacitor C of the RC network 123, and may initiate the timer function of the delay / LIP enable circuit 120.

[0056] Similarly, when the second voltage adjustable shunt regulator 124 conducts current, the voltage at the base of the SCR enable switch 126 drops to a low voltage state or value (e.g., at or near zero volts), which increases the voltage difference between the base and emitter of the SCR enable switch 126. The increased voltage difference between the base and emitter of the SCR enable switch 126 allows the SCR enable switch 126 to conduct current between the emitter and collector of the SCR enable switch 126. This allows a gate voltage and current to be applied to the gate of SCR 130D.

[0057] When a gate voltage and current are applied to the gate of SCR130D, SCR130D can pass a forward conduction current between its first and second terminals. SCR130D can continue to pass a forward conduction current between its first and second terminals even if the gate voltage and gate current at the gate of SCR130D return to zero. Thus, only a momentary increase in gate voltage and current, such as a pulse at the gate of SCR130D, may be required to make SCR130D conductive. However, SCR130D can stop conducting a forward conduction current between its first and second terminals when the gate voltage at the gate of SCR130D returns to zero, for example, and the current between the first and second terminals becomes less than the hold current of SCR130D. For example, if the holding current of SCR 130D is very low, SCR 130D may continue to conduct forward current until the voltage on high voltage line 102 is at or about zero volts (eg, "pulled to ground").

[0058] As can be appreciated, the calculated current value of series resistor 130R for a voltage on high voltage line 102 in an operating or non-overvoltage condition can be zero or less than the latching current of SCR 130D. In contrast, if high voltage line 102 is in an overvoltage condition, the current through series resistor 130R can be greater than the latching value of SCR 130D. Thus, if SCR 130D is enabled by a gate voltage and current to conduct forward conduction current, for example, if high voltage line 102 is subjected to an overvoltage condition, SCR 130D can conduct forward conduction current.

[0059] In normal operation, which may be defined as when input 100i does not experience an overvoltage condition, delay circuit switch 116 and SCR enable switch 126 do not conduct current. More specifically, the bases of delay circuit switch 116 and SCR enable switch 126 do not have sufficient voltage to conduct current between the respective emitters and collectors of delay circuit switch 116 and SCR enable switch 126. Thus, no gate voltage and current are applied to the gate of SCR 130D unless input 100i experiences an overvoltage condition.

[0060] Referring to the delay circuit switch 116, when the high voltage line 102 does not experience an overvoltage condition, no current flows between the emitter and collector of the delay circuit switch 116, and therefore no voltage is applied to the first terminal of the RC network 123. As a result, the reference voltage terminal of the second voltage adjustable shunt regulator 124 may have a voltage lower than the reference voltage of the second voltage adjustable shunt regulator 124. Thus, the voltage at the first terminal of the second voltage adjustable shunt regulator 124 may be greater than the voltage that the SCR enable switch 126 would allow current to flow if it were less than that. As a result, when the high voltage line 102 does not experience an overvoltage condition, the switchable low impedance path 130 remains open, thereby preventing current from flowing through the switchable low impedance path 130. More specifically, the SCR 130D may prevent forward conduction current from flowing.

[0061] When input 100i is in an overvoltage condition, the voltage on high voltage line 102 may cause the first voltage reference V1 value to be greater than the internal voltage reference value of first voltage adjustable shunt regulator 114. As a result, the voltage at the base of delay circuit switch 116 may be low enough (e.g., at a low voltage state or value) for delay circuit switch 116 to conduct current between the collector and emitter of delay circuit switch 116. This may cause a voltage to be applied to the first terminal of RC network 123.

[0062] Thus, the voltage at the first terminal of RC network 123 may increase over time, i.e., capacitor C of RC network 123 may charge when high voltage line 102 is in an overvoltage condition. When the voltage at the first terminal of RC network 123 is greater than the voltage reference value of second voltage adjustable shunt regulator 124, second voltage adjustable shunt regulator 124 may conduct, which may cause SCR enable switch 126 to conduct current between the emitter and collector of SCR enable switch 126.

[0063] As a result, an overvoltage condition on the high voltage line 102 closes the switchable low impedance path 130, thereby allowing a relatively high forward conduction current to flow through the switchable low impedance path 130. More specifically, SCR 130D conducts, thereby allowing a forward conduction current to flow from the high voltage line 102 to the low voltage line 104 through SCR 130D and series resistor 130R.

[0064] A high forward conduction current through the switchable low impedance path 130 may decrease or reduce the voltage value of the high voltage line 102. For example, if an overvoltage condition on the high voltage line 102 is due to a transient voltage being applied to the high voltage line 102, the voltage value of the high voltage line 102 may decrease due to a forward conduction current through the switchable low impedance path 130. It will also be appreciated that a decrease in the voltage value of the high voltage line 102 may cause the delay circuit switch 116 to open, thereby preventing current from flowing through the RC network 123.

[0065] As a result, the capacitor C can be discharged through the sixth resistor R6 to the low voltage line 104, e.g., ground. This can cause the voltage value at the first terminal of the RC network 123 to decrease over time. When the voltage at the first terminal of the RC network 123 decreases below the voltage reference value V of the second voltage adjustable shunt regulator 124, the voltage reference value V REFWhen the high voltage line 102 drops to a voltage value less than 0.5 V, the SCR enable switch 126 opens, thereby removing the gate voltage and current from the gate of SCR 130D, but allowing SCR 130D to continue to conduct forward current until the high voltage line 102 goes to zero volts (e.g., is pulled to ground), as explained above.

[0066] As can be appreciated, there are a variety of possible ways to implement a timer-based fault protection circuit. The timer-based fault protection circuit 100 described above may be advantageous because it uses relatively few components. However, as the following examples show, other timer-based fault protection circuits using different components and / or topologies may be used.

[0067] Another detailed example of a timer-based fault protection circuit FIG. 3 illustrates another timer-based fault protection circuit 300. As shown in FIG. 3, the timer-based fault protection circuit 300 includes an input 300i, a high voltage line 302, an intrinsically safe load ISL, and a low voltage line 304, which correspond to the input 100i, the high voltage line 102, the intrinsically safe load ISL, and the low voltage line 104 described above with reference to FIG. 2, respectively. Also, as shown in FIG. 3, the timer-based fault protection circuit 300 includes a voltage limiter 310, a delay / LIP enable circuit 320, a switchable low impedance path 330, and a TVS diode 340, which correspond to the voltage limiter 110, the delay / LIP enable circuit 120, the switchable low impedance path 130, and the TVS diode 140 described above with reference to FIG. 2, respectively. In contrast to the timer-based fault protection circuit 100 shown in FIG. 2, the TVS diode 340 in FIG. 3 is shown near the intrinsically safe load ISL.

[0068] As shown in Figure 3, the voltage limiter 310 includes a voltage divider 312, a first voltage adjustable shunt regulator 314, and a delay circuit switch 316. Also shown in Figure 3, the delay / LIP enable circuit 320 includes a resistor-capacitor (RC) network 323, a second voltage adjustable shunt regulator 324, and an SCR enable switch 326. The switchable low impedance path 330 is shown as including an SCR 330D and a series resistor 330R as described with reference to Figure 1. The TVS diode 140 described with reference to Figure 1 is shown in Figure 3 as including four TVS diodes, although more or less diodes and / or other elements may be employed.

[0069] The voltage divider 312 comprises a first resistor R1 and a second resistor R2 electrically connected in series. A first terminal of the first resistor R1 is electrically coupled to the high voltage line 302 and a second terminal of the first resistor R1 is electrically coupled to a first terminal of the second resistor R2. A second terminal of the second resistor R2 is electrically coupled to the low voltage line 304. A first voltage reference V1 is between the first and second resistors R1, R2 of the voltage divider 312.

[0070] The first voltage adjustable shunt regulator 314 is shown as being electrically coupled to the high voltage line 302 and the low voltage line 304 via a third resistor R3. Thus, the first voltage adjustable shunt regulator 314 is electrically in parallel with the terminals of the input 300i. The first voltage adjustable shunt regulator 314 also includes a voltage reference V1 electrically coupled to the first voltage reference V1 between the first and second resistors R1, R2 of the voltage divider 312. REF 1 is shown having terminals.

[0071] The delay circuit switch 316 is shown as a bipolar junction transistor (BJT), specifically a model BC857 available from a variety of manufacturers, although any suitable switch may be employed. The delay circuit switch 316 includes an emitter electrically coupled to the high voltage line 302, a base electrically coupled to a fourth resistor R4, and a collector electrically coupled to a first terminal of a voltage dropping resistor 322. As shown in FIG. 3, a first terminal of the fourth resistor R4 is electrically coupled to the base of the delay circuit switch 316, and a second terminal of the fourth resistor R4 is electrically coupled to a second terminal of the third resistor R3.

[0072] 3, the voltage dropping resistor 322 includes a first terminal electrically coupled to the collector of the delay circuit switch 316. More specifically, the collector of the delay circuit switch 316 is electrically coupled to a first terminal of a fifth resistor R5. The fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 are electrically coupled in series with each other.

[0073] The collector of the delay circuit switch 316 is also electrically coupled to a ninth resistor R9. More specifically, the ninth resistor R9 has a first terminal electrically coupled to the collector of the delay circuit switch 316 and a second terminal electrically coupled to the low voltage line 304. Thus, a voltage dropping resistor 322 is also electrically coupled in parallel with the ninth resistor R9.

[0074] A first terminal of the RC network 323 is electrically coupled to the second terminal of the voltage dropping resistor 322. A second terminal of the RC network 323 is electrically coupled to the low voltage line 304. The RC network 323 is shown in FIG. 3 to include an eighth resistor R8, a first capacitor C1, and a second capacitor C2 electrically in parallel with one another. More specifically, first terminals of the eighth resistor R8, the first capacitor C1, and the second capacitor C2 are electrically coupled. Additionally, second terminals of the eighth resistor R8, the first capacitor C1, and the second capacitor C2 are electrically coupled to the low voltage line 304.

[0075] The first terminal of the RC network 323 is connected to a reference terminal resistor R REF via the voltage reference terminal V REF 3, the second terminal of the second voltage adjustable shunt regulator 324 is directly coupled to the low voltage line 304, although an indirect electrical coupling, such as a low resistance path, may also be employed.

[0076] A first terminal of the tenth resistor R10 is electrically coupled to the high voltage line 302. A first terminal of the eleventh resistor R11 is electrically coupled to a base of an SCR enable switch 326. The SCR enable switch 326 includes an emitter electrically coupled to the high voltage line 302 and a collector electrically coupled to a first terminal of a twelfth resistor R12. A second terminal of the twelfth resistor R12 is electrically coupled to a switchable low impedance path 330.

[0077] As shown in FIG. 3, the switchable low impedance path 330 includes an SCR 330D and a series resistor 330R, which correspond to the SCR 130D and the series resistor 130R described with reference to FIG. 1, respectively. A first terminal and a second terminal of the SCR 330D are electrically coupled to the high voltage line 302 and the low voltage line 304, respectively. Although the SCR 330D can be electrically coupled directly to the low voltage line 304, as shown in FIG. 3, the second terminal of the SCR 330 is electrically coupled to the low voltage line 304 through the series resistor 330R. It is noted that the series resistor 330R is also referred to as a thirteenth resistor. The SCR 330D and the series resistor 330R are arranged in series as shown in FIG. 1. The SCR 330D is shown as being a TS420 SCR, such as the TS420-600B-TR SCR manufactured by STMicroelectronics, although any suitable silicon controlled rectifier or thyristor may be used. The SCR 330D includes a gate electrically coupled to a second terminal of a twelfth resistor R12, the first terminal of which is electrically coupled to the collector of the SCR enable switch 326.

[0078] As discussed above and shown in FIG. 3, TVS diode 340 comprises four transient voltage shunt diodes. In particular, TVS diode 340 is shown as being comprised of four 5KP6 TVS diodes manufactured by Littelfuse. The four 5KP6 TVS diodes are in series, although any suitable circuit may be used. TVS diode 340 is arranged similarly to TVS diode 140 described with reference to FIG. 1. More particularly, a first terminal of TVS diode 340 is electrically coupled to high voltage line 302 and a second terminal of TVS diode 340 is electrically coupled to low voltage line 304. TVS diode 340 is electrically in parallel with intrinsically safe load ISL.

[0079] The first and second voltage adjustable shunt regulators 314, 324 may be Texas Instruments TLV431 shunt regulators, although any suitable adjustable shunt regulator may be used. As shown in FIG. 3, the first and second voltage adjustable shunt regulators 314, 324 are connected to a voltage reference terminal V REF The first and second voltage adjustable shunt regulators 314, 324 include a voltage reference terminal V REF If the voltage at the voltage reference terminal V is greater than the internal voltage reference value of the first and second voltage adjustable shunt regulators 314, 324, current can be conducted. REF is less than the internal voltage references of the first and second voltage adjustable shunt regulators 314, 324, the first and second voltage adjustable shunt regulators 314, 324 may be prevented from conducting.

[0080] 3, the first voltage adjustable shunt regulator 314 can be conductive when the voltage of the high voltage line 302 is greater than the voltage threshold and the first voltage reference V1 value is greater than the voltage reference value of the first voltage adjustable shunt regulator 314. As can be understood, the first voltage reference V1 value can be determined from the resistance values ​​of the first and second resistors R1, R2 of the voltage limiter 310. In the delay / LIP enable circuit 320, the second voltage adjustable shunt regulator 324 can be conductive when the voltage of the first terminal of the RC network 323 is greater than the voltage reference value of the second voltage adjustable shunt regulator 324.

[0081] As can be appreciated, when the first voltage adjustable shunt regulator 314 conducts current, the voltage at the base of the delay circuit switch 316 drops to a low state or value (e.g., zero volts or about zero volts), which increases the voltage difference between the base and emitter of the delay circuit switch 316. When the voltage difference between the base and emitter of the delay circuit switch 316 increases, the delay circuit switch 316 can conduct current between the emitter and collector of the delay circuit switch 316. This applies a voltage to the first terminal of the RC network, which begins to charge the first and second capacitors C1, C2 of the RC network 323, which can initiate the timer function of the delay / LIP enable circuit 320.

[0082] Similarly, when the second voltage adjustable shunt regulator 324 conducts current, the voltage at the base of the SCR enable switch 326 drops to a low voltage state or value (e.g., at or about zero volts), which increases the voltage difference between the base and emitter of the SCR enable switch 326. When the voltage difference between the base and emitter of the SCR enable switch 326 increases, the SCR enable switch 326 can conduct current between the emitter and collector of the SCR enable switch 326. This allows a gate voltage and current to be applied to the gate of SCR 130D.

[0083] When a gate voltage and current are applied to the gate of the SCR330D, the SCR330D can conduct a forward conduction current between its first and second terminals. The SCR330D can continue to conduct a forward conduction current between its first and second terminals even if the gate voltage and gate current at the gate return to zero. Thus, only a momentary increase in the gate voltage and current, such as a pulse at the gate, may be required to turn on the SCR330D. However, the SCR330D can stop conducting a forward conduction current between its first and second terminals when the gate voltage and current at the gate return to zero, for example, and the forward conduction current between the first and second terminals becomes less than the hold current of the SCR330D.

[0084] As will be appreciated, the calculated current value of series resistor 330R for a voltage on high voltage line 302 under operating conditions or in a non-overvoltage state may be zero or less than the latched value of SCR 330D. In contrast, when high voltage line 302 is in an overvoltage state, the current through series resistor 330R may be greater than the latched value of SCR 330D. Thus, when SCR 330D is enabled at a voltage that conducts forward conduction current, e.g., when high voltage line 302 is in an overvoltage state, SCR 330D can conduct forward conduction current.

[0085] Normal operation may be defined as when input 300i is not in an overvoltage condition, but delay circuit switch 316 and SCR enable switch 326 are not conducting current, more specifically, the bases of delay circuit switch 316 and SCR enable switch 326 do not have sufficient voltage to conduct current between the emitter and collector of delay circuit switch 316 and SCR enable switch 326, respectively.

[0086] Referring to the delay circuit switch 316, when the high voltage line 302 is not in an overvoltage state, no current flows between the emitter and collector of the delay circuit switch 316, and therefore no voltage is applied to the first terminal of the RC network 323. As a result, the reference voltage terminal of the second voltage adjustable shunt regulator 324 may have a voltage lower than the reference voltage of the second voltage adjustable shunt regulator 324. Thus, the voltage of the first terminal of the second voltage adjustable shunt regulator 324 may be greater than the voltage that the SCR enable switch 326 would allow current to flow if it were less than that. As a result, when the high voltage line 302 is not in an overvoltage state, the switchable low impedance path 330 remains open, thereby preventing current from flowing through the switchable low impedance path 330. More specifically, the SCR 330D may be prevented from allowing forward conduction current to flow.

[0087] When the input 300i is in an overvoltage condition, the voltage on the high voltage line 302 may cause the first voltage reference V1 value to be greater than a voltage reference value internal to the first voltage adjustable shunt regulator 314. As a result, the voltage at the base of the delay circuit switch 316 may be low enough (e.g., a low voltage state or value) for the delay circuit switch 316 to conduct current between the collector and emitter of the delay circuit switch 316. This may cause a voltage to be applied to the first terminal of the RC network 323.

[0088] Thus, the voltage at the first terminal of the RC network 323 may increase over time, i.e., the first and second capacitors C1, C2 of the RC network 323 may charge when the high voltage line 302 is in an overvoltage condition. When the voltage at the first terminal of the RC network 323 is greater than the voltage reference value of the second voltage adjustable shunt regulator 324, the second voltage adjustable shunt regulator 324 may conduct, which may cause the SCR enable switch 326 to conduct current between the emitter and the collector of the SCR enable switch 326.

[0089] As a result, an overvoltage condition on the high voltage line 302 closes the switchable low impedance path 330, thereby allowing forward conduction current to flow through the switchable low impedance path 330. More specifically, SCR 330D conducts, thereby allowing forward conduction current to flow from the high voltage line 302 to the low voltage line 304 through SCR 330D and series resistor 330R.

[0090] A high forward conduction current through the switchable low impedance path 330 may decrease or reduce the voltage value of the high voltage line 302. For example, if an overvoltage condition on the high voltage line 302 is due to a transient voltage being applied to the high voltage line 302, the voltage value of the high voltage line 302 may decrease due to a forward conduction current through the switchable low impedance path 330. It will also be appreciated that a decrease in the voltage value of the high voltage line 302 may cause the delay circuit switch 316 to open, thereby preventing current from flowing through the RC network 323.

[0091] As a result, the first and second capacitors C1, C2 can be discharged through the eighth resistor R8 to the low voltage line 304, e.g., ground. This can cause the voltage value at the first terminal of the RC network 323 to decrease over time. When the voltage at the first terminal decreases to the voltage reference value V REF When the high voltage line 102 decreases to a voltage value less than , the SCR enable switch 326 opens, thereby removing the gate voltage and current from the gate of the SCR 330D, but allowing the SCR 330D to continue to conduct forward current until the high voltage line 102 goes to zero volts (e.g., is pulled to ground), as explained above.

[0092] Operation of the timer-based protection circuit As will be appreciated, the voltage limiter 110, 310, delay / LIP enable circuit 120, 320, and switchable low impedance path 130, 330 can work in conjunction to allow current to flow through the TVS diode 140, 340 for a predetermined period of time. This predetermined period can be selected to ensure that the TVS diode 140, 340 does not catastrophically fail. For example, the sequence of events can be as follows: When an overvoltage condition is applied to the input 100i, 300i, the voltage limiter 110, 310 enables the timer function of the delay / LIP enable circuit 120, 320.

[0093] Thus, the voltage limiter 110, 310 and delay / LIP enable circuit 120, 320 require a delay before triggering the switchable low-impedance path 130, 330, thereby preventing false triggering of the switchable low-impedance path 130, 330. After a predetermined period of time, which is at or near the charge time of one or more capacitors of the RC network 123, 323, the delay / LIP enable circuit 120, 320 can provide a signal to the switchable low-impedance path 130, 330. This signal allows the switchable low-impedance path 130, 330 to conduct forward conduction current between the high voltage line 102, 302 and the low voltage line 104, 304. As a result, the voltage value of the high voltage line 102, 302 can be reduced or dropped to a value at which the voltage limiter 110, 310 no longer applies a voltage to the delay / LIP enable circuit 120, 320. As a result, the delay / LIP enable circuit 120 , 320 may not apply a signal to the switchable low impedance path 130 , 330 .

[0094] However, even if the switchable low impedance path 130, 330 no longer receives a signal, the switchable low impedance path 130, 330 can still carry a forward conduction current as long as the current between the high voltage line 102, 302 and the low voltage line 104, 304 is greater than the holding current of the switchable low impedance path 130, 330. Depending on the holding current of the low impedance path 130, 330, the forward conduction current through the switchable low impedance path 130, 330 can be greater than the holding current as long as the input 100i, 300i is in an overvoltage condition or is experiencing any voltage.

[0095] It should also be appreciated that while the switchable low-impedance path 130, 330 is conducting, no current may be flowing through the TVS diode 140, 340. That is, the voltage at which the switchable low-impedance path 130, 330 passes current may be less than the voltage (e.g., breakdown voltage) required to pass current through the TVS diode 140, 340. The above timing is described in more detail below with reference to FIG.

[0096] Illustrative Timing Diagram FIG. 4 shows a timing diagram 400 illustrating the timing of a timer-based fault protection circuit, such as the timer-based fault protection circuits 100, 300 described above with reference to FIGS. 1-3. As shown in FIG. 3, the timing diagram 400 includes a time axis 410 in milliseconds (ms) and a voltage axis 420 in volts (V). The scale of the time axis 410 is 100 ms per main line division. The time axis 410 has 10 main line divisions. Thus, the range of the time axis 410 is 1000 ms or 1 second. The scale of the voltage axis is channel dependent, with each channel indicated on the timing diagram by an arrow with a channel number on the left side of the timing diagram 400. The voltage scale is 2.00 V for channel 1 Ch1, 5.00 V for channel 2 Ch2, and 10.0 V for channel 3 Ch3.

[0097] The timing diagram 400 also includes voltage plots 430, including a timer capacitor voltage plot 432, an SCR series resistor voltage plot 434, and a supply line voltage plot 436. The timer capacitor voltage plot 432 is associated with channel 1 Ch1, the SCR series resistor voltage plot 434 is associated with channel 2 Ch2, and the supply line voltage plot 436 is associated with channel 3 Ch3. From 0 ms to about 300 ms, the timer capacitor voltage plot 432 is near zero volts. From about 300 ms to about 600 ms, the timer capacitor voltage plot 432 increases from zero to about 1.88V. The period from about 300 ms to about 600 ms illustrates the functionality of the timer-based fault protection circuits 100, 300 described above, as will be described in more detail below.

[0098] From time T1 to time T2, a normal operating voltage of 22V is applied to the input 100i, 300i of the timer-based fault protection circuit 100, 300. Thus, the supply line voltage plot 436 remains at 22V. Similarly, the timer capacitor voltage plot 432 remains at zero, indicating that the voltage limiter 110, 310 has not yet started applying voltage to the first terminal of the RC network 123, 323. This is because the reference voltage V1 has not yet exceeded the internal voltage reference value of the first voltage adjustable shunt regulator 114, 314.

[0099] From time T2 to T3, the supply line voltage plot 336 increases from 22V to approximately 29V due to the fault voltage of 32V being applied to the input 100i, 300i. That is, the TVS diode 140, 340 prevents the voltage on the high voltage line 102, 302 from exceeding a threshold voltage, such as the breakdown voltage of the TVS diode 140, 340. However, the TVS diode 140, 340 may need to conduct a large amount of current to do so. While the TVS diode 140, 340 is suitable for preventing transient or very short duration high voltage events, it may not be as suitable as, for example, an SCR, thyristor, etc., to conduct current during an overvoltage condition that is longer than the duration of a transient event. For example, the TVS diode 140, 340 has a tendency to fail if it conducts current for more than a few seconds. Thus, to prevent this from happening, the timing described below may be used, although any suitable timing and timer-based fault protection circuitry may be used.

[0100] Immediately after the 32V fault voltage is applied at time T2, the timer capacitor voltage plot 432 begins to increase from zero volts due to the voltage limiter 110, 310 applying a voltage to the delay circuit switch 116, 316, which causes a charging current to flow to the first terminal of the RC network 123, 323. At time T3, the supply line voltage plot 436 shows a level of approximately 29V as the TVS diode 140, 340 conducts at its breakdown voltage.

[0101] From time T3 to T4, the supply line voltage plot 436 remains at approximately 29V and the timer capacitor voltage plot 432 continues to increase because the delay circuit switch 116 continues to apply a voltage to the first terminal of the RC network 123, 323. The SCR series resistor voltage plot 434 remains at zero volts because the SCR enable switch 126, 326 is not enabling the SCR 130D, 330D.

[0102] At time T4, the voltage at the first terminal of the RC network 123, 323 closes the second voltage adjustable shunt regulator 124, 324, which causes the SCR enable switch 126, 326 to close the switchable low impedance path 130, 330. This allows current to flow through the switchable low impedance path 130, 330. More specifically, the SCR enable switch 126, 326 applies a non-zero gate voltage and sufficient gate current to the gate of the SCR 130D, 330D, thereby causing the SCR 130D, 330D to conduct.

[0103] As a result, at time T4, the supply line voltage plot 436 drops from 29V to approximately 7V. At substantially the same time, the SCR series resistor voltage plot 434 increases from zero volts to approximately 7 volts because the SCRs 130D, 330D are conducting current through the series resistors 130R, 330R. Thus, the following method 500 can be performed using the timer-based fault protection circuits 100, 300, or another similar timer-based fault protection circuit.

[0104] FIG. 5 illustrates a method 500 for forming a timer-based fault protection circuit. As shown in FIG. 5, the method 500 begins in step 510 by electrically coupling a voltage limiter and a delay / LIP enable circuit to the high and low voltage lines in electrical parallel with the intrinsically safe load. In step 520, the method 500 electrically couples a switchable low impedance path to the high and low voltage lines in a shunt configuration with respect to the intrinsically safe load. In step 530, the method 500 communicatively couples the voltage limiter to the delay / LIP enable circuit and configures the voltage limiter to provide a signal to the delay / LIP enable circuit. In step 540, the method 500 communicatively couples the delay / LIP enable circuit to the switchable low impedance path and configures the delay / LIP enable circuit to provide a signal to the switchable low impedance path. In step 550, the method 500 can be configured to configure the delay / LIP enable circuit to provide a signal to the switchable low impedance path.

[0105] The method 500 may also include configuring a high voltage line to be electrically coupled to a first terminal of an intrinsically safe load and / or configuring a low voltage line to be electrically coupled to a second terminal of an intrinsically safe load. For example, the method 500 may attach a terminal, a lead, a connector, another wire, or the like to an end of the high voltage line and / or the low voltage line. Additionally, the method 500 may further include electrically coupling a first terminal of a transient voltage suppression diode to the high voltage line and a second terminal to the low voltage line. The transient voltage suppression diode may be configured to conduct current between the high voltage line and the low voltage line when the voltage of the high voltage line is greater than a breakdown voltage of the transient voltage suppression diode. The transient voltage suppression diode of the method 500 may be the TVS diode 140, 340 described above, although any suitable transient voltage diode may be employed.

[0106] Method 500 may also include configuring the switchable low impedance path to conduct current between the high voltage line and the low voltage line at a voltage less than the breakdown voltage of the transient voltage suppression diode when a signal is received from the delay / LIP enable circuit. Method 500 may also configure the voltage limiter to sense the voltage of the high voltage line relative to the voltage of the low voltage line and provide a signal to the delay / LIP enable circuit when the voltage of the high voltage line relative to the voltage of the low voltage line is greater than an overvoltage threshold. Method 500 may also configure the delay / LIP enable circuit to receive a signal from the voltage limiter, start a timer function of the delay / LIP enable circuit when the signal is received from the voltage limiter, and provide a signal to the switchable low impedance path when the timer function reaches a delay threshold.

[0107] The method 500 may include, in step 510, any suitable voltage limiter coupled to the high voltage line and the low voltage line. For example, the voltage limiter of the method 500 may be the voltage limiter 110, 310 described above. Thus, the voltage limiter of the method 500 may include a voltage divider having a first terminal electrically coupled to the high voltage line and a second terminal electrically coupled to the low voltage line. The voltage divider may be configured to provide a reference voltage based on a voltage of the high voltage line relative to a voltage of the low voltage line. The voltage limiter of the method 500 may include a first voltage adjustable shunt regulator comprising a first terminal electrically coupled to the high voltage line, a second terminal electrically coupled to the low voltage line, and a voltage reference terminal configured to receive the reference voltage. The first voltage adjustable shunt regulator may be configured to conduct a current based on the reference voltage.

[0108] Method 500 may also include, at step 510, coupling any suitable delay / LIP enable circuit to the high and low voltage lines. For example, the delay / LIP enable circuit of method 500 may include one of the delay / LIP enable circuits 120, 320 described above. Thus, the delay / LIP enable circuit of method 500 may include an RC network configured to receive a signal from a voltage limiter and to charge one or more capacitors in the RC network to a voltage using the signal from the voltage limiter, a second voltage adjustable shunt regulator electrically coupled to the RC network and configured to receive the voltage of the one or more capacitors in the RC network and conduct a current based on the voltage of the one or more capacitors in the RC network, and an SCR enable switch electrically coupled to the second voltage adjustable shunt regulator. The SCR enable switch is configured to provide a signal to a switchable low impedance path when the second voltage adjustable shunt regulator conducts current.

[0109] The second voltage adjustable shunt regulator can include a first terminal electrically coupled to the high voltage line and to the base terminal of the SCR enable switch, a second terminal electrically coupled to the low voltage line, and a reference voltage terminal configured to receive a voltage across the one or more capacitors of the RC network. The second voltage adjustable shunt regulator is configured to direct a current from the high voltage line to the low voltage line in proportion to the voltage across the one or more capacitors of the RC network.

[0110] The switchable low impedance path of step 520 may include an SCR having a first terminal electrically coupled to the high voltage line, a second terminal electrically coupled to the low voltage line, and a gate electrically coupled to the SCR enable switch to receive a signal from the delay / LIP enable circuit. The SCR may be configured to conduct a forward conduction current between the high voltage line and the low voltage line when the signal from the delay / LIP enable circuit exceeds a gate threshold. The signal received from the delay / LIP enable circuit may include a gate voltage and current that exceeds a gate threshold that is sufficient to safely trigger the SCR.

[0111] The timer-based fault protection circuit 100, 300 and method 500 described above may allow the switchable low impedance path 130, 330 to conduct forward conduction current between the high voltage line 102, 302 and the low voltage line 104, 304 after a period of time or delay. The period of time may be from the time when an overvoltage condition is applied to the high voltage line. The period of time or delay may be configurable, for example, by selecting the capacitance value of the RC network 123, 323 described above. The switchable low impedance path 130, 330 may conduct forward conduction current at a voltage value that is less than the breakdown voltage of the TVS diodes 140, 340 electrically coupled to the high voltage line 102, 302 and the low voltage line.

[0112] As a result, the TVS diode 140, 340 is not subjected to current for longer than the period or delay, which can be selected to ensure that the overvoltage condition does not cause a current to flow through the TVS diode 140, 340 for longer than the rated period of the TVS diode 140, 340 for the voltage of the overvoltage condition, for example. Furthermore, the timer-based fault protection circuit 100, 300 automatically returns to a normal operating state in which the switchable low impedance path 130, 330 does not conduct current after the overvoltage condition has ended. This ensures that the only return path from the high voltage line to the low voltage line is via the intrinsically safe load ISL.

[0113] Thus, the timer-based fault protection circuits 100, 300 and method 500 can ensure adequate protection against a variety of overvoltage conditions while minimizing the amount of interference and resistive losses required in providing such protection. The timer-based fault protection circuits 100, 300 and method 500 can also minimize the power consumption required while an overvoltage condition exists. Thus, the required form factor size and cost can be smaller than, for example, a high wattage Zener diode only circuit.

[0114] The detailed description of the above embodiments is not an exhaustive description of all embodiments contemplated by the inventors to be within the scope of the present specification. Indeed, those skilled in the art will recognize that certain elements of the above embodiments can be combined or deleted in various ways to create further embodiments, and that such further embodiments will fall within the scope and teachings of the present specification. It will also be apparent to those skilled in the art that the above embodiments can be combined in whole or in part to create additional embodiments within the scope and teachings of the present specification.

[0115] Thus, while specific embodiments have been described herein for illustrative purposes, those skilled in the art will recognize that various equivalent modifications are possible within the scope of the present disclosure. The teachings provided herein may be applied to timer-based fault protection circuits as well as the embodiments described above and illustrated in the accompanying drawings. Thus, the scope of the above-described embodiments should be determined from the following claims.

Claims

1. A timer-based fault protection circuit (100, 300), comprising: a high voltage line (102, 302) configured to be electrically coupled to a first terminal of an intrinsically safe load (ISL); a low voltage line (104, 304) configured to be electrically coupled to a second terminal of the intrinsically safe load (ISL); a voltage limiter (110, 310) and a delay / LIP enable circuit (120, 320) coupled to the high voltage line (102, 302) and the low voltage line (104, 304) in electrical parallel with the intrinsically safe load (ISL); and a switchable low impedance path (130, 330) electrically coupled to the high voltage line (102, 302) and the low voltage line (104, 304) in a shunt configuration with respect to the intrinsically safe load (ISL); Equipped with the voltage limiter (110, 310) is communicatively coupled to the delay / LIP enable circuit (120, 320) and configured to provide a signal to the delay / LIP enable circuit (120, 320); A timer-based fault protection circuit (100, 300), wherein the delay / LIP enable circuit (120, 320) is communicatively coupled to the switchable low-impedance path (130, 330) and configured to provide a signal to the switchable low-impedance path (130, 330).

2. a transient voltage suppression diode (140, 340) having a first terminal electrically coupled to the high voltage line (102, 302) and a second terminal electrically coupled to the low voltage line (104, 304); 2. The timer-based fault protection circuit of claim 1, wherein the transient voltage suppression diode is configured to conduct current between the high voltage line and the low voltage line when a voltage on the high voltage line is greater than a breakdown voltage of the transient voltage suppression diode.

3. 3. The timer-based fault protection circuit of claim 2, wherein upon receiving the signal from the delay / LIP enable circuit, the switchable low impedance path is configured to conduct a forward conduction current between the high voltage line and the low voltage line at a voltage less than a breakdown voltage of the transient voltage suppression diode.

4. The voltage limiter (110, 310) Sensing the voltage of the high voltage line (102, 302) relative to the voltage of the low voltage line (104, 304); 2. The timer-based fault protection circuit of claim 1, further comprising: a delay / LIP enable circuit configured to provide said signal when a voltage on said high voltage line relative to a voltage on said low voltage line is greater than an overvoltage threshold.

5. The voltage limiter (110, 310) a voltage divider (112, 312) having a first terminal electrically coupled to the high voltage line (102, 302) and a second terminal electrically coupled to the low voltage line (104, 304), the voltage divider being configured to provide a reference voltage (V1) based on a voltage of the high voltage line (102, 302) relative to a voltage of the low voltage line (104, 304); and a first terminal electrically coupled to the high voltage line (102, 302), a second terminal electrically coupled to the low voltage line (104, 304), and a voltage reference terminal (V ＲＥＦ a first voltage adjustable shunt regulator (114, 314) having Equipped with 5. The timer-based fault protection circuit of claim 4, wherein the first voltage adjustable shunt regulator is configured to draw a current based on the reference voltage.

6. The delay / LIP enable circuit (120, 320) receiving the signal from the voltage limiter (110, 310); starting a timer function of said delay / LIP enable circuit (120, 320) upon receiving said signal from said voltage limiter (110, 310); providing said signal to said switchable low impedance path (130, 330) when said timer function reaches a delay threshold value; 2. The timer-based fault protection circuit (100) of claim 1, configured to:

7. The delay / LIP enable circuit (120, 320) an RC network (123, 323) configured to receive the signal from the voltage limiter (110, 310) and to charge one or more capacitors in the RC network (123, 323) to a voltage using the signal from the voltage limiter (110, 310); a second voltage adjustable shunt regulator (124, 324) electrically coupled to the RC network (123, 323) and configured to receive the voltage across one or more capacitors in the RC network (123, 323) and to direct a current based on the voltage across the one or more capacitors of the RC network (123, 323); and an SCR enable switch (126, 323) electrically coupled to the second voltage adjustable shunt regulator (124, 324), the SCR enable switch (126, 326) configured to provide the signal to the switchable low impedance path (130, 330) when the second voltage adjustable shunt regulator (124, 324) conducts the current; The timer-based fault protection circuit (100, 300) of claim 6, comprising:

8. The second voltage adjustable shunt regulator (124, 324): a first terminal electrically coupled to the high voltage line (102, 302) and to a base terminal of the SCR enable switch (126, 326); a second terminal electrically coupled to the low voltage line (104, 304); a reference voltage terminal (V ) configured to receive the voltage of the one or more capacitors of the RC network (123, 323); ＲＥＦ )and Equipped with 8. The timer-based fault protection circuit of claim 7, wherein the second voltage adjustable shunt regulator is configured to direct the current from the high voltage line to the low voltage line in proportion to the voltage of one or more capacitors of the RC network.

9. The switchable low impedance path (130, 330) an SCR (130D, 330D) having a first terminal electrically coupled to the high voltage line (102, 302), a second terminal electrically coupled to the low voltage line (104, 304), and a gate electrically coupled to the SCR enable switch (126, 326) to receive the signal from the delay / LIP enable circuit (120, 320); 2. The timer-based fault protection circuit of claim 1, wherein the SCR is configured to conduct a forward conduction current between the high voltage line and the low voltage line when the signal from the delay / LIP enable circuit exceeds a gate threshold.

10. 10. The timer-based fault protection circuit of claim 9, wherein the signal received from the delay / LIP enable circuit comprises a voltage value of the high voltage line that exceeds the gate threshold.

11. 10. The timer-based fault protection circuit of claim 9, wherein the SCR is configured to conduct the forward conduction current while the forward conduction current is greater than a holding current of the SCR.

12. A method for forming a timer-based fault protection circuit, configuring a high voltage line to electrically couple to a first terminal of an intrinsically safe load; configuring a low voltage line to electrically couple to a second terminal of the intrinsically safe load; coupling a voltage limiter and delay / LIP enable circuit to the high voltage line and the low voltage line in electrical parallel to the intrinsically safe load; electrically coupling a switchable low impedance path to the high voltage line and the low voltage line in a shunt configuration to the intrinsically safe load; communicatively coupling the voltage limiter to the delay / LIP enable circuit and configuring the voltage limiter to provide a signal to the delay / LIP enable circuit; communicatively coupling the delay / LIP enable circuit to the switchable low impedance path. and configuring said delay / LIP enable circuit to provide a signal to said switchable low impedance path; 13. A method for forming a timer based fault protection circuit, comprising:

13. electrically coupling a first terminal of a transient voltage suppression diode to the high voltage line and a second terminal of the transient voltage suppression diode to the low voltage line; 13. The method of claim 12, wherein the transient voltage suppression diode is configured to conduct current between the high voltage line and the low voltage line when the voltage on the high voltage line is greater than a breakdown voltage of the transient voltage suppression diode.

14. 14. The method of claim 13, further comprising, upon receiving the signal from the delay / LIP enable circuit, configuring the switchable low impedance path to conduct forward conduction current between the high voltage line and the low voltage line at a voltage less than a breakdown voltage of the transient voltage suppression diode.

15. The voltage limiter, sensing a voltage on the high voltage line relative to a voltage on the low voltage line; providing said signal to said delay / LIP enable circuit when a voltage on said high voltage line relative to a voltage on said low voltage line is greater than an overvoltage threshold; The method of claim 12 , further comprising the step of:

16. electrically coupling the voltage limiter to the high voltage line and the low voltage line; electrically coupling a first terminal of a voltage divider to the high voltage line and a second terminal of the voltage divider to the low voltage line, the voltage divider being configured to provide a reference voltage based on a voltage of the high voltage line relative to a voltage of the low voltage line; electrically coupling a first terminal of a first voltage adjustable shunt regulator to the high voltage line and a second terminal of the first voltage adjustable shunt regulator to the low voltage line, receiving the reference voltage at a voltage reference terminal of the first voltage adjustable shunt regulator, and configuring the first voltage adjustable shunt regulator to conduct a current based on the reference voltage; 16. The method of claim 15, comprising:

17. The delay / LIP enable circuit receiving the signal from the voltage limiter; starting a timer function of said delay / LIP enable circuit upon receiving said signal from said voltage limiter; providing said signal to said switchable low impedance path when said timer function reaches a delay threshold; The method of claim 12 , further comprising the step of:

18. said delay / LIP enable circuit comprising: an RC network configured to receive the signal from the voltage limiter and to charge one or more capacitors in the RC network to a voltage using the signal from the voltage limiter; a second voltage adjustable shunt regulator (124, 324) electrically coupled to the RC network and configured to receive the voltage across one or more capacitors in the RC network and to direct a current based on the voltage across the one or more capacitors of the RC network; and an SCR enable switch electrically coupled to the second voltage adjustable shunt regulator and configured to provide the signal to the switchable low impedance path when the second voltage adjustable shunt regulator conducts the current; 20. The method of claim 17 comprising:

19. the second voltage adjustable shunt regulator comprising: a first terminal electrically coupled to the high voltage line and to a base terminal of the SCR enable switch; A second terminal electrically coupled to the low voltage line. and a reference voltage terminal (V ＲＥＦ ) Equipped with 20. The method of claim 18, wherein the second voltage adjustable shunt regulator is configured to direct the current from the high voltage line to the low voltage line in proportion to the voltage across one or more capacitors of the RC network.

20. the switchable low impedance path being: an SCR having a first terminal electrically coupled to the high voltage line, a second terminal electrically coupled to the low voltage line, and a gate electrically coupled to the SCR enable switch to receive a signal from the delay / LIP enable circuit; 13. The method of claim 12, wherein the SCR is configured to conduct a forward conduction current between the high voltage line and the low voltage line when the signal from the delay / LIP enable circuit exceeds a gate threshold.

21. 21. The method of claim 20, wherein the signal received from the delay / LIP enable circuit comprises a voltage value of the high voltage line that exceeds the gating threshold.

22. 21. The method of claim 20, wherein the SCR is configured to conduct the forward conduction current while the forward conduction current is greater than a holding current of the SCR.

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