Output current sensing in high-side switch

Abstract

In one example, a system (100) includes a first power stage (102) including a first power field effect transistor (FET) (104) and a first sense transistor (106) coupled to the first power FET. The system (100) also includes a second power stage (162) including a second power FET (172) and a second sense transistor (174) coupled to the second power FET (172), the second power stage (162) being smaller than the first power stage. The system (100) includes a first switch (160) coupled to a gate (108) and a drain (112) of the first power FET, and a second switch (130) coupled to the first power stage and to the second power stage (162). The system (100) also includes a sense amplifier (132) coupled to the second switch (130), and the first power stage (102), the second power stage (162), and the sense amplifier (132) are coupled to a load terminal (140).

Description

[Technical field]

[0001] A high-side switch in an automotive or industrial application can couple to a power source and provide power from the main power source to downstream circuitry. The high-side switch can include diagnostic and protection circuitry. A cable or other connection may connect the high-side switch to the downstream circuitry. Wire break detection detects a disconnection between the high-side switch and the downstream circuitry. Summary of the Invention

[0002] In at least one example of the present description, a system includes a first power stage including a first power field effect transistor (FET) and a first sense transistor coupled to the first power FET. The system also includes a second power stage including a second power FET and a second sense transistor coupled to the second power FET, the second power stage being smaller than the first power stage. The system includes a first switch coupled to a gate and drain of the first power FET and a second switch coupled to the first power stage and the second power stage. The system also includes a sense amplifier coupled to the second switch, and the first power stage, the second power stage, and the sense amplifier are coupled to a load terminal.

[0003] In at least one example of the present description, a system includes a first power stage, the first power stage including a first power FET and a first sense transistor coupled to the first power FET, the first power stage configured to provide a first current to a load terminal. The system also includes a second power stage, the second power stage including a second power FET and a second sense transistor coupled to the second power FET. The second power stage is smaller than the first power stage, the second power stage configured to provide a second current to the load terminal. The system includes a first switch coupled to a gate and drain of the first power FET, the first switch configured to connect the gate of the first power FET to the drain. The system also includes a second switch coupled to the first power stage and the second power stage, the second switch configured to connect the first power stage or the second power stage to the sense amplifier.

[0004] In at least one example of the present description, a method includes providing a first current to a load using a first power stage in a first mode of operation, the first power stage including a first power FET and a first sense transistor. The method includes switching to a second mode of operation. In response to switching to the second mode of operation, the method includes providing a second current to the load using a second power stage, the second power stage including a second power FET and a second sense transistor. The method also includes connecting the first power FET in a diode-connected configuration. The method includes coupling the second sense transistor to a sense amplifier.

[0005] In at least one example of the present description, a system includes a first transistor configured to provide a first current to a load terminal in a first mode of operation. The system also includes a second transistor configured to provide a second current to the load terminal in a second mode of operation. The system includes a switch coupled to a gate and a drain of the first transistor, the switch configured to place the first transistor in a diode-connected configuration during the second mode of operation. The system also includes a comparator having a comparator output, a first comparator input, and a second comparator input, the first comparator input coupled to a voltage supply terminal and the second comparator input coupled to the load terminal, the comparator configured to provide a signal to exit the second mode of operation based on a comparison between the supply voltage and a voltage at the load terminal. [Brief description of the drawings]

[0006] [Figure 1A] 1A-1C are circuit diagrams of high-side switches in various examples.

[0007] [Figure 1B] 1A-1C are circuit diagrams of high-side switches in various examples.

[0008] [Figure 2A] 1 is a collection of graphs illustrating wire interruption modes and detection in various examples.

[0009] [Figure 2B] 1 is a collection of graphs illustrating wire interruption modes and detection in various examples.

[0010] [Diagram 3] 1 is a block diagram of a high-side switch according to various examples.

[0011] [Figure 4] FIG. 1 is a block diagram of a system including a high-side switch in accordance with various examples.

[0012] [Diagram 5] 1 is a flowchart of a method for low power mode output current sensing in a high side switch in accordance with various examples.

[0013] [Figure 6] 4 is a circuit diagram of a low power mode channel driver according to various examples. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The high-side switch may include a main power field effect transistor (FET) that couples power from a power source to a load, such as downstream circuitry. The high-side switch may include additional diagnostic and protection circuitry coupled to the high-side switch. The high-side switch may include a sense FET coupled to the power FET for sensing the current provided by the power FET to the load. The sense current is useful for controlling the current output of the power FET. The sense current may also be useful for detecting whether a wire break has occurred between the power FET and the load. A wire break may be detected by the output current dropping below a wire break threshold.

[0015] In some cases, the high-side switch includes sensing circuitry that detects the output current provided to the load, which may range from a few hundred milliamps to as high as 40 amps. However, the sensing circuitry may not be able to accurately detect the output current when it is in the range of 300 microamps to a few milliamps. This narrow range is useful for detecting whether a wire break has occurred between the high-side switch and the load.

[0016] In the examples herein, additional circuitry is included in the high-side switch, which allows the high-side switch to accurately detect both high load currents and much smaller currents for wire break detection. In a normal operating mode, a sense FET coupled to the power FET provides a sense current to a sense amplifier, which is useful for controlling the output current of the power FET. In response to an output current below a wire break detection threshold, a second operating mode, called a wire break mode, is enabled. In the wire break mode, a controller disables some of the circuitry in the high-side switch, allowing additional circuitry in the high-side switch to accurately measure a lower output current range to determine if a wire break has occurred. In the wire break mode, the gate of the power FET is connected to the drain of the power FET to form a diode-connected power FET. Also, a PMOS power stage comprising a p-channel metal-oxide semiconductor (PMOS) sense FET is turned on and coupled to the load (or load terminal) and the sense amplifier. The transistors of the PMOS power stage are smaller than the power FETs and can accurately sense the smaller output currents. The PMOS power stage provides a sense current to the sense amplifier based on the output current. A comparator determines whether the sensed current is below a wire break threshold, and in response to the sensed current being below a wire break threshold, a wire break fault is triggered.

[0017] In the examples herein, the PMOS power stage improves current sensing accuracy for wire break detection in parallel with the power FET sense circuitry. The existing sense amplifier of the high side switch is useful for wire break mode, therefore no additional amplifier is added to the circuitry, saving area. Multiple thresholds can be enabled for entering / exiting wire break mode and for detecting wire break. Also, by connecting the power FET in a diode-connected configuration during wire break mode, the output voltage drop can be limited during a sudden increase in output load current, which may not otherwise be supported by the smaller PMOS power stage.

[0018] 1A and 1B are circuit diagrams of a high-side switch with broken wire detection in accordance with various embodiments of the present disclosure. FIG. 1A illustrates a normal mode of operation of the high-side switch, and FIG. 1B illustrates a broken wire mode of operation. As described herein, certain circuit elements may be enabled or disabled in response to switching from the normal mode to the broken wire mode, and vice versa.

[0019] FIG. 1A is a circuit diagram of a high-side switch 100 in a normal operating mode in various examples herein. In the normal operating mode, some wire break detection circuitry is disabled, as described below. Also in the normal operating mode shown in FIG. 1A, a current sense loop uses a sense current to detect the output current and control the output current provided by the power FET. In this example, the high-side switch 100 includes a main power stage 102. The main power stage 102 includes a power FET 104 and a sense FET 106 (e.g., a sense transistor). The power FET 104 and the sense FET 106 are n-channel devices, such as n-channel metal-oxide semiconductor (NMOS) transistors in this example, although other types of transistors are useful in other examples. The power FET 104 and the sense FET 106 have a size ratio of M:1 in one example. The power FET 104 includes a gate 108, a source 110, and a drain 112. The gate 108 is coupled to a charge pump 114. The charge pump 114 is coupled to a charge pump voltage source V CP The charge pump 114 includes a pull-up current source 116 coupled to the gate 108 and source 110 of the power FET 104. The drain 112 of the power FET 104 is coupled to a supply voltage V at a node 122, which may be a voltage supply terminal. S In one example, V S is about 13V.

[0020] The sense FET 106 has a gate 124 that is coupled to the gate 108 of the power FET 104. The sense FET 106 has a drain 126 that is coupled to the node 122 and a source 128 that is coupled to a switch 130. The switch 130 couples the sense FET 106 to a sense amplifier 132. The sense amplifier has a first amplifier input 134, a second amplifier input 136, and an amplifier output 138. The first amplifier input 134 is coupled to the switch 130. The second amplifier input 136 is coupled to a load 140 (or a load terminal). The amplifier output 138 is coupled to a transistor 142. The transistor 142 is coupled to a resistor R3 144 that is coupled to ground 146. The resistor R3 and the transistor 142 are also coupled to a current sense amplifier 148. The current sense amplifier 148 is coupled to a voltage reference V REF The current sense amplifier 148 has a first current sense amplifier input 150 coupled to resistor R3 144. The current sense amplifier 148 has a second current sense amplifier input 152 coupled to resistor R3 144. The current sense amplifier 148 has a current sense amplifier output 154 coupled to the charge pump 114.

[0021] The high-side switch 100 also includes wire break detection circuitry that is disabled during normal operation mode. The wire break detection circuitry includes, in this example, a switch 160 and a PMOS power stage 162. The switch 160 is configured to connect the power FET 104 in a diode-connected configuration during the wire break mode. The switch 160 includes transistors 164 and 166, a resistor R1 168, and a current source 170. The transistors 164 and 166 may be PMOS transistors in one example. The switch 160 is coupled between the gate 108 of the power FET 104 and the drain 112 of the power FET 104. As will be described below, the switch 160 connects the power FET 104 in a diode-connected configuration during the wire break detection mode.

[0022] The PMOS power stage 162 includes a PMOS power FET 172, a PMOS sense FET 174, a resistor R2 176, and a current source 178. The PMOS power FET 172 and the PMOS sense FET 174 have a size ratio of N:1 in one example. The PMOS power FET 172 couples a supply voltage V S 1B , and is coupled to the load 140 in response to the PMOS power stage 162 being enabled. The PMOS power stage 162 is coupled to the sense amplifier 132 via the switch 130 during a wire break detection mode, which will be described below with respect to FIG. 1B . In this example, the PMOS power stage 162 includes PMOS transistors, although the power stage may have other types of transistors in other examples.

[0023] Figure 1A also shows the output current I OUT 182 and the sensed current I SNS 1A also includes a controller 186. The controller 186 controls some of the operation of the high-side switch 100. For example, the controller 186 is a digital controller that controls a switch that allows the high-side switch 100 to switch from a normal operation mode to a wire break detection mode and vice versa. During the normal operation mode, the switch 130 connects the sense FET 106 to the sense amplifier 132. During the wire break detection mode, the controller 186 switches the switch 130 to connect the PMOS power stage 162 to the sense amplifier 132. During the wire break detection mode, the controller 186 also disables the charge pump 114 and connects the switch 160 to the power FET 104. The operation of the wire break detection mode is described below with respect to FIG. 1B.

[0024] 1A, in normal operation mode, switch 160 and PMOS power stage 162 are disabled. Power FET 104 supplies output current I OUT 182 and at the load 140 an output voltage V OUT The sense FET 106 senses the current provided by the power FET 104 in a ratio of M:1 to generate an output current I OUT182 is mirrored to obtain the sensed current I SNS 184. The sensed current I SNS 184 travels through resistor R3 144, which in turn transfers the voltage V SNS which is then provided to a second current sense amplifier input 152. The current sense amplifier 148 and transistor 142 generate a sensed current I SNS The output of the current sense amplifier 148 at current sense amplifier output 154 controls the pull-up current source 116 and the pull-down current source 120 in the charge pump 114. The charge pump 114 controls the output current I provided by the power FET 104 to the load 140. OUT 182. Thus, the sense FET 106 controls the amount of sense current I 182 to control the operation of the power FET 104 during the normal operating mode, as shown in FIG. 1A. SNS 184 is provided to the current loop.

[0025] The normal operating mode can accurately sense currents from a few hundred milliamps to as high as 40 amps, which is a current detection range of 40 times to 100 times or more. However, the sensing circuitry enabled during the normal operating mode may not be able to accurately sense the output current when it is in the range of 300 microamps to a few milliamps, which may be the current range during a wire break condition. Detecting currents from 300 microamps to 40 amps is a range of over 100,000 times and is difficult to detect with a single current detection loop.

[0026] In the examples herein, a separate current sensing loop to sense a narrower range of output current is useful for broken wire detection, which involves activating switch 160 and activating PMOS power stage 162 via switch 130 during broken wire detection mode. The broken wire detection mode is described below in connection with FIG. 1B.

[0027] 1B is a circuit diagram of the high-side switch 100 in a wire break detection mode according to various examples herein. The components shown in FIG. 1B are similar to those shown in FIG. 1A, with like numbers referring to like components. In the wire break detection mode, the charge pump 114 is disabled and the sense FET 106 is disconnected from the sense amplifier 132 by the switch 130. Also in the wire break detection mode, the switch 160 is activated, which places the power FET 104 in a diode-connected configuration. The PMOS power stage 162 is activated in the wire break detection mode. Thus, in this mode, the PMOS power stage 162 provides an output current I OUT 182 to the load 140, and a sensed current I SNS 1B, the power FET 104 may also provide an auxiliary current 188 to the load 140 in some circumstances, as will be described below.

[0028] In operation, during the wire break detection mode, the power FET 104 is configured in a diode connected configuration via the switch 160. In response to entering the wire break detection mode, the controller 186 enables the switch 160, which couples the gate 108 to the drain 112 of the power FET 104. The charge pump 114 is disconnected from the power FET 104 and / or disabled. In response to entering the wire break detection mode, the sense FET 106 is disabled by switching the switch 130. In response to entering the wire break detection mode, the PMOS power stage 162 is enabled, which connects the PMOS power stage 162 to the sense amplifier 132. Enabling the PMOS power stage 162 couples the PMOS power FET 172 to the load 140 and the second amplifier input 136. In response to entering the wire break detection mode, the current sense amplifier output 154 is disconnected from the charge pump 114. In some examples, the acts of coupling, decoupling, connecting, and disconnecting in response to the wire break detection modes may be controlled by the controller 186. Any type of circuit element may be useful for connecting and disconnecting various circuit components in response to the switching modes of operation as described herein, such as switches, transistors, etc.

[0029] After the switch 160 is enabled, it reconfigures the power FET 104 as a diode-connected FET. By connecting the power FET 104 in a diode configuration, the power FET 104 can provide current to the load 140 in response to a large load current increase. In some examples, the PMOS power stage 162 is smaller than the main power stage 102. When a large load current increase occurs, the voltage V at the load 140 decreases. OUTmay not be able to be sustained by the PMOS power stage 162 alone. As an example, the impedance across the PMOS power FET 172 may be 25-50 ohms, and the impedance across the power FET 104 may be 10-100 milliohms. For a load current of 100 milliamps, the PMOS power FET 172 may create a voltage drop across the load 140 of 2.5-5 V. However, during operation in some examples, the voltage V across the load 140 may be 10-100 milliohms. OUT supply voltage V S It is useful to keep it close to the OUT The voltage at may be maintained by a diode-configured power FET 104.

[0030] In this example, the power FET 104 is a large FET and is configured as a diode. OUT is the threshold voltage V of the diode-configured power FET 104. Threshold When the voltage at gate 108 drops below V S (e.g., about 13V), the voltage at source 110 drops above the threshold voltage for turning on power FET 104, about 1V, in this example, and so turns on. S -V OUT >V Threshold , power FET 104 turns on. When turned on, power FET 104 provides additional current to load 140 beyond the current that PMOS power stage 162 can provide to the load. The additional current provided by power FET 104 is shown in FIG. 1B as auxiliary current 188. Thus, the diode-configured power FET 104 reduces the V OUT Limit the voltage drop at V OUT V S If the gate-source voltage of the power FET 104 remains near V Threshold and the power FET 104 remains off in the broken wire sensing mode.

[0031] In the wire break detection mode, the sense FET 106 is disconnected via the switch 130. Thus, the PMOS power stage 162 provides current sensing via the PMOS sense FET 174. The ratio of the PMOS power FET 172 to the PMOS sense FET 174 is N:1, which in one example may be on the order of 10:1. Because the PMOS power FET 172 and the PMOS sense FET 174 are smaller than the power FET 104, they can sense currents several times smaller than the normal current sense loop of FIG. 1A. In one example, wire break detection requires current sensing from about 300 microamps down to a few milliamps. The normal sense current loop may not be as sensitive as this, but the PMOS power stage 162 can sense currents this small.

[0032] In the broken wire detection mode, the PMOS sense FET 174 divides the output current I OUT 182 and sense current I SNS 184. The sensed current I SNS 184 passes through resistor R3 144 and the voltage V SNS Generates a voltage V SNS is provided to a comparator 190. The comparator 190 includes a first comparator input 192, a second comparator input 194, and a comparator output 196. The comparator output 196 is coupled to a wire break fault node WB_fault 198. SNS The voltage is provided to a second comparator input 194. A wire interruption reference voltage V WB is provided. SNS Voltage is V WB If the voltage is less than the threshold voltage, a wire break fault is reported in WB_fault 198. Thus, as shown in FIG. 1B, the output voltage V OUT while still maintaining a broken wire fault determination in a broken wire detection mode during low output current conditions.

[0033] 2A and 2B are a collection of graphs illustrating wire break modes and detection in various examples herein. In FIG. 2A, graph 200 shows an example of output current versus time, including wire break detection modes and wire break defect conditions. In FIG. 2B, graph 250 shows another example of output current versus time, where the output current is noisy and may cause glitch issues.

[0034] Referring again to FIG. 2A, graph 200 shows an I OUT The graph 200 shows OUT 2 shows two thresholds for ON_WB_DET 204 and WB_fault 206. When waveform 202 falls below ON_WB_DET 204, the wire break detection mode is on. Waveform 208 shows the state of the wire break detection mode. When waveform 208 is low, the wire break detection mode is off (e.g., high-side switch 100 is in normal operating mode). When waveform 208 is high, the wire break detection mode is on. As shown in graph 200, waveform 202 (I OUT ) falls below ON_WB_DET 204 at time t1. In response to waveform 202 falling below ON_WB_DET 204, waveform 208 goes from low to high. Thus, at time t1, high-side switch 100 enters broken wire detection mode. In this example, high-side switch 100 remains in broken wire detection mode until waveform 202 rises above ON_WB_DET 204. At time t4, waveform 202 rises above ON_WB_DET 204. Thus, at time t4, waveform 208 goes from high to low and high-side switch 100 exits broken wire detection mode.

[0035] As described above, the high-side switch 100 OUTThe wire break detection mode is entered and exited based on the value of I. FIG. 1B shows the circuit elements that are enabled and disabled during the wire break detection mode. The controller 186 or other digital circuit elements may enable and disable certain circuit components during the wire break detection mode. The controller 186 may also enable and disable certain circuit components during the wire break detection mode. OUT can be monitored to determine whether a broken wire detection mode is entered, such as at time t1 in graph 200.

[0036] When the high-side switch 100 is in wire break detection mode, I OUT A wire break fault will not be detected until I falls below the wire break fault threshold. A threshold 206 for wire break fault is shown in the graph 200. The threshold 206 for wire break fault threshold is less than the threshold 204 for wire break detection (ON_WB_DET). Thus, the high-side switch 100 detects I OUT When I falls below the threshold 204 for broken wire detection (ON_WB_DET), the broken wire detection mode is entered. While in broken wire detection mode, I OUT If I falls below a wire break fault threshold 206, a wire break fault is detected. As shown in graph 200, I OUT falls below the broken wire fault threshold 206 at time t2. Thus, at time t2, a broken wire is detected. Waveform 210 illustrates the broken wire fault detection. At time t2, the broken wire fault detection goes from low to high, indicating a broken wire fault. The broken wire fault indication continues until waveform 202 rises above the broken wire fault threshold 206. At time t3, I OUT exceeds the broken wire fault threshold 206. Thus, at time t3, the broken wire fault indicator goes from high to low.

[0037] FIG. 2A illustrates the state when the high-side switch 100 detects a current I OUT indicates that the wire break detection mode may be entered based on the value of I OUTIf the value of falls below a second threshold, a wire break is indicated. The second threshold is less than the first threshold. In one example, the first threshold can be about 4 mA. The second threshold can be, in one example, 300 microamps to 2 mA. The first threshold is OUT As long as I remains above the first threshold, it allows the high-side switch 100 to operate in normal mode. OUT If I falls below the first threshold, the high-side switch 100 enters wire break detection mode and detects a wire break at the second threshold. OUT Monitor.

[0038] FIG. 2B shows a graph 250 of output current versus time, where the output current can be noisy and cause glitch problems. OUT is shown as waveform 252. Graph 250 shows I OUT 2A shows two thresholds for the on-wire break detection (ON_WB_DET) threshold 254 and the wire break fault (WB_fault) threshold 256. These two thresholds operate as described above with respect to FIG.

[0039] Graph 250 also shows waveform 258, which is the state of the wire break detection mode. Waveform 260 is the state of a wire break fault WB_fault. Waveform 252 shows the I OUT 2, indicates that the high-side switch 100 enters the broken wire detection mode (e.g., waveform 258 goes high) as ON_WB_DET falls below threshold 254. At time t2, the high-side switch 100 exits the broken wire detection mode (e.g., waveform 258 goes low). At time t3, the high-side switch 100 again enters the broken wire detection mode (e.g., waveform 258 goes high).

[0040] As high-side switch 100 thus goes in and out of broken wire detection mode, waveform 258 is shown as switching between an on state and an off state, causing glitches in area 262 of graph 250. Similarly, at time t4, high-side switch 100 goes in and out of broken wire detection mode as shown in waveform 252 (e.g., I OUT ) drops below threshold 256. Waveform 260 goes high at time t4 to indicate a wire break. At time t5, waveform 252 rises above threshold 256 and the wire break fault is released (e.g., waveform 260 goes low). At time t6, high-side switch 100 again detects the wire break fault as waveform 252 drops below threshold 256. Then, at time t7, waveform 252 rises above threshold 256 and the wire break fault is again released (e.g., waveform 260 goes low). Thus, waveform 260 also glitches in area 264 as waveform 252 repeatedly crosses threshold 256 for a short period of time.

[0041] A deglitching process may be implemented to remove the glitches in areas 262 and 264. Any suitable deglitching process may be useful. For example, hysteresis may be added to the system to prevent high-side switch 100 from quickly switching in and out of broken wire detection mode to prevent broken wire faults from turning on and off as shown in graph 250. In another example, digital control circuitry performing deglitching, such as a digital state machine, may be implemented.

[0042] FIG. 3 is a block diagram of a high-side switch 300 in various examples herein. The components within the high-side switch 300 are described above with respect to FIGS. 1A and 1B, with like numerals indicating like components. The high-side switch 300 illustrates the main components of a high-side switch, including the load 140. The components illustrated in the high-side switch 300 may be implemented using any suitable digital or analog circuitry. FIGS. 1A and 1B illustrate example circuitry for these components, but other circuitry is useful in other examples. For example, the switch 160 is a PMOS switch in FIGS. 1A and 1B, but any circuitry that constitutes a switch is useful in other examples. As another example, the main power stage 102 includes an NMOS power FET in FIGS. 1A and 1B, but other circuitry is useful in other examples to create the main power stage 102. The controller 186 may be any type of digital controller, digital circuitry, microcontroller, processor, or other suitable component.

[0043] FIG. 4 is a block diagram of a system 400 with a high-side switch in various examples herein. System 400 includes an integrated circuit ("chip") 401. System 400 is useful in some examples for automotive or industrial applications. System 400 is one example system that may include wire break detection, although wire break circuitry as described herein may be included in other systems in other examples. In this example, chip 401 includes wire break detection 402, a serial peripheral interface (SPI) 404, an analog to digital converter 406, and a multiplexer 408. Chip 401 also includes an input supply output voltage monitor 410, a charge pump 412, and a light emitting diode (LED) module 414. LED module 414 may be coupled to an LED 416, which may be located external to chip 401. Chip 401 also includes a gate drive 418, an output clamp 420, a current sense 422, and a temperature sense 424. The system 400 includes a microcontroller (MCU) 426 in this example.

[0044] In one example, the wire break detection 402 includes some of the circuit elements described above with respect to Figures 1A and 1B. When the wire break detection 402 detects a wire break, a fault signal is sent to the MCU 426 via the SPI 404. The voltage supply V S may be 24V in one example, and other voltages may be derived from a 24V power supply.

[0045] 5 is a flow chart of a method 500 for low power mode output current detection in a high side switch in accordance with various examples herein. The steps of method 500 may be performed in any suitable order. The hardware components described above with respect to FIG. 1A, FIG. 1B, FIG. 3, or FIG. 4 may perform method 500 in some examples.

[0046] The method 500 begins at 510, where a first power stage, such as the main power stage 102, provides a first current to a load (or load terminals) in a first operating mode, the first power stage including a first power FET (such as the power FET 104) and a first sense transistor (such as the sense FET 106).

[0047] The method 500 continues at 520 where the method switches to a second mode of operation. In some examples, the method 500 includes: OUT 182 falls below the first threshold, the second operating mode is switched to. OUT 182 may indicate near the broken wire detection threshold, therefore the system switches into broken wire detection mode.

[0048] The method 500 continues at 530, where in response to switching to the second operating mode, a second power stage (such as PMOS power stage 162) provides a second current to the load (or load terminals). The second power stage includes a second power FET (such as PMOS power FET 172) and a second sense transistor (such as PMOS sense FET 174). In other examples, transistors other than PMOS transistors are useful in the second power stage.

[0049] The method 500 continues at 540 where, in response to switching to the second mode of operation, a first power FET (e.g., power FET 104) is connected in a diode configuration. In one example, switch 160 is actuated to connect power FET 104 in a diode configuration. In other examples, different types of switches or connections are useful.

[0050] The method 500 continues at 550 where, in response to switching to the second mode of operation, a second sense transistor is coupled to the sense amplifier. In one example, the switch 130 switches to couple a second sense transistor (e.g., PMOS sense FET 174) to the sense amplifier 132. In the second mode of operation, the PMOS sense FET 174 provides a sense current for determining wire break detection.

[0051] 6 is a circuit diagram of a low power mode (LPM) channel driver 600 according to various examples herein. Some components shown in FIG. 6 are similar to components shown in FIG. 1A and FIG. 1B, and like numbers refer to like components. The channel driver 600 also includes a transistor 602, a resistor R2 604, a first bias current source 606, a second bias current source 608, and a comparator 610. The comparator 610, in one example, has a low input offset and a low quiescent current (I Q6.) voltage comparator. Comparator 610 includes a first comparator input 612, a second comparator input 614, and a comparator output 616. Comparator output 616 may provide a signal to digital circuitry or a controller (not shown in FIG. 6) in response to a certain condition being met in channel driver 600. FIG. 6 also includes an auxiliary output current 618, which in one example may provide auxiliary power to a load.

[0052] The channel driver 600, in one example, may have a diode-connected power FET 104 as a voltage clamp. In this example, the switch 160 is actuated to place the power FET 104 in a diode-connected configuration by coupling the gate 108 of the power FET 104 to the drain 112 of the power FET 104. In the diode-connected configuration, the charge pump 114 is disconnected from the gate 108 of the power FET 104. In this configuration, as shown in FIG. 6, the channel driver 600 is operating in a low power mode, where the transistor 602 is on and provides an output current I to the load 140. OUT 182. The transistor 602 may be a p-channel FET (PFET) in this example. In some examples, the transistor 602 may have an I Q In one example, the first bias current source 606 and the second bias current source 608 may provide small currents, on the order of a few hundred nanoamps. Thus, in this configuration, the channel drive I Q can be as small as a few microamps per channel.

[0053] Comparator 610 is connected to a voltage source V S 122 and a second comparator input 614 coupled to the load 140. The comparator 610 is configured to detect any load condition changes by performing a comparison and providing an LPM Exit Control signal at a comparator output 616 based on the comparison. OUT is the voltage source V S122 by a predetermined threshold, the comparator 610 provides an LPM Exit Control signal at a comparator output 616. The LPM Exit Control signal may be provided to digital circuitry or a controller, in one example. In response to the LPM Exit Control signal, the channel driver 600 exits LPM. To exit LPM, the controller causes the switch 160 to disconnect the power FET 104 from the diode-connected configuration and causes the charge pump 114 to resume providing a voltage to the gate 108 of the power FET 104. The charge pump 114 provides a voltage to the gate 108 to turn on and drive the power FET 104 for operation in normal mode (e.g., non-low power mode). The detection threshold may be determined, in one example, by the size of the transistor 602 and the maximum output current I supported in LPM. OUT 182. As an example, the voltage threshold of the comparator 610 may be determined based on the output current I multiplied by the resistance of the transistor 602 when the transistor 602 is on. OUT A maximum direct current (DC) value of 182 may be used.

[0054] In the examples herein, the PMOS power stage 162 improves current sensing accuracy for wire break detection in parallel with the sense circuitry of the power FET 104. The existing sense amplifier 132 of the high side switch is useful for wire break mode, therefore no additional amplifier is added to the circuit, saving area. As discussed above with respect to Figures 2A and 2B, multiple thresholds can be enabled for entering / exiting wire break mode and for detecting wire break. Also, by connecting the power FET 104 in a diode connected configuration during wire break mode, the output voltage V OUT The drop may be limited, which may not be supported by the smaller PMOS power stage 162.

[0055] In another example, a low power mode channel driver is provided. A comparator 610 can place the channel driver in either an LPM or normal operating mode by providing a signal to a controller or digital circuitry. The output voltage V OUT If falls below a tolerance threshold, the comparator 610 may provide a signal to exit LPM and resume operation in normal mode. LPM may, in some examples, be Q can be reduced to as little as a few microamps per channel.

[0056] The term "couple" in this description may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A provides a signal to control device B to perform a certain action, (a) in a first example, device A is directly connected to device B, or (b) in a second example, device A is coupled to device B via an intervening component C, where intervening component C does not change the functional relationship between device A and device B, thereby allowing device B to be controlled by device A via the control signal provided by device A.

[0057] A device that is "configured to" perform a certain task or function may be configured (e.g., programmed and / or hardwired) at the time of manufacture by a manufacturer to perform that function and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the hardware components, the interconnections of the device, or through a combination thereof.

[0058] A circuit or device described herein as including certain components may instead be adapted to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources during or after manufacture, e.g., by an end user and / or a third party, to form the described structure.

[0059] Although certain components may be described herein as being of a particular process technology, these components may be replaced with components of other process technologies. The circuits described herein are reconfigurable to include replaced components to provide functionality at least partially similar to that available prior to the component replacement. A component shown as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown, unless otherwise noted. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as a single resistor or capacitor.

[0060] Use of the term "ground" in the preceding description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of the present description. As used herein, unless otherwise indicated, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of that parameter. Modifications may be made to the described examples and other embodiments are possible within the scope of the present claims.

Claims

1. 1. A system comprising: a first power stage including a first power field effect transistor (FET) and a first sense transistor coupled to the first power FET; a second power stage including a second power FET and a second sense transistor coupled to the second power FET, the second power stage being smaller than the first power stage; a first switch coupled between the gate and drain of the first power FET; a second switch having a first terminal coupled to the first power stage, a second terminal coupled to the second power stage, and a third terminal; a sense amplifier coupled to the third terminal of the second switch; Including, The system wherein the first power stage, the second power stage, and the sense amplifier are each coupled independently to a load terminal.

2. 10. The system of claim 1, The system wherein the first power stage is a high-side switch power stage.

3. 10. The system of claim 1, The system further includes a charge pump coupled to a gate of the first power FET.

4. 10. The system of claim 1, The system wherein the first sense transistor is coupled to a first input of the sense amplifier via the second switch during a first mode of operation.

5. 10. The system of claim 1, The system wherein the second sense transistor is coupled to the first input of the sense amplifier via the second switch during a second mode of operation.

6. 1. A system comprising: a first power stage including a first power field effect transistor (FET) coupled to a load terminal and a first sense transistor coupled to the first power FET, the first power FET configured to provide a first current to the load terminal; a second power stage including a second power FET coupled to the load terminal and a second sense transistor coupled to the second power FET, the second power stage being smaller than the first power stage, the second power FET configured to provide a second current to the load terminal; a first switch coupled between a gate and a drain of the first power FET, the first switch configured to connect the gate of the first power FET to the drain of the first power FET; a second switch having a first terminal coupled to the first power stage, a second terminal coupled to the second power stage, and a third terminal, the second switch configured to connect the first power stage or the second power stage to the third terminal; Including, the system.

7. 7. The system of claim 6, The system further comprising a charge pump coupled to a gate of the first power FET, the charge pump configured to bias the first power FET.

8. 7. The system of claim 6, a sense amplifier coupled to the third terminal of the second switch; the first switch is further configured to disconnect a gate of the first power FET from a drain of the first power FET during a first mode of operation, and the second switch is further configured to connect the first power stage to the sense amplifier during the first mode of operation.

9. 7. The system of claim 6, a sense amplifier coupled to the third terminal of the second switch; the first switch is further configured to connect a gate of the first power FET to a drain of the first power FET during a wire-breaking mode of operation, and the second switch is further configured to connect the second power stage to the sense amplifier during the wire-breaking mode of operation.

10. 10. The system of claim 9, a charge pump coupled to a gate of the first power FET; A system wherein entering the cut-wire mode of operation disables the charge pump.

11. 7. The system of claim 6, a sense amplifier coupled to the third terminal of the second switch; a controller configured to change states of the first switch and the second switch in response to a first sense current provided to the sense amplifier falling below a first threshold; The system further comprises:

12. 12. The system of claim 11, The system wherein the first sense transistor is configured to provide the sense current to the sense amplifier.

13. 12. The system of claim 11, The system, wherein the controller is further configured to generate a wire break fault in response to the second sensed current falling below a second threshold.

14. 14. The system of claim 13, The second threshold is lower than the first threshold.

15. 14. The system of claim 13, The system wherein the second sense transistor is configured to provide the second sense current to the sense amplifier.

16. 1. A method comprising: providing a first current to a load using a first power stage including a first power field effect transistor (FET) and a first sense transistor in a first mode of operation; switching to a second mode of operation; responsive to the second mode of operation, providing a second current to the load using a second power stage including a second power FET and a second sense transistor, connecting the first power FET in a diode-connected configuration and coupling the second sense transistor to a sense amplifier; A method comprising:

17. 17. The method of claim 16, The method, wherein switching to the second mode of operation includes switching to the second mode of operation in response to the first current crossing a first threshold.

18. 18. The method of claim 17, The method further includes generating, by a controller, a wire-broken fault in response to the second current falling below a second threshold.

19. 17. The method of claim 16, The method further includes providing, by the first power FET, an auxiliary current to the load in the second mode of operation.

20. 17. The method of claim 16, The method of claim 1, wherein the first sense transistor is configured to be coupled to the sense amplifier during the first mode of operation.

21. 1. A system comprising: a first transistor configured to provide a first current to the load terminal in a first mode of operation; a second transistor configured to provide a second current to the load terminal in a second mode of operation; a switch coupled between the gate and drain of the first transistor, the switch configured to place the first transistor in a diode-connected configuration during the second mode of operation; a comparator having a comparator output and a first comparator input coupled to a voltage supply terminal and a second comparator input coupled to the load terminal, the comparator being configured to provide a signal to exit the second operating mode based on a comparison between a supply voltage and a voltage at the load terminal; Including, the system.

22. 22. The system of claim 21, Exiting the second mode of operation comprises: disconnecting the first transistor from the diode-connected configuration; coupling a charge pump to a gate of the first transistor; providing the first current to the load terminals; Including, the system.

23. 22. The system of claim 21, The system, wherein the comparator is further configured to exit the second mode of operation in response to a voltage at the load terminals falling below a predetermined threshold.

24. 22. The system of claim 21, The system wherein the second operating mode is a low power operating mode.

25. 22. The system of claim 21, The system, wherein the first transistor is further configured to provide an auxiliary current to the load terminal during the second mode of operation.

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