Process for fabricating a dual semiconductor-on-insulator structure

Abstract

The invention relates to a process for producing a double semiconductor-on-insulator structure, the double semiconductor-on-insulator structure comprising, from the back side to the front side of the structure, a handle substrate, a first electrically insulating layer (1b), a first monocrystalline semiconductor layer (2), a second electrically insulating layer (2b) and a second monocrystalline semiconductor layer (3), characterized in that the process comprises a first step of oxide layer formation on the front and back sides of the handle substrate to form the first electrically insulating layer (1b) and an oxide layer (1a') on the back side of the handle substrate, a first step of layer transfer to transfer the first monocrystalline semiconductor layer (2), a second step of oxide layer formation to form the second electrically insulating layer (2b) and a second step of layer transfer to transfer the second monocrystalline semiconductor layer (3).

Description

[Technical field]

[0001] The present invention relates to a process for fabricating a dual semiconductor-on-insulator structure. [Background technology]

[0002] A semiconductor-on-insulator structure is a multi-layer structure comprising a handle substrate, generally made of a semiconductor such as silicon, an electrically insulating layer, generally an oxide layer, such as a layer of silicon oxide, disposed on the handle substrate, and a semiconductor layer, generally a silicon layer, disposed on the insulating layer. Such a structure is called a SeOI structure (SeOI stands for semiconductor-on-insulator), or more specifically, when the semiconductor is silicon, a SOI structure (SOI stands for silicon-on-insulator). The oxide layer is thus placed between the substrate and the semiconductor layer. The oxide layer is said to be "buried" and is called "BOX" (BOX stands for buried oxide). In the following, generally, the term "SOI" is adopted to denote a semiconductor-on-insulator structure.

[0003] In addition to the SOI structure with one BOX layer and one semiconductor layer disposed on the BOX layer, a "double SOI" structure has been fabricated. The so-called "double SOI" structure comprises a handle substrate, a first oxide layer or lower buried oxide layer disposed on the handle substrate, a first semiconductor layer or lower semiconductor layer disposed on the first oxide layer, a second oxide layer or upper buried oxide layer disposed on the first semiconductor layer, and a second semiconductor layer or upper semiconductor layer disposed on the second oxide layer. In this double SOI structure, the first oxide layer and the first semiconductor layer form a first SOI disposed on the lower part of the structure, whereas the second oxide layer and the second semiconductor layer form a second SOI disposed on the upper part of the structure.

[0004] One known process for producing SOI structures is a process called SmartCut™. The SmartCut™ process involves the implantation of atomic species such as hydrogen (H) and / or helium (He) to create a weakened region in a donor substrate, bonding the donor substrate to a receiver substrate, then removing the donor substrate level with the weakened region and transferring a thin layer from the donor substrate to the receiver substrate. The donor and receiver substrates are preferably in the form of 300 mm diameter wafers. The donor substrate is a semiconductor substrate whose surface has been pre-oxidized, and H and / or He atoms are implanted through the oxide layer to a given depth in the bulk of the semiconductor. The bonding is between the surface of the receiver substrate and the surface of the oxide layer of the donor substrate.

[0005] One proposed method of obtaining a double SOI structure is to implement two successive Smart-Cut™ processes, using the SOI obtained after the first Smart-Cut™ process as a receiver substrate and the second semiconductor substrate, the surface of which has been pre-oxidized, as a donor substrate in the second Smart-Cut™ process. In the final double SOI structure, the oxide layer and the semiconductor layer of the first SOI obtained after the first Smart-Cut™ process form the lower oxide layer and the lower semiconductor layer, respectively. The oxide layer and the semiconductor layer fabricated from the second donor substrate after the second Smart-Cut™ process form the upper oxide layer and the upper semiconductor layer, respectively, of the obtained double SOI.

[0006] For a given depth of the weakened area of ​​the donor substrate, the thickness of the semiconductor layer intended to be transferred is limited by the thickness of the oxide layer present on the surface of the donor substrate. In particular, the maximum thickness through which hydrogen and / or helium atoms can penetrate into a donor substrate covered by an oxide layer is set by the maximum energy of the implantation device. This thickness depends on the thickness of the oxide passed by the implanted atoms. This thickness generally remains on the order of a few hundred nanometers of silicon. The "Double Smart Cut" process described above therefore does not allow large thicknesses to be obtained for both the semiconductor layer and the oxide layer. However, double SeOI structures with oxide and semiconductor layers of large thickness (for example, on the order of a few hundred nanometers each) are of interest in certain applications, especially in photonics.

[0007] Moreover, the effectiveness of the bond formed in the second Smart-Cut™ process depends on the quality of the surface of the SOI serving as the receiver substrate. Surface treatments, such as, for example, heat treatments, can be performed before the second donor substrate is bonded, in particular to reduce the roughness of the surface of the SOI serving as the receiver substrate. However, once such heat treatments are finished, deformations (or warping) can be observed in the wafers formed by the first SOI and / or by the double SOI. All the wafers are more sensitive to deformations because they have a large diameter, in particular a diameter of 300 mm in the desired application. Industrial equipment for making and processing semiconductor wafers is designed to handle planar wafers. Moreover, using a warped and deformed (or warped) wafer as the receiver substrate when forming the second bond with the second donor substrate can lead to defects being generated during this second bonding operation and therefore to a low-quality bond. Summary of the Invention

[0008] One object of the present invention is to fabricate a double semiconductor-on-insulator type multilayer structure in which the thicknesses of the semiconductor and electrically insulating layers are sufficient for certain applications in photonics.

[0009] Another object of the invention is to limit deformation (or warping) of the wafer after thermal treatments, in particular surface treatments, carried out in the course of the processes used to produce said multi-layer structure of the double semiconductor-on-insulator type.

[0010] To this end, the present invention provides a process for producing a double semiconductor-on-insulator structure, the double semiconductor-on-insulator structure comprising, in succession from the back surface to the front surface of the structure, a handle substrate, a first electrically insulating layer, a first monocrystalline semiconductor layer, a second electrically insulating layer and a second monocrystalline semiconductor layer, the process comprising: a first step of forming an oxide layer on the front and back surfaces of the handle substrate to form a first electrically insulating layer on the front surface of the handle substrate and an oxide layer on the back surface of the handle substrate; a first step of layer transfer for transferring a first monocrystalline semiconductor layer from a first donor substrate to a first electrically insulating layer to form a first semiconductor-on-insulator substrate, the first semiconductor-on-insulator substrate comprising, successively from a back surface to a front surface of the first semiconductor-on-insulator substrate, an oxide layer, a handle substrate, a first electrically insulating layer and a first monocrystalline semiconductor layer; a second step of forming an oxide layer on the front side of the first semiconductor-on-insulator substrate to form a second electrically insulating layer and to thicken the oxide layer; a second step of layer transfer to transfer a second monocrystalline semiconductor layer from the second donor substrate to the second electrically insulating layer to form a dual semiconductor-on-insulator substrate; Including, the oxide layer contributes to maintaining the flatness of the handle substrate during the first and second transfer steps; The present invention provides a process comprising:

[0011] Since the various layers of a double SOI structure have different thermal expansion coefficients, such a structure may undergo deformations. Such deformations occur in particular during cooling of said structure upon completion of various thermal treatments that may be applied to the structure. The formation of an oxide layer on the back side of the double SOI structure according to the invention advantageously allows a structural equilibrium to be achieved, so that the effects of thermal expansion are counteracted in the structure as a whole, thereby significantly limiting the deformations that the structure undergoes.

[0012] According to other features of the invention which are optional and which may be implemented alone or in combination, where this is technically possible: the thickness of the first electrically insulating layer is between 100 nm and 3000 nm; In the resulting final dual semiconductor-on-insulator structure, the thickness of the first single crystal semiconductor layer is between 50 nm and 500 nm; In the resulting final dual semiconductor-on-insulator structure, the thickness of the second electrically insulating layer is between 100 nm and 1100 nm; In the resulting final dual semiconductor-on-insulator structure, the thickness of the second single crystal semiconductor layer is between 50 nm and 500 nm; the step of transferring the first monocrystalline semiconductor layer from the first donor substrate to the first electrically insulating layer is carried out using a process comprising successively implanting an atomic species to create in the first donor substrate a weakened region defining the first monocrystalline semiconductor layer, bonding the implanted side of the first donor substrate of the first monocrystalline semiconductor layer to the first electrically insulating layer, and separating the first donor substrate level having the weakened region; the remainder of the first donor substrate resulting from the separation is used to form a second donor substrate; the process of transferring the first monocrystalline semiconductor layer from the first donor substrate to the first electrically insulating layer further comprises oxidizing a surface of the first donor substrate prior to implanting nuclear species into said first donor substrate, thereby forming a first protective oxide layer such that the nuclear species are implanted through said first protective oxide layer; the first protective oxide layer formed on the surface of the first donor substrate is removed after the nuclear species are implanted and before the first donor substrate is bonded to the first electrically insulating layer; the step of transferring the second monocrystalline semiconductor layer from the second donor substrate to the second electrically insulating layer is carried out using a process comprising successively implanting an atomic species to create in the second donor substrate a weakened region defining the second monocrystalline semiconductor layer, bonding the implanted side of the second donor substrate of the second monocrystalline semiconductor layer to the second electrically insulating layer, and separating the second donor substrate level having the weakened region; the process of transferring the second monocrystalline semiconductor layer from the second donor substrate to the second electrically insulating layer further comprises oxidizing a surface of the second donor substrate prior to implanting the nuclear species into said second donor substrate, thereby forming a second protective oxide layer such that the nuclear species are implanted through said second protective oxide layer; the second protective oxide layer formed on the surface of the second donor substrate is removed after the nuclear species are implanted and before the second donor substrate is bonded to the second electrically insulating layer; The process includes carrying out a process of treatment of a surface of a first single semiconductor-on-insulator substrate before a second step of forming an oxide layer on the surface of the first single semiconductor-on-insulator substrate, the surface treatment process comprising: a first step of rapid thermal annealing; a second step of thermal oxidation followed by deoxidation; a third step of long-term heat treatment or a third step of rapid thermal annealing, where the long-term heat treatment and rapid thermal annealing are carried out at a temperature above 1000° C. in a non-oxidizing atmosphere; The fourth step of chemical mechanical polishing The method further includes the step of performing a process of treating a surface of the first single semiconductor-on-insulator substrate, the process being characterized by: The handle substrate and each donor substrate preferably take the form of a 300 mm diameter wafer. [Brief description of the drawings]

[0013] Other features and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings. [Figure 1] FIG. 4 is a cross-sectional view of a handle substrate. [Diagram 2] FIG. 2 is a cross-sectional view of the handle substrate after a first step of oxidation of the front and back surfaces of the handle substrate. [Diagram 3] FIG. 2A is a cross-sectional view of a first layer transfer from a first donor substrate to the front side of a handle substrate. [Figure 4] FIG. 2 is a cross-sectional view of the intermediate structure obtained after bonding the first donor substrate. [Diagram 5] FIG. 2 is a cross-sectional view of the intermediate semiconductor-on-insulator structure obtained after the first layer transfer. [Figure 6] 6 is a cross-sectional view of an intermediate structure obtained after a second step of oxidation on the front and back sides of the semiconductor-on-insulator substrate of FIG. 5. [Figure 7] 7 is a cross-sectional view of a second layer transfer from a second donor substrate to the front side of the intermediate structure of FIG. 6. FIG. [Figure 8] FIG. 13 is a cross-sectional view of the structure obtained after bonding of a second donor substrate. [Figure 9] 1 shows the final double semiconductor-on-insulator structure obtained after the second layer transfer. For ease of reading, the drawings are not necessarily drawn to scale. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The present invention provides a process for fabricating a dual semiconductor-on-insulator substrate structure comprising, from the backside to the frontside, a handle substrate, a first buried oxide layer corresponding to a first electrically insulating layer, a first monocrystalline semiconductor layer, a second buried oxide layer corresponding to a second electrically insulating layer, and a second monocrystalline semiconductor layer.

[0015] The first electrically insulating layer and the first monocrystalline semiconductor layer together form a first semiconductor-on-insulator structure, called the lower SOI structure. The second electrically insulating layer and the second monocrystalline semiconductor layer together form a second semiconductor-on-insulator structure, called the upper SOI structure. Moreover, the handle substrate advantageously comprises, on its rear side, an oxide layer that makes it possible to limit the deformations generated in the handle during the implementation of the process that is the subject of the present invention.

[0016] The sum of the thicknesses of the layers forming the dual semiconductor-on-insulator substrate structure obtained using the process that is the subject of the present invention is large. In particular, The thickness of the first electrically insulating layer is preferably greater than 100 nm; The thickness of the first monocrystalline semiconductor layer is preferably greater than 50 nm and less than 500 nm. The thickness of the second electrically insulating layer is preferably greater than 100 nm and less than 1100 nm; The thickness of the second single crystal semiconductor layer is preferably greater than 50 nm and less than 500 nm.

[0017] For example, in the context of applications in photonics, such layer thicknesses enable passive photonic components (such as waveguides) or active photonic components (such as resonators) to be fabricated.

[0018] Such thicknesses are not achievable using the conventional Smart-Cut™ process, in which a monocrystalline semiconductor layer is defined via implantation of atomic species in a donor substrate covered with an oxide layer intended to form an electrically insulating layer in an SOI structure. In particular, industrial implantation devices have a maximum energy that prevents hydrogen and / or helium atoms from passing through oxide layers and monocrystalline semiconductor layers of such thickness.

[0019] First Oxidation Step With reference to Figure 1, a handle substrate 1 is first prepared. The handle substrate 1 takes the form of a semiconductor wafer, preferably a wafer of 300 mm diameter and 775 μm thickness. The handle substrate 1 is for example a silicon wafer, preferably a high resistivity silicon wafer with a high content of interstitial oxygen Oi, in other words what is commonly called a HR substrate or high Oi substrate.

[0020] In a first step, shown in FIG. 2, the front and back surfaces of the substrate 1 as well as the edges of said substrate 1 are oxidized.

[0021] During the oxidation of the front side, the handle substrate 1 is partially consumed to form a first electrically insulating oxide layer 1b. By way of example, if the handle substrate is a silicon substrate, the first electrically insulating oxide layer 1b is therefore a silicon oxide layer. The oxidation conditions are controlled to obtain a first electrically insulating oxide layer 1b having a desired thickness.

[0022] Such an oxidation operation can for example be carried out by heating the handle substrate 1 to a temperature between 800° C. and 1100° C. in an oxidizing atmosphere for a period ranging from a few minutes to a few hours in order to obtain a first electrically insulating oxide layer 1b of a large thickness ranging between 100 nm and 3000 nm.

[0023] The simultaneous oxidation of the back side advantageously leads to the formation on the back side of the handle of an oxide layer 1a having substantially the same thickness as the oxide layer 1b formed on the front side. The oxide layer 1a has a lower thermal expansion coefficient than that of the unoxidized handle substrate 1. In the remainder of the process, and in particular once the implemented thermal treatments are finished, the presence of the oxide layer 1a on the back side of the handle substrate 1 allows deformations in said handle substrate 1 to be limited, thus allowing the quality of subsequent bonding of new layers to the front side of the structure to be improved.

[0024] The thickness of the oxide layer 1a obtained under the oxidation conditions described above is identical to that of the first electrically insulating layer 1b. In the course of the subsequent heat treatment and of the cooling period that follows said treatment, such a thickness of the oxide layer 1a makes it possible to counterbalance the effects of thermal expansion experienced by the structure as a whole, and therefore to avoid deformation of said structure.

[0025] First step of layer transfer 3, a first donor substrate of a first monocrystalline semiconductor layer 2 is provided. The first donor substrate is a monocrystalline semiconductor substrate, for example a substrate of monocrystalline silicon. The first donor substrate takes the form of a wafer of the same diameter as the handle substrate 1 and a thickness between 670 μm and 775 μm.

[0026] According to one embodiment, the first layer transfer is carried out using the Smart-Cut™ process. Weakened areas (dotted lines in FIG. 3) are formed in the first donor substrate to define the first semiconductor layer 2. The weakened areas are formed in the donor substrate at a predefined depth that substantially corresponds to the thickness of the semiconductor layer 2 to be transferred. The weakened areas are preferably created by implantation of hydrogen and / or helium atoms in the substrate that will donate the semiconductor layer.

[0027] Since the first electrically insulating layer 1b was formed from the receiver substrate, in other words the handle substrate 1, and not from the first donor substrate, the thickness of the transferred first semiconductor layer 2 is limited only by the maximum energy of the implantation device, which is about 100 keV. Such a maximum implantation energy corresponds to a maximum thickness of the transferred first semiconductor layer 2 of about 600 nm, depending on the implanted species. The invention therefore allows a first semiconductor layer 2 of large thickness to be transferred while having a first electrically insulating layer 1b with an equally large thickness.

[0028] Referring to Figure 4, the first semiconductor layer 2 is then transferred by bonding the side of the first donor substrate that has received the implantation to the first electrically insulating oxide layer 1b and by detaching the remainder of the donor substrate along the weakened area (see Figure 5). The detachment along the weakened area can be induced by mechanical action and / or by the provision of thermal energy. In the first step of the layer transfer, at least one part of the oxide layer on the back side of the handle substrate is maintained to limit problems related to wafer deformation.

[0029] Before the nuclear species are implanted in said first donor substrate, a very small thickness, for example between 20 and 30 nm, of the surface of the first donor substrate can be optionally oxidized. In particular, the implantation of the nuclear species in the first donor substrate is better if the implantation is carried out through said very thin oxide layer, which is in an amorphous phase, rather than directly into a monocrystalline material. Moreover, the very thin oxide layer protects the first semiconductor layer 2 during the atomic implantation. In this case, the very thin oxide layer on the surface of the first donor substrate is removed after the nuclear species are implanted and before the first donor substrate is bonded to the first electrical insulating layer 1b.

[0030] Oxidation of a very small thickness of the surface of the first donor substrate can be achieved by applying a temperature between 800° C. and 1000° C. for a few minutes to a few tens of minutes in an oxidizing atmosphere.

[0031] As an alternative to the Smart-Cut™ process described above, the first layer transfer may be accomplished by thinning the donor substrate from the side of the donor substrate opposite the side bonded to the handle substrate until the desired thickness for the first semiconductor layer is obtained.

[0032] Following the first layer transfer, referring to FIG. 5, a first semiconductor-on-insulator substrate is obtained, comprising a first electrically insulating layer 1b and a first monocrystalline semiconductor layer 2. Said semiconductor-on-insulator substrate has a surface roughness that depends on the process used by the layer transfer. To allow a good bonding quality and to limit the formation of holes during the bonding of the second donor substrate described below, various treatments can be applied to the free surface of the first monocrystalline semiconductor layer 2 to reduce the defect level and roughness of said surface, for example a smoothing heat treatment, a sacrificial oxidation and / or cleaning. This surface treatment allows the quality of the subsequent bonding with the second donor substrate in the second step of the layer transfer to be improved.

[0033] Once the thermal treatment is finished and the structure has returned to thermal equilibrium (e.g. room temperature), the presence of the oxide layer 1a (with a predefined thickness) makes it possible to maintain the structural equilibrium, the planarity of the substrate and thus the quality of the bond with the second donor substrate.

[0034] Second Oxidation Step The front and back surfaces of the first semiconductor-on-insulator substrate are then oxidized as shown in FIG.

[0035] The oxidation at the front side leads to a partial consumption of the first monocrystalline semiconductor layer 2 and therefore to a reduction in the thickness of said previously transferred monocrystalline semiconductor layer 2 and to the formation of a second electrically insulating layer 2b. By way of example, if the first donor substrate is a silicon substrate, the second electrically insulating oxide layer 2b is therefore a silicon oxide layer.

[0036] The oxidation at the front side leads to an increase in the thickness of the initial oxide layer 1a.

[0037] The second oxidation step can for example be carried out by annealing the semiconductor-on-insulator structure obtained after the first layer transfer at a temperature between 800° C. and 1100° C. in an oxidizing atmosphere for a period ranging from a few minutes to a few hours in order to obtain a second electrically insulating oxide layer 2b with a thickness ranging between 100 nm and 1100 nm.

[0038] The thickness of the first semiconductor layer 2 in the final structure is essentially the thickness of the transferred first semiconductor layer 2 minus the thickness of the semiconductor layer 2 consumed to form the second electrically insulating layer 2b. The maximum thickness of the first semiconductor layer 2 at the moment of transfer is limited only by the implantation process, which is generally less than 2 μm, preferably less than about 600 nm. The thickness of the first semiconductor layer 2 in the final structure may therefore preferably be between 50 nm and 1 μm, even more preferably between 50 nm and 500 nm.

[0039] As an example, if the transferred first semiconductor layer 2 has a thickness of 600 nm, the surface treatment to improve the surface quality of said first semiconductor layer 2 consumes more than about 100 nm of semiconductor. A second oxidation step may then consume 450 nm of semiconductor, leaving a first semiconductor layer 2 with a thickness of 50 nm, and form a second electrically insulating layer 2b with a thickness of about 1000 nm.

[0040] Prior to the second layer transfer, the free surface of the second electrically insulating layer 2b may advantageously be cleaned and / or chemically mechanically polished.

[0041] Second step of layer transfer Moreover, referring to FIG. 7, a second donor substrate of a second monocrystalline semiconductor layer 3 is prepared. Like the first donor substrate, the second donor substrate is a monocrystalline semiconductor substrate, for example a substrate of monocrystalline silicon. The second donor substrate takes the form of a wafer of the same diameter as the handle substrate 1 and the first donor substrate. Optionally, the remainder of the first donor substrate can be recycled to form a second donor substrate. For this purpose, the remainder of the first donor substrate is treated to remove defects related to implantation and detachment and to give it a surface state compatible with a new bonding operation.

[0042] According to one embodiment, the second layer transfer is performed using the Smart-Cut™ process. A weakened area defining the second monocrystalline semiconductor layer 3 is formed in this second donor substrate (see dotted lines in FIG. 7). The weakened area can be formed in the same way as used to define the first monocrystalline semiconductor layer 2 in the first donor substrate. With reference to FIG. 8, the second monocrystalline semiconductor layer 3 is transferred by bonding the side of the second donor substrate that has received the implantation to the second electrically insulating layer 2b. With reference to FIG. 9, the remainder of the second donor substrate is removed by separating it along the weakened area.

[0043] Before the weakened regions are formed in said second donor substrate, a very small thickness, for example between 20 and 30 nm, of the surface of the second donor substrate may be optionally oxidized. The very thin oxide layer on the surface of the second donor substrate is preferably removed after the weakened regions are formed and before the second donor substrate is bonded to the second electrically insulating layer 2b.

[0044] As in the case of the first donor substrate, oxidation of a very small thickness of the surface of the second donor substrate can be achieved by applying a temperature between 800°C and 1000°C for a period of a few minutes to a few tens of minutes in an oxidizing atmosphere.

[0045] Alternatively, the second layer transfer may be achieved by thinning the second donor substrate from the side of the second donor substrate opposite the side bonded to the second electrically insulating layer 2b until the desired thickness for the second semiconductor layer 3 is obtained.

[0046] In the second step of the layer transfer, at least a portion of the oxide layer on the back side of the handle substrate is maintained to limit problems related to wafer deformation.

[0047] After performing a second layer transfer, a second semiconductor-on-insulator structure is obtained comprising a second electrically insulating layer 2b and a second monocrystalline semiconductor layer 3, which structure forms the upper semiconductor-on-insulator structure of the final double semiconductor-on-insulator structure (see FIG. 9).

[0048] Since the second electrically insulating layer 2b is formed from a second receiver substrate, in other words from the first semiconductor-on-insulator substrate which has been oxidized on its front side, and not from a second donor substrate, the thickness of the transferred second semiconductor layer 3 is limited only by the maximum energy of the implantation process. Such a maximum implantation energy corresponds to a thickness of the second semiconductor layer 3 of about 600 nm, depending on the species to be implanted. The invention therefore allows a second semiconductor layer 3 of large thickness to be obtained whilst having a second electrically insulating layer 2b which also has a large thickness.

[0049] Optionally, various treatments can be carried out on the free surface of the second semiconductor layer 3, for example to perfect the thickness of said layer or to improve the quality of said free surface, with a view to a potential subsequent functionalization. In case of thermal treatments, the oxide layer 1a on the back side of the handle substrate 1 advantageously limits the deformation of the double semiconductor-on-insulator structure.

[0050] Optional Surface Treatment Optionally, the free surface of the first semiconductor layer 2 can be treated before the oxidation step leading to the formation of the second electrically insulating layer 2b in order to reduce the defect level and roughness of the free surface of the first semiconductor layer 2. Reducing the defect level and roughness of the surface of the first semiconductor layer 2 allows the second electrically insulating layer 2b to be produced, the surface of which also has properties compatible with the formation of a subsequent bond of high quality, in particular a low defect level and low roughness. Alternatively or additionally, the free surface of the second electrically insulating layer 2 can be treated, for example before the second layer transfer, chemical mechanical polishing and / or cleaning are performed. These surface treatments improve the bonding of the second monocrystalline semiconductor layer 3, in particular by limiting the formation of holes and other defects.

[0051] The treatment of the free surface of the first semiconductor layer 2 prior to the second oxidation step and / or of the second electrically insulating layer 2b prior to the second step of layer transfer may itself involve carrying out a multi-step process. One example of a process preferably used for treating the free surface of the first monocrystalline semiconductor layer 2 (prior to the formation of the oxide layer 2b) comprises the following successive steps: (E1) rapid thermal annealing; (E2) Oxidation / deoxygenation sequence; (E3) Long-term thermal annealing (also known as batch annealing) and (E4) Chemical Mechanical Polishing Includes.

[0052] Alternatively, the long term thermal annealing step (E3) is replaced by a rapid thermal annealing step (E3').Further alternatively, steps (E1), (E2) and (E3 / E3') of the process can be performed on the free surface of the first monocrystalline semiconductor layer 2 and step (E4) can be performed before and after a second oxidation step (to form an oxide layer 2b) on the surface of the first monocrystalline semiconductor layer 2 and on the surface of the second electrically insulating layer 2b, respectively.

[0053] What is meant by "rapid thermal annealing" is annealing in a controlled atmosphere for a period of a few seconds or tens of seconds. Such annealing is generally designated by the acronym RTA. Rapid thermal annealing (E1) is carried out at temperatures between 1100°C and 1250°C for a period of a few seconds up to about 100 seconds. Rapid thermal annealing (E1) is carried out in an atmosphere containing a mixture of hydrogen and / or argon.

[0054] The oxidation / deoxidation step (E2) comprises the following operations: Thermal oxidation operation (E2a) and Deoxygenation operation (E2b) and It should be understood that the sequence includes the sequence

[0055] The oxidation operation (E2a) may for example be carried out by heating the structure in an oxidizing atmosphere at a temperature between 800° C. and 1100° C. for a period ranging from a few minutes to a few hours. The deoxidation operation (E2b) may for example be carried out by exposing the front surface of the structure to a HF solution (HF stands for hydrofluoric acid) for a period ranging from a few seconds to a few minutes in order to remove the oxide layer formed on the front surface, without removing the oxide layer present on the rear surface of the structure. This oxidation / deoxidation step allows the thickness of the semiconductor layer to be adjusted through the consumption of the surface portion of silicon by oxidation.

[0056] The long-term thermal annealing or batch annealing advantageously corresponds to a thermal annealing in a furnace under a controlled atmosphere for a time period of about a few minutes to a few hours (generally more than 15 minutes). The furnace annealing (E3) is carried out at a temperature lying between 1050° C. and 1250° C. Moreover, the furnace annealing (E3) is carried out for example under an inert atmosphere, for example under argon.

[0057] In the process of chemical mechanical polishing or CMP, the surface to be polished is modified using a chemical agent, for example a suspension of colloidal silica particles in a mother liquor, and the modified surface is removed through mechanical abrasion. The rotation speed and pressure used in the CMP step (E4) are optimized to remove material from the surface of the first semiconductor layer 2 or the second electrically insulating layer 2b uniformly, but without degrading the finish of said surface, in particular without increasing the roughness of said surface.

[0058] Alternatively, a rapid thermal annealing (E3') is carried out at a temperature between 1100° C. and 1250° C. for a few seconds up to about 100 seconds in an atmosphere containing, for example, a mixture of hydrogen and / or argon.

[0059] Optionally, the free surface of the second semiconducting layer 3 may be further treated or functionalized depending on the targeted application.

[0060] During these various surface treatment steps, especially during the thermal treatment steps, the oxide layer 1a very advantageously limits wafer deformation.

Claims

1. A process for making a double semiconductor-on-insulator structure, said double semiconductor-on-insulator structure comprising, in succession from the back side to the front side of said structure, a handle substrate (1), a first electrically insulating layer (1 b), a first monocrystalline semiconductor layer (2), a second electrically insulating layer (2 b) and a second monocrystalline semiconductor layer (3), said process comprising: a first step of formation of an oxide layer on the front and back surfaces of the handle substrate (1) to form the first electrically insulating layer (1b) on the front surface of the handle substrate and an oxide layer (1a) on the back surface of the handle substrate; a first step of layer transfer for transferring the first monocrystalline semiconductor layer (2) from a first donor substrate to the first electrically insulating layer (1b) to form a first semiconductor-on-insulator substrate, the first semiconductor-on-insulator substrate comprising, successively from the back side to the front side of the first semiconductor-on-insulator substrate, the oxide layer (1a), the handle substrate (1), the first electrically insulating layer (1b) and the first monocrystalline semiconductor layer (2); a second step of oxide layer formation on the front side of the first semiconductor-on-insulator substrate to form the second electrically insulating layer (2b) and to thicken the oxide layer (1a); a second step of layer transfer for transferring said second monocrystalline semiconductor layer (3) from a second donor substrate to said second electrically insulating layer (2b) to form a double semiconductor-on-insulator substrate; Including, the oxide layer (1a) contributes to maintaining the flatness of the handle substrate during the first and second transfer steps; A process characterized in that

2. 2. The process of claim 1, wherein the thickness of the first electrically insulating layer (1b) is between 100 and 3000 nm.

3. 3. The process according to claim 1 or 2, wherein in the final obtained double semiconductor-on-insulator structure, the thickness of the first monocrystalline semiconductor layer (2) is between 50 nm and 500 nm.

4. The process according to any one of claims 1 to 3, wherein in the final obtained double semiconductor-on-insulator structure the thickness of the second electrically insulating layer (2b) is between 100 nm and 1100 nm.

5. The process according to any one of claims 1 to 4, wherein in the final obtained double semiconductor-on-insulator structure, the thickness of the second monocrystalline semiconductor layer (3) is between 50 nm and 500 nm.

6. 6. The process according to any one of claims 1 to 5, wherein the step of transferring the first monocrystalline semiconductor layer (2) from a first donor substrate to the first electrically insulating layer (1b) is carried out using a process comprising successively: implantation of atomic nuclear species to create a weakened region in the first donor substrate that defines the first monocrystalline semiconductor layer (2), bonding the side of the first donor substrate of the first monocrystalline semiconductor layer (2) that has been implanted to the first electrically insulating layer (1b), and separating the level of the first donor substrate that has the weakened region.

7. The process of claim 6 , wherein a remnant of the first donor substrate resulting from separation is used to form the second donor substrate.

8. 8. The process of claim 6 or 7, wherein the process of transfer of the first monocrystalline semiconductor layer (2) from a first donor substrate to the first electrically insulating layer (1 b) further comprises an oxidation of a surface of the first donor substrate prior to the implantation of atomic species into the first donor substrate, thereby forming a first protective oxide layer such that the atomic species are implanted through the first protective oxide layer.

9. 9. The process of claim 8, wherein the first protective oxide layer formed on the surface of the first donor substrate is removed after the nuclear species are implanted and before the first donor substrate is bonded to the first electrically insulating layer (1b).

10. 10. The process according to any one of claims 1 to 9, wherein the step of transferring the second monocrystalline semiconductor layer (3) from a second donor substrate to the second electrically insulating layer (2b) is carried out using a process comprising in succession the implantation of atomic nuclear species to create in the second donor substrate a weakened region defining the second monocrystalline semiconductor layer (3), bonding the second donor substrate side of the second monocrystalline semiconductor layer (3) that has been implanted to the second electrically insulating layer (2b) and separating the second donor substrate level having the weakened region.

11. 11. The process of claim 10, wherein the process of transferring the second monocrystalline semiconductor layer (3) from a second donor substrate to the second electrically insulating layer (2b) further comprises an oxidation of a surface of the second donor substrate prior to the implantation of atomic species into the second donor substrate, thereby forming a second protective oxide layer such that the atomic species are implanted through the second protective oxide layer.

12. 12. The process of claim 11, wherein the second protective oxide layer formed on the surface of the second donor substrate is removed after the nuclear species are implanted and before the second donor substrate is bonded to the second electrically insulating layer (2b).

13. carrying out a process of treatment of the surface of the first single semiconductor-on-insulator substrate before the second step of forming an oxide layer on the surface of the first single semiconductor-on-insulator substrate, the surface treatment process comprising: a first step of rapid thermal annealing; a second step of thermal oxidation followed by deoxidation; a third step of long-term heat treatment or a third step of rapid thermal annealing, the long-term heat treatment and the rapid thermal annealing being carried out at a temperature above 1000° C. in a non-oxidizing atmosphere; A fourth step of chemical mechanical polishing; The process according to any one of claims 1 to 12, further comprising the step of performing a process of treatment of the surface of the first single semiconductor-on-insulator substrate, characterized in that

14. The process of any one of claims 1 to 13, wherein the handle substrate and each donor substrate are in the form of a 300 mm diameter wafer.

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