Device for transmitting ultrasound

Abstract

An apparatus for transmitting ultrasound, the apparatus comprising: a microchip (300) for driving a resonant circuit, the resonant circuit being at least one of an LC tank, an antenna, and a piezoelectric transducer. The microchip (300) is a single unit comprising multiple interconnected embedded components and subsystems including at least an oscillator (315), a pulse width modulation (PWM) signal generator subsystem (329), an analog to digital converter (ADC) subsystem (318), and a digital to analog converter (DAC) subsystem (327).

Description

[Technical field]

[0001] The present invention relates to a device for transmitting ultrasound, and more particularly to a device for transmitting ultrasound comprising a microchip driving a resonant circuit in the form of an LC tank, an antenna or a piezo transducer. [Background technology]

[0002] Therapeutic aerosol delivery is a mainstay of the treatment of asthma, chronic obstructive pulmonary disease (COPD) and cystic fibrosis. Therapeutic aerosols also have applications for the treatment of influenza, osteoporosis and for the delivery of vaccines.

[0003] Pulmonary delivery of therapeutic agents for the treatment of non-respiratory systemic diseases is attractive due to the high pulmonary vascularity, thin blood-alveolar barrier, large surface area, avoidance of gastric enzymes and first-pass hepatic metabolism. It is also attractive due to improved patient comfort and adherence. The pulmonary system can be utilized to deliver antibodies, proteins, analgesics and nucleic acids. Treatment of central nervous system disorders such as tobacco addiction can be significantly enhanced through efficient delivery of nicotine through the lungs to the systemic circulation.

[0004] The effectiveness of a therapeutic aerosol is related to the amount of drug deposited beyond the oropharyngeal region. The area where deposition occurs is a function of the size of the inhaled particles.

[0005] Devices currently used to administer inhaled medications fall into three categories: nebulizers, metered dose inhalers, and dry powder inhalers. Nebulizers are typically divided into two types: jet and ultrasonic, but both types have weaknesses and present problems with conventional devices.

[0006] Jet nebulizers are based on the Bernoulli principle and produce relatively large droplets, which generally deposit in the oropharyngeal region and are therefore not particularly effective. Ultrasonic nebulizers use a piezo crystal that vibrates at frequencies ranging from 1 MHz to 1.7 MHz, transferring vibrational energy to the liquid and converting it into an aerosol. It has been observed that ultrasonic nebulizers are not effective when viscous suspensions or solutions are used and tend to heat the drug, thus breaking down the molecules and eliminating the benefit of inhalation.

[0007] There are other applications that require a resonant circuit to be efficiently driven in an optimal manner at or near the resonant frequency of the resonant circuit. For example, devices that incorporate a resonant circuit in the form of an antenna typically need to drive the antenna with a precise AC drive signal to enable the antenna to function optimally. Additionally, devices that incorporate a resonant circuit in the form of an ultrasonic piezo transducer must generate an AC drive signal to optimally drive the ultrasonic transducer.

[0008] Therefore, there is a need in the art for an apparatus for delivering ultrasound that seeks to address at least some of the problems described herein. Summary of the Invention

[0009] The present invention provides an apparatus as claimed in claim 1, claim 12 or claim 15. The present invention also provides preferred embodiments as claimed in the dependent claims.

[0010] Various examples of the present disclosure described below have several benefits and advantages over conventional devices, which are set forth in the following description.

[0011] Because example devices of the present disclosure allow for more efficient operation than conventional devices, example devices of the present disclosure have environmental benefits due to reduced power requirements. [Brief description of the drawings]

[0012] In order that the present disclosure may be more readily understood, preferred embodiments thereof will now be described, by way of example only, with reference to the accompanying drawings, in which: [Figure 1] FIG. 1 is a schematic diagram of an apparatus of the present disclosure. [Diagram 2] FIG. 1 is a schematic diagram of an integrated circuit of the present disclosure. [Diagram 3] FIG. 1 is a schematic diagram of a pulse width modulation generator of the present disclosure. [Figure 4] FIG. 2 is a timing diagram of an example of the present disclosure. [Diagram 5] FIG. 2 is a timing diagram of an example of the present disclosure. [Figure 6] 1 is a table illustrating port functions of an example of the present disclosure. [Figure 7] FIG. 1 is a schematic diagram of an integrated circuit of the present disclosure. [Figure 8] FIG. 2 is a circuit diagram of an example H-bridge of the present disclosure. [Figure 9] FIG. 2 is a circuit diagram of an example current sensing configuration of the present disclosure. [Figure 10] FIG. 2 is a circuit diagram of an example H-bridge of the present disclosure. [Figure 11] 9 is a graph showing voltages during phases of operation of the H-bridge of FIG. 8; [Figure 12] 9 is a graph showing voltages during phases of operation of the H-bridge of FIG. 8; [Figure 13] 9 is a graph showing the voltage and current at the terminals of an ultrasonic transducer while the ultrasonic transducer is driven by the H-bridge of FIG. 8. [Figure 14] FIG. 2 is a schematic diagram showing connections between integrated circuits of the present disclosure. [Figure 15] FIG. 1 is a schematic diagram of an integrated circuit of the present disclosure. [Figure 16] FIG. 2 illustrates steps of an example authentication method of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, various features have not been drawn to scale. In fact, dimensions of various features may be arbitrarily increased or decreased for clarity of illustration.

[0014] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. To simplify the disclosure, specific examples of ingredients, concentrations, applications, and configurations are described below. Of course, these are merely examples and are not intended to be limiting. For example, the attachment of a first feature and a second feature in the following description may include embodiments in which the first feature and the second feature are attached in direct contact, and may also include embodiments in which an additional feature may be disposed between the first feature and the second feature such that the first feature and the second feature do not have to be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for purposes of brevity and clarity, and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0015] The following disclosure describes representative examples, each of which may be considered an embodiment, and any reference to "examples" may be changed to "embodiments" in this disclosure.

[0016] Referring now to Figure 1 of the accompanying drawings, the driver device 202 comprises a microchip, herein referred to as a power management integrated circuit or PMIC 300. The PMIC 300 is a microchip for driving a resonant circuit. The resonant circuit is an LC tank, an antenna or a piezo transducer. In this example, the resonant circuit is an ultrasonic transducer 215 provided in the resonant circuit device 201. In this example, the resonant circuit device 201 is a separate device that is releasably coupled to the driver device 202. In other examples, the elements of the resonant circuit device 201 are combined in the same device as the driver device 202.

[0017] In this disclosure, the terms chip, microchip, and integrated circuit are interchangeable. A microchip or integrated circuit is a single unit that comprises multiple interconnected embedded components and subsystems. A microchip is at least partially a semiconductor, e.g., silicon, and is fabricated using semiconductor fabrication techniques.

[0018] The present disclosure describes an exemplary resonant circuit device 201 that is a mist inhaler device that includes an ultrasonic transducer 215. When the ultrasonic transducer 215 is activated by a driver device 202, the ultrasonic transducer 215 atomizes a liquid to produce a mist for inhalation by a user.

[0019] However, it should be understood that the elements of the driver device are used differently in other applications involving a resonant circuit, in which the ultrasonic transducer 215 is replaced with another resonant circuit, such as an LC tank or an antenna.

[0020] In one example, the resonant circuit device 201 comprises a resonant circuit in the form of a piezo ultrasonic transducer that generates ultrasonic waves used for wireless power transmission. In this example, the ultrasonic transducer is driven by the driver device 202 to generate ultrasonic waves that can be focused and sent to a receiver transducer. The receiver transducer converts the ultrasonic waves back to electrical energy and stores the energy in an energy storage device such as a battery or uses the electrical energy to power a device. In this way, the device can be charged or powered remotely via power transmitted wirelessly via ultrasound without the device needing to be plugged into an electrical outlet.

[0021] As described below, the driver device 202 is configured to modulate the frequency and duty cycle of an AC power signal that drives an ultrasonic transducer with high precision and efficiency. In the case of a power transfer system, this allows the driver device 202 to encode information for wireless transmission by modulating ultrasonic waves that carry the encoded information. In one example, the driver device 202 is configured for use in a wireless power transfer system, such as, but not limited to, the type described in U.S. Patent No. 9,001,622, entitled "Receiver Communications for Wireless Power Transfer," which is incorporated herein in its entirety.

[0022] In another example, the driver device 202 drives a resonant circuit in the form of an ultrasound transducer to deliver ultrasound waves at precise frequencies and high intensities to treat tumors. The high intensity focused ultrasound waves from the ultrasound transducer are used as a non-invasive targeted therapy to raise the temperature within the tumor to above 65° C. and kill the cells in the tumor without damaging the surrounding tissue.

[0023] In a further application, the driver device 202 is used to drive a resonant circuit in the form of an antenna to precisely control the frequency and power of the waves transmitted by the antenna. In this example, the antenna may be used for any purpose. In one example, the driver device 202 drives an antenna to transmit waves at a precise frequency for the purpose of searching for materials such as minerals or gold in the earth.

[0024] The driver device 202 comprises a second microchip, referred to herein as a bridge integrated circuit or bridge IC 301, electrically connected to the PMIC 300. The bridge IC 301 is a microchip for driving a resonant circuit such as an LC tank, an antenna or a piezo transducer. The bridge IC 301 is a single unit comprising multiple interconnected embedded components and subsystems.

[0025] In this example, the PMIC 300 and the bridge IC 301 are mounted on the same PCB of the driver device 202. In this example, the physical dimensions of the PMIC 300 are 1-3 mm wide and 1-3 mm long, and the physical dimensions of the bridge IC 301 are 1-3 mm wide and 1-3 mm long.

[0026] In this example, the resonant circuit device 201 includes an optional programmable or one-time programmable integrated circuit or OTP IC 242. When the resonant circuit device 201 is coupled to the driver device 202, the OTP IC is electrically connected to the PMIC 300 to receive power from the PMIC 300 such that the PMIC 300 can manage the voltage supplied to the OTP IC 242. The OTP IC 242 is also connected to a communication bus 302 within the driver device 202. In this example, the communication bus 302 is an I2C bus, but in other examples, the communication bus 302 is another type of digital serial communication bus.

[0027] The OTP IC 242 provides security features as described below, however, it should be understood that the OTP IC 242 may be omitted in examples of the present disclosure that do not require such security features.

[0028] The ultrasonic transducer 215 in the resonant circuit device 201 is electrically connected to the bridge IC 301 such that the ultrasonic transducer 215 can be driven by an AC drive signal generated by the bridge IC 301 when the device 200 is in use.

[0029] The driver device 202 comprises a processor in the form of a microcontroller 303 electrically coupled for communication with a communication bus 302. In this example, the microcontroller 303 is a Bluetooth® Low Energy (BLE) microcontroller, but in other examples, the microcontroller 303 is a general-purpose processor. The microcontroller 303 receives power from a low dropout regulator (LDO) 304 that is powered by the battery 250. The LDO 304 provides a stable regulated voltage to the microcontroller 303 to enable the microcontroller 303 to operate consistently with variations in the voltage of the battery 250.

[0030] The driver device 202 includes a voltage regulator in the form of a DC-DC boost converter 305 powered by the battery 250. The boost converter 305 boosts the voltage of the battery 250 to a programmable voltage VBOOST. The programmable voltage VBOOST is set by the boost converter 305 in response to a voltage control signal VCTL from the PMIC 300. As will be described in more detail below, the boost converter 305 outputs a voltage VBOOST to the bridge IC 301. In another example, the voltage regulator is a buck converter or another type of voltage regulator that outputs a selectable voltage.

[0031] The voltage control signal VCTL is generated by a digital-to-analog converter (DAC) implemented in this example within PMIC 300. Because the DAC is integrated within PMIC 300, the DAC is not visible in FIG. 1. The DAC and the technical benefits of integrating the DAC within PMIC 300 are described in more detail below.

[0032] In this example, the PMIC 300 is connected to a power connector in the form of a Universal Serial Bus (USB) connector 306 such that the PMIC 300 can receive a charging voltage VCHRG when the USB connector 306 is coupled to a USB charger.

[0033] In this example, the driver device 202 includes a first pressure sensor 307, which in this example is a static pressure sensor. The driver device 202 also includes a second pressure sensor 308, which in this example is a dynamic pressure sensor. However, in other examples, the driver device 202 includes only one of the two pressure sensors 307, 308, or the pressure sensors 307, 308 are omitted entirely. In this example of a mist generator device, the pressure sensors 307, 308 sense changes in pressure in an aerosol chamber (not shown) to sense when a user is drawing mist from the aerosol chamber.

[0034] In this example, the driver device 202 includes a number of LEDs 308 that are controlled by the PMIC 300. In other examples, the LEDs 308 are omitted.

[0035] The microcontroller 303 acts as a master device on the communication bus 302, the PMIC 300 is the first slave device, the OTP IC 242 is the second slave device, the second pressure sensor 308 is the third slave device, and the first pressure sensor 307 is the fourth slave device. The communication bus 302 allows the microcontroller 303 to control the following functions in the driver device 202: 1. All functions of the PMIC are highly configurable by the microcontroller 303. 2. The current flowing through the resonant circuit (ultrasonic transducer 215) is sensed by a high bandwidth sensing and rectification circuit at a high common mode voltage (high side of the bridge). The sensed current is converted to a voltage proportional to the rms current and provided as a buffered voltage at the current sense output pin 309 of the bridge IC 301. This voltage is provided to the PMIC 300 to be sampled and made available as a digital representation via an I2C request. Sensing the current flowing through the ultrasonic transducer 215 forms part of the resonant frequency tracking function. As described herein, the device's ability to enable this function within the bridge IC 301 provides a significant technical advantage. 3. A DAC (not shown in FIG. 1) integrated within the PMIC 300 allows the DC-DC boost converter voltage VBOOST to be programmed to be between 10V and 20V. 4. Microcontroller 303 enables the charger subsystem of device 202 to manage the charging of the battery, which in this example is a single cell battery. 5. A light emitting diode (LED) driver module (not shown) is powered by the PMIC 300 to digitally drive and dim the LEDs 308 in either linear or gamma corrected modes. 6. The microcontroller 303 can read the Pressure #1 and Pressure #2 sensor values ​​from the pressure sensors 307, 308.

[0036] 2 of the accompanying drawings, PMIC 300, in this example, is a self-contained chip or integrated circuit that includes an integrated subsystem and a number of pins that provide electrical inputs and outputs to PMIC 300. References to integrated circuits or chips in this disclosure are interchangeable and either term encompasses semiconductor devices, which may be made of silicon, for example.

[0037] The PMIC 300 comprises an analog core 310 that comprises analog components including a reference block (BG) 311 , an LDO 312 , a current sensor 313 , a temperature sensor 314 , and an oscillator 315 .

[0038] As described in more detail below, oscillator 315 is coupled to a delay locked loop (DLL) that outputs pulse width modulation (PWM) phases A and B. Oscillator 315 and the DLL generate a two-phase center-matched PWM output that drives an H-bridge in bridge IC 301.

[0039] The DLL comprises multiple delay lines connected end-to-end, with the total delay of the delay lines equal to the period of the main clock signal clk_m. In this example, the DLL is implemented in a digital processor subsystem, referred to herein as digital core 316, of PMIC 300, which receives a clock signal from oscillator 315 and a regulated power supply voltage from LDO 312. The DLL is implemented in a large number (e.g., on the order of millions) of delay gates connected end-to-end in digital core 316.

[0040] The implementation of the oscillator 315 and DLL in the same integrated circuit of the PMIC 300 to generate a two-phase center-aligned PWM signal is unique since there are currently no signal generator components on the integrated circuit market that include this implementation.

[0041] As described herein, PWM is part of the functionality that allows the driver device 202 to precisely track the resonant frequency of the ultrasonic transducer 215 to maintain efficient transfer of electrical to kinetic energy to optimize mist production. The same functionality enables other examples with different resonant circuits by efficiently driving the resonant circuits at high power and high frequency.

[0042] In this example, the PMIC 300 includes a charger circuit 317 that controls the charging of the battery 250, for example with power from a USB power source. The charger circuit 317 is omitted in other examples where a battery is not required.

[0043] The PMIC 300 includes an integrated power switch VSYS that configures the PMIC 300 to power the analog core 310 with power from the battery 250, or from an external power source if the battery 250 is being charged.

[0044] The PMIC 300 includes an embedded analog-to-digital converter (ADC) subsystem 318. Implementing the ADC 318 together with the oscillator 315 in the same integrated circuit is unique in itself, since there are no other integrated circuits in the integrated circuit market with an oscillator and an ADC implemented as sub-blocks in an integrated circuit. In conventional devices, the ADC is typically provided as a separate component separate from the oscillator, and the separate ADC and oscillator are mounted on the same PCB. A problem with this conventional configuration is that the two separate components, the ADC and the oscillator, unnecessarily occupy space on the PCB. A further problem is that conventional ADCs and oscillators are typically connected together by a serial data communication bus, such as an I2C bus, which has a limited communication speed of only up to 400 kHz. In contrast to conventional devices, the PMIC 300 has the ADC 318 and the oscillator 315 integrated within the same integrated circuit which eliminates any delay in communication between the ADC 318 and the oscillator 315, meaning that the ADC 318 and the oscillator 315 can communicate with each other at high speeds, such as the speed of the oscillator 315 (e.g., 3 MHz to 5 MHz).

[0045] In this example PMIC 300, oscillator 315 is running at 5 MHz and generates a 5 MHz clock signal SYS CLOCK. However, in other examples, oscillator 315 generates a clock signal at a much higher frequency, up to 105 MHz. All of the integrated circuits described herein are configured to operate at the high frequency of oscillator 315.

[0046] The ADC 318 includes multiple feedback input terminals or analog inputs 319 that include multiple GPIO inputs (IF_GPIO1-3). At least one of the feedback input terminals or analog inputs 319 receives a feedback signal from an H-bridge circuit in the bridge IC 301, the feedback signal being indicative of a parameter of the operation of the H-bridge circuit or AC drive signal when the H-bridge circuit is driving a resonant circuit, such as the ultrasonic transducer 215, with the AC drive signal. As described below, the GPIO inputs are used to receive a current sense signal from the bridge IC 301 that is indicative of the root-mean-square (rms) current reported by the bridge IC 301. In this example, one of the GPIO inputs is a feedback input terminal that receives a feedback signal from the H-bridge in the bridge IC 301.

[0047] The ADC subsystem 318 samples analog signals received at a number of ADC input terminals 319 at a sampling frequency proportional to the frequency of the main clock signal. The ADC subsystem 318 then uses the sampled analog signals to generate ADC digital signals.

[0048] In this example, the ADC 318 built into the PMIC 300 samples not only the RMS current flowing through the H-bridge 334 and the ultrasonic transducer 215, but also the voltages available in the system (e.g., VBAT, VCHRG, VBOOST), the temperature of the PMIC 300, the temperature of the battery 250, and GPIO inputs (IF_GPIO 1-3) to allow for future expansion.

[0049] The digital core 316 receives the ADC generated digital signal from the ADC subsystem and processes the ADC digital signal to generate the driver control signal. The digital core 316 communicates the driver control signal to the PWM signal generator subsystem (DLL 332) to control the PWM signal generator subsystem.

[0050] Rectification circuits present on the market today have very limited bandwidth (typically less than 1 MHz). Since the oscillator 315 of the PMIC 300 operates at up to 5 MHz or even up to 105 MHz, a high bandwidth rectification circuit is implemented in the PMIC 300. As described below, sensing the RMS current in the H-bridge of the bridge IC 301 forms part of a feedback loop that allows the driver device 202 to drive the ultrasonic transducer 215 with high accuracy. The feedback loop is a game changer in the industry of driving ultrasonic transducers, as it responds to any process variations in piezo transducer manufacturing (variations in resonant frequency) and compensates for temperature effects on the resonant frequency. This is achieved, in part, by the implementation of the present invention, which integrates the ADC 318, the oscillator 315, and the DLL in the same integrated circuit of the PMIC 300. The integration allows these subsystems to communicate with each other at high speeds (e.g., at clock frequencies up to 5 MHz or 105 MHz). Reducing the latency between these subsystems is a game changer in the ultrasonic industry, especially in the field of mist generator devices.

[0051] The ADC 318 includes a battery voltage monitoring input VBAT and a charger input voltage monitoring input VCHG, as well as voltage monitoring inputs VMON and VRTH, and a temperature monitoring input TEMP.

[0052] The temperature monitoring input TEMP receives a temperature signal from a temperature sensor 314 embedded in the PMIC 300. This allows the PMIC 300 to accurately sense the actual temperature within the PMIC 300, so that the PMIC 300 can detect any malfunction within the PMIC 300, as well as malfunctions to other components on the printed circuit board that affect the temperature of the PMIC 300. The PMIC 300 can then control the bridge IC 301 to prevent excitation of the ultrasonic transducer 215 in the event of a malfunction, in order to maintain the safety of the resonant circuit device 201.

[0053] An additional temperature sensor input VRTH receives a temperature sensing signal from an external temperature sensor within the driver device 202 that monitors the temperature of the battery. Thus, the PMIC 300 can react to stop the battery from charging or otherwise shut down the driver device 202 in the event of a high battery temperature to reduce the risk of damage caused by an excessively high battery temperature.

[0054] The PMIC 300, in this example, includes an LED driver 320 that receives digital drive signals from the digital core 316 and provides LED drive output signals to six LEDs 321-326 that are configured to be coupled to output pins of the PMIC 300. The LED driver 320 can thus drive and dim the LEDs 321-326 on up to six independent channels.

[0055] The PMIC 300 includes a first digital-to-analog converter (DAC) 327 that converts digital signals within the PMIC 300 to an analog voltage control signal that is output from the PMIC 300 via output pin VDAC0. The first DAC 327 converts the digital control signal generated by the digital core 316 to an analog voltage control signal that is output via output pin VDAC0 to control a voltage regulator circuit, such as the boost converter 305. The voltage control signal thus controls the voltage regulator circuit to generate a predetermined voltage for modulation by an H-bridge circuit to drive a resonant circuit, such as the ultrasonic transducer 215, in response to a feedback signal indicative of operation of the resonant circuit (ultrasonic transducer 215).

[0056] In this example, the PMIC 300 includes a second DAC 328 that converts digital signals within the PMIC 300 to analog signals that are output from the PMIC 300 via a second analog output pin VDAC1.

[0057] Embedding the DAC 327 or DACs 327, 328 on the same microchip as other subsystems of the PMIC 300 allows the DACs 327, 328 to communicate with the digital core 316 and other components in the PMIC 300 at high speed with no or minimal communication delays. The DACs 327, 328 provide analog outputs that control an outer feedback loop. For example, the first DAC 327 provides a control signal VCTL to the boost converter 305 to control the operation of the boost converter 305. In another example, the DACs 327, 328 are configured to provide a drive signal to a DC-DC buck converter instead of or in addition to the boost converter 305. Integrating two independent DAC channels into the PMIC 300 allows the PMIC 300 to operate the feedback loop of any regulator used in the driver device 202, allowing the driver device 202 to adjust the ultrasonic processing power of the ultrasonic transducer 215 or set analog thresholds for the absolute maximum current and temperature settings of the ultrasonic transducer 215.

[0058] The PMIC 300 includes a serial communications interface, which in this example is an I2C interface that incorporates an external I2C address that is set via pins.

[0059] The PMIC 300 also includes various functional blocks, including a functional block digital machine (FSM) for implementing the functionality of the microchip, which are described in more detail below.

[0060] 3 of the accompanying drawings, a pulse width modulation (PWM) signal generator subsystem 329 is embedded within the PMIC 300. The PWM generator system 329 comprises an oscillator 315, a frequency divider 330, a multiplexer 331, and a delay locked loop (DLL) 332. As described below, the PWM generator system 329 is a two-phase center-matched PWM generator.

[0061] Divider 330 , multiplexer 331 , and DLL 332 are implemented in digital logic components (eg, transistors, logic gates, etc.) within digital core 316 .

[0062] In the examples of the present disclosure, the frequency ranges covered by the oscillator 315 and the PWM generator system 329, respectively, are 50 kHz to 5 MHz or up to 105 MHz. The frequency accuracy of the PWM generator system 329 is ±1% and the spread over temperature is ±1%. In today's IC market, there is no IC with an embedded oscillator and a two-phase center-matched PWM generator that can provide a frequency range from 50 kHz to 5 MHz or 105 MHz.

[0063] Oscillator 315 generates a main clock signal (clk_m) having a frequency from 50 kHz to 5 MHz or up to 105 MHz. The main clock clk_m is input to divider 330, which divides the frequency of main clock clk_m by one or more predetermined divisor amounts. In this example, divider 330 divides the frequency of main clock clk_m by 2, 4, 8, and 16 and provides the divided frequency clocks as outputs to multiplexer 331. Multiplexer 331 multiplexes the divided frequency clocks and provides a divided frequency output to DLL 332. This signal passed to DLL 332 is a frequency reference signal that controls DLL 332 to output a signal at a desired frequency. In other examples, divider 330 and multiplexer 331 are omitted.

[0064] The oscillator 315 also generates two phases, a first phase clock signal Phase1 and a second phase clock signal Phase2. The phases of the first phase clock signal and the second phase clock signal are center-aligned. As shown in FIG. A first phase clock signal Phase1 is high for a variable amount of the positive half-cycle of clk_m and low for the negative half-cycle of clk_m. · The second phase clock signal phase 2 is high for a variable amount of the negative half-cycle of clk_m and low for the positive half-cycle of clk_m.

[0065] Phase1 and Phase2 are then sent to DLL 332, which uses the first phase clock signal Phase1 and the second phase clock signal Phase2 to generate a double frequency clock signal. The double frequency clock signal is twice the frequency of the main clock signal clk_m. In this example, an "OR" gate in DLL 332 generates a double frequency clock signal using the first phase clock signal Phase1 and the second phase clock signal Phase2. This double frequency clock or divided frequency coming from divider 330 is selected based on the selected target frequency and then used as a reference for DLL 332.

[0066] In the DLL 332, the signal hereafter called "clock" represents the main clock clk_m multiplied by two, and the signal hereafter called "clock_del" is a replica of the clock delayed by one period of frequency. Clock and clock_del pass through a phase frequency detector. Then, node Vc is charged or discharged by a charge pump based on the phase error polarity. A control voltage is directly supplied to control the delay of every single delay unit in the DLL 332 until the total delay of the DLL 332 is exactly one period.

[0067] The DLL 332 controls the first phase clock signal Phase1 and the second phase clock signal Phase2 to synchronize their rising edges with the rising edges of the double frequency clock signal. The DLL 332 adjusts the frequency and duty cycle of the first phase clock signal Phase1 and the second phase clock signal Phase2 in response to the respective frequency reference signals and duty cycle control signals to generate the first phase output signal Phase A and the second phase output signal Phase B to drive the H-bridge or inverter to generate an AC drive signal for driving the ultrasonic transducer.

[0068] The PMIC 300 includes a first phase output signal terminal PHASE_A that outputs a first phase output signal Phase A to the H-bridge circuit, and a second phase output signal terminal PHASE_B that outputs a second phase output signal Phase B to the H-bridge circuit.

[0069] In this example, DLL 332 adjusts the duty cycles of first phase clock signal Phase1 and second phase clock signal Phase2 in response to the duty cycle control signal by varying the delay of each delay line within DLL 332 in response to the duty cycle control signal.

[0070] The clock is used at twice its frequency to ensure better accuracy. As shown in FIG. 5, for illustration purposes, if the frequency of the main clock clk_m is used (not used in the example of this disclosure), Phase A is synchronized with the rising edge R of the clock and Phase B is synchronized with the falling edge F of the clock. Because the delay line of the DLL 332 controls the rising edge R, for the falling edge F, the PWM generator system 329 must rely on perfect matching of the delay units of the DLL 332, which may be imperfect. However, to eliminate this error, the PWM generator system 329 uses a double frequency clock such that both Phase A and Phase B are synchronized with the rising edge R of the double frequency clock.

[0071] To implement a duty cycle from 20% to 50% with a step size of 2%, the delay line of DLL 332 comprises 25 delay units, with the output of each respective delay unit representing a phase nth. Finally, the phase of the output of the last delay unit corresponds to the input clock. Considering that all the delays are approximately the same, a particular duty cycle can be obtained using the output of a particular delay unit with simple logic in digital core 316.

[0072] It is important to handle the start-up of the DLL 332 because the DLL 332 can be locked not on one delay period, but on two or more periods, potentially putting the DLL 332 in a non-convergence zone. To avoid this issue, a start-up circuit is implemented in the PWM generator system 329 that allows the DLL 332 to start from a known deterministic condition. The start-up circuit also allows the DLL 332 to start with a minimum delay.

[0073] In the example of the present disclosure, the frequency range covered by the PWM generator system 329 is extended, and therefore the delay units in the DLL 332 can provide delays from 4 ns (for a 5 MHz oscillator frequency) to 400 ns (for a 50 kHz oscillator frequency). To accommodate these different delays, capacitors Cb are included in the PWM generator system 329, with the capacitor values ​​selected to provide the required delays.

[0074] Phase A and Phase B are output from DLL 332 and passed to bridge IC 301 via digital IO so that Phase A and Phase B can be used to control the operation of bridge IC 301.

[0075] The battery charging functionality of the driver device 202 will now be described in more detail. The battery charging subsystem comprises a charger circuit 317 embedded in the PMIC 300 and controlled by a digital charge controller hosted in the PMIC 300. The charger circuit 317 is controlled by the microcontroller 303 via the communication bus 302. The battery charging subsystem can charge single cell Lithium Polymer (LiPo) or Lithium Ion (Li-ion) batteries.

[0076] In this example, the battery charging subsystem can charge one or more batteries from a 5V power source (e.g., a USB power source) with a maximum charging current of 1 A. To adapt the charging parameters of the batteries, one or more of the following parameters can be programmed via the communication bus 302 (I2C interface): The charging voltage can be set between 3.9V and 4.3V in 100mV increments. The charging current can be set between 150mA and 1000mA in 50mA increments. The pre-charge current is 1 / 10 of the charge current. Precharge and fast charge timeouts can be set between 5 and 85 minutes at 20 minutes and 340 minutes respectively. Optionally, an external Negative Temperature Coefficient (NTC) thermistor can be used to monitor the battery temperature.

[0077] In some examples, the battery charging subsystem reports one or more of the following events by generating an interrupt to the host microcontroller 303: Battery is detected The battery is charged The battery is fully charged No battery present Charging timeout reached -Charging supply is below the undervoltage limit

[0078] The main advantage of having the charger circuit 317 embedded in the PMIC 300 is that it allows all the enumerated programming options and event instructions to be implemented within the PMIC 300 ensuring safe operation of the battery charging subsystem. Furthermore, significant manufacturing cost and PCB space savings can be achieved compared to conventional resonant circuit devices such as mist inhaler devices with separate components of the charging system mounted separately on the PCB. The charger circuit 317 also allows highly versatile settings of charging current and voltage, different fault timeouts, and multiple event flags for detailed condition analysis.

[0079] We now turn to a more detailed description of the analog-to-digital converter (ADC) 318. The inventors had to overcome significant technical challenges to integrate the ADC 318 with the high-speed oscillator 315 in the PMIC 300. Furthermore, integrating the ADC 318 in the PMIC 300 runs counter to conventional approaches in the art, which rely on using one of the many discrete ADC devices available in the IC market.

[0080] In this example, the ADC 318 samples at least one parameter in the ultrasonic transducer driver chip (PMIC 300) at a sampling rate equal to the frequency of the main clock signal clk_m. In this example, the ADC 318 is a 10-bit analog-to-digital converter that can offload digital sampling from the microprocessor 303 to conserve microprocessor 303 resources. Integrating the ADC 318 into the PMIC 300 also avoids the need to use an I2C bus that would otherwise slow down the sampling capability of the ADC (conventional devices rely on an I2C bus to communicate data between a dedicated discrete ADC and a microcontroller at a limited clock speed, typically up to 400 kHz).

[0081] In the examples of the present disclosure, one or more of the following parameters may be sampled sequentially by the ADC 318: i. The rms current signal received at the ultrasonic transducer driver chip (PMIC 300) from an external inverter circuit driving the ultrasonic transducer. In this example, this parameter is the root-mean-square (rms) current reported by the bridge IC 301. Sensing the rms current is important to implement the feedback loop used to drive the ultrasonic transducer 215. Because the ADC 318 does not rely on this information being conveyed over the I2C bus, the ADC 318 can sense the rms current directly from the bridge IC 301 via a signal with minimal or no delay. This provides significant speed and accuracy benefits over conventional devices that are constrained by the relatively slow speed of the I2C bus. ii. The voltage of the battery connected to the PMIC 300. iii. The voltage of the charger connected to the PMIC 300. A temperature signal, such as a temperature signal indicative of the PMIC 300 chip temperature. As mentioned above, this temperature can be measured very accurately because the temperature sensor 314 is embedded in the same IC as the oscillator 315. For example, if the temperature of the PMIC 300 increases, the current, frequency, and PWM are adjusted by the PMIC 300 to control the transducer oscillation, which in turn controls the temperature. v. Two external pins. vi. An external NTC temperature sensor for monitoring the battery pack temperature.

[0082] In some examples, the ADC 318 sequentially samples one or more of the above sources, for example in a round robin fashion. The ADC 318 samples the sources at a high rate, such as the rate of the oscillator 315, which may be up to 5 MHz or up to 105 MHz.

[0083] In some examples, the device 202 is configured to allow a user or manufacturer of the device to specify how many samples should be taken from each source for averaging. For example, a user may configure the system to take 512 samples from the rms current input, 64 samples from the battery voltage, 64 samples from the charger input voltage, 32 samples from the external pin, and 8 samples from the NTC pin. Additionally, the user may specify whether one of the above sources should be skipped.

[0084] In some examples, for each source, the user can specify two digital thresholds that divide the total range into multiple zones, such as three zones. The user can then set the system to release an interrupt when the sampled value changes from a zone, for example from zone 2 to zone 3.

[0085] Conventional ICs available on the market today are unable to implement the above features of the PMIC 300. Sampling with such flexibility and granularity is paramount when driving resonant circuits or components such as ultrasonic transducers.

[0086] In this example, the PMIC 300 includes 8-bit general purpose digital input / output ports (GPIOs). Each port can be configured as a digital input and a digital output. Some of the ports also have analog input capabilities, as shown in the table in FIG.

[0087] The GPIO7-GPIO5 ports of the PMIC 300 may be used to set the address of a device on the communication (I2C) bus 302. Eight identical devices can then be used on the same I2C bus. This is a unique feature in the IC industry as it allows eight identical devices to be used on the same I2C bus without conflicting addresses. This is implemented by each device reading the state of GPIO7-GPIO5 during the first 100 μs after the PMIC 300 powers up and storing that portion of the address internally to the PMIC 300. After the PMIC 300 is powered up, the GPIOs may be used for any other purpose.

[0088] As mentioned above, the PMIC 300 includes a 6-channel LED driver 320. In this example, the LED driver 320 includes a 5V tolerant N-channel metal oxide semiconductor (NMOS) current source. The LED driver 320 is configured to set the LED current to four discrete levels: 5mA, 10mA, 15mA, and 20mA. The LED driver 320 is configured to dim each LED channel with a 12-bit PWM signal with or without gamma correction. The LED driver 320 is configured to vary the PWM frequency from 300Hz to 1.5kHz. This feature is unique in the field of resonant circuit devices, such as ultrasonic mist inhaler devices, since the function is embedded as a subsystem of the PMIC 300.

[0089] In this example, the PMIC 300 includes two independent 6-bit digital-to-analog converters (DACs) 327, 328 that are integrated into the PMIC 300. The purpose of the DACs 327, 328 is to output an analog voltage to drive the feedback path of an external regulator (e.g., a DC-DC boost converter 305, a buck converter, or an LDO). Additionally, in some examples, the DACs 327, 328 may also be used to dynamically adjust the overcurrent shutdown level of the bridge IC 301, as described below.

[0090] The output voltage of each DAC 327, 328 is programmable between 0V and 1.5V, or between 0V and V_battery (Vbat). In this example, control of the DAC output voltage is via I2C commands. Having two DACs built into the PMIC 300 is unique and allows for dynamic monitoring control of the current. If either of the DACs 327, 328 were an external chip, the speed would be subject to the same speed limitations imposed by the I2C protocol. The active power monitoring architecture of the device 202 operates at optimal efficiency when all these embedded features are within the PMIC. If they are external components, the active power monitoring architecture is overall inefficient.

[0091] 7 of the accompanying drawings, the bridge IC 301 is a microchip with embedded power switching circuitry 333. In this example, the power switching circuitry 333 is an H-bridge 334, as shown in FIGURE 8 and described in detail below. However, it should be understood that other example bridge ICs 301 may incorporate alternative power switching circuits for the H-bridge 334, provided that the power switching circuitry performs an equivalent function for generating an AC drive signal to drive the ultrasonic transducer 215.

[0092] Bridge IC 301 includes a first phase terminal PHASE A that receives a first phase output signal Phase A from the PWM signal generator subsystem of PMIC 300. Bridge IC 301 also includes a second phase terminal PHASE B that receives a second phase output signal Phase B from the PWM signal generator subsystem of PMIC 300.

[0093] Bridge IC 301 includes a current sense circuit 335 that directly senses the current in H-bridge 334 and provides an RMS current output signal via the RMS_CURR pin of bridge IC 301. Current sense circuit 335 is configured for overcurrent monitoring to detect when the current through H-bridge 334 exceeds a predetermined threshold. The integration of power switching circuit 333 with H-bridge 334 and current sense circuit 335 all within the same embedded circuit of bridge IC 301 is a unique combination in the IC market. Currently, no other integrated circuit in the IC market includes an H-bridge with embedded circuitry for sensing the RMS current through the H-bridge.

[0094] Bridge IC 301 includes a temperature sensor 336 that includes over-temperature monitoring. Temperature sensor 336 is configured to shut down or disable at least a portion of bridge IC 301 if temperature sensor 336 detects that bridge IC 301 is operating at a temperature above a predetermined threshold. Thus, temperature sensor 336 provides an integrated safety feature that prevents damage to bridge IC 301 or other components within driver device 202 if bridge IC 301 operates at an excessively high temperature.

[0095] The bridge IC 301 includes a digital state machine 337 integrally connected to the power switching circuit 333. The digital state machine 337 receives the Phase A and Phase B signals from the PMIC 300 and an ENABLE signal, for example, from the microcontroller 303. The digital state machine 337 generates timing signals based on the first phase output signal Phase A and the second phase output signal Phase B.

[0096] The digital state machine 337 outputs timing signals corresponding to the A-phase signal and the B-phase signal, as well as a BRIDGE PR signal and a BRIDGE EN signal to the power switching circuit 333 to control the power switching circuit 333. Thus, the digital state machine 337 outputs timing signals to the switches T1-T4 of the H-bridge circuit 334 to control the switches T1-T4 to turn on and off in sequence so that the H-bridge circuit outputs an AC drive signal for driving a resonant circuit such as the ultrasonic transducer 215.

[0097] As described in more detail below, the switching sequence includes a free-floating period during which the first switch T1 and the second switch T1 are turned off and the third switch T3 and the fourth switch T4 are turned on to dissipate energy stored by the resonant circuit (ultrasonic transducer 215).

[0098] Bridge IC 301 includes a test controller 338 that allows bridge IC 301 to be tested to determine if embedded components within bridge IC 301 are operating correctly. Test controller 338 is coupled to the TEST_DATA, TEST_CLK, and TEST_LOAD pins such that bridge IC 301 can be connected to an external control device that feeds data to and from bridge IC 301 to test the operation of bridge IC 301. Bridge IC 301 also includes a TEST BUS that allows the digital communication bus within bridge IC 301 to be tested via the TST_PAD pin.

[0099] Bridge IC 301 includes a power-on reset circuit (POR) 339 that controls the start-up operation of bridge IC 301. POR 339 ensures that bridge IC 301 starts up properly only if the supply voltage is within a predetermined range. If the power supply voltage is outside the predetermined range, e.g., if the power supply voltage is too high, POR 339 delays the start-up of bridge IC 301 until the power supply voltage is within the predetermined range.

[0100] Bridge IC 301 includes a reference block (BG) 340 that provides a precise reference voltage for use by other subsystems of bridge IC 301 .

[0101] Bridge IC 301 includes a current reference 341 that provides accurate current to other subsystems within bridge IC 301 , such as power switching circuit 333 and / or current sensor 335 .

[0102] Temperature sensor 336 continuously monitors the temperature of the silicon of bridge IC 301. If the temperature exceeds a predetermined temperature threshold, power switching circuit 333 is automatically switched off. Additionally, over-temperature can be reported to an external host to notify the external host that an over-temperature event has occurred.

[0103] A digital state machine (FSM) 337 generates timing signals for the power switching circuit 333 , in this example, timing signals for controlling the H-bridge 334 .

[0104] Bridge IC 301 includes comparators 342, 343 that compare signals from various subsystems of bridge IC 301 with voltage and current references 340, 341 and provide reference output signals via pins of bridge IC 301.

[0105] Referring again to Figure 8 of the accompanying drawings, the H-bridge 334 in this example comprises four switches in the form of NMOS field effect transistor (FET) switches on either side of the H-bridge 334. The H-bridge 334 comprises four switches or transistors T1-T4 connected in an H-bridge configuration, with each transistor T1-T4 driven by a respective logic input A-D. The transistors T1-T4 are configured to be driven by a bootstrap voltage generated internally by two external capacitors Cb connected as shown in Figure 8.

[0106] H-bridge 334 has various power inputs and outputs that are connected to respective pins of bridge IC 301. H-bridge 334 receives the programmable voltage VBOOST output from boost converter 305 via a first power supply terminal, labeled VBOOST in FIG. 8. H-bridge 334 has a second power supply terminal, labeled VSS_P in FIG. 8.

[0107] The H-bridge 334 has outputs OUTP, OUTN configured to connect to respective terminals of the ultrasonic transducer 215 such that the AC drive signal output from the H-bridge 334 can drive the ultrasonic transducer 215.

[0108] The switching of the four switches or transistors T1-T4 is controlled by switching signals from digital state machine 337 via logic inputs A-D. Although Figure 8 shows four transistors T1-T4, it should be understood that in other examples, H-bridge 334 incorporates a greater number of transistors or other switching components to implement the functionality of an H-bridge.

[0109] In this example, the H-bridge 334 operates with a switching power of 22 W to 50 W to provide an AC drive signal with enough power to optimally drive the ultrasonic transducer 215 at or near the resonant frequency of the ultrasonic transducer 215. The voltage switched by the H-bridge 334 in this example is ±15 V. In another example, the voltage is ±20 V.

[0110] In this example, the H-bridge 334 switches at a frequency of 3 MHz to 5 MHz or up to 105 MHz. This is a high switching speed compared to conventional integrated circuit H-bridges available in the IC market. For example, conventional integrated circuit H-bridges available in the IC market today are configured to operate at a maximum frequency of only 2 MHz. Apart from the bridge IC 301 described herein, conventional integrated circuit H-bridges available in the IC market cannot operate at 22V to 50V power at frequencies up to 5 MHz, much less up to 105 MHz.

[0111] Referring now to Figure 9 of the accompanying drawings, the current sensor 335 comprises positive and negative current sensing resistors RshuntP, RshuntN connected in series with the respective high and low sides of the H-bridge 334 as shown in Figure 8. The current sensing resistors RshuntP, RshuntN are low value resistors, in this example 0.1 Ω. The current sensor 335 comprises a first voltage sensor in the form of a first operational amplifier 344 measuring the voltage drop across the first current sensor resistor RshuntP and a second voltage sensor in the form of a second operational amplifier 345 measuring the voltage drop across the second current sensor resistor RshuntN. In this example, the gain of each operational amplifier 344, 345 is 2V / V. The output of each operational amplifier 344, 345 is in this example 1 mA / V. The current sensor 335 comprises a pull-down resistor Rcs, in this example 2 kΩ. The outputs of the operational amplifiers 344, 345 provide an output CSout which is passed through a low pass filter 346 which removes transients in the signal CSout. The output Vout of the low pass filter 346 is the output signal of the current sensor 335.

[0112] Thus, the current sensor 335 measures the AC current flowing through the H-bridge 334 and the ultrasonic transducer 215, respectively. The current sensor 335 converts the AC current into an equivalent RMS output voltage (Vout) relative to ground. The current sensor 335 has high bandwidth capability because the H-bridge 334 can operate at frequencies up to 5 MHz, or in some examples up to 105 MHz. The output Vout of the current sensor 335 reports a positive voltage equal to the measured AC rms current flowing through the ultrasonic transducer 215. The output voltage Vout of the current sensor 335 is, in this example, fed back to a control circuit in the bridge IC 301, enabling the bridge IC 301 to shut down the H-bridge 334 if the current flowing through the H-bridge 334, and therefore through the transducer 215, exceeds a predetermined threshold. Additionally, the overcurrent threshold event is reported to a first comparator 342 within bridge IC 301 so that bridge IC 301 can report the overcurrent event via its OVC_TRIGG pin.

[0113] 10 of the accompanying drawings, control of the H-bridge 334 will now be described with reference to an equivalent piezo model of the ultrasonic transducer 215.

[0114] To generate a positive voltage across the outputs OUTP, OUTN of H-bridge 334, as indicated by V_out in FIG. 10 (note the direction of the arrows), the switching sequence of transistors T1-T4 via inputs A-D is as follows: 1. Positive output voltage across ultrasonic transducer 215: A-ON, B-OFF, C-OFF, D-ON. 2. Transition from positive output voltage to 0: A-OFF, B-OFF, C-OFF, D-ON. During this transition, if there is a switching error or delay in A, C is switched off first to minimize or avoid power loss by minimizing or avoiding current flowing through A and C. 3.0 output voltage: A-OFF, B-OFF, C-ON, D-ON. During this 0 output voltage phase, the output OUTP, OUTN terminals of the H-bridge 334 are grounded by the C and D switches which remain on. This dissipates the energy stored by the capacitors in the equivalent circuit of the ultrasonic transducer and minimizes voltage overshoot in the switching waveform voltage applied to the ultrasonic transducer. 4.0 to negative output voltage transition: A-OFF, B-OFF, C-ON, D-OFF. 5. Negative output voltage across ultrasonic transducer 215: A-OFF, B-ON, C-ON, D-OFF.

[0115] It will be appreciated that at high frequencies up to 5 MHz or even up to 105 MHz, the duration of each part of the switching sequence is very short, on the order of nanoseconds or picoseconds, for example at a switching frequency of 6 MHz, each part of the switching sequence occurs in approximately 80 ns.

[0116] A graph showing the output voltages OUTP, OUTN of the H-bridge 334 according to the above switching sequence is shown in Figure 11 of the accompanying drawings. The zero output voltage portion of the switching sequence is included to accommodate energy stored by the ultrasonic transducer 215 (e.g., energy stored by a capacitor in the equivalent circuit of the ultrasonic transducer). As discussed above, this minimizes voltage overshoot in the switching waveform voltage applied to the ultrasonic transducer, and therefore minimizes unnecessary power dissipation and heating in the ultrasonic transducer.

[0117] Minimizing or eliminating voltage overshoot also reduces the risk of damage to transistors in the bridge IC 301 by preventing the transistors from experiencing voltages above their rated voltage. Furthermore, minimizing or eliminating voltage overshoot allows the bridge IC 301 to accurately drive the ultrasonic transducer in a manner that minimizes disruptions to the current sense feedback loop described herein. As a result, the bridge IC 301 can drive ultrasonic transducers at powers as high as 22W to 50W or 70W at high frequencies up to 5MHz or up to 105MHz.

[0118] The bridge IC 301 in this example is configured to be controlled by the PMIC 300 to operate in two different modes, referred to herein as forced mode and natural frequency mode. These two operating modes are novel with respect to existing bridge ICs. In particular, the natural frequency mode is a major innovation that provides substantial benefits in the accuracy and efficiency of driving ultrasonic transducers compared to conventional devices.

[0119] Forced Frequency Mode (FFM) In the forced frequency mode, the H-bridge 334 is controlled in the sequence described above, but at a user-selectable frequency. As a result, the H-bridge transistors T1-T4 are forcibly controlled to switch the output voltage across the ultrasonic transducer 215, regardless of the natural resonant frequency of the ultrasonic transducer 215. Thus, the forced frequency mode allows the H-bridge 334 to drive an ultrasonic transducer 215 having a resonant frequency f1 at a different frequency f2.

[0120] Driving an ultrasonic transducer at a frequency different from its resonant frequency may be appropriate to adapt the operation to different applications. For example, it may be appropriate to drive an ultrasonic transducer at a frequency slightly off the resonant frequency (for mechanical reasons to prevent mechanical damage to the transducer). Alternatively, it may be appropriate to drive an ultrasonic transducer at a low frequency, but the ultrasonic transducer has a different natural resonant frequency due to its size.

[0121] The driver device 202 controls the bridge IC 301 to drive the ultrasonic transducer 215 in a forced frequency mode in response to a configuration of the driver device 202 for a particular application or a particular ultrasonic transducer. For example, the driver device 202 may be configured to operate in a forced frequency mode when the resonant circuit device 201 is being used for a particular application, such as generating a mist from a liquid of a particular viscosity containing a drug for delivery to a user.

[0122] Natural Frequency Mode (NFM) The following natural frequency operating mode is a significant development, offering benefits in improved accuracy and efficiency over conventional ultrasonic drivers available in the IC market today.

[0123] The natural frequency mode of operation follows the same switching sequence as described above, but the timing of the zero output portion of the sequence is adjusted to minimize or avoid problems that may arise due to current spikes in the forced frequency mode operation. These current spikes occur when the voltage across the ultrasonic transducer 215 is switched to its opposite voltage polarity. An ultrasonic transducer that includes a piezo crystal has an electrical equivalent circuit that incorporates a parallel connected capacitor (see, for example, the piezo model in FIG. 10). When the voltage across the ultrasonic transducer is hard switched from a positive voltage to a negative voltage, a large current may flow as the energy stored in the capacitor dissipates due to the high dV / dt.

[0124] The natural frequency mode avoids hard switching the voltage across the ultrasonic transducer 215 from a positive voltage to a negative voltage (and vice versa). Instead, before applying the reverse voltage, the ultrasonic transducer 215 (piezo crystal) is left free floating with zero voltage applied across its terminals for a free floating period. The PMIC 300 sets the drive frequency of the bridge IC 301 such that the bridge 334 sets the free floating period, and the current flow in the ultrasonic transducer 215 (due to the energy stored in the piezo crystal) reverses the voltage across the terminals of the ultrasonic transducer 215 during the free floating period.

[0125] As a result, when the H-bridge 334 applies a negative voltage to the terminals of the ultrasonic transducer 215, no current spike occurs because the ultrasonic transducer 215 (the capacitor in the equivalent circuit) is already back-charged and there is no high dV / dt.

[0126] However, it should be understood that when the ultrasonic transducer 215 is first activated, it takes time for the charge in the ultrasonic transducer 215 (piezo crystal) to build up. Thus, the ideal situation where the energy in the ultrasonic transducer 215 reverses the voltage during the free floating period occurs only after the oscillations in the ultrasonic transducer 215 have built up the charge. To accommodate this, when the bridge IC 301 first activates the ultrasonic transducer 215, the PMIC 300 controls the power delivered to the ultrasonic transducer 215 through the H-bridge 334 to a first value that is a low value (e.g., 5V). The PMIC 300 then controls the power delivered to the ultrasonic transducer 215 through the H-bridge 334 to increase to a second value (e.g., 15V) that is higher than the first value for a period of time in order to build up the energy stored in the ultrasonic transducer 215. Current spikes still occur during this ramp of oscillation until the current in the ultrasonic transducer 215 is fully developed. However, by using a low first voltage at start-up, these current spikes are kept low enough to minimize their impact on the operation of the ultrasonic transducer 215.

[0127] To implement the natural frequency mode, the driver device 202 precisely controls the frequency of the oscillator 315 and the duty cycle (ratio of on time to free floating time) of the AC drive signal output from the H-bridge 334. In this example, the driver device 202 executes three control loops to adjust the oscillator frequency and duty cycle so that the voltage reversal at the terminals of the ultrasonic transducer 215 is as precise as possible and current spikes are minimized or avoided as much as possible. The precise control of the oscillator and duty cycle using the control loops is a significant advance in the field of IC ultrasonic drivers.

[0128] During the natural frequency operating mode, the current sensor 335 senses the current flowing through the ultrasonic transducer 215 (resonant circuit) during the free-floating period. The digital state machine 337 adapts the timing signals to switch on either the first switch T1 or the second switch T2 when the current sensor 335 senses that the current flowing through the ultrasonic transducer 215 (resonant circuit) during the free-floating period is zero.

[0129] 12 of the accompanying drawings shows an oscillator voltage waveform 347 (V(osc)), a switching waveform 348 resulting from the turning on and off of the left high switch T1 of the H-bridge 334, and a switching waveform 349 resulting from the turning on and off of the right high switch T2 of the H-bridge 334. During the intervening free-floating period 350, both high switches T1, T2 of the H-bridge 334 are turned off (free-floating phase). The duration of the free-floating period 350 is controlled by the magnitude of the free-floating control voltage 351 (Vphioff).

[0130] 13 of the accompanying drawings shows the voltage waveform 352 at a first terminal of the ultrasonic transducer 215 (the voltage waveform is inverted at a second terminal of the ultrasonic transducer 215) and the piezo current 353 flowing through the ultrasonic transducer 215. The piezo current 353 represents a (near) ideal sinusoidal waveform (which is never possible with any bridge in forced frequency mode or on the IC market).

[0131] Before the sinusoidal wave of the piezo current 353 reaches zero, the left high switch T1 of the H-bridge 334 is turned off (here, switch T1 is turned off when the piezo current 353 is about 6 A). The remaining piezo current 353 flowing in the ultrasonic transducer 215 due to the energy stored in the ultrasonic transducer 215 (the capacitor of the piezo equivalent circuit) is responsible for the voltage reversal during the free-floating period 350. The piezo current 353 decays to zero during the free-floating period 350 and then decays into a negative current flow domain. The terminal voltage at the ultrasonic transducer 215 drops from the supply voltage (19V in this case) to less than 2V, and this drop stops when the piezo current 353 reaches zero. This is the perfect time to turn on the low-side switch T3 of the H-bridge 334 to minimize or avoid current spikes.

[0132] Compared to the forced frequency mode described above, the natural frequency mode has at least three advantages. 1. Current spikes associated with hard switching of package capacitors are significantly reduced or avoided entirely. 2. Power losses due to hard switching are almost eliminated. 3. The frequency is regulated by a control loop to keep it close to the resonance of the piezo crystal (i.e., the natural resonant frequency of the piezo crystal).

[0133] For frequency regulation by control loop (advantage 3 above), the PMIC 300 starts by controlling the bridge IC 301 to drive the ultrasonic transducer 215 at a frequency above the resonance of the piezo crystal. The PMIC 300 then controls the bridge IC 301 such that the frequency of the AC drive signal is attenuated / reduced during startup. As soon as the frequency approaches the resonant frequency of the piezo crystal, the piezo current is generated / increased rapidly. When the piezo current is high enough to cause the desired voltage reversal, the frequency attenuation / reduction is stopped by the PMIC 300. The control loop of the PMIC 300 then takes over regulating the frequency and duty cycle of the AC drive signal.

[0134] In forced frequency mode, the power delivered to the ultrasonic transducer 215 is controlled through duty cycle and / or frequency shifting and / or by varying the supply voltage. However, in this example, in natural frequency mode, the power delivered to the ultrasonic transducer 215 is controlled only by the supply voltage.

[0135] In this example, during a setup phase of the driver device's operation, the bridge IC 301 is configured to measure the length of time it takes for the current through the ultrasonic transducer 215 (resonant circuit) to fall to zero when the first switch T1 and the second switch T2 are turned off and the third switch T3 and the fourth switch T4 are turned on. The bridge IC 301 then sets the length of time of the free floating period to be equal to the measured length of time.

[0136] 14 of the accompanying drawings, the PMIC 300 and bridge IC 301 in this example are designed to work together as a companion chipset. The PMIC 300 and bridge IC 301 are electrically connected to each other to communicate with each other. In this example, there are interconnections between the PMIC 300 and bridge IC 301 that allow two categories of communication: 1. Control Signals 2. Feedback Signal

[0137] The connections between the PHASE_A and PHASE_B pins of the PMIC 300 and bridge IC 301 carry the PWM modulated control signals that drive the H-bridge 334. The connection between the EN_BR pin of the PMIC 300 and bridge IC 301 carries the EN_BR control signal that triggers the start of the H-bridge 334. The timing between the PHASE_A, PHASE_B, and EN_BR control signals is critical and is handled by the digital bridge control of the PMIC 300.

[0138] The connections between the CS, OC, and OT pins of the PMIC 300 and the bridge IC 301 carry the CS (current sense), OC (overcurrent), and OT (overtemperature) feedback signals from the bridge IC 301 back to the PMIC 300. Most notably, the CS (current sense) feedback signal comprises a voltage equal to the rms current flowing through the ultrasonic transducer 215, as measured by the current sensor 335 of the bridge IC 301.

[0139] The OC (overcurrent) and OT (overtemperature) feedback signals are digital signals that indicate that either an overcurrent or overvoltage event has been detected by the bridge IC 301. In this example, the overcurrent and overtemperature thresholds are set by external resistors. Alternatively, the thresholds can also be dynamically set in response to a signal passed from one of the two DAC channels VDAC0, VDAC1 from the PMIC 300 to the OC_REF pin of the bridge IC 301.

[0140] In this example, the design of PMIC 300 and bridge IC 301 allows the pins of these two integrated circuits to be directly connected to each other (e.g., via copper tracks on a PCB), thereby ensuring minimal or no delay in the communication of signals between PMIC 300 and bridge IC 301. This provides a significant speed advantage over conventional bridges in the IC market that are typically controlled by signals over a digital communication bus. For example, a standard I2C bus is clocked at only 400 kHz, which is too slow to communicate data sampled at the high clock speeds of up to 5 MHz in the examples of this disclosure.

[0141] Although examples of the present disclosure are described above with respect to microchip hardware, it should be understood that other examples of the present disclosure include methods of operating each microchip's components and subsystems to perform the functions described herein, such as operating PMIC 300 and bridge IC 301 in either forced frequency mode or natural frequency mode.

[0142] 15 of the accompanying drawings, the optional OTP IC 242 comprises a power-on reset circuit (POR) 354, a bandgap reference (BG) 355, a capless low dropout regulator (LDO) 356, a communication (e.g., I2C) interface 357, a one-time programmable memory bank (e-fuse) 358, an oscillator 359, and a general-purpose input / output interface 360. The OTP IC 242 also comprises a digital core 361 that includes a cryptographic authenticator. In this example, the cryptographic authenticator is used within the OTP IC 242 to encrypt / decrypt data stored within the OTP IC as well as data communicated to and from the OTP IC 242 using the Elliptic Curve Digital Signature Algorithm (ECDSA).

[0143] The POR 354 ensures that the OTP IC 242 powers up properly only if the supply voltage is within a predetermined range. If the supply voltage is outside the predetermined range, the POR 354 resets the OTP IC 242 and waits until the supply voltage is within the predetermined range.

[0144] BG 355 provides precision reference voltages and currents to LDO 356 and oscillator 359. LDO 356 supplies digital core 361, communication interface 357, and electronic fuse memory bank 358.

[0145] The OTP IC 242 is configured to operate in at least the following modes: Fuse programming (fusing): During e-fuse programming (programming of one-time programmable memory), high currents are required to blow the associated fuses in the electronic fuse memory bank 358. In this mode, higher bias currents are provided to maintain the gain and bandwidth of the regulation loop. Fuse Read. In this mode, an intermediate level of current is required to maintain the e-fuse read in the e-fuse memory bank 358. This mode is performed during power-up of the OTP IC 242 to transfer the fuse contents to the shadow registers. In this mode, the gain and bandwidth of the regulation loop are set to lower values ​​than in the fusing mode. · Normal operation: In this mode, the LDO 356 is driven at very low bias current conditions to operate the OTP IC 242 at low power so that the OTP IC 242 consumes as little power as possible.

[0146] Oscillator 359 provides the necessary clocks for digital core / engine 361 during testing (SCAN test), fusing, and normal operation. Oscillator 359 is trimmed to handle the strict timing requirements during fusing mode.

[0147] In this example, the communication interface 357 is compliant with the FM+ specification of the I2C standard, but also with low-speed and high-speed modes. The OTP IC 242 uses the communication interface 357 to communicate with the driver device 202 (host) for data and key exchange.

[0148] Digital core 361 implements the control and communication functions of OTP IC 242. A cryptographic authentication unit in digital core 361 allows OTP IC 242 to authenticate itself (e.g., using ECDSA encrypted messages) with driver device 202 (e.g., for a particular application) to ensure that OTP IC 242 is authentic and authorized to connect to driver device 202 (or another product).

[0149] With reference to FIG. 16 of the accompanying drawings, the OTP IC 242 performs the following PKI procedures to authenticate the OTP IC 242 for use with a host (eg, driver device 202). 1. Verify signer public key: The host requests the manufacturing public key and certificate. The host verifies the certificate with the certification public key. 2. Verify Device Public Key: If the verification is successful, the host requests the device public key and certificate. The host verifies the certificate with the manufacturing public key. 3. Challenge-Response: If the verification is successful, the host creates a random challenge and sends it to the device, which then signs the random challenge with the device's private key. 4. The signature is sent back to the host for verification using the device public key.

[0150] If all steps of the authentication procedure are completed successfully, the chain of trust is verified back to the root of trust and the OTP IC 242 is successfully authenticated for use with the host. However, if any step of the authentication procedure fails, the OTP IC 242 is not authenticated for use with the host and use of the device incorporating the OTP IC 242 may be limited or prevented.

[0151] The above outlines features of some examples or embodiments to enable those skilled in the art to better understand various aspects of the present disclosure. It should be appreciated that those skilled in the art can readily use this disclosure as a basis for designing or modifying other processes and structures to carry out the same purposes and / or achieve the same advantages of the various examples or embodiments presented herein. It should also be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

[0152] Although the subject matter has been described in language specific to structural features or methodological acts, it is to be understood that the appended claims subject matter is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing at least some of the claims.

[0153] Various operations of examples or embodiments are provided herein. The order in which some or all of the operations are described should not be construed as implying that these operations are necessarily order dependent. It will be understood that alternative orderings have the benefit of this description. Furthermore, it will be understood that not all operations are necessarily present in each embodiment provided herein. It will also be understood that not all operations are required in some examples or embodiments.

[0154] Furthermore, "exemplary" is used herein to mean serving as an example, instance, illustration, or the like, and not necessarily advantageous. When used in this application, "or" is intended to mean an inclusive "or" rather than an exclusive "or". Furthermore, "a" and "an" as used in this application and the appended claims are generally construed to mean "one or more" unless otherwise specified or unless it is clear from the context that a singular form is intended. Also, at least one of A and B, etc. generally means A or B, or both A and B. Furthermore, to the extent that "includes," "having," "has," "with," or variations thereof are used, such terms are intended to be inclusive in the same manner as the term "comprising." Also, unless otherwise specified, "first," "second," etc. are not intended to imply any temporal or spatial aspect, order, or the like, and such terms are merely used as identifiers, names, or the like for features, elements, items, and the like. For example, a first element and a second element generally correspond to element A and element B, or two different or two identical elements or the same element.

[0155] Also, although the present disclosure has been shown and described with respect to one or more implementations, equivalent changes and modifications will occur to those skilled in the art based on reading and understanding the present specification and the accompanying drawings. The present disclosure includes all such modifications and modifications, and is limited only by the scope of the following claims. In particular, with respect to the various functions performed by the above-mentioned features (e.g., elements, resources, etc.), the terms used to describe such features are intended to correspond to any features that perform the specific function (e.g., functionally equivalent) of the described features, but are not structurally equivalent to the disclosed structures, unless otherwise indicated. In addition, although a particular feature of the present disclosure may be disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of other implementations, as may be desired and advantageous for any given or specific application.

[0156] Examples or embodiments of the subject matter and functional operations described in this specification can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, or in combinations of one or more of them, including the structures disclosed herein and structural equivalents thereof.

[0157] Some examples or embodiments are implemented using one or more modules of computer program instructions encoded on a computer readable medium for execution by or to control the operation of a data processing apparatus. The computer readable medium may be an article of manufacture, such as a hard drive or an embedded system in a computer system. The computer readable medium may be obtained separately and later encoded with one or more modules of computer program instructions, such as by delivery of one or more modules of computer program instructions over a wired or wireless network. The computer readable medium may be a machine readable storage device, a machine readable storage substrate, a memory device, or a combination of one or more of them.

[0158] The terms "computing device" and "data processing apparatus" encompass all apparatus, devices, and machines for processing data, including, by way of example, a programmable processor, computer, or multiple processors or computers. In addition to hardware, an apparatus may include code that creates an execution environment for the computer program in question, such as code that constitutes processor firmware, a protocol stack, a database management system, an operating system, a runtime environment, or a combination of one or more of these. Additionally, an apparatus may employ a variety of different computing model infrastructures, such as web services, distributed computing, and grid computing infrastructures.

[0159] The processes and logic flows described herein may be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output.

[0160] Processors suitable for executing computer programs include, by way of example, both general purpose and special purpose microprocessors, as well as any one or more processors of any kind of digital computer. Generally, a processor receives instructions and data from a read-only memory or a random access memory or both. The essential elements of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer also includes one or more mass storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical disks, or is operatively coupled to receive data from them, transfer data to them, or both. However, a computer need not have such devices. Devices suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices.

[0161] As used in this specification and claims, the terms "comprises" and "comprising" and variations thereof mean that the specified features, steps or integers are included. These terms are not to be interpreted as excluding the presence of other features, steps or components.

[0162] The invention may also broadly reside in any and all combinations of two or more of the moieties, elements, steps, examples and / or features referred to or indicated herein, individually or collectively. In particular, one or more features in any of the embodiments described herein may be combined with one or more features from any other embodiment(s) described herein.

[0163] Protection may be sought for any features disclosed in any one or more of the publications referenced herein in combination with this disclosure.

[0164] Although specific exemplary embodiments of the present invention have been described, the appended claims are not intended to be limited to only those embodiments, and the claims should be construed literally, intentionally, and / or to encompass equivalents.

[0165] Representative features Representative features are described in the following clauses, which may be combined independently or in any combination with one or more features disclosed in the text and / or drawings of this specification. 1. An apparatus for transmitting ultrasound, comprising: a resonant circuit, the resonant circuit being at least one of an LC tank, an antenna, and a piezoelectric transducer; an H-bridge circuit connected to the resonant circuit, the H-bridge circuit configured to generate an AC drive signal to drive the resonant circuit to generate and transmit ultrasonic waves; a microchip connected to an H-bridge circuit, the microchip configured to control the H-bridge circuit to generate an AC drive signal, the microchip being a single unit comprising a plurality of interconnected embedded components and subsystems; 1. An oscillator comprising: A main clock signal; a first phase clock signal that is initially high during a positive half-cycle of the main clock signal and low during a negative half-cycle of the main clock signal; a second phase clock signal that is high a second time during a negative half-period of the main clock signal and that is low during a positive half-period of the main clock signal, the second phase clock signal being center-aligned in phase with the first phase clock signal; a pulse width modulation (PWM) signal generator subsystem, comprising: a delay locked loop configured to generate a double frequency clock signal, which is twice the frequency of a main clock signal, using a first phase clock signal and a second phase clock signal, the delay locked loop being configured to control rising edges of the first phase clock signal and the second phase clock signal to be synchronized with rising edges of the double frequency clock signal, the delay locked loop being configured to adjust frequencies and duty cycles of the first phase clock signal and the second phase clock signal in response to a driver control signal to generate a first phase output signal and a second phase output signal, the first phase output signal and the second phase output signal being configured to drive an H-bridge circuit to generate an AC drive signal for driving a resonant circuit; a first phase output signal terminal configured to output the first phase output signal to the H-bridge circuit; a second phase output signal terminal configured to output a second phase output signal to the H-bridge circuit; a PWM signal generator subsystem comprising: a feedback input terminal configured to receive a feedback signal from the H-bridge circuit, the feedback signal being indicative of a parameter of operation of the H-bridge circuit or the AC drive signal when the H-bridge circuit is driving the resonant circuit with the AC drive signal; 1. An analog-to-digital converter (ADC) subsystem, comprising: a plurality of ADC input terminals configured to receive a plurality of respective analog signals, one ADC input terminal of the plurality of ADC input terminals being connected to a feedback input terminal such that the ADC subsystem receives a feedback signal from the H-bridge circuit, the ADC subsystem being configured to sample the analog signals received at the plurality of ADC input terminals at a sampling frequency proportional to a frequency of the main clock signal, the ADC subsystem being configured to generate an ADC digital signal using the sampled analog signals; an ADC subsystem comprising: a digital processor subsystem configured to receive an ADC digital signal from the ADC subsystem and process the ADC digital signal to generate a driver control signal, the digital processor subsystem configured to communicate the driver control signal to the PWM signal generator subsystem to control the PWM signal generator subsystem; 1. A digital-to-analog converter (DAC) subsystem, comprising: a digital-to-analog converter (DAC) configured to convert the digital control signals generated by the digital processor subsystem into analog voltage control signals to control a voltage regulator circuit configured to generate a voltage for modulation by the H-bridge circuit; and a DAC output terminal configured to output an analog voltage control signal for controlling a voltage regulator circuit to generate a predetermined voltage for modulation by an H-bridge circuit to drive the resonant circuit in response to a feedback signal indicative of operation of the resonant circuit. 2. The apparatus of claim 1, wherein the oscillator is configured to generate a main clock signal at a frequency between 50 kHz and 105 MHz. 3. Microchips 3. The apparatus of claim 1 or 2, further comprising a divider connected to the oscillator to receive the main clock signal from the oscillator and configured to divide the main clock signal by a predetermined divisor amount and output a frequency reference signal to the delay locked loop. 4. An apparatus as described in any one of clauses 1 to 3, wherein the delay locked loop comprises a plurality of delay lines connected end to end, the total delay of the delay lines being equal to the period of the main clock signal. 5. The apparatus of clause 4, wherein the delay locked loop is configured to adjust the duty cycle of the first phase clock signal and the second phase clock signal in response to the driver control signal by varying a delay of each delay line in the delay locked loop. 6. An apparatus as described in any one of clauses 1 to 5, wherein the feedback input terminal is configured to receive a feedback signal from the H-bridge circuit in the form of a voltage indicative of the rms current of the AC drive signal driving the resonant circuit. 7. An apparatus described in any one of clauses 1 to 6, wherein the ADC subsystem comprises a plurality of further ADC input terminals configured to receive feedback signals indicative of at least one of the voltage of a battery connected to the apparatus or the voltage of a battery charger connected to the apparatus. 8. Microchips The apparatus of any one of clauses 1 to 7, further comprising a temperature sensor embedded in the microchip, the temperature sensor configured to generate a temperature signal indicative of a temperature of the microchip, the temperature signal being received by a further ADC input terminal of the ADC subsystem, and the temperature signal being sampled by the ADC. 9. An apparatus as described in any one of clauses 1 to 8, wherein the ADC subsystem is configured to sequentially sample signals received at a plurality of ADC input terminals, each signal being sampled by the ADC subsystem a respective predetermined number of times. 10. Microchips 10. The apparatus of any one of clauses 1 to 9, further comprising a battery charging subsystem configured to control charging of an external battery connected to the microchip. 11. The DAC subsystem 11. The apparatus of any one of clauses 1 to 10, further comprising a further digital-to-analog converter (DAC) configured to convert a further digital control signal generated by the digital processor subsystem into a further analog voltage control signal for controlling the voltage regulator circuit. 12. A device for transmitting ultrasound, comprising: a resonant circuit, the resonant circuit being at least one of an LC tank, an antenna, and a piezoelectric transducer; a microchip connected to a resonant circuit, the microchip being a single unit comprising a plurality of interconnected embedded components and subsystems; A first power terminal; A second power terminal; 1. An H-bridge circuit incorporating a first switch, a second switch, a third switch, and a fourth switch, the first switch and the third switch are connected in series between the first power supply terminal and the second power supply terminal; the first output terminal is electrically connected between the first switch and the third switch; the second switch and the fourth switch are connected in series between the first power supply terminal and the second power supply terminal; an H-bridge circuit, the second output terminal of which is electrically connected between the second switch and the fourth switch; a first phase terminal configured to receive a first phase output signal from a pulse width modulated (PWM) signal generator; a second phase terminal configured to receive a second phase output signal from the PWM signal generator; a digital state machine configured to generate a timing signal based on the first phase output signal and the second phase output signal, and output the timing signal to switches of an H-bridge circuit to control the switches on and off in a sequence such that the H-bridge circuit outputs an AC drive signal to the resonant circuit to drive the resonant circuit to generate and transmit ultrasonic waves, the sequence including a free floating period during which the first switch and the second switch are turned off and the third switch and the fourth switch are turned on to dissipate energy stored by the resonant circuit; A current sensor comprising: a first current sensing resistor connected in series between the first switch and the first power supply terminal; a first voltage sensor configured to measure a voltage drop across a first current sense resistor and provide a first voltage output indicative of a current flowing through the first current sense resistor; a second current sensing resistor connected in series between the second switch and the first power supply terminal; a second voltage sensor configured to measure a voltage drop across a second current sensor resistor and provide a second voltage output indicative of a current flowing through the second current sensing resistor; a current sensor output terminal configured to provide an rms output voltage relative to ground equal to the first voltage output and the second voltage output; and a microchip, wherein the rms output voltage is indicative of the rms current through the first switch or the second switch and the current through a resonant circuit connected between the first output terminal and the second output terminal. 13. The apparatus of clause 12, wherein the H-bridge circuit is configured to output 22 W to 50 W of power to a resonant circuit connected to the first output terminal and the second output terminal. 14. Microchips 14. The apparatus of claim 12 or 13, further comprising a temperature sensor embedded in the microchip, the temperature sensor configured to measure a temperature of the microchip and to disable at least a portion of the microchip if the temperature sensor senses that the microchip has a temperature above a predetermined threshold. 15. An apparatus for transmitting ultrasound, comprising: a resonant circuit, the resonant circuit being at least one of an LC tank, an antenna, and a piezoelectric transducer; a first microchip coupled to the resonant circuit, the first microchip being a single unit comprising a plurality of interconnected embedded components and subsystems; A first power terminal; A second power terminal; 1. An H-bridge circuit incorporating a first switch, a second switch, a third switch, and a fourth switch, the first switch and the third switch are connected in series between the first power supply terminal and the second power supply terminal; The first output terminal is electrically connected between the first switch and the third switch, and the first output terminal is connected to a first terminal of the resonant circuit; the second switch and the fourth switch are connected in series between the first power supply terminal and the second power supply terminal; an H-bridge circuit, the second output terminal of which is electrically connected between the second switch and the fourth switch, the second output terminal of which is connected to a second terminal of the resonant circuit; a first phase terminal configured to receive a first phase output signal from a pulse width modulation (PWM) signal generator subsystem; a second phase terminal configured to receive a second phase output signal from the PWM signal generator; a digital state machine configured to generate a timing signal based on the first phase output signal and the second phase output signal, and output the timing signal to switches of an H-bridge circuit to control the switches on and off in a sequence such that the H-bridge circuit outputs an AC drive signal to the resonant circuit to drive the resonant circuit to generate and transmit ultrasonic waves, the sequence including a free floating period during which the first switch and the second switch are turned off and the third switch and the fourth switch are turned on to dissipate energy stored by the resonant circuit; A current sensor comprising: a first current sensing resistor connected in series between the first switch and the first power supply terminal; a first voltage sensor configured to measure a voltage drop across a first current sense resistor and provide a first voltage output indicative of a current flowing through the first current sense resistor; a second current sensing resistor connected in series between the second switch and the first power supply terminal; a second voltage sensor configured to measure a voltage drop across a second current sensor resistor and provide a second voltage output indicative of a current flowing through the second current sensing resistor; a current sensor output terminal configured to provide an rms output voltage relative to ground equal to the first voltage output and the second voltage output; a first microchip, the rms output voltage being indicative of the rms current through the first switch or the second switch and the current through a resonant circuit connected between the first output terminal and the second output terminal; a second microchip connected to the first microchip and controlling the H-bridge circuit to generate an AC drive signal, the second microchip being a single unit comprising a plurality of interconnected embedded components and subsystems; 1. An oscillator comprising: A main clock signal; a first phase clock signal that is initially high during a positive half-cycle of the main clock signal and low during a negative half-cycle of the main clock signal; a second phase clock signal that is high a second time during a negative half-period of the main clock signal and that is low during a positive half-period of the main clock signal, the second phase clock signal being center-aligned in phase with the first phase clock signal; 1. A pulse width modulation (PWM) signal generator subsystem, comprising: a delay locked loop configured to generate a double frequency clock signal, which is twice the frequency of a main clock signal, using a first phase clock signal and a second phase clock signal, the delay locked loop being configured to control rising edges of the first phase clock signal and the second phase clock signal to be synchronized with rising edges of the double frequency clock signal, the delay locked loop being configured to adjust frequencies and duty cycles of the first phase clock signal and the second phase clock signal in response to a driver control signal to generate a first phase output signal and a second phase output signal, the first phase output signal and the second phase output signal being configured to drive an H-bridge circuit to generate an AC drive signal for driving a resonant circuit; a first phase output signal terminal configured to output the first phase output signal to the H-bridge circuit; a second phase output signal terminal configured to output a second phase output signal to the H-bridge circuit; a PWM signal generator subsystem comprising: a feedback input terminal configured to receive a feedback signal from the H-bridge circuit, the feedback signal being indicative of a parameter of operation of the H-bridge circuit or the AC drive signal when the H-bridge circuit is driving the resonant circuit with the AC drive signal; 1. An analog-to-digital converter (ADC) subsystem, comprising: a plurality of ADC input terminals configured to receive a plurality of respective analog signals, one ADC input terminal of the plurality of ADC input terminals being connected to a feedback input terminal such that the ADC subsystem receives a feedback signal from the H-bridge circuit, the ADC subsystem being configured to sample the analog signals received at the plurality of ADC input terminals at a sampling frequency proportional to a frequency of the main clock signal, the ADC subsystem being configured to generate an ADC digital signal using the sampled analog signals; an ADC subsystem comprising: a digital processor subsystem configured to receive an ADC digital signal from the ADC subsystem and process the ADC digital signal to generate a driver control signal, the digital processor subsystem configured to communicate the driver control signal to the PWM signal generator subsystem to control the PWM signal generator subsystem; 1. A digital-to-analog converter (DAC) subsystem, comprising: a digital-to-analog converter (DAC) configured to convert the digital control signals generated by the digital processor subsystem into analog voltage control signals to control a voltage regulator circuit that generates a voltage for modulation by the H-bridge circuit; and a second microchip comprising a DAC subsystem comprising a DAC output terminal configured to output an analog voltage control signal for controlling a voltage regulator circuit to generate a predetermined voltage for modulation by an H-bridge circuit to drive the resonant circuit in response to a feedback signal indicative of operation of the resonant circuit. 16. The device is 16. The apparatus of claim 15, further comprising a boost converter circuit configured to increase a voltage of the power supply to a boost voltage in response to an analog voltage output signal from the DAC output terminal, the boost converter circuit configured to provide a boost voltage at the first power supply terminal such that the boost voltage is modulated by switching of a switch of the H-bridge circuit. 17. The apparatus of clause 15 or 16, wherein the current sensor is configured to sense a current through the resonant circuit during the free-floating period, and the digital state machine is configured to adapt the timing signals to switch on either the first switch or the second switch when the current sensor senses that the current through the resonant circuit is zero during the free-floating period. 18. During the setup phase of the device's operation, the second microchip measuring a time length until a current flowing through the resonant circuit becomes zero when the first switch and the second switch are turned off and the third switch and the fourth switch are turned on; 18. The apparatus of any one of clauses 15 to 17, configured to set a length of time of the free-floating period to be equal to the measured length of time.

Claims

1. 1. An apparatus for transmitting ultrasound, comprising: a resonant circuit, the resonant circuit being at least one of an LC tank, an antenna, and a piezoelectric transducer; an H-bridge circuit connected to the resonant circuit and configured to generate an AC drive signal to drive the resonant circuit to generate and transmit the ultrasonic waves; a microchip connected to the H-bridge circuit, the microchip configured to control the H-bridge circuit to generate the AC drive signal, the microchip being a single unit comprising a plurality of interconnected embedded components and subsystems; 1. An oscillator comprising: A main clock signal; a first phase clock signal that is initially high during a positive half-period of the main clock signal and initially low during a negative half-period of the main clock signal; a second phase clock signal that is high a second time during the negative half-period of the main clock signal and that is low during the positive half-period of the main clock signal, wherein the phases of the first phase clock signal and the second phase clock signal are center-aligned; 1. A pulse width modulation (PWM) signal generator subsystem, comprising: a delay locked loop configured to generate a double frequency clock signal using the first phase clock signal and the second phase clock signal, the delay locked loop being configured to control rising edges of the first phase clock signal and the second phase clock signal to be synchronized with rising edges of the double frequency clock signal, the delay locked loop being configured to adjust frequencies and duty cycles of the first phase clock signal and the second phase clock signal in response to a driver control signal to generate a first phase output signal and a second phase output signal, the first phase output signal and the second phase output signal being configured to drive the H-bridge circuit to generate an AC drive signal for driving the resonant circuit; a first phase output signal terminal configured to output the first phase output signal to the H-bridge circuit; a second phase output signal terminal configured to output the second phase output signal to the H-bridge circuit; a feedback input configured to receive a feedback signal from the H-bridge circuit, the feedback signal indicative of a parameter of operation of the H-bridge circuit or the AC drive signal when the H-bridge circuit is driving the resonant circuit with the AC drive signal; and 1. An analog-to-digital converter (ADC) subsystem, comprising: a plurality of ADC input terminals configured to receive a plurality of respective analog signals, one ADC input terminal of the plurality of ADC input terminals being connected to the feedback input terminal such that the ADC subsystem receives the feedback signal from the H-bridge circuit, the ADC subsystem being configured to sample the analog signals received at the plurality of ADC input terminals at a sampling frequency proportional to the frequency of the main clock signal, the ADC subsystem being configured to generate an ADC digital signal using the sampled analog signals; an ADC subsystem comprising: a digital processor subsystem configured to receive the ADC digital signal from the ADC subsystem and process the ADC digital signal to generate the driver control signal, the digital processor subsystem configured to communicate the driver control signal to the PWM signal generator subsystem to control the PWM signal generator subsystem; 1. A digital-to-analog converter (DAC) subsystem, comprising: a digital-to-analog converter (DAC) configured to convert digital control signals generated by the digital processor subsystem into analog voltage control signals to control a voltage regulator circuit configured to generate a voltage for modulation by the H-bridge circuit; and a DAC output terminal configured to output the analog voltage control signal for controlling the voltage regulator circuit to generate a predetermined voltage for modulation by the H-bridge circuit to drive the resonant circuit in response to a feedback signal indicative of operation of the resonant circuit.

2. 2. The apparatus of claim 1, wherein the oscillator is configured to generate the main clock signal at a frequency between 50 kHz and 105 MHz.

3. The microchip is 3. The apparatus of claim 1, further comprising a frequency divider connected to the oscillator to receive the main clock signal from the oscillator and configured to divide the main clock signal by a predetermined divisor amount and output the frequency reference signal to the delay locked loop.

4. 4. Apparatus according to claim 1, wherein the delay locked loop comprises a plurality of delay lines connected end-to-end, the total delay of the delay lines being equal to the period of the main clock signal.

5. 5. The apparatus of claim 4, wherein the delay locked loop is configured to adjust the duty cycle of the first phase clock signal and the second phase clock signal in response to the driver control signal by varying a delay of each delay line in the delay locked loop.

6. 6. The apparatus of claim 1 , wherein the feedback input terminal is configured to receive a feedback signal from the H-bridge circuit in the form of a voltage indicative of the rms current of an AC drive signal driving the resonant circuit.

7. 7. The apparatus of claim 1, wherein the ADC subsystem comprises a plurality of further ADC input terminals configured to receive feedback signals indicative of at least one of a voltage of a battery connected to the apparatus or a voltage of a battery charger connected to the apparatus.

8. The microchip is 8. The apparatus of claim 1, further comprising a temperature sensor embedded in the microchip, the temperature sensor configured to generate a temperature signal indicative of a temperature of the microchip, the temperature signal being received by a further ADC input terminal of the ADC subsystem, the temperature signal being sampled by the ADC.

9. 9. The apparatus of claim 1, wherein the ADC subsystem is configured to sequentially sample signals received at the plurality of ADC input terminals, each signal being sampled by the ADC subsystem a respective predetermined number of times.

10. The microchip is 10. The apparatus of claim 1, further comprising a battery charging subsystem configured to control charging of an external battery connected to the microchip.

11. the DAC subsystem:

11. The apparatus of claim 1, further comprising a further digital-to-analog converter (DAC) configured to convert a further digital control signal generated by the digital processor subsystem into a further analog voltage control signal for controlling the voltage regulator circuit.

12. 1. An apparatus for transmitting ultrasound, comprising: a resonant circuit, the resonant circuit being at least one of an LC tank, an antenna, and a piezoelectric transducer; a microchip coupled to said resonant circuit, said microchip being a single unit comprising a plurality of interconnected embedded components and subsystems; A first power supply terminal; A second power supply terminal; 1. An H-bridge circuit incorporating a first switch, a second switch, a third switch, and a fourth switch, the first switch and the third switch are connected in series between the first power supply terminal and the second power supply terminal; a first output terminal electrically connected between the first switch and the third switch; the second switch and the fourth switch are connected in series between the first power supply terminal and the second power supply terminal; an H-bridge circuit, a second output terminal of which is electrically connected between the second switch and the fourth switch; a first phase terminal configured to receive a first phase output signal from a pulse width modulated (PWM) signal generator; a second phase terminal configured to receive a second phase output signal from the PWM signal generator; a digital state machine configured to generate a timing signal based on the first phase output signal and the second phase output signal, and output the timing signal to the switches of the H-bridge circuit to control the switches on and off in a sequence such that the H-bridge circuit outputs an AC drive signal to the resonant circuit to drive the resonant circuit to generate and transmit the ultrasonic wave, the sequence including a free floating period during which the first switch and the second switch are turned off and the third switch and the fourth switch are turned on to dissipate energy stored by the resonant circuit; A current sensor comprising: a first current sensing resistor connected in series between the first switch and the first power supply terminal; a first voltage sensor configured to measure a voltage drop across the first current sense resistor and provide a first voltage output indicative of a current flowing through the first current sense resistor; a second current sensing resistor connected in series between the second switch and the first power supply terminal; a second voltage sensor configured to measure a voltage drop across the second current sense resistor and provide a second voltage output indicative of a current flowing through the second current sense resistor; a current sensor output terminal configured to provide an rms output voltage with respect to ground equal to said first voltage output and said second voltage output; a microchip, wherein the rms output voltage is indicative of the rms current flowing through the first switch or the second switch and the current flowing through the resonant circuit connected between the first output terminal and the second output terminal.

13. 13. The apparatus of claim 12, wherein the H-bridge circuit is configured to output between 22 W and 50 W of power to the resonant circuit connected to the first output terminal and the second output terminal.

14. The microchip is 14. The apparatus of claim 12 or 13, further comprising a temperature sensor embedded in the microchip, the temperature sensor configured to measure a temperature of the microchip and to disable at least a portion of the microchip if the temperature sensor senses that the microchip is at a temperature above a predetermined threshold.

15. 1. An apparatus for transmitting ultrasound, comprising: a resonant circuit, the resonant circuit being at least one of an LC tank, an antenna, and a piezoelectric transducer; a first microchip connected to the resonant circuit, the first microchip being a single unit comprising a plurality of interconnected embedded components and subsystems; A first power supply terminal; A second power supply terminal; 1. An H-bridge circuit incorporating a first switch, a second switch, a third switch, and a fourth switch, the first switch and the third switch are connected in series between the first power supply terminal and the second power supply terminal; a first output terminal electrically connected between the first switch and the third switch, the first output terminal being connected to a first terminal of the resonant circuit; the second switch and the fourth switch are connected in series between the first power supply terminal and the second power supply terminal; an H-bridge circuit, the second output terminal of which is electrically connected between the second switch and the fourth switch, the second output terminal of which is connected to a second terminal of the resonant circuit; a first phase terminal configured to receive a first phase output signal from a pulse width modulation (PWM) signal generator subsystem; a second phase terminal configured to receive a second phase output signal from the PWM signal generator subsystem; a digital state machine configured to generate a timing signal based on the first phase output signal and the second phase output signal, and output the timing signal to the switches of the H-bridge circuit to control the switches on and off in a sequence such that the H-bridge circuit outputs an AC drive signal to the resonant circuit to drive the resonant circuit to generate and transmit the ultrasonic wave, the sequence including a free floating period during which the first switch and the second switch are turned off and the third switch and the fourth switch are turned on to dissipate energy stored by the resonant circuit; A current sensor comprising: a first current sensing resistor connected in series between the first switch and the first power supply terminal; a first voltage sensor configured to measure a voltage drop across the first current sense resistor and provide a first voltage output indicative of a current flowing through the first current sense resistor; a second current sensing resistor connected in series between the second switch and the first power supply terminal; a second voltage sensor configured to measure a voltage drop across the second current sense resistor and provide a second voltage output indicative of a current flowing through the second current sense resistor; a current sensor output terminal configured to provide an rms output voltage relative to ground equal to the first voltage output and the second voltage output; a first microchip, the rms output voltage being indicative of the rms current through the first switch or the second switch and the current through the resonant circuit connected between the first output terminal and the second output terminal; a second microchip connected to the first microchip and controlling the H-bridge circuit to generate the AC drive signal, the second microchip being a single unit comprising a plurality of interconnected embedded components and subsystems; 1. An oscillator comprising: A main clock signal; a first phase clock signal that is initially high during a positive half-period of the main clock signal and initially low during a negative half-period of the main clock signal; a second phase clock signal that is high a second time during the negative half-period of the main clock signal and that is low during the positive half-period of the main clock signal, wherein the phases of the first phase clock signal and the second phase clock signal are center-aligned; The PWM signal generator subsystem, a delay locked loop configured to generate a double frequency clock signal using the first phase clock signal and the second phase clock signal, the delay locked loop being configured to control rising edges of the first phase clock signal and the second phase clock signal to be synchronized with rising edges of the double frequency clock signal, the delay locked loop being configured to adjust frequencies and duty cycles of the first phase clock signal and the second phase clock signal in response to a driver control signal to generate first phase output signals and second phase output signals, the first phase output signals and the second phase output signals being configured to drive the H-bridge circuit to generate an AC drive signal for driving the resonant circuit; a first phase output signal terminal configured to output the first phase output signal to the H-bridge circuit; a second phase output signal terminal configured to output the second phase output signal to the H-bridge circuit; a feedback input configured to receive a feedback signal from the H-bridge circuit, the feedback signal indicative of a parameter of operation of the H-bridge circuit or the AC drive signal when the H-bridge circuit is driving the resonant circuit with the AC drive signal; and 1. An analog-to-digital converter (ADC) subsystem, comprising: a plurality of ADC input terminals configured to receive a plurality of respective analog signals, one ADC input terminal of the plurality of ADC input terminals being connected to the feedback input terminal such that the ADC subsystem receives the feedback signal from the H-bridge circuit, the ADC subsystem being configured to sample the analog signals received at the plurality of ADC input terminals at a sampling frequency proportional to a frequency of the main clock signal, the ADC subsystem being configured to generate an ADC digital signal using the sampled analog signals; an ADC subsystem comprising: a digital processor subsystem configured to receive the ADC digital signal from the ADC subsystem and process the ADC digital signal to generate a driver control signal, the digital processor subsystem configured to communicate the driver control signal to the PWM signal generator subsystem to control the PWM signal generator subsystem; 1. A digital-to-analog converter (DAC) subsystem, comprising: a digital-to-analog converter (DAC) configured to convert digital control signals generated by the digital processor subsystem into analog voltage control signals to control a voltage regulator circuit that generates a voltage for modulation by the H-bridge circuit; and a DAC output terminal configured to output the analog voltage control signal for controlling the voltage regulator circuit to generate a predetermined voltage for modulation by the H-bridge circuit to drive the resonant circuit in response to a feedback signal indicative of operation of the resonant circuit.

16. The apparatus, 16. The apparatus of claim 15, further comprising a boost converter circuit configured to increase the voltage of a power supply to a boost voltage in response to the analog voltage output signal from the DAC output terminal, the boost converter circuit configured to provide the boost voltage at the first power supply terminal such that the boost voltage is modulated by the switching of the switches of the H-bridge circuit.

17. 17. The apparatus of claim 15 or 16, wherein the current sensor is configured to sense a current through the resonant circuit during the free-floating period, and the digital state machine is configured to adapt the timing signals to switch on either the first switch or the second switch when the current sensor senses that the current through the resonant circuit is zero during the free-floating period.

18. During a setup phase of operation of the device, the second microchip: measuring a time length until a current flowing through the resonant circuit becomes zero when the first switch and the second switch are turned off and the third switch and the fourth switch are turned on; 18. Apparatus according to any one of claims 15 to 17, configured to set the length of time of the free-floating period to be equal to the measured length of time.

Images