Analog Signal Monitoring for Functional Safety

Abstract

A method of operating a memory device includes supplying one or more power supply voltages to a memory array and monitoring the one or more power supply voltages, the monitoring including selecting a selected power supply voltage from the one or more power supply voltages, converting an internal reference voltage of the memory device and a scaled version of the selected power supply voltage to one or more digital values ​​using an analog-to-digital converter (ADC), generating a calibrated measurement result using the one or more digital values, and determining whether the calibrated measurement result is within a predetermined range.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Patent Application No. 17 / 862,917, filed July 12, 2022, which claims the benefit of U.S. Provisional Application No. 63 / 311,693, filed February 18, 2022, which application is incorporated herein by reference.

[0002] The present disclosure relates generally to electronic systems and methods, and in particular embodiments to circuits and methods for analog signal monitoring for functional safety. [Background technology]

[0003] Memory devices, such as random access memory (RAM), read only memory (ROM), flash memory, etc., are widely used in electronic devices for storing application data and / or user data. To use a memory device, an electronic device may perform various memory access operations, such as read, write, erase, etc., on a memory array of the memory device.

[0004] Generally, in a memory device, one or more analog voltages and / or analog currents are provided or generated to drive circuits for performing various memory access operations. The signal levels (e.g., voltage or current values) of the analog signals are critical to the proper functioning of the memory device. For example, to program (e.g., write or erase) a memory array, a programming voltage, either nominal or within a specified range from the nominal value, is used to program the memory array. If the programming voltage deviates from the nominal value by more than an acceptable range (e.g., a predetermined range), the memory array may not be properly programmed. Similarly, during a read operation on the memory array, an electrical characteristic (e.g., current or voltage value) indicative of the stored digital value is measured and compared to a threshold value to determine the digital value stored in the memory array. If the ready voltage for performing a read operation is outside the acceptable range, the digital value stored in the memory array may not be read correctly.

[0005] If an analog signal (e.g., an analog voltage and / or an analog current) used in performing a memory access operation is not monitored and goes out of range, the memory device may complete the memory access operation and report the memory access operation as successfully completed without knowing that the analog signal is out of range. When the analog signal used in the memory access operation is out of range, a large amount of data errors may occur. If the amount of data errors exceeds the error correction / error detection capability of the error correction code (ECC) used in the memory device, the uncorrected / undetected data errors may cause performance degradation at the system level. There is a need in the art for a memory device with an integrated analog signal monitoring capability for improved system performance and efficient error reduction / prevention capabilities. Summary of the Invention [Means for solving the problem]

[0006] According to one embodiment, a memory device includes a memory array comprising memory cells, and a power management circuit for the memory array, the power management circuit including a voltage source configured to provide one or more power supply voltages to the memory array, an internal voltage reference configured to provide an internal reference voltage, a multiplexer configured to receive the one or more power supply voltages and configured to output a selected power supply voltage selected from the one or more power supply voltages, an analog-to-digital converter (ADC) configured to convert scaled versions of the internal reference voltage and the selected power supply voltage to one or more digital values, and a digital comparator. The digital comparator is configured to generate a calibrated measurement result using the one or more digital values, a first stored digital value of the internal reference voltage and a second stored digital value of the external reference voltage, compare the calibrated measurement result with a predetermined range, and set an error flag indicating a fault condition of the memory device in response to detecting that the calibrated measurement result is outside the predetermined range.

[0007] According to one embodiment, an integrated circuit (IC) device includes a memory array including memory cells, a controller coupled to the memory array, and a power management circuit coupled to the memory array and the controller, the power management circuit including a voltage supply circuit configured to provide a power supply voltage to the memory array, a multiplexer coupled to the voltage supply circuit and configured to output a selected power supply voltage selected from the power supply voltage, an internal voltage reference configured to provide an internal reference voltage, an analog-to-digital converter (ADC) configured to convert a scaled version of the internal reference voltage and the selected power supply voltage into an ADC output, and a digital comparator configured to generate a calibrated measurement result using the ADC output, a first pre-stored digital value of the internal reference voltage, and a second pre-stored digital value of the external reference voltage, determine whether the calibrated measurement result is within a predetermined range, and set an error flag indicating a fault condition of the IC device in response to determining that the calibrated measurement result is outside the predetermined range.

[0008] According to one embodiment, a method of operating a memory device includes supplying one or more power supply voltages to a memory array and monitoring the one or more power supply voltages, the monitoring including selecting a selected power supply voltage from the one or more power supply voltages, converting an internal reference voltage of the memory device and a scaled version of the selected power supply voltage to one or more digital values ​​using an analog-to-digital converter (ADC), generating a calibrated measurement result using the one or more digital values, and determining whether the calibrated measurement result is within a predetermined range.

[0009] For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0010] [Figure 1] FIG. 2 illustrates a memory device with integrated analog signal monitoring capabilities in accordance with one embodiment. [Diagram 2] FIG. 2 is a block diagram of an analog signal monitoring circuit in one embodiment. [Diagram 3] 3 is a timing diagram of the analog signal monitoring circuit of FIG. 2 in one embodiment. [Figure 4] 4 is a flow chart of a method for monitoring an analog signal in one embodiment. [Diagram 5] 1 is a flow chart of a method for operating a memory device in one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Making and using examples of the present disclosure are described in detail below. However, it should be appreciated that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The illustrated examples are merely illustrative of specific ways to make and use the invention and do not limit the scope of the invention. Throughout this description, the same or similar reference numbers in different figures refer to the same or similar components unless otherwise specified.

[0012] Although the present disclosure is described with respect to an example in a particular context, namely analog signal monitoring in a memory device, those skilled in the art will readily appreciate that the principles disclosed herein may be applied to analog signal monitoring for other types of systems or applications.

[0013] 1 illustrates a memory device 100 incorporating analog signal monitoring functionality in one embodiment. As illustrated in FIG. 1, memory device 100 includes a memory array 101 and a memory control circuit 110. Memory control circuit 110 further includes a power management circuit 120, a controller 103, a system clock circuit 115, and an input / output (I / O) driver circuit 111, among other circuits, as described in more detail below.

[0014] The memory array 101 includes a plurality of memory cells (e.g., multi-bit, multi-level memory cells) for storing digital values ​​(e.g., 0 and 1) or analog values. The memory array 101 may comprise any suitable type of memory cell, such as one transistor one capacitor (1T1C) memory cells, split gate (1.5T) memory cells, two transistor memory cells, etc. Each of the memory cells of the memory array 101 may store one or more bits of digital data. The memory cells may be organized into rows and columns and may be individually addressable by address lines (e.g., bit lines, word lines) of the memory array 101. Addressing of the memory cells and data transfer (e.g., read / write) between the memory cells may be controlled by the controller 103, for example, via control signal / data paths 114 between the controller 103 and the memory array 101. Memory arrays are known in the art, and therefore will not be repeated in detail here.

[0015] The controller 103 may be a microcontroller, a processor, a digital logic circuit, an application specific integrated circuit (ASIC), etc. FIG. 1 shows a ROM module 107 and a static random access memory (SRAM) module 109 coupled to the controller 103. The ROM module 107 and the SRAM module 109 are used to store programs (e.g., computer code) executed by the controller 103 and / or program data or user data used by the controller 103. The controller 103 may have multiple registers 105 or other types of memory components that may be used to store target values ​​(e.g., target nominal values, or ranges around nominal values) of analog signals (e.g., voltages or currents) used in memory access operations, or to store pass / fail results for analog signal monitoring. The system clock circuit 115 generates one or more system clocks used to drive the controller 103 and the power management circuit 120.

[0016] 1 further illustrates an I / O driver circuit 111 coupled between the controller 103 and an I / O pad 113 of the memory device 100. The I / O driver circuit 111 may be used to improve the drive capability of the controller 103 and / or to convert signal levels (e.g., voltage levels) between an I / O voltage of the controller 103 and an I / O voltage applied to the I / O pad 113. The I / O pad 113 enables communication between the controller 103 and an external device (e.g., another processor or another device). In some embodiments, a target value of an analog signal (e.g., voltage or current) used for memory access operations is received by the controller 103 via the I / O pad 113. In some embodiments, a pass / fail result for analog signal monitoring is output at the I / O pad 113.

[0017] 1, memory device 100 includes a power management circuit 120 coupled to controller 103, for example, via control signal / data paths 116 and 118. In some embodiments, power management circuit 120 includes circuitry for generating one or more power supply voltages (or power supply currents) used in memory access operations. In addition, power management circuit 120 includes circuitry for monitoring the power supply voltages (or power supply currents). In the description herein, monitoring the power supply voltages (or power supply currents) may be referred to as analog signal monitoring. The description herein uses an example in which the analog signal being monitored is a power supply voltage, and it is understood that the principles disclosed therein may be readily applied to monitor any power supply current, for example, by monitoring the voltage drop across a fixed (e.g., known) resistor through which the power supply current flows.

[0018] As shown in FIG. 1, the power management circuit 120 includes a voltage supply circuit 121 that generates one or more power supply voltages (e.g., having different voltage values ​​such as +1V, +1.5V, +3V, etc.) used, for example, in memory access operations or the operation of other circuits of the memory device 100. The voltage supply circuit 121 may include, for example, a DC-DC power converter, a low drop power regulator, etc. In some embodiments, the DC-DC power converter of the voltage supply circuit 121 converts an analog voltage VDD1 to one or more different DC voltages for use in memory access operations. The analog voltage VDD1 is an external input voltage signal to the memory device 100 in an exemplary embodiment. FIG. 1 further illustrates a charge pump 123 coupled to the memory array 101 and / or the voltage supply circuit 121. In some embodiments, using an analog voltage VDD1 (e.g., an external voltage signal of +3V), the charge pump 123 generates one or more high voltages (e.g., +10V) and the voltage supply circuit 121 generates one or more low voltages (e.g., +1V, +1.5V, +3V) for use by the memory device 100. In the description herein, unless otherwise specified, the voltages provided by the charge pump 123 are not distinguished from the power supply voltages provided by the voltage supply circuit 121, and all voltages provided to the memory array 101 are collectively referred to as one or more power supply voltages for the memory array 101 (or for memory access operations). It should be noted that in embodiments in which a power supply current is used to drive the memory array 101 for memory access operations, the voltage supply circuit 121 may be replaced by a current supply circuit that generates one or more power supply currents. Thus, the voltage supply circuit 121 may also be collectively referred to as a power supply circuit.

[0019] The voltage used for the memory access operation is sent to the analog signal monitoring circuit 130 of the power management circuit 120. As shown in FIG. 1, the analog signal monitoring circuit 130 includes a MUX & voltage divider circuit 131, an internal voltage reference 135, and an analog functional safety circuit 133. The internal voltage reference 135 is a circuit that provides an internal reference voltage (e.g., a fixed, known voltage). In one embodiment, the internal voltage reference 135 is a bandgap voltage reference that provides a reference voltage of, for example, 1.25V. In some embodiments, the MUX & voltage divider circuit 131 includes a multiplexer (MUX) 132 (see FIG. 2) that selects (e.g., selects) a selected power supply voltage for monitoring from one or more power supply voltages. The MUX & voltage divider circuit 131 further includes a scaling circuit 134 (see FIG. 2) that scales the selected power supply voltage by a scaling factor such that the voltage at the output of the scaling circuit is within the measurement range of a subsequent analog-to-digital converter (ADC). The analog functional safety circuit 133 includes an ADC 137 (see FIG. 2) and a digital comparator 139 (see FIG. 2). Details of the analog signal monitoring circuit 130 are described below with reference to FIG.

[0020] In some embodiments, the control signal / data path 118 is used to transfer control signals and data between the controller 103 and the voltage supply circuit 121. For example, depending on the type / structure of the memory array 101, the controller 103 can use the control signal / data path 118 to control the voltage levels and dynamic behavior (e.g., timing sequence) of the power supply voltage generated by the voltage supply circuit 121. In some embodiments, the control signal / data path 116 is used to transfer control signals and data between the controller 103 and the analog signal monitoring circuit 130. Various control signals and data transferred between the controller 103 and the analog signal monitoring circuit 130 are described below.

[0021] Figure 2 illustrates a block diagram of the analog signal monitoring circuit 130 of Figure 1 in one embodiment. In the example of Figure 2, the analog signal monitoring circuit 130 includes an internal voltage reference 135, a MUX 132 (e.g., an analog MUX), a scaling circuit 134 (sometimes called a voltage divider), an ADC 137, and a digital comparator 139. An enable signal (labeled "fusa_en" in Figure 2) serves as an enable signal for the analog signal monitoring circuit 130. The MUX 132 selects an internal voltage reference 135, a MUX 132 (e.g., an analog MUX), a scaling circuit 134 (sometimes called a voltage divider), an ADC 137, and a digital comparator 139 to be monitored. <1> ,...,analog_in <n>2, MUX 132 further accepts an external reference signal (labeled as “External Reference” in FIG. 2) as an input signal. The external reference signal may be used to generate a pre-stored digital value of an external reference voltage during factory testing, the details of which are described below. MUX 132 may also accept other analog signals of memory device 100 for monitoring. MUX 132 is controlled by a control signal (labeled as “Input Selector” in FIG. 2) to select which analog signal is sent to the output of MUX 132 as the selected analog signal (e.g., the selected power supply voltage). The control signal for MUX 132 may be generated by controller 103 and sent to analog signal monitoring circuit 130 via control signal / data path 116, as shown in FIG. 1.

[0022] The output of MUX 132 is sent to an input terminal of scaling circuit 134, which scales (e.g., divides or multiplies) the output of MUX 132 by a scaling factor. The scaling factor of scaling circuit 134 is selected by a control signal (labeled “Divide Coefficient” in FIG. 2 ), which may be generated by controller 103 and sent to analog signal monitoring circuit 130 via control signal / data path 116. Because the input analog signal to MUX 132 may span a wide range of signal levels (e.g., voltage or current values), an appropriate scaling factor is selected by controller 103 according to the signal level of the selected analog signal at the output of MUX 132, such that the signal level of the selected analog signal at the output of scaling circuit 134 is within the input range of ADC 137. In some embodiments, the scaling factor is selected so that the scaled selected analog signal at the output of the scaling circuit 134 is at an optimal or near optimal level for the ADC 137, e.g., about 80% of the maximum input signal level of the ADC 137, maximizing the signal-to-noise ratio (SNR) of the ADC output while leaving some headroom to avoid saturation of the ADC output.

[0023] In FIG. 2, ADC 137 accepts the output of internal voltage reference 135 as a first measurement input (labeled “refer_in” in FIG. 2) and the scaled selected analog signal from scaling circuit 134 as a second measurement input (labeled “meas_in” in FIG. 2). In some embodiments, a multiplexer, not shown, may be included in ADC 137 to, for example, select the first measurement input and then the second measurement input as inputs to ADC 137, such that the first measurement input and the second measurement input are converted sequentially to digital values ​​by ADC 137. In some embodiments, the first measurement input and the second measurement input are used as a pair of differential input signals to ADC 137, and the pair of differential signals is converted to a digital value by ADC 137. In some embodiments, ADC 137 may include two parallel ADC circuits, each coupled to a respective one of the first measurement input and the second measurement input, such that the first measurement input and the second measurement input are converted to digital values ​​in parallel. These and other variations are possible and are fully intended to be within the scope of the present disclosure. As a non-limiting example, the following description uses an example in which the first measurement input and the second measurement input are each converted to a respective digital value, it being understood that the principles disclosed herein may be modified for other variations.

[0024] To monitor a selected analog signal, the ADC 137 converts a first measurement input to a first digital value (also referred to as a first ADC output) and converts a second measurement input to a second digital value (also referred to as a second ADC output). The first and second digital values ​​from the ADC 137 are, for example, 16-bit binary digital words for a 16-bit ADC. The first and second digital values ​​are sent to a digital comparator 139 for processing. FIG. 2 shows a clock signal (labeled “clk” in FIG. 2) for driving the ADC 137 and a control signal (labeled “start” in FIG. 2) for starting (e.g., enabling) the ADC 137. The clock signal may be generated by the system clock circuit 115 and sent to the analog signal monitoring circuit 130, and the control signal for the ADC 137 may be generated by the controller 103 and sent to the analog signal monitoring circuit 130 via the control signal / data path 116.

[0025] The output of ADC 137 (e.g., the first digital value and the second digital value) is sent to digital comparator 139 via a data path (labeled “DATA” in FIG. 2) between the output of ADC 137 and an input of digital comparator 139. FIG. 2 further shows an enable signal (labeled “COMPARATION ENABLE” in FIG. 2) generated by ADC 137 and sent to digital comparator 139 to enable a comparison of the measurement result generated by digital comparator 139 to a target value.

[0026] Digital comparator 139 includes data processing circuitry 141 that generates a calibrated measurement result using the output of ADC 137 (e.g., the first digital value and the second digital value), the first pre-stored digital value of the internal reference voltage, and the second pre-stored digital value of the external reference voltage. The first pre-stored digital value and the second pre-stored digital value may be stored in registers of digital comparator 139 during factory testing of memory device 100. Details for generating the calibrated measurement result are described below with reference to FIG. 4.

[0027] The calibrated measurement corresponds to a metric that indicates a value (e.g., a voltage value) of a selected analog signal. As a non-limiting example, the calibrated measurement may correspond to (e.g., be proportional to) a difference between the value of the selected analog signal and a value of an internal reference voltage, or may correspond to a ratio between the value of the selected analog signal and a value of an internal reference voltage.

[0028] The digital comparator 139 compares the calibrated measurement result to a target value (labeled "Target" in FIG. 2 ), and the comparison result is used to set an error flag indicating a "pass" or "fail" of the monitored analog signal, where "pass" means that the monitored analog signal is at the target value (or within a predetermined range from the target value) and "fail" means that the monitored analog signal is not at the target value (or not within a predetermined range from the target value). The target value (which may be a predetermined value or a range around the predetermined value) may be sent from the controller 103 to the analog signal monitoring circuit 130 via the control signal / data path 116. Note that in some embodiments, the target value takes into account the scaling factor of the scaling circuit 134. The output of the digital comparator 139 (e.g., a pass / fail result) may be sent back to the controller 103 via the control signal / data path 116 and stored in the register 105 of the controller 103 in some embodiments.

[0029] In some embodiments, after a first analog signal is selected and monitored (e.g., converted by ADC 137 and processed by digital comparator 139 to find a "pass / fail" result), controller 103 selects a second analog signal as the output of MUX 132 to monitor the second analog signal. In some embodiments, the process is repeated until all or at least all of the analog signal selections at the inputs of MUX 132 have been monitored.

[0030] 3 illustrates a timing diagram of the analog signal monitoring circuit 130 of FIG. 2 in one embodiment. As shown in FIG. 3, at time t1, the control signal fusa_en (corresponding to the control signal "fusa_en" of FIG. 2) rises from low to high, enabling the analog signal monitoring circuit 130. After the control signal fusa_en rises high, after a period of time (e.g., a predetermined duration), after time t2, the control signal fusa_start (corresponding to the control signal "start" of FIG. 2) rises from low to high, thus enabling the ADC 137. The ADC 137 starts outputting digital samples after time t2. The ADC output is the M-bit data signal fusa_data of FIG. 3, which corresponds to the data signal "data" of FIG. 2. <m-1:0>After a period of time (e.g., a predetermined duration) depending on the type / structure of the ADC 137, at time t3, the control signal fusa_data_ready (corresponding to the control signal “compare enable” in FIG. 2) rises from low to high, and the ADC output signal fusa_data <m-1:0>is valid and ready to be used for comparison, and digital comparator 139 begins processing the ADC output signal. At time t4, the output signal pass / fail of digital comparator 139 (corresponding to the "Result" signal in FIG. 2) is ready. Then, at time t5, the control signal fusa_start falls from high to low, signaling the end of monitoring of the currently selected analog signal. The falling edge of the control signal fusa_start causes the control signal fusa_en to fall from high to low, signaling the end of monitoring of the ADC output signal fusa_data <m-1:0>and the output signal fusa_data_ready is reset. The analog signal monitoring circuit 130 is now ready to process the next selected analog signal.

[0031] In some embodiments, the memory device 100 of FIG. 1 is implemented as an integrated circuit (IC) formed on a semiconductor substrate (e.g., silicon) using semiconductor fabrication techniques. An IC device may also be referred to as a semiconductor die or semiconductor chip. In some embodiments, portions of the memory device 100, such as the memory array 101 and the power management circuitry 120, are integrated into the IC device, and the controller 103 is not integrated into the IC device, thereby allowing user selection of a different controller 103 within the semiconductor device 100. Different levels of integration for the IC device are possible and are fully intended to be within the scope of this disclosure.

[0032] 4 illustrates a flow chart of a method 1000 for monitoring an analog signal, according to one embodiment. At block 1010, voltage monitoring begins. At block 1020, during factory testing of memory device 100, an internal reference voltage provided by internal voltage reference 135 is measured and converted to a digital value A, e.g., by ADC 137. sort and the external reference voltage is also measured and converted to a digital value, e.g., K sort In block 1030, the measurement result obtained in block 1020 (e.g., digital value A sort and K. sort ) is a pre-stored digital value (e.g., the first pre-stored digital value A of the internal reference voltage sort and a second pre-stored digital value of the external reference voltage, K sort ) in memory device 100 (e.g., in a register of digital comparator 139). These pre-stored digital values ​​are used in calculating the calibrated measurement results in later processing.

[0033] It should be noted that in some embodiments, the processing of blocks 1020 and 1030 may be performed only once during factory testing (sometimes referred to as a sorting process) of memory device 100. Here, factory testing refers to a device testing / qualification process (e.g., quality control process) performed at a factory where memory device 100 is manufactured before memory device 100 is shipped and deployed in the field (e.g., used in an electronic device that includes memory device 100). During the processing of block 1020, an external reference voltage is generated by a high-precision external voltage reference (e.g., a laboratory test instrument used during factory testing that provides a known, calibrated, high-precision reference voltage). The external reference voltage, which has a higher accuracy (e.g., does not deviate much from its nominal value) than the internal reference voltage, is applied to input terminal 117 (see FIG. 1) of memory device 100 and transmitted as an external reference signal to MUX 132 (see label "External Reference" in FIG. 2). MUX132 selects the external reference signal under factory test as the output signal to ADC137, which converts the external reference voltage into a digital value, K sort Convert to.

[0034] In some embodiments, the digital value K sort is used to calculate the actual internal reference voltage provided by internal voltage reference 135. As a non-limiting example, consider a scenario in which internal voltage reference 135 is designed to generate an internal reference voltage having a nominal value of, for example, 1.25 V. However, due to manufacturing limitations and other non-ideal conditions, the actual internal reference voltage V provided by internal voltage reference 135 may be greater than 1.25 V. INT The actual internal reference voltage V INT To find an estimate of V, we use an external reference voltage provided during factory testing: EXT The actual internal reference voltage V INT teeth,

number

[0035] The processing of blocks 1040-1090 is performed after the memory device 100 is deployed in the field, for example, when an electronic device including the memory device 100 is monitoring an analog signal during operation. In block 1040, one of the analog signals at the input of MUX 132 is selected and sent to ADC 137 for measurement. In block 1050, the selected analog signal from MUX 132 (e.g., a power supply voltage provided by the voltage supply circuit 121) is converted to a digital value B by ADC 137 after being scaled by the scaling circuit 134, and the internal reference voltage provided by the internal voltage reference 135 is converted to a digital value A by ADC 137. It should be noted here that the internal reference voltage is measured again to compensate for various factors, such as component aging, temperature-induced drift, etc., that may cause the internal reference voltage to drift over time. Details will be described in the processing of block 1060.

[0036] Next, in block 1060, a transformation function f(A,B,A sort ,K sort ) a digital value A of an internal reference voltage, a digital value B of a selected analog signal (e.g., a scaled selected power supply voltage), a first pre-stored digital value A of the internal reference voltage, sort and a second pre-stored digital value of the external reference voltage, K sort A calibrated measurement is calculated using:

[0037] The digital values ​​A and B measured during operation of memory device 100 may contain uncontrolled / unpredictable errors caused by factors such as component aging, temperature induced measurement drift, etc. In addition, the internal voltage reference may not be perfect (e.g., the internal reference voltage is not exactly at the nominal value of 1.25V), and the internal reference voltage may or may not drift over time. To eliminate or reduce the uncontrolled / unpredictable errors, the digital values ​​A and B are converted to a conversion function f(A,B,A sort ,K sort ) the first pre-stored digital value A sort and a second pre-stored digital value K sort It is used together with the transformation function f(A,B,A sort ,K sort An example of this is given in equation (4) below.

[0038] In some embodiments, the first pre-stored digital value A sort and a second pre-stored digital value K sort is used to reduce errors in the digital values ​​A and B, or other related values ​​(e.g., calibrated measurements). As an example, given the digital value A of the internal reference voltage (which may or may not drift over time) measured when the nth analog signal is selected by MUX 132, the calibrated value V of the internal reference voltage is INT (n) is

number

[0039] Similarly, the calibration value V of a selected analog signal (e.g., a selected supply voltage) B teeth,

number

[0040] As previously mentioned, the calibrated measurement corresponds to a metric that indicates a value (e.g., a voltage value) of a selected analog signal, such as, by way of example, a difference or ratio between the value of the selected analog signal and the value of an internal reference voltage. Depending on, for example, the structure / implementation of various circuits within IC device 100, different ways of calculating the calibrated measurement are possible, as will be readily appreciated by those skilled in the art. As a non-limiting example, a calibrated measurement expressed as CMR is:

number

[0041] Next, in block 1070, the calibrated measurement result CMR calculated in block 1060 is compared to an expected range to determine whether the signal level (e.g., voltage value) of the selected analog signal is within the expected range. The expected range of the selected analog signal may be stored as a target value in a register 105 of the controller 103 and transmitted by the controller 103 to the analog signal monitoring circuit 130. For example, a digital comparator 139 may compare the calibrated measurement result CMR with the expected range and determine whether the calibrated measurement result CMR is within the expected range (Range low <= CMR <= Range high ), the digital comparator 139 declares a "pass" state of the selected analog signal, otherwise the digital comparator 139 declares a "fail" state of the selected analog signal, and low and Range high are the lower and upper limits of the expected range. In other words, the digital comparator 139 sets an error flag to "1" if the calibrated measurement result is outside the expected range.

[0042] A "pass" or "fail" result is then reported to controller 103 by digital comparator 139, e.g., via control signal / data path 116, at block 1080. In some embodiments, controller 103 initiates an error recovery action in response to receiving the error flag, e.g., by repeating the last memory access operation, monitoring the analog signal to ensure that the analog signal level is within a target range, or by resetting memory device 100 or resetting power management circuit 120.

[0043] Next, in block 1090, controller 103 checks whether all analog signals at the input of MUX 132 have been examined (e.g., monitored). If not, processing returns to block 1040, where controller 103 selects the next analog signal at the input of MUX 132 as the analog signal selected for examination. Processing continues until all analog signals at the input of MUX 132 have been examined. Then, in block 1010, monitoring is stopped. Processing between blocks 1040 and 1090 may begin again when controller 103 instructs power management circuit 120 to do so.

[0044] The analog signal monitoring disclosed herein reduces or prevents data errors in low level processing of an electronic device, for example, during memory access operations. This advantageously provides early detection of data errors, reduces or prevents catastrophic data errors (e.g., long sequences of data errors during memory access), and enables early error recovery operations to improve system performance and reduce latency. Data stored in a memory array is generally protected by an error correction code (ECC). ECC provides some degree of protection against data errors. For example, ECC may be designed to detect / correct a certain number of bit errors for a particular data size. However, when a burst error (e.g., long sequence of bit errors) occurs where the analog signal (e.g., power supply voltage) used for memory access is likely outside of a specified range, ECC is unable to detect or correct the error. In fact, without the disclosed analog signal monitoring, an electronic device may think that a memory access operation has completed successfully, when in fact the analog signal used for memory access is outside of a specified range, causing a long sequence of errors in the data being read or written. If data having a long sequence of errors is used by an application running on an electronic device, serious performance degradation or system failure may occur. For example, even if a data error is detected at a high level of processing, such as in an application running on an electronic device, data recovery operations (e.g., rewrite, reread, or retransmit) initiated by the application may cause longer processing delays, higher computational complexity, or higher power consumption. In contrast, the disclosed analog signal monitoring enables early detection of data errors and early error recovery operations by monitoring analog signals at the memory access level, thereby reducing the processing delays, computational complexity, and power consumption of the electronic device.

[0045] The circuits and methods for analog signal monitoring disclosed herein may be performed at different stages of operation of the memory device 100. For example, analog signal monitoring may be performed during a dedicated calibration process or during a test mode when no memory access operations are being performed. As another example, analog signal monitoring may be performed periodically at a lower frequency, such as every 10 ms, every 100 ms, etc., to periodically check the signal level of the analog signal. As another example, analog signal monitoring may be performed when the controller 103 issues a command instructing the power management circuit 120 to perform analog signal monitoring. As yet another example, analog signal monitoring may be performed as a built-in operation that is automatically performed in parallel with, for example, all memory access operations. These and other variations are fully intended to be within the scope of the present disclosure.

[0046] 5 illustrates a flow chart of a method 2000 of operating a memory device in some embodiments. It should be understood that the exemplary method illustrated in FIG. 5 is merely an example of many possible exemplary methods. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, various steps illustrated in FIG. 5 may be added, removed, substituted, rearranged, or repeated.

[0047] 5, in block 2010, one or more power supply voltages are provided to a memory array. In block 2020, the one or more power supply voltages are monitored, where the monitoring includes selecting a selected power supply voltage from the one or more power supply voltages, converting an internal reference voltage of the memory device and a scaled version of the selected power supply voltage to one or more digital values ​​using an analog-to-digital converter (ADC), generating a calibrated measurement result using the one or more digital values, and determining whether the calibrated measurement result is within a predetermined range.

[0048] The embodiments can achieve advantages as described below. In the disclosed embodiments, an analog signal used in a memory access operation is checked (e.g., monitored) to determine whether the signal level of the analog signal is within a specified range. If the analog signal is outside the specified range, a corresponding error flag is set. A memory device incorporating an analog signal monitoring function can detect data errors early in the processing chain and reduce or prevent data errors by initiating an error recovery operation early if necessary, thereby reducing processing delays, processing complexity, and power consumption of the memory device. In addition, the disclosed method generates calibrated measurement results using pre-stored values ​​of the external and internal reference voltages stored during factory testing, thereby improving the accuracy of the measurement and achieving better analog signal monitoring results.

[0049] Examples of the present invention are summarized here. Other examples can be seen throughout the specification and claims appended hereto.

[0050] Example 1. In one embodiment, a memory device comprises a memory array comprising memory cells, and a power management circuit for the memory array, the power management circuit comprising: a voltage source configured to provide one or more power supply voltages to the memory array, an internal voltage reference configured to provide an internal reference voltage, a multiplexer configured to receive the one or more power supply voltages and configured to output a selected power supply voltage selected from the one or more power supply voltages, an analog-to-digital converter (ADC) configured to convert scaled versions of the internal reference voltage and the selected power supply voltage to one or more digital values, and a digital comparator. The digital comparator is configured to generate a calibrated measurement result using the one or more digital values, a first stored digital value of the internal reference voltage and a second stored digital value of the external reference voltage, compare the calibrated measurement result with a predetermined range, and set an error flag indicating a fault condition of the memory device in response to detecting that the calibrated measurement result is outside the predetermined range.

[0051] Example 2. The memory device of Example 1, wherein the first stored digital value and the second stored digital value are ADC outputs for an internal reference voltage and an external reference voltage, respectively, that were generated during factory testing of the memory device and stored in the memory device before the memory device was deployed in the field.

[0052] Example 3. The memory device of example 2, wherein the external reference voltage has a higher accuracy than the internal reference voltage.

[0053] Example 4. The memory device of example 2, wherein the power management circuitry comprises an input terminal configured to receive an external reference voltage during factory testing of the memory device.

[0054] Example 5. The memory device of example 4, wherein the internal voltage reference is a bandgap voltage reference.

[0055] Example 6. The memory device of Example 1, further comprising a controller, the controller configured to send the predetermined range to the power management circuitry and receive the error flag from the power management circuitry.

[0056] Example 7. The memory device of example 6, wherein the controller is further configured to instruct the memory device to repeat a previous memory access operation of the memory array in response to receiving the error flag.

[0057] Example 8. The memory device of example 6, wherein the controller is further configured to reset the power management circuitry in response to receiving the error flag.

[0058] Example 9. The memory device of Example 6, further comprising an input / output (I / O) driver circuit coupled to the controller, and an I / O pad coupled to the I / O driver circuit for communication between the controller and an external device.

[0059] Example 10. The memory device of Example 1, wherein the power management circuitry further comprises a scaling circuit coupled between the multiplexer and the ADC and configured to scale the selected power supply voltage by a scaling factor.

[0060] Example 11. In one embodiment, an integrated circuit (IC) device includes a memory array including memory cells, a controller coupled to the memory array, and a power management circuit coupled to the memory array and the controller, the power management circuit including a voltage supply circuit configured to provide a power supply voltage to the memory array, a multiplexer coupled to the voltage supply circuit and configured to output a selected power supply voltage selected from the power supply voltage, an internal voltage reference configured to provide an internal reference voltage, an analog-to-digital converter (ADC) configured to convert a scaled version of the internal reference voltage and the selected power supply voltage into an ADC output, and a digital comparator. The digital comparator is configured to generate a calibrated measurement using the ADC output, a first pre-stored digital value of the internal reference voltage, and a second pre-stored digital value of the external reference voltage, determine whether the calibrated measurement is within a predetermined range, and set an error flag indicating a fault condition of the IC device in response to determining that the calibrated measurement is outside the predetermined range.

[0061] Example 12. The IC device of example 11, wherein the power management circuit is configured to send an error flag to the controller.

[0062] Example 13. The IC device of example 12, wherein the controller is configured to initiate an error recovery action for the IC device in response to the error flag.

[0063] Example 14. The IC device of example 13, wherein initiating the error recovery operation includes resetting the power management circuitry or repeating a previous memory access operation of the memory array.

[0064] Example 15. A digital comparator is used to convert the transformation function f(A,B,A sort ,K sort ), where A is a first ADC output for an internal reference voltage, B is a second ADC output for a scaled version of a selected power supply voltage, and A sort is the first prestored digital value of the internal reference voltage, and K sort is a second pre-stored digital value of the external reference voltage, the external reference voltage having a higher accuracy than the internal reference voltage.

[0065] Example 16. The IC device of Example 15, wherein the first pre-stored digital value and the second pre-stored digital value are ADC outputs for an internal reference voltage and an external reference voltage, respectively, that were generated during factory testing of the IC device and stored in the IC device before the IC device was deployed in the field.

[0066] Example 17. In one embodiment, a method of operating a memory device includes supplying one or more power supply voltages to a memory array and monitoring the one or more power supply voltages, the monitoring including selecting a selected power supply voltage from the one or more power supply voltages, converting an internal reference voltage of the memory device and a scaled version of the selected power supply voltage to one or more digital values ​​using an analog-to-digital converter (ADC), generating a calibrated measurement result using the one or more digital values, and determining whether the calibrated measurement result is within a predetermined range.

[0067] Example 18. The method of example 17, further comprising setting an error flag indicative of a fault condition of the memory device in response to determining that the calibrated measurement is outside of a predetermined range.

[0068] Example 19. The method of example 18, further comprising initiating a recovery operation in response to the error flag being set, where initiating the recovery operation comprises repeating a previous memory access operation of the memory array or resetting power management circuitry of the memory device.

[0069] Example 20. Producing a calibrated measurement result is a transformation function f(A,B,A sort ,K sort ), where A is a first digital value of the internal reference voltage converted by the ADC, and B is a second digital value of the scaled version of the selected power supply voltage converted by the ADC, and A sort is the first prestored digital value of the internal reference voltage, and K sort is a second pre-stored digital value of the external reference voltage, the external reference voltage having a higher accuracy than the internal reference voltage.

[0070] Example 21. The method of example 20, wherein the first pre-stored digital value and the second pre-stored digital value are ADC outputs for an internal reference voltage and an external reference voltage, respectively, that were generated during factory testing of the memory device and stored in the memory device before the memory device was deployed in the field.

[0071] While the present invention has been described with reference to illustrative examples, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative examples, as well as other examples of the present invention, will be apparent to those skilled in the art upon reference to the description. It is therefore intended that the appended claims cover any such modifications or examples. < / n>

Claims

1. a memory array comprising memory cells; a power management circuit for the memory array; A memory device comprising: The power management circuit includes: a voltage source configured to provide one or more power supply voltages to the memory array; an internal voltage reference configured to provide an internal reference voltage; a multiplexer configured to receive the one or more power supply voltages and configured to output a selected power supply voltage selected from the one or more power supply voltages; an analog-to-digital converter (ADC) configured to convert a scaled version of the internal reference voltage and the selected power supply voltage into one or more digital values; A digital comparator; Equipped with The digital comparator is generating a calibrated measurement result using the one or more digital values, the first stored digital value of the internal reference voltage, and the second stored digital value of an external reference voltage; Comparing the calibrated measurement result with a predetermined range; configured to set an error flag indicative of a fault condition of the memory device in response to detecting the calibrated measurement result being outside the predetermined range. Memory device.

2. the first stored digital value and the second stored digital value are ADC outputs for the internal reference voltage and the external reference voltage, respectively, the ADC outputs being generated during factory testing of the memory device and stored in the memory device before the memory device is deployed in the field; The memory device of claim 1 .

3. The external reference voltage has a higher accuracy than the internal reference voltage. The memory device of claim 2 .

4. the power management circuit comprises an input terminal configured to receive the external reference voltage during the factory testing of the memory device. The memory device of claim 2 .

5. the internal voltage reference is a bandgap voltage reference; The memory device of claim 4.

6. The memory device further comprises a controller, the controller comprising: transmitting the predetermined range to the power management circuit; configured to receive the error flag from the power management circuit; The memory device of claim 1 .

7. The controller: and further configured, in response to receiving the error flag, to instruct the memory device to repeat a previous memory access operation of the memory array. The memory device of claim 6.

8. The controller: further configured to reset the power management circuit in response to receiving the error flag. The memory device of claim 6.

9. The memory device comprises: an input / output (I / O) driver circuit coupled to the controller; an I / O pad coupled to the I / O driver circuit for communication between the controller and an external device; Further comprising: The memory device of claim 6.

10. the power management circuit further comprising a scaling circuit coupled between the multiplexer and the ADC, the scaling circuit configured to scale the selected power supply voltage by a scaling factor. The memory device of claim 1 .

11. a memory array comprising memory cells; a controller coupled to the memory array; a power management circuit coupled to the memory array and to the controller; 1. An integrated circuit (IC) device comprising: The power management circuit includes: a voltage supply circuit configured to provide a power supply voltage to the memory array; a multiplexer coupled to the voltage supply circuit and configured to output a selected power supply voltage selected from the power supply voltages; an internal voltage reference circuit configured to provide an internal reference voltage; an analog-to-digital converter (ADC) configured to convert a scaled version of the internal reference voltage and the selected power supply voltage into an ADC output; A digital comparator; Equipped with The digital comparator is generating a calibrated measurement result using the ADC output, a first pre-stored digital value of the internal reference voltage, and a second pre-stored digital value of an external reference voltage; determining whether the calibrated measurement is within a predetermined range; configured to set an error flag indicative of a fault condition of the IC device in response to determining that the calibrated measurement is outside the predetermined range. IC device.

12. the power management circuitry is configured to transmit the error flag to the controller; The IC device of claim 11.

13. the controller is configured to initiate an error recovery action for the IC device in response to the error flag. The IC device of claim 12.

14. Initiating the error recovery operation includes resetting the power management circuitry or repeating a previous memory access operation of the memory array. The IC device of claim 13.

15. The digital comparator has a conversion function f(A, B, A ｓｏｒｔ , K ｓｏｒｔ ) to generate the calibrated measurement result; A is a first ADC output for the internal reference voltage; B is a second ADC output for the scaled version of the selected power supply voltage; A ｓｏｒｔ is the first pre-stored digital value of the internal reference voltage; K ｓｏｒｔ is the second pre-stored digital value of the external reference voltage; The external reference voltage has a higher accuracy than the internal reference voltage. The IC device of claim 11.

16. the first pre-stored digital value and the second pre-stored digital value are ADC outputs for the internal reference voltage and the external reference voltage, respectively, the ADC outputs being generated during factory testing of the IC device and stored in the IC device before the IC device is deployed in the field; 16. The IC device of claim 15.

17. 1. A method of operating a memory device, the method comprising: providing one or more power supply voltages to the memory array; monitoring the one or more power supply voltages; Including, The monitoring steps are: selecting a selected power supply voltage from the one or more power supply voltages; converting, using an analog-to-digital converter (ADC), a scaled version of the internal reference voltage of the memory device and the selected power supply voltage into one or more digital values; generating a calibrated measurement using the one or more digital values; determining whether the calibrated measurement is within a predetermined range; The method includes:

18. The method comprises: and in response to determining that the calibrated measurement is outside the predetermined range, setting an error flag indicating a fault condition of the memory device.

20. The method of claim 17.

19. The method further includes initiating a recovery action in response to the error flag being set; Initiating the recovery operation includes repeating a previous memory access operation of the memory array or resetting power management circuitry of the memory device.

20. The method of claim 18.

20. The step of generating a calibrated measurement result comprises: Transformation function f(A, B, A ｓｏｒｔ , K ｓｏｒｔ ) to generate the calibrated measurement result; A is a first digital value of the internal reference voltage converted by the ADC; B is a second digital value of the scaled version of the selected power supply voltage converted by the ADC; A ｓｏｒｔ is a first pre-stored digital value of the internal reference voltage; K ｓｏｒｔ is a second pre-stored digital value of the external reference voltage; The external reference voltage has a higher accuracy than the internal reference voltage.

20. The method of claim 17.

21. the first pre-stored digital value and the second pre-stored digital value are ADC outputs for the internal reference voltage and the external reference voltage, respectively, the ADC outputs being generated during factory testing of the memory device and stored in the memory device before the memory device is deployed in the field; 21. The method of claim 20.

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