Screening Edge Placement Uniformity Wafer Probability

Abstract

A simulated tool signal is determined from design data and tool characteristics of the tool performing the measurements. A design-aided composite signal is determined from the measurements. An edge placement uniformity signal is then determined by comparing the simulated tool signal and the design-aided composite signal. The edge placement uniformity signal can be analyzed in shape and / or area. The edge placement uniformity signal allows screening of structures with respect to wafer stochasticity without having to fully characterize every individual structure.

Description

[Technical field]

[0001] REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 328,017, filed and assigned on April 6, 2022, the disclosure of which is incorporated herein by reference. The present disclosure relates to semiconductor metrology. [Background technology]

[0002] The revolution in semiconductor manufacturing is placing greater demands on yield management, especially on metrology and inspection systems. As critical dimensions continue to shrink, the die industry must decrease the time to achieve high-yield, high-value production. Minimizing the total time from detecting a yield problem to fixing it maximizes the return on investment for semiconductor manufacturers.

[0003] Fabricating semiconductor devices, such as logic and memory devices, typically involves processing a semiconductor wafer using multiple manufacturing processes to form the various features and levels of the semiconductor device. For example, lithography is a semiconductor manufacturing process that involves transferring a pattern from a reticle to a photoresist arranged on a semiconductor wafer. Further examples of semiconductor manufacturing processes include, but are not limited to, chemical mechanical polishing (CMP), etching, deposition, and ion implantation. An array of multiple semiconductor devices fabricated on a single semiconductor wafer can be separated into individual semiconductor devices.

[0004] Metrology processes are used at various steps during semiconductor manufacturing to monitor and control the process. Metrology processes differ from inspection processes in that defects are detected on the wafer and metrology processes are used to measure one or more characteristics of the wafer that cannot be determined using existing inspection tools. Metrology processes can be used to measure one or more characteristics of the wafer such that the performance of the process can be determined from the one or more characteristics. For example, metrology processes can measure dimensions (e.g., line width, thickness, etc.) of features formed on the wafer during the process. Furthermore, if one or more characteristics of the wafer are unacceptable (e.g., outside a predetermined range of characteristics), the measurements of one or more characteristics of the wafer can be used to modify one or more parameters of the process such that additional wafers produced by the process have acceptable characteristics.

[0005] Metrology tools are designed to perform many different types of measurements for semiconductor manufacturing, such as measuring the characteristics of one or more targets. These characteristics can include, for example, critical dimension (CD), overlay, sidewall angle, film thickness, line edge roughness (LER), line width roughness (LWR), pattern placement error, or process related parameters (e.g., focus and / or dose). Targets can include specific regions of interest that are periodic in nature, such as gratings in a memory die. Metrology targets can have various spatial characteristics and are typically composed of one or more cells that can include features in one or more layers printed in one or more lithographically separate exposures. Targets or cells can have various symmetries, such as two- or four-fold rotational symmetry and / or reflection symmetry. Different cells or combinations of cells can belong to separate layers or exposure steps. Individual cells may include isolated non-periodic features or may be built from one-, two-, or three-dimensional periodic structures or combinations of non-periodic and periodic structures. The periodic structures may be non-segmented, or they may be constructed from finely segmented features that may be at or near the minimum design rules of the lithography process used to print them. Metrology targets may also be aligned with or adjacent to dummification structures in the same layer or layers above, below, or between layers of metrology structures. Targets may include multiple layers (or films) whose thicknesses may be measured by a metrology tool. Targets may include target designs that are placed (or already present) on a semiconductor wafer for use (e.g., using alignment and / or overlay alignment operations). Some targets may be placed at various locations on a semiconductor wafer. For example, targets may be placed in scribe lines (e.g., between dies) and / or on the dies themselves. In some embodiments, multiple targets are measured with the same or multiple metrology tools, either simultaneously or at different times. Data from such measurements may be combined.Data from metrology tools are used in semiconductor manufacturing processes for feed-forward, feedback, and / or feed-sideway corrections to the process (eg, lithography, etch) resulting in a complete process control solution.

[0006] Photolithography can have defects driven by the quantized nature of light and materials. For example, light is quantized into photons, and the chemical reactants in photoresist are discrete molecules. These are often referred to as shot noise defects or stochastic defects. These stochastic defects may be prevalent in extreme ultraviolet (EUV) lithography, but may appear at exposure wavelengths used in other lithography processes, such as ArF immersion. By "stochastic," we mean that the average behavior may be within the desired specifications (e.g., photoresist width, tip-to-tip measurement of line ends, or photoresist thickness) while at the same time exhibiting variations that cause the pattern to fail with a nonzero probability (e.g., bridging or breaking of line / space patterns). Assuming a wafer contains billions of transistors, even a small failure probability can lead to substantial yield loss.

[0007] Stochastic defects can present multiple challenges in a manufacturing environment. Typically, defects can be assumed to be deterministic such that a known defect will always be present when manufactured according to a known manufacturing recipe that includes the pattern and exposure parameters of the elements to be manufactured on the specimen. For example, process window qualification (PWQ) typically identifies process-limiting defects that always occur when the exposure conditions are outside the process window. In one example, the process window can define a limit of defocus associated with the position of the specimen along the optical axis of the lithography tool (e.g., the focal position of the specimen, or the dose of energy from an illumination source incident on the specimen during exposure).

[0008] Previously, features on semiconductor wafers were measured individually. For example, scanning electron microscopes (SEM) or critical dimension SEMs (CDSEM) were used for high-resolution imaging of individual patterns on the wafer. Each pattern was evaluated and fully characterized separately, which resulted in low sampling or low throughput. Low sampling limits the information about the wafer probability. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] International Publication No. 2021 / 016407 [Patent Document 2] US Patent Application Publication No. 2020 / 0082523 Summary of the Invention [Problem to be solved by the invention]

[0010] Improved systems and techniques are needed. [Means for solving the problem]

[0011] In a first embodiment, a method is provided. The method includes using a processor to determine a design-aided composite signal from a plurality of features on the wafer using measurements of the wafer from a wafer metrology tool and a design of the wafer. Using the processor, a simulated tool signal is determined for the design of the wafer, accounting for noise sources and imaging characteristics of the wafer metrology tool. Using the processor, an edge placement uniformity signal is determined that is the difference between the design-aided composite signal and the simulated tool signal.

[0012] The wafer metrology tool may be a scanning electron microscope.

[0013] The measurements of the wafer can be generated during overlay metrology of the wafer.

[0014] The method can further include analyzing a shape and / or area of ​​the edge placement uniformity signal. The shape and area arise at least probabilistically. A distribution of edge placement errors can be determined based on the shape. The method further includes inspecting the wafer at locations with edge placement errors.

[0015] The measurements may be of a plurality of lines of a device on the wafer, each of the plurality of lines may have one of the edge placement uniformity signals.

[0016] The method may further include comparing, using a processor, the edge placement uniformity signal to a specification for the wafer.

[0017] The design aid composite signal may be an average of the measurements.

[0018] The feature may be the edge of a structure on the wafer or the center of a structure on the wafer.

[0019] A computer readable medium storing a program may be configured to instruct a processor to perform the method of the first embodiment.

[0020] In a second embodiment, a system is provided that includes a particle beam source generating an electron beam, a stage configured to hold a wafer in a path of the particle beam, a detector to receive particles from the wafer, and a processor in electronic communication with the detector, the processor determines a design-aided composite signal from a plurality of features on the wafer using measurements of the wafer and a design of the wafer, determines a simulated tool signal for the design of the wafer that accounts for noise sources and imaging characteristics of a wafer metrology tool, and determines an edge placement uniformity signal that is the difference between the design-aided composite signal and the simulated tool signal.

[0021] The particle beam can be an electron beam, a photon beam, an ion beam, or a neutral particle beam. In one example, the system is a scanning electron microscope.

[0022] The processor may be further configured to analyze a shape and / or area of ​​the edge placement uniformity signal, the shape and area being caused by at least a probability theory. The processor may be further configured to determine a distribution of edge placement errors based on the shape. The processor may also be configured to transmit instructions to inspect the wafer at locations having edge placement errors using the particle beam.

[0023] The processor may be further configured to compare the edge placement uniformity signal to a specification for the wafer. [Brief description of the drawings]

[0024] For a more complete understanding of the nature and objects of the present disclosure, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, in which: [Figure 1] FIG. 2 is an exemplary diagram illustrating the combination of multiple edge signals to generate a design-support synthesis signal. [Diagram 2] 1 is an example of image-based averaging. [Diagram 3] 13 is an example of generation of design-aided synthetic data for a repeating instance of a line structure. [Figure 4] 1 is an example of simulated tool signals generated from design intent. [Diagram 5] 13 is a comparison of edge placement uniformity signals with design-aided synthetic signals and simulated tool signals. [Figure 6] 1 is a flow chart of one embodiment of a method according to the present disclosure. [Figure 7] FIG. 1 is a block diagram of an exemplary system according to the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Although the claimed subject matter is described with respect to certain embodiments, other embodiments, including embodiments that do not provide all of the benefits and features described herein, are also within the scope of this disclosure. Various structural, logical, process step, and electronic changes may be made without departing from the scope of the disclosure. Accordingly, the scope of the disclosure is defined solely by reference to the appended claims.

[0026] The embodiments disclosed herein compare the design aided synthetic signal with the simulated tool signal. The difference between both signals can be used to characterize the wafer probability of the measured feature, called Edge Placement Uniformity (EPU). This can be used for fast screening of wafer probability while performing other measurements such as overlay metrology. Depending on the EPU, various actions for process control can be taken.

[0027] Scanning metrology tools are particularly suitable for generating high-resolution measurements of a specimen (e.g., a wafer). For example, the resolution of a scanning metrology tool may be based on the spot size of the illumination spot, which may be tightly controlled. However, scanning metrology may suffer from various limitations, such as low measurement throughput (e.g., long measurement times) and / or damage to the specimen during measurement induced by the illumination beam.

[0028] When using some types of metrology measurements, it can be beneficial to mitigate various sources of stochastic noise associated with the manufacturing process, such as LER or LWR. Common examples include, but are not limited to, dimensional measurements (e.g., CD measurements), pattern placement (e.g., registration) measurements, or overlay measurements (e.g., relative positions of features manufactured using different exposures). Techniques for mitigating such stochastic noise typically involve generating high-resolution images of the fabricated structures on the sample and then averaging measurements at different locations on the structure. However, such image-based techniques may similarly suffer from low measurement throughput and / or sample damage during the measurement. As a result, users typically either generate measurements of a small number of structures to provide a reasonable throughput, or generate measurements of a desired number of structures at a low throughput. In all cases, users must further take steps to limit energy deposition on the sample during the measurement (e.g., exposure dose related to incident energy per area on the sample), which may adversely affect measurement sensitivity or sacrifice some samples during the measurement.

[0029] The embodiments disclosed herein use detection signals associated with multiple instances of a fabricated structure that are combined into a single data set, referred to herein as design-aided synthetic data. For example, a metrology system may scan an illumination beam in a scan pattern that contacts common features on multiple instances of a fabricated structure (e.g., common locations on the multiple instances). By way of example, common features of a line structure may include, but are not limited to, a left edge, a center portion, and a right edge. As a result, the scan pattern may traverse the same location or multiple locations on various instances of the structure such that repeated measurements of the structure are generated. Design data related to the intended location and / or orientation of the instances of the structure across the specimen can then be used to correlate and combine the detection data of the common features from the multiple instances of the structure. The design-aided synthetic data may then include any statistical combination of data from various instances of the structure, such as, but not limited to, averages, medians, etc. This design-aided synthetic data can then be used to generate various metrology measurements of the structure.

[0030] The use of design-aided synthetic data provides flexibility in selecting scan patterns, which may overcome many of the limitations of typical scan-based metrology techniques, such as image-based averaging. For example, metrology using design-aided synthetic data does not require the formation of an image of any particular instance of the structure of interest. Rather, a low-noise signal is generated by combining data from measurements of multiple instances of the structure. In this manner, metrology using design-aided synthetic data may be analogized to a phase-locked loop measurement that utilizes signal periodicity to provide sensitive measurements. This analogy is merely exemplary and not limiting. For example, metrology using design-aided synthetic data does not require any type of periodic signal, but rather utilizes design information to correlate data related to common features of the structure to provide sensitive, low-noise measurements.

[0031] Metrology based on design-aided synthetic data as disclosed herein can provide multiple benefits. For example, design-aided synthetic data from many instances of a structure of interest across a sample may generally provide substantially more sample points for averaging (or other statistical combinations) than is possible with conventional imaging techniques, resulting in high signal-to-noise ratios and more sensitive measurements. For example, while conventional image-based averaging may be limited by the averaging direction and / or the length of the structure of interest across the imaging field of view (FOV), design-aided synthetic data may be formed from any number of instances of the structure. As another example, a scan pattern may generally include any number of traces of any design, since an image of any particular structure is not required. In another example, a scan pattern may be selected to limit or avoid damage to the sample during measurement. Expanding the FOV can reduce the exposure dose for a given measurement by spreading the deposited energy over a larger area. In some embodiments, the scan pattern includes a sparse set of traces across a relatively large FOV, which may beneficially contact many instances of the structure of interest and also limit or avoid damage to the sample. For example, the set of sparse traces may be spaced substantially further apart than would be needed for a typical high resolution image of any particular structure.

[0032] Metrology using design-aided synthetic data as disclosed herein may be implemented with any type of scanning metrology system known in the art, including particle-based scanning systems (e.g., electron, ion, or neutral particles) or optical scanning systems. Thus, the systems and methods disclosed herein may be implemented using particle beams, light beams, or any combination thereof.

[0033] 6 illustrates a method 200. Some or all of the steps of the method 200 may be performed using a processor.

[0034] At 201, a design-aided composite signal is determined from a plurality of edges of features on a wafer. This can use measurements of the wafer from a wafer metrology tool (e.g., SEM) and the design of the wafer. The measurements can be of repeating features across the surface of the wafer, such as edges of structures on the wafer or centers of structures on the wafer. For example, the measurements can be of lines of a device on the wafer. Each line has one of the edge placement signals.

[0035] The design-assisted composite signal may be generated using embodiments of U.S. Patent Application No. 17 / 524,152, entitled "Design-Assisted Large Field of View Metrology," which is incorporated herein in its entirety. Figures 1-3 show examples of generating the design-assisted composite signal. Measurements may be combined to form the design-assisted composite signal.

[0036] In some metrology applications, stochastic variations may be considered as noise that reduces the signal-to-noise ratio, measurement sensitivity, and / or measurement accuracy. Common, but non-limiting examples include measurements of the shape, orientation, or position of a manufactured structure, such as CD measurements, position (e.g., alignment) measurements, or overlay measurements.

[0037] Figure 1 shows the design aided composite signal, which is the average or other composite of the various single edge signals measured. These can be compared to the design intent, which is the desired structure on the wafer. The design intent is the expected measurement of the design. Tool inaccuracies and noise can blur the single edge signal relative to the design intent. Differences between the design intent and the single edge signal can also be caused by structures being inaccurately positioned on the wafer, such as through LER or other stochasticity.

[0038] FIG. 2 is a conceptual diagram of an image-based averaging technique for metrology according to one embodiment of the present disclosure. In particular, FIG. 2 illustrates averaging multiple measurements at different locations of a line structure 102. A typical scanning metrology process may include using a dense array of linear traces 106 across the FOV to generate a high-resolution image 104 of a sample that includes at least one instance of a structure of interest (here, three instances of the line structure 102). In this manner, the multiple traces 106 generate data associated with a particular line structure 102 at different locations. For example, inset 108 illustrates a conceptual diagram of detection signals associated with five traces 106 at different locations along a line structure 102 (e.g., five rows in image 104) having a region of interest 110. In this inset 108, each pixel 112 represents a measurement along a trace 106, and the variation in the value of the pixel 112 along the traces 106 corresponds to stochastic noise.

[0039] The trace 106 represents the signal generated along the path of the beam, which in the case of imaging as in Figure 2 may be equivalent to a pixel line, which may be a row or a column depending on the scanning method.

[0040] In this typical image-based technique, stochastic noise can be mitigated by averaging the data along a direction orthogonal to the trace 106 (here vertical direction 114). Inset 116 shows a conceptual plot of such image average data 118. Image averaged data 118 can include the single edge signal of FIG. 1 and / or the design-aided synthetic signal of FIG. 1. Image-based averaging averages multiple pixel lines without using a design. Noise can be reduced somewhat. Tool noise reduction is comparable, but wafer stochasticity tends to be only on a local scale and not to the same extent as with full design-aided averaging.

[0041] The image-based averaging technique shown in FIG. 2 may be subject to various limitations. For example, the number of data points available for averaging is limited by the number of traces 106 on any particular instance of a structure of interest, which may in turn be limited by the size, shape, or geometry of the structure. Although FIG. 2 shows line structures filling the FOV of image 104, the structures of interest may generally have any shape, size, or orientation. As a result, the number of data points available for averaging may in practice be more limited. In another example, the number of traces 106 (and the number of data points available for averaging) may not be arbitrarily increased. Rather, the density of traces 106, and therefore the number of data points available for averaging, may be limited by the damage threshold of the sample or structures thereon. As an example, a photomask (e.g., photoresist) may have a relatively low damage threshold that may limit the effectiveness of image-based averaging techniques. In another example, the generation of such high-resolution images is typically time-consuming and may limit the size of the FOV and overall measurement throughput.

[0042] The existence of repeated instances of the structure of interest can be used to provide high throughput metrology with high sensitivity. In particular, data relating to common features (e.g., positions) of multiple instances of the structure of interest can be combined based on design data including the intended positions and / or orientations of the various instances of the structure across the sample. Such data can be referred to as design-aided synthetic data. In this way, the number of data points available for combination (e.g., by averaging or any other statistical combination) can be limited only by the number of instances of the structure of interest along the scan pattern. The diagram in FIG. 1 averages various single edge signals. Furthermore, it is not necessary to generate an image of any particular structure. A single trace across each instance of the structure may be sufficient in some applications. As a result, the FOV and exposure dose can be substantially reduced, which can enable the measurement of relatively high intensities without causing damage and / or provide the desired measurement throughput.

[0043] The design data associated with the intended location and / or orientation of the instance of the structure across the sample can then be used to correlate and combine the detection data of the common features from multiple instances of the structure. The design-aided synthetic data may then include any statistical combination of data from the various instances of the structure, such as, but not limited to, averages, medians, etc. This design-aided synthetic data can then be used to generate various metrology measurements of the structure.

[0044] The design of the various manufactured instances of the structure on the specimen can be used in determining the design-aided synthetic data. The specimen can include a semiconductor device at any stage of manufacturing that includes repeated instances of the various manufactured structures, a photomask (e.g., photoresist) that includes repeated instances of a photomask structure used in the manufacturing process, or any other material that includes repeated instances of one or more structures of interest.

[0045] Design data may include any type of data from any source that provides information about the intended design of structures of interest on a specimen, including, but not limited to, the location of the structures, the shape of the structures, or the orientation of the structures at each location. For example, design data may include schematics of the specimen used to guide the manufacture of various layers (e.g., graphic design system (GDS) data, etc.), metrology measurements of the specimen taken at the current or any previous process step, or a combination thereof.

[0046] In some embodiments, the illumination spot can be scanned along a scan pattern (e.g., using a scanning metrology tool, etc.) relative to the sample, where the scan pattern traverses at least one common feature on multiple fabricated instances of the structure on the sample. The scan pattern can include any type or design of trace suitable for intersecting at least one common feature of the instances of the structure to be measured. For example, the scan pattern can include one or more linear scan traces, which may be, but need not be, parallel. In another example, the scan pattern can include one or more curved scan traces.

[0047] The detected signals from the scanning metrology tool may be related to the scan pattern such that the detected signals generated by the scanning metrology tool along the scan pattern may be correlated to a position on the sample.

[0048] The design-aided synthetic data of the structure can be determined by combining detection signals from common features of the structure from fabricated instances of the structure using the design data. For example, the design data can be used to correlate detection signals of common features of the structure across multiple instances of the structure across the sample. The design-aided synthetic data may then include any statistical combination of detection signals from common features of the structure, such as average values. Common features across multiple instances of the structure may include any characteristic of the structure, such as an edge or center location.

[0049] To correlate the detected signals, the design data can be analyzed to find design-intended locations of identical / similar patterns (e.g., lines of the same width and similar perimeter). Only traces containing these locations can be used for signal processing. Traces can be optimized prior to measurement to maximize the amount of usable signal.

[0050] The design-aid synthetic data can be generated with or without generating a conventional high-resolution image of any particular instance of the structure of interest. Rather, the design-aid synthetic data can be constructed by measurements of common features on many different instances of the structure of interest.

[0051] 3 is an example of generation of design-aided synthetic data 152 for repeated instances of line structure 154, according to one or more embodiments of the present disclosure. Inset 150 shows five instances of line structure 154 and a portion of a scan pattern 158 (e.g., linear trace 160) across various instances of line structure 154.

[0052] Inset 162 is a schematic diagram of a detection signal generated by a scanning metrology tool along a portion of a scan pattern. For example, the detection signal includes a series of pixels 164 related to the sampling rate of the scanning metrology tool. The scanning metrology tool may include any type of scanning metrology tool known in the art that utilizes any type of scanning illumination beam, such as a particle beam (e.g., an electron beam, an ion beam, a neutral particle beam, etc.) or an optical beam of any wavelength.

[0053] Inset 166 is an example plot of design-aided synthetic data 152 generated using design data related to the design of the detection signal and line structure 154. For example, design-aided synthetic data 152 may be generated by correlating particular pixels 164 of the detection signal that relate to common features of line structure 154 using the design data.

[0054] As an example, pixels 164a-1, 164a-2, ..., 164a-5 may be associated with a left edge 168 of the line structure 154 (e.g., a first common feature), while pixels 164b-1, 164b-2...164b-5 may be associated with a right edge 170 of the line structure 154 (e.g., a second common feature). Similarly, pixels 164c-1, 164c-2, ..., 164c-5 may be associated with a central portion 172 of the line structure 154 (e.g., a third common feature). The correlated pixels 164 may then be combined into the design-aided synthetic data 152 using any statistical combination, such as, but not limited to, averaging of the correlated pixels 164. In this manner, various sources of stochastic noise, such as LER or LWR, may be mitigated or otherwise suppressed. The design-aided synthetic data 152 may then be used as the basis for any number or type of metrology measurements of the target line features 154. For example, the design-aided synthetic data 152 shown in inset 166 may be utilized for metrology measurements such as the location of a left edge 168, the location of a right edge 170, the width of the line features 154 (e.g., a CD measurement), or the lateral position along the direction of the linear trace.

[0055] As shown in FIG. 3, the design-aided synthetic data 152 may be generated without generating a conventional high-resolution image of any particular instance of the structure of interest (e.g., line structure 154 in FIG. 3). Rather, the design-aided synthetic data 152 may be constructed by measurements of common features on many different instances of the structure of interest. Metrology based on the design-aided synthetic data 152 as disclosed herein may beneficially provide high sensitivity and high throughput while also limiting damage to the sample 108 during the measurement process. In particular, the lack of a requirement to generate an image of the structure of interest allows substantial flexibility to tailor the scan pattern 158 for a particular application or sample design. For example, the scan pattern 158 may include one or more traces 160 of any length or curvature. As another example, the scan pattern 158 may include a sparse distribution of the traces 160. Additionally, the scan pattern 158 may be designed to limit the exposure dose to the sample 108. For example, the scan pattern 158 may be designed to limit the exposure dose to a level below the damage threshold of the sample 108 or any structure thereon.

[0056] Returning to FIG. 6, at 202, a simulated tool signal is determined from noise sources, imaging characteristics of the wafer metrology tool, and the design of the wafer. An example is shown in FIG. 4. A tool model can be applied to account for tool characteristics such as imaging characteristics, beam characteristics (e.g., beam jitter), and / or tool noise (e.g., shot noise or stage jitter). The simulated tool signal is the expected outcome of the design intent after accounting for the tool characteristics. Thus, the simulated tool signal may be an ideal measurement, taking into account relevant, e.g., stage vibrations on the tool.

[0057] An example of determining a simulated tool signal is disclosed in Villarubia et al., "3D Monte Carlo Modeling of the SEM: Are There Applications to Photomask Metrology" (2014), which is incorporated by reference in its entirety. The imaging model can be combined with models of other error sources, such as stage vibration. Thus, the combined model can use a tool sensor signal (e.g., from a stage interferometer). The simulated tool signal can be generated by combining imaging noise from the imaging model with other tool noise from the tool model.

[0058] In one example, the edges in the design file are infinitely sharp and binary. This can indicate the inside of the structure versus the outside of the structure. The model for determining the simulated tool signal can include amplitude and offset of the signal inside the structure and outside the structure. The model for determining the simulated tool signal can also include beam characteristics of the edge shape. These beam characteristics can be similar to a point spread function in optics.

[0059] As shown in FIG. 6, an EPU signal is determined at 203. The EPU signal is the difference between the design-aided synthetic signal and the simulated tool signal, and is shown in FIG. 5. For example, the EPU signal can be the total area of ​​the difference between the design-aided synthetic signal and the simulated tool signal. The detailed shape and / or area of ​​the EPU signal are mainly caused by wafer stochasticity. Thus, global information such as the distribution of edge placement errors can be determined from the EPU signal.

[0060] Ignoring additive variations (e.g., thickness, sidewall angle) and noise, the single-edge signals should have the same shape with different deviations (e.g., edge placement). Edge placement errors tend to be caused by stochastic effects (e.g., LER, LWR, CD uniformity, or pattern placement variations). The shape of the resulting measured signal contains information about the amplitude and the underlying distribution (e.g., Gaussian / normal, uniform distribution). This allows the convolution of the single-edge signal with a random distribution. Extraction of the single-edge signal and distribution can be done using various techniques such as blind deconvolution.

[0061] In addition to the area between the design-aided synthetic signal and the simulated tool signal, the EPU signal may also be determined based on local slope and / or slope difference, local curvature difference, or local asymmetry. Any of these other measurements may be combined with or without the area between the design-aided synthetic signal and the simulated tool signal to determine the EPU signal.

[0062] The EPU signal can be analyzed. The shape can be caused at least by stochasticity. The EPU signal can be used to extract edge noise (e.g., LER, LWR, CD uniformity), edge shape variation (e.g., sidewall angle, sidewall angle variation), or signal intensity variation (e.g., stack thickness variation). Analyzing the shape of the EPU signal can be used to determine the stochastic placement or degree. For example, the average placement (μ) can be determined by the relative shift between the simulated and measured signals. If the simulated tool signal takes into account the tool error, the EPU signal can be caused by issues with the wafer, such as stochasticity.

[0063] Analyzing the EPU signal can be used to evaluate what is simulated and what is not simulated in the EPU signal. An EPU signal that differs from the simulated tool signal can indicate the presence of a stochastic error or other error. A difference in shape or area between the simulated tool signal and the EPU signal can indicate the type of stochasticity. The shape can include the slope, curvature, asymmetry, or other aspects of the EPU signal boundary relative to the simulated tool signal boundary.

[0064] In an embodiment, a distribution of edge placement error or other variation (σ) can be determined based on the shape. The wafer can be inspected at a location with edge placement error.

[0065] The EPU signal can be compared to wafer specifications (i.e., control limits). The specifications may be maximum area, shape, slope, curvature, asymmetry, or other targets between the simulated tool signal and the design-aided synthetic signal. For example, areas where the EPU signal is within specification are accepted. Areas where the EPU signal is out of specification are marked for additional review. In one example, the additional review is to fully characterize the wafer stochasticity (e.g., CD or LER) using an SEM or optical tool.

[0066] By taking into account the tool characteristics in the simulated tool signal, the EPU signal can take into account the rest caused by the wafer. The simulated tool signal is configured to take into account the tool error. Thus, the rest can be stochastic on the wafer.

[0067] In one example, design data for the wafer is received. This design data is used to determine a simulated tool signal. The simulated tool signal can also account for various tool characteristics of the tool performing the measurements. The design and measurements are used to determine a design-aided composite signal. In one example, the design-aided composite signal is determined from measurements made during overlay metrology. The EPU signal is then determined by comparing the simulated tool signal and the design-aided composite signal. An extraction algorithm can be applied to the EPU signal. This example can provide high speed screening of structures with respect to wafer stochasticity without the need to fully characterize every individual structure. During this screening, a larger FOV can be used, which can affect speed. If the same electron beam is used over a larger FOV, each structure is also exposed to a lower dose because the electron dose is spread over a larger area. In one example, only areas with stochasticity that give out-of-specification results need to be considered to detect problematic or defective features.

[0068] 7 is a block diagram of an embodiment of a system 300. System 300 includes a wafer metrology tool (including an electron column 301) configured to generate a signal of a wafer 304. The signal can be an image, although other data is possible.

[0069] The wafer metrology tool includes an output acquisition subsystem including at least an energy source and a detector. The output acquisition subsystem may be an electron beam based output acquisition subsystem. For example, in one embodiment, the energy directed at the wafer 304 includes electrons and the energy detected from the wafer 304 includes electrons. In this manner, the energy source may be an electron beam source. In one such embodiment shown in FIG. 7, the output acquisition subsystem includes an electron column 301 coupled to a computer subsystem 302. A stage 310 may hold the wafer 304 or another type of sample.

[0070] 7, electron column 301 includes an electron beam source 303 configured to generate electrons that are focused onto wafer 304 by one or more elements 305. Electron beam source 303 may include, for example, a cathode source or an emitter tip. One or more elements 305 may include, for example, a gun lens, an anode, a beam limiting aperture, a gate valve, a beam current selection aperture, an objective lens, and a scanning subsystem, all of which may include any such suitable elements known in the art.

[0071] Electrons returning from wafer 304 (e.g., secondary electrons) may be focused onto detector 307 by one or more elements 306. One or more elements 306 may include a scanning subsystem, which may be, for example, the same scanning subsystem included in element 305.

[0072] Electron column 301 may also include any other suitable elements known in the art.

[0073] 7 as being configured such that electrons are directed at the wafer 304 at an oblique angle of incidence and scattered from the wafer 304 at another oblique angle, the electron beam may be directed at and scattered from the wafer 304 at any suitable angle. Additionally, the electron beam-based output acquisition subsystem may be configured to use multiple modes to generate a signal for the wafer 304 (e.g., having different illumination angles, collection angles, etc.). The multiple modes of the electron beam-based output acquisition subsystem may differ in any signal generation parameter of the output acquisition subsystem.

[0074] The computer subsystem 302 may be coupled to the detector 307 as described above. The detector 307 may detect electrons returning from the surface of the wafer 304, thereby forming a signal related to the wafer 304. The signal may include any suitable electron beam image or other data. The computer subsystem 302 may be configured to perform any of the functions described herein using the output and / or signal of the detector 307. The computer subsystem 302 may be configured to perform any additional steps described herein. The system 300 including the output acquisition subsystem shown in FIG. 7 may be further configured as described herein.

[0075] It should be noted that FIG. 7 is provided herein to diagrammatically illustrate configurations of an electron beam-based power acquisition subsystem that may be used in the embodiments described herein. The electron beam-based power acquisition subsystem configurations described herein may be modified to optimize the performance of the power acquisition subsystem, as is typically done when designing a commercial power acquisition system. In addition, the systems described herein may be implemented using existing systems (e.g., by adding the functionality described herein to an existing system). For some such systems, the methods described herein may be provided as optional functionality of the system (e.g., in addition to other functions of the system). Alternatively, the systems described herein may be designed as entirely new systems.

[0076] Although the output acquisition subsystem is described above as being an electron beam-based output acquisition subsystem, the output acquisition subsystem may be an ion beam-based or neutral beam-based output acquisition subsystem. Such an output acquisition subsystem may be configured as shown in FIG. 7, except that the electron beam source may be replaced with any suitable beam source known in the art. In addition, the output acquisition subsystem may be any other suitable beam-based output acquisition subsystem, such as those included in commercially available focused ion beam (FIB) systems, helium ion microscope (HIM) systems, and secondary ion mass spectrometry (SIMS) systems. Although illustrated with an electron beam, other output acquisition subsystems or different systems may be used, such as scanning near-field optical microscopy (SNON), near-field scanning optical microscopy (NSOM), scanning probe, atomic force microscopy (AFM), or other optical scanning using photons (e.g., TDI, photodiode).

[0077] The computer subsystem 302 includes a processor 308 and an electronic data storage unit 309. The processor 308 may include a microprocessor, microcontroller, or other device.

[0078] The computer subsystem 302 may be coupled to the components of the system 300 in any suitable manner (e.g., via one or more transmission media, which may include wired and / or wireless transmission media) such that the processor 308 may receive the output. The processor 308 may be configured to perform a number of functions using the output. The wafer metrology tool may receive instructions or other information from the processor 308. The processor 308 and / or electronic data storage unit 309 may optionally be in electronic communication with another wafer metrology tool, wafer inspection tool, or wafer review tool (not shown) to receive additional information or send instructions.

[0079] The processor 308 is in electronic communication with a wafer metrology tool, such as the detector 307. The processor 308 may be configured to process signals generated using measurements from the detector 307. For example, the processor may perform an embodiment of the method 200.

[0080] The computer subsystem 302, other systems, or other subsystems described herein may be part of a variety of systems, including a personal computer system, an image computer, a mainframe computer system, a workstation, a network appliance, an Internet appliance, or other devices. The subsystem or system may also include any suitable processor 308 known in the art, such as a parallel processor. In addition, the subsystem or system may include a platform with high speed processing and software, either as a stand-alone tool or a network tool.

[0081] The processor 308 and electronic data storage unit 309 may be located in or otherwise part of the system 300 or another device. In one example, the processor 308 and electronic data storage unit 309 may be part of a stand-alone control unit or may be a centralized quality control unit. Multiple processors 308 or electronic data storage units 309 may be used.

[0082] The processor 308 may in fact be implemented by any combination of hardware, software, and firmware. Also, its functions as described herein may be performed by one unit or may be divided among different components, each of which may in turn be implemented by any combination of hardware, software, and firmware. Program codes or instructions for the processor 308 to implement the various methods and functions may be stored in a readable storage medium, such as a memory in the electronic data storage unit 309 or other memory.

[0083] Where system 300 includes multiple computer subsystems 302, the different subsystems may be coupled to one another such that images, data, information, instructions, etc. may be transmitted between the subsystems. For example, one subsystem may be coupled to additional subsystems by any suitable transmission medium, which may include any suitable wired and / or wireless transmission medium known in the art. Two or more of such subsystems may also be effectively coupled by a shared computer-readable storage medium (not shown).

[0084] The processor 308 may be configured to perform a number of functions using the output of the system 300 or other outputs. For example, the processor 308 may be configured to transmit the output to an electronic data storage unit 309 or another storage medium. The processor 308 may be further configured as described herein.

[0085] The processor 308 or computer subsystem 302 may also be part of a defect review system, an inspection system, a metrology system, or some other type of system. Thus, the embodiments disclosed herein describe several configurations that can be tailored in several ways for systems having different capabilities that are more or less suitable for different applications.

[0086] The processor 308 may be configured according to any of the embodiments described herein. The processor 308 may also be configured to perform other functions or additional steps using the output of the system 300 or using data from other sources.

[0087] Processor 308 may be communicatively coupled to any of the various components or subsystems of system 300 in any manner known in the art. Additionally, processor 308 may be configured to receive and / or acquire data or information from other systems (e.g., inspection results from an inspection system such as a review tool, a remote database containing design data, etc.) by way of a transmission medium that may include wired and / or wireless portions. In this manner, the transmission medium may serve as a data link between processor 308 and other subsystems of system 300 or systems external to system 300.

[0088] For example, various steps described throughout this disclosure may be performed by a single processor 308 (or computer subsystem 302), or alternatively, by multiple processors 308 (or multiple computer subsystems 302). Additionally, different subsystems of system 300 may include one or more computing or logic systems. Thus, the above description should not be construed as a limitation on the disclosure, but merely as an example.

[0089] Further embodiments relate to a non-transitory computer-readable medium storing program instructions executable on a processor to perform a computer-implemented method for determining an EPU signal as disclosed herein. In particular, as shown in FIG. 7, an electronic data storage unit 309 or other storage medium may include a non-transitory computer-readable medium including program instructions executable on a processor 308. The computer-implemented method may include any step of any method described herein.

[0090] Program instructions implementing methods such as those described herein may be stored on a computer-readable medium, such as an electronic data storage unit 309 or other storage medium. The computer-readable medium may be a storage medium, such as a magnetic or optical disk, magnetic tape, or any other suitable non-transitory computer-readable medium known in the art.

[0091] The program instructions may be implemented in any of a variety of ways, including procedure-based techniques, component-based techniques, and / or object-oriented techniques, among others. For example, the program instructions may be implemented using ActiveX controls, C++ objects, JavaBeans, Microsoft Foundation Classes (MFC), Streaming SIMD Extensions (SSE), or other techniques or methodologies, as desired.

[0092] Each of the steps of the method may be performed as described herein. The method may also include any other steps that may be performed by a processor and / or computer subsystem or system described herein. The steps may be performed by one or more computer systems that may be configured according to any of the embodiments described herein. In addition, the above-mentioned method may be implemented by any of the system embodiments described herein.

[0093] Although the present disclosure has been described with respect to one or more particular embodiments, it will be understood that other embodiments of the present disclosure may be made without departing from the scope of the present disclosure, and therefore the present disclosure is deemed to be limited only by the appended claims and their reasonable interpretation.

Claims

1. 1. A method comprising: using a processor to determine a design-aided composite signal from a plurality of features on the wafer using measurements of the wafer from a wafer metrology tool and a design of the wafer; determining, using the processor, a simulated tool signal for the wafer design accounting for noise sources and imaging characteristics of the wafer metrology tool; determining, with the processor, an edge placement uniformity signal that is the difference between the design aided synthetic signal and the simulated tool signal; analyzing a shape and / or area of ​​the edge placement uniformity signal, the shape and area being driven by at least a probability theory; The method according to claim 1, further comprising:

2. The method of claim 1 , wherein the wafer metrology tool is a scanning electron microscope.

3. 2. The method of claim 1, wherein the measurements of the wafer are generated during an overlay metrology of the wafer.

4. determining a distribution of edge placement errors based on the shape; The method of claim 1 further comprising:

5. Inspecting the wafer at a location having the edge placement error. The method of claim 4 further comprising:

6. 2. The method of claim 1, wherein the measurements are for multiple lines of devices on the wafer.

7. 7. The method of claim 6, wherein each of said plurality of lines comprises one of said edge placement uniformity signals.

8. Using the processor, comparing the edge placement uniformity signal to a specification for the wafer. The method of claim 1 further comprising:

9. 2. The method of claim 1, wherein the design aid composite signal is an average of the measurements.

10. 2. The method of claim 1, wherein the feature is an edge of a structure on the wafer.

11. 2. The method of claim 1, wherein the feature is a center of a structure on the wafer.

12. A computer readable medium storing a program configured to instruct the processor to perform the method of claim 1.

13. 1. A system comprising: a particle beam source for generating a particle beam; a stage configured to hold a wafer in the path of the particle beam; a detector for receiving particles from the wafer; a processor in electronic communication with the detector, the processor comprising: determining a design-aided composite signal from a plurality of features on the wafer using measurements of the wafer and a design of the wafer; Determine a simulated tool signal for the wafer design that comprises noise sources and imaging characteristics of the wafer metrology tool; determining an edge placement uniformity signal that is the difference between the design aided synthetic signal and the simulated tool signal; configured to analyze a shape and / or an area of ​​the edge placement uniformity signal, the shape and the area being caused by at least a probability theory. system.

14. The system of claim 13 , wherein the system is a scanning electron microscope.

15. The system of claim 13 , wherein the processor is further configured to determine a distribution of edge placement errors based on the shape.

16. 16. The system of claim 15, wherein the processor is further configured to send instructions to inspect the wafer at a location having the edge placement error using the particle beam.

17. 14. The system of claim 13, wherein the processor is further configured to compare the edge placement uniformity signal to a specification for the wafer.

18. The system of claim 13 , wherein the particle beam is an electron beam, a photon beam, an ion beam, or a neutral particle beam.

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