Wafer positioning system and method - Patents.com

Abstract

In the present invention, a wafer positioning system and method are provided. [Solution] The wafer positioning method of the present invention includes the steps of: a manipulator transporting a wafer to a predetermined position on a first support area of ​​a lower cavity of a semiconductor processing device, i.e., a position corresponding to the current position setting parameter, according to a set or updated current position setting parameter; etching an edge area of ​​the wafer; acquiring etched edge information of the wafer by performing image collection and image recognition on the wafer mounted at the predetermined position and etched according to the current position setting parameter; calculating a position deviation parameter of the current position setting parameter according to the acquired etched edge information of the wafer; a control device updating the current position setting parameter with the position deviation parameter to acquire an updated current position setting parameter, and controlling the manipulator to transport the wafer onto the first support area of ​​the lower cavity according to the updated current position setting parameter. By calibrating the manipulator, the position of the wafer can be determined more accurately.

Description

[Technical field]

[0001] The present invention relates to the technical field of wafer positioning, and more particularly to a wafer positioning system and method. [Background technology]

[0002] In the semiconductor manufacturing process, various processes are performed on semiconductor wafers to meet the high standards of the semiconductor industry. In the semiconductor wafer manufacturing process, the edges of the wafers must be uniform, flat, undamaged, and smooth. Since the edges of the wafers must be uniform and the edges of the wafers must be precisely etched, the semiconductor wafer manufacturing process needs to be improved.

[0003] FIG. 1a is a plan view showing the structure of a semiconductor wafer 100. The semiconductor wafer 100 includes a substrate 101 and a thin film layer 102 laminated on the substrate 101. FIG. 1b is a cross-sectional view showing the AA section of FIG. 1a. Measurement points 1 to 8 in FIG. 1a are positions for measuring predetermined values ​​of the semiconductor wafer. As shown in FIG. 1b, the corrosion width refers to the difference between the radius of the substrate 101 and the radius of the thin film layer 102. Each of the corrosion widths located at measurement points 1 to 8 is approximately the same. The smaller the difference between the maximum and minimum corrosion widths, the better the uniformity of the corrosion. For example, when the width of the edge is designed to be 0.7 mm, the difference between the maximum width of the corrosion and the minimum width of the corrosion is required to be 0.1 mm or less, and if this is not met, the width of the edge may be uneven. If the difference between the maximum width of the corrosion and the minimum width of the corrosion exceeds 0.1 mm, it may affect subsequent processing. This may affect the performance of the integrated circuit chip and reduce the manufacturing yield rate of the chip. 1a is a schematic diagram of a semiconductor wafer 100. An actual semiconductor wafer is not formed in a pure circular shape. For example, a 6-inch wafer may be a polygon having a wafer flat, and a positioning notch may be formed in the 6-inch wafer.

[0004] The wet processing method of semiconductor wafers has the advantages of simple principle, good process versatility, and low cost. Conventional wet etching methods for processing the edge of semiconductor wafer surface include various methods, such as polishing the edge area of ​​semiconductor wafer, rotating semiconductor wafer, and removing one thin film layer on the substrate by mechanical friction means and chemical etching method. When adopting the polishing method, the remaining thin film layer and the substrate may be damaged, so the polishing method is usually used in the manufacture of semiconductor wafers with low precision requirements. The edge of the semiconductor wafer may be damaged, causing the wafer to move during processing, which may result in the wafer being discarded. Another commonly used method is to suck the semiconductor wafer by vacuum. In the vacuum suction method, the wafer is sucked by a vacuum suction part. When the wafer is sucked by the vacuum suction part, a certain part of the thin film that does not need to be removed is covered by the vacuum suction part, and a certain part of the thin film that needs to be removed is exposed to the outside of the vacuum suction part. Next, the vacuum suction part and the wafer are immersed in a chemical corrosion solution together to remove a certain portion of the thin film exposed outside the vacuum suction part. However, when the vacuum suction method is adopted, the thin film layer cannot be removed smoothly, and the width of corrosion may be uneven. Another commonly used method is the thin film bonding method. In the thin film bonding method, a certain portion of the thin film that needs to be removed is protected by a high-purity anticorrosive plastic such as PTFE, PE, etc. Then, the exposed portion is corroded by feeding them into a chemical corrosion gas or immersing them in a chemical corrosion solution. When the thin film bonding method is adopted, it is difficult to overlap the center of the pre-cut thin film with the center of the wafer substrate, and therefore the width of corrosion may be uneven. In addition, the thin film bonding method requires many steps and the use of many devices, such as a thin film bonding device, a wet corrosion device, a cleaning device, and a thin film removal device. To solve these problems, a spraying method has been proposed. The spraying method can perform corrosion accurately, evenly, flatly, and without damage by precisely spraying the etching liquid from a certain nozzle onto the peripheral area of ​​the rotating wafer.Although the spraying method can improve the corrosion effect, it places high requirements on the design and parts of the equipment, which increases the cost of the equipment, and places high requirements on the process, which increases the processing cost.

[0005] Both the advanced wafer edge etching technology and its equipment require accurate wafer positioning, because the uniformity and range of the etching of the edge of the current wafer are more demanding. When etching the edge of the wafer, the accurate positioning of the wafer determines the uniformity of the etching width of the edge of the wafer. Therefore, it is necessary to propose a wafer positioning system and method that can constantly fine-tune. Summary of the Invention [Problem to be solved by the invention]

[0006] It is an object of the present invention to provide an improved wafer positioning system and method for fine-tuning and calibrating the positioning parameters of a manipulator so that the manipulator accurately loads a wafer in a predetermined location. [Means for solving the problem]

[0007] In order to achieve the above object, a first embodiment of the present invention provides a wafer positioning system. The wafer positioning system of the present invention includes a semiconductor processing device, an image edge detection device, a wafer transport device, and a positioning and calibration module. The semiconductor processing device includes a lower cavity in which a first support area is formed and an upper cavity in which a second support area is formed. When the upper cavity and the lower cavity are combined, a wafer is mounted between the first support area and the second support area, a first passage is formed in the edge area of ​​the first support area or the second support area, a first space is formed by the first passage, and the edge area of ​​the wafer is etched with one or more chemical fluids injected into the first space. The wafer transport device includes a manipulator and a control device, the control device sets or updates a current position setting parameter, and the manipulator transports the wafer to a predetermined position on the first support area of ​​the lower cavity of the semiconductor processing device, i.e., a position corresponding to the current position setting parameter, according to the set or updated current position setting parameter. The image edge detection device acquires the etched edge of the wafer by performing image acquisition and image recognition on the wafer mounted at the predetermined position and etched according to the current position setting parameter. The positioning and calibration module calculates a position deviation parameter of a current position setting parameter according to the etched edge information of the wafer obtained by image recognition, and the control device updates the current position setting parameter with the position deviation parameter to obtain an updated current position setting parameter, and controls the manipulator to transfer the wafer to a predetermined position on the first support area of ​​the lower cavity according to the updated current position setting parameter, i.e., a position corresponding to the updated current position setting parameter.

[0008] In order to achieve the above object, a second embodiment of the present invention further provides a wafer positioning method, which includes the steps of: a manipulator transporting a wafer to a predetermined position on a first support area of ​​a lower cavity of a semiconductor processing device, i.e., a position corresponding to the current position setting parameter, according to a set or updated current position setting parameter; a semiconductor processing device etching an edge area of ​​the wafer; a wafer mounted at a predetermined position and etched according to the current position setting parameter by performing image acquisition and image recognition, thereby obtaining etched edge information of the wafer; a positioning and calibration module calculating a position deviation parameter of the current position setting parameter according to the obtained etched edge information of the wafer; a control device updating the current position setting parameter with the position deviation parameter to obtain an updated current position setting parameter, and controlling the manipulator to transport the wafer to a predetermined position on a first support area of ​​the lower cavity, i.e., a position corresponding to the updated current position setting parameter, according to the updated current position setting parameter. Effect of the Invention

[0009] Compared with the prior art, the wafer positioning system and method of the present invention obtains the etched edge of the wafer by image recognition of the etched wafer, calculates the position deviation parameter of the current position setting parameter according to the etched edge information of the wafer obtained by image recognition, and updates the current position setting parameter with the position deviation parameter to obtain the updated current position setting parameter. That is, the present invention fine-tunes and calibrates the current position setting parameter of the manipulator according to the etched edge information of the wafer, so that the manipulator can accurately mount the wafer at a predetermined position on the first support area of ​​the lower cavity of the semiconductor processing device, and make the etch of the wafer edge more uniform.

[0010] It should be noted that the purpose of the above description of the invention is to provide a general understanding of the subject matter of the invention by referring to the description of the embodiments of the invention. The above embodiments are merely illustrative of the invention, and are not intended to limit the scope or gist of the invention. The following specific embodiments and drawings of the invention will allow the reader to easily understand the features, forms and effects of the embodiments of the invention. In other words, the principles of the invention will be described in detail with reference to the drawings and embodiments of the invention. [Brief description of the drawings]

[0011] The present invention can be readily understood by reference to the following drawings and detailed description, in which like reference numerals refer to like structures, and in which: [Figure 1a] FIG. 2 is a bottom view showing the structure of a semiconductor wafer. [Figure 1b] FIG. 1B is a cross-sectional view showing the section AA of FIG. [Figure 2a] 1 is a cross-sectional view showing a semiconductor processing apparatus according to an embodiment of the present invention. [Figure 2b] FIG. 2b is an enlarged view of part A of FIG. 2a. [Figure 2c] FIG. 2b is an enlarged view of part B of FIG. [Figure 2d] FIG. 2c is an enlarged view of part C of FIG. [Figure 2e] FIG. 2b is a bottom view of the upper cavity of the semiconductor processing apparatus of FIG. 2a. [Figure 2f] FIG. 2b is a plan view of the lower cavity of the semiconductor processing apparatus of FIG. 2a. [Diagram 3] 1 illustrates a semiconductor processing system according to an embodiment of the present invention, including semiconductor processing equipment and a material storage device; [Figure 4] 1 illustrates an exemplary method for processing an edge area of ​​a semiconductor wafer in a semiconductor processing apparatus according to an embodiment of the present invention. [Diagram 5] 1 is a block diagram illustrating a wafer positioning system according to an embodiment of the present invention. [Figure 6] 1 is a perspective view showing an image edge detection device according to one embodiment of the present invention; [Figure 7] 7 is a side view showing the image edge detection device of FIG. 6. [Figure 8] FIG. 13 shows the results obtained by recognition of the wafer edge on the collected images. [Figure 9] FIG. 11 is a comparison plot comparing a captured image of an etched inventive wafer and its HLS image. [Figure 10] FIG. 13 is a diagram showing a number of lines obtained by performing edge recognition on an HLS image. [Figure 11] 2 is a flow chart showing a method for measuring the erosion edge of a wafer according to an embodiment of the present invention. [Figure 12] FIG. 1 is a top view of a 6 inch wafer with etched edges. [Figure 13] FIG. 1 is a plan view of an 8 inch or larger wafer with edge etched. [Figure 14] 4 is a flow chart illustrating a wafer positioning method according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings of the present invention. The following embodiments are only some of the embodiments of the present invention and do not show all the embodiments of the present invention. The embodiments of the present invention may further include various forms of embodiments in addition to the following embodiments. The purpose of providing the following embodiments is to describe the matters of the present invention in detail and to allow those skilled in the art to understand the matters of the present invention in detail. For example, unless otherwise specified, terms such as first, second, etc. do not imply an order of the matters. Although a certain part is described as being on top of another part, the part may be on the bottom of the other part (due to different viewing directions) (unless otherwise specified), and vice versa. Furthermore, although a certain part is described as being on the left side, the part may be on the right side (due to different viewing directions), and vice versa. Unless otherwise specified, the same reference numerals always represent the same parts.

[0013] 1a and 1b are diagrams illustrating the structure of a semiconductor wafer 100. FIG. 1a is a bottom view illustrating the structure of the semiconductor wafer 100, and FIG. 1b is a cross-sectional view illustrating the AA section of FIG. 1a. As shown in FIGS. 1a and 1b, the semiconductor wafer 100 includes a substrate 101 and a thin film layer 102 laminated on an upper surface of the substrate 101, and a portion of the substrate 101 may be covered by the thin film layer 102. In another embodiment, the entire substrate 101 may be covered by the thin film layer 102. In another embodiment, both sides of the surface of the substrate 101 may be covered by the thin film layer 102, respectively.

[0014] In this embodiment, the edge of the thin film layer 102 on the substrate 101 is removed by processing the semiconductor wafer. As shown in FIG. 1a-FIG. 1b, the radius of the thin film layer 102 is smaller than the radius of the substrate 101, and the corrosion width refers to the difference between the radius of the thin film layer 102 and the radius of the substrate 101. Measurement points 1-8 in FIG. 1a are positions for measuring certain values ​​of the semiconductor wafer. The corrosion widths located at the measurement points 1-8 are approximately the same, and the smaller the difference between the maximum and minimum corrosion widths, the better the corrosion uniformity. For example, when the edge width is 0.7 mm, it is required that the difference between the maximum corrosion width and the minimum corrosion width is 0.1 mm or less. In the embodiment of the present invention, a part or all of the thin film layer 102 covering both sides of the surface of the substrate 101 is removed. The corrosion widths on each side of the substrate 101 can be the same or different.

[0015] first part 2a to 2f, which are diagrams illustrating a structure of a semiconductor processing apparatus 200 according to an embodiment of the present invention. Fig. 2a is a cross-sectional view of the semiconductor processing apparatus 200, Fig. 2b is an enlarged view of part A of Fig. 2a, Fig. 2c is an enlarged view of part B of Fig. 2b (through holes are omitted), Fig. 2d is an enlarged view of part C of Fig. 2c, Fig. 2e is a bottom view of an upper cavity 220 of the semiconductor processing apparatus 200 of Fig. 2a, and Fig. 2f is a plan view of a lower cavity 210 of the semiconductor processing apparatus 200 of Fig. 2a.

[0016] In an embodiment of the present invention, as shown in FIG. 1 and FIG. 2a-2f, the semiconductor processing apparatus 200 includes a lower cavity 210 in which a first support area 212 is formed. The first support area 212 can support the wafer 100. As shown in FIG. 2a, the first support area 212 has an upper surface facing the wafer 100. The wafer 100 can be mounted on the upper surface of the first support area 212. In an embodiment of the present invention, the semiconductor processing apparatus 200 includes an upper cavity 220 in which a second support area 222 is formed. As shown in FIG. 2a, the second support area 222 has a lower surface facing the wafer 100. When the upper cavity 220 and the lower cavity 210 are coupled, the wafer 100 is mounted between the first support area 212 and the second support area 222. The upper cavity 220 can be moved between two positions relative to the lower cavity 210. When the upper cavity 220 is located at the first position, the wafer 100 can be loaded or removed from the first support area 212. As shown in FIG. 2a, when the upper cavity 220 is located at the second position, the upper cavity 220 and the lower cavity 210 are coupled, and the wafer 100 can be processed by being fixed between the upper surface of the first support area 212 and the lower surface of the second support area 222. In an embodiment of the present invention, the upper cavity 220 can be moved between two positions by driving, and the lower cavity 210 can be stationary. In another embodiment, the lower cavity 210 can be moved between two positions by driving, and the upper cavity 220 can be stationary, or the upper cavity 220 and the lower cavity 210 can be moved simultaneously by driving.

[0017] In one embodiment or a combination of embodiments of the present invention, referring to FIG. 2a-FIG. 2c, the semiconductor processing apparatus 200 includes a first passage 230 formed in an edge area of ​​the first support area 212 or the second support area 222. The first passage 230 forms a first space 232, and one or more chemical fluids can be injected into the first space 232 to etch the edge area of ​​the wafer 100. Referring to FIG. 2a-FIG. 2c, the first passage 230 forms an edge area of ​​the second support part 222 of the upper cavity 220. The first passage 230 is formed on the lower surface of the upper cavity 220, and an opening on one side of the first passage 230 faces the wafer 100. In this embodiment, the first passage 230 forms a first space 232, and one or more chemical fluids can be injected into the first space 232 to etch the edge area of ​​the wafer 100. 2a-2c, the first space 232 is formed by the first passage 230 and the inner surface of the wafer 100. In this embodiment, the first passage 230 is formed in an annular shape and is formed to surround the edge region of the wafer 100. The entire edge region of the wafer 100 is accommodated within the first space 232. In another embodiment, the first passage 230 is formed in an arc shape with an included angle of less than 360°, so that the edge region of the wafer 100 can be accommodated within a predetermined area of ​​the first space 232. One or more chemical fluids can flow in the arc portion of the first space 232 to etch the edge region of the wafer 100.

[0018] In the semiconductor processing apparatus 200 according to one embodiment or a combination of embodiments of the present invention, referring to FIG. 2a-FIG. 2c, the upper cavity 220 includes a protruding portion 240 that abuts against the edge of the wafer 100. The protruding portion 240 can directly contact and abut against the edge of the wafer 100. Referring to FIG. 2a, the central axis XX of the wafer 100 is perpendicular to the upper surface of the wafer 100, and the central axis X'-X' of the second support area 222 is perpendicular to the lower surface of the second support area 222. The central axis XX of the wafer 100 and the central axis X'-X' of the second support area 222 can overlap with each other due to the protruding portion 240. When the upper cavity 220 is located at the first position, the wafer 100 is mounted on the first support area 212. The central axis XX of the wafer 100 and the central axis X'-X' of the second support area 222 do not have to overlap with each other. When the upper cavity 220 moves from the first position to the second position, the protrusion 240 can contact the edge of the wafer 100 and then abut against the edge of the wafer 100 to move the wafer 100 on the upper surface of the first support area 212. When the upper cavity 220 is located at the second position, the wafer 100 is fixed on the upper surface of the first support area 212, and the central axis XX of the wafer 100 and the central axis X'-X' of the second support area 222 can be aligned parallel to each other, or the central axis XX of the wafer 100 and the central axis X'-X' of the second support area 222 can overlap each other.

[0019] In the semiconductor processing apparatus 200 according to one embodiment or a combination of embodiments of the present invention, the protrusion 240 is adjacent to the second support area 222 and extends in a direction toward the lower cavity 210. Referring to FIG. 2a and FIG. 2b, the protrusion 240 is connected to the second support area 222. When the upper cavity 220 is located in the second position, the protrusion 240 extends to the lower cavity 210. Referring to FIG. 2a and FIG. 2b, in this embodiment, the protrusion 240 is located beside the first passage 230. Referring to FIG. 2a, the central axis XX of the wafer 100 is perpendicular to the upper surface of the wafer 100, the central axis X'-X' of the second support area 222 is perpendicular to the lower surface of the second support area 222, and the upper surface of the wafer 100 is parallel to the lower surface of the second support area 222. In an embodiment of the present invention, when the upper cavity 220 is located in the second position, a portion of the upper surface of the wafer 100 overlaps with the lower surface of the second support area 222, and the central axis XX of the wafer 100 overlaps with the central axis X'-X' of the second support area 222.

[0020] In the semiconductor processing apparatus 200 according to one or a combination of the embodiments of the present invention, the protrusion 240 may be a closed loop surrounding the wafer 100. Referring to FIG. 2a, the protrusion 240 includes a closed loop. The closed loop surrounds the entire edge region of the wafer 100. The protrusion 240 abuts against the edge region of the wafer 100, so that the central axis XX of the wafer 100 and the central axis X'-X' of the second support region 222 can overlap. In another embodiment, the closed loop is an arc shape with an included angle of 360° or less, and a predetermined portion of the closed loop can abut against the edge region of the wafer 100. The protrusion 240 is formed so that the central axis XX of the wafer 100 and the central axis X'-X' of the second support region 222 can be arranged parallel to each other or can overlap each other. In another embodiment, the protrusion 240 may be an open loop.

[0021] In the semiconductor processing apparatus 200 according to one or a combination of embodiments of the present invention, the protrusion 240 includes an interior angle facing the central axis X'-X' of the second support area 222. Referring to FIG. 2c, the protrusion 240 includes an interior surface 242, and an included angle between the interior surface 242 and a first reference direction Y-Y is α. The first reference direction Y-Y is parallel to the lower surface of the second support area 222. The included angle α ranges from 20° to 90°. As shown in FIG. 2b and FIG. 2c, the interior angle is formed by the interior surface 242 of the protrusion 240 and the inner surface of the first passage 230 and faces the central axis X'-X' of the second support area 222. In the embodiment of the present invention, the interior angle abuts the edge area of ​​the wafer 100. 2b, when the upper cavity 220 moves from the first position to the second position, the inner corner of the protrusion 240 contacts the edge of the wafer 100 and then abuts against the edge of the wafer 100, thereby moving the wafer 100. When the upper cavity 220 is located at the second position, the wafer 100 is fixed on the upper surface of the first support area 212, and the central axis XX of the wafer 100 and the central axis X'-X' of the second support area 222 are arranged parallel to each other, or the central axis XX of the wafer 100 and the central axis X'-X' of the second support area 222 can overlap each other.

[0022] In the semiconductor processing apparatus 200 according to one or a combination of embodiments of the present invention, a first tank 250 is formed in the peripheral area 214 of the lower cavity 210, and one or more chemical fluids can flow in a first tank space 252 formed by the first tank 250. Referring to Figures 2a, 2b and 2f, the first tank 250 is formed in the peripheral area 214 of the lower cavity 210 and is adjacent to the first support area 212 of the lower cavity 210. The first tank space 252 is formed by the first tank 250, and one or more chemical fluids can flow from the first space 232 of the first passage 230 to the first tank space 252.

[0023] In the semiconductor processing apparatus 200 according to one or a combination of embodiments of the present invention, the passage 260 is located between the upper cavity 220 and the lower cavity 210. Referring to FIG. 2b and FIG. 2f, the lower cavity 210 has a first upper surface 262 located between the first support area 212 and the first bath 250. The passage 260 is located between the first upper surface 262 of the lower cavity 210 and the inner surface 242 of the protruding portion 240. The passage 260 connects the first space 232 and the first bath space 252, so that one or more chemical fluids can flow from the first space 232 to the first bath space 252 through the passage 260. In the embodiment of the present invention, the passage 260 is blocked by the protruding portion 240, so that one or more chemical fluids can be prevented from flowing from the first space 232 to the first bath space 252. In another embodiment, the passageway 260 can be blocked by the first support area 212 to prevent the flow of one or more chemical fluids from the first volume 232 to the first reservoir volume 252 .

[0024] In the semiconductor processing apparatus 200 according to one or a combination of embodiments of the present invention, as shown in FIG. 2a-FIG. 2c, the first passage 230 is located in the peripheral area of ​​the second support area 222. The upper cavity 220 includes a first through hole 270, through which one or more chemical fluids can flow between the first space 232 and the outside of the semiconductor processing apparatus 200. The first through hole 270 passes through the upper cavity 220 from the outside of the semiconductor processing apparatus 200 and is connected to the first space 232 in a communicative state. In the embodiment of the present invention, one or more chemical fluids can flow between the first space 232 and the outside of the semiconductor processing apparatus 200 through the first through hole 270. In another embodiment, the upper cavity 220 can include two or more through holes similar to the first through hole 270 (e.g., another first through hole 272 in FIG. 2a and FIG. 2e). In this embodiment, at least one first through-hole (e.g., the first through-hole 270) can be used as an inlet, and another first through-hole (e.g., the other first through-hole 272) can be used as an outlet. The first space 232 can be connected in communication with the outside through the first through-hole 270 and the other first through-hole 272. In this embodiment, one or more chemical fluids can flow from the outside of the semiconductor processing device 200 to the first space 232 of the first passage 230 through the first through-hole 270, and flow from the first space 232 to the outside of the semiconductor processing device 200 through the other first through-hole 272.

[0025] In the semiconductor processing apparatus 200 according to one or a combination of the embodiments of the present invention, the second passage 280 is formed in the peripheral area of ​​the first support area 212, and one or more chemical fluids can be injected into the second space 282 of the second passage 280 to etch the peripheral area of ​​the wafer 100. Referring to FIG. 2a-FIG. 2c, the second passage 280 is formed in the peripheral area of ​​the first support area 212 of the lower cavity 210. Referring to FIG. 2a-FIG. 2c, the second passage 280 is formed on the upper surface of the lower cavity 210, and one side opening of the second passage 280 faces the wafer 100. In this embodiment, the second passage 280 forms a second space 282, and one or more chemical fluids can be injected into the second space 282 to etch the peripheral area of ​​the wafer 100. Referring to FIG. 2a-FIG. 2c, the second space 282 can be formed by the inner surface of the second passage 280 and the wafer 100. In an embodiment of the present invention, the second passage 280 is formed in an annular shape and is formed to surround the edge area of ​​the wafer 100. In another embodiment, the second passage 280 is formed in an arc shape with an included angle of less than 360°, and the edge area of ​​the wafer 100 can be exposed to a certain area of ​​the second space 282. In this case, one or more chemical fluids can flow in the arc portion of the second space 282 to etch the edge area of ​​the wafer 100. In an embodiment of the present invention, the shape of the second passage 280 and the shape of the first passage 230 can be designed similarly. The second passage 280 is close to the first upper surface 262 and is located between the first support area 212 and the first tank 250. The passage 260 is located between the first upper surface 262 of the lower cavity 210 and the inner surface 242 of the upper cavity 220. Due to the passage 260 being formed, one or more chemical fluids can flow from the second space 282 to the first tank space 252 through the passage 260. In some embodiments, the passage 260 may be blocked by the protrusion 240, thereby preventing the flow of one or more chemical fluids from the second space 282 to the first reservoir space 252. In other embodiments, the passage 260 may be blocked by the first support area 212, thereby preventing the flow of one or more chemical fluids from the second space 282 to the first reservoir space 252.

[0026] In the semiconductor processing apparatus 200 according to one or a combination of the embodiments of the present invention, the second through-hole 290 is formed in the lower cavity 210, so that one or more chemical fluids can flow between the second space 282 and the outside of the semiconductor processing apparatus 200. Referring to FIG. 2a and FIG. 2b, the second through-hole 290 passes through the lower cavity 210 from the outside of the semiconductor processing apparatus 200, and then is connected to the second space 282 of the second passage 280 in a communicating state. In the embodiment of the present invention, one or more chemical fluids can flow between the second space 282 and the outside of the semiconductor processing apparatus 200 through the second through-hole 290. In another embodiment, one or more chemical fluids can flow from the outside of the semiconductor processing apparatus 200 to the second space 282 of the second passage 280 through the second through-hole 290, and then flow from the second space 282 of the second passage 280 to the first tank space 252 of the first tank 250 through the passage 260. In another embodiment, the lower cavity 210 may further include one or more second through holes similar to the second through hole 290 (e.g., may further include another second through hole 292 in FIG. 2a). In that case, at least one second through hole (e.g., the second through hole 290) may be used as an inlet, and another first through hole (e.g., the other second through hole 292) may be used as an outlet. The second space 282 may be connected in communication with the outside through the second through hole 290 and the other second through hole 292. In this embodiment, one or more chemical fluids may flow from the outside of the semiconductor processing device 200 to the second space 282 of the second passage 280 through the second through hole 290, and then flow from the second space 282 to the outside of the semiconductor processing device 200 through the other second through hole 292. In another embodiment, one or more chemical fluids can flow from outside the semiconductor processing apparatus 200 to the second space 282 of the second passage 280 through the second through hole 290 and the other second through hole 292, and then flow from the second space 282 of the second passage 280 to the first tank space 252 of the first tank 250 through the passage 260.

[0027] FIG. 3 is a diagram showing a semiconductor processing system 300 according to an embodiment of the present invention, which includes a semiconductor processing device 310 and a material storage device 320. The semiconductor processing device 310 may refer to the semiconductor processing device 200 shown in FIGS. 2a to 2f. The semiconductor processing device 310 includes a lower cavity in which a first support area for supporting a wafer is formed, and an upper cavity in which a second support area is formed. The upper cavity and the lower cavity can be coupled to fix the wafer between the first support area and the second support area. The first passage is located in the edge area of ​​the first support area or the second support area, and the first passage forms a first space. The edge area of ​​the wafer can be etched by injecting one or more chemical fluids into the first space. In an embodiment of the present invention, the upper cavity includes a protrusion, and the protrusion abuts against the edge of the wafer, thereby allowing the central axis of the wafer to overlap with the central axis of the second support area. The material storage device 320 is coupled to the semiconductor processing device 310, and the material storage device 320 stores one or more chemical fluids and transfers the one or more chemical fluids between the semiconductor processing device 510 and the material storage device 520. In an embodiment of the present invention, the one or more chemical fluids may be H3PO4, HF, HCl, HNO3, H2O2, or a combination thereof.

[0028] In the semiconductor processing system 300 according to one or a combination of embodiments of the present invention, the protrusion is adjacent to the second support area and extends in a direction toward the lower cavity. The central axis of the wafer is perpendicular to the upper surface of the wafer, the central axis of the second support area is perpendicular to the lower surface of the upper cavity, and the upper surface of the wafer is parallel to the lower surface of the second support area. In an embodiment of the present invention, the protrusion includes a closed loop surrounding the wafer, and the protrusion evenly abuts against the edge area of ​​the wafer, thereby allowing the central axis of the wafer to overlap with the central axis of the second support area.

[0029] In the semiconductor processing system 300 according to one or a combination of embodiments of the present invention, the convex portion is adjacent to the second support area and extends in a direction toward the lower cavity. The central axis of the wafer is perpendicular to the upper surface of the wafer, the central axis of the second support area is perpendicular to the lower surface of the upper cavity, and the upper surface of the wafer is parallel to the lower surface of the second support area. In an embodiment of the present invention, the convex portion includes a plurality of protrusions arranged in an annular shape around the wafer, and the plurality of protrusions evenly abut the edge area of ​​the wafer.

[0030] In the semiconductor processing system 300 according to one or a combination of embodiments of the present invention, a first tank is formed in the peripheral area of ​​the lower cavity, and one or more chemical fluids can flow in the space of the first tank formed by the first tank. In an embodiment of the present invention, a passage is formed between the upper cavity and the lower cavity, and the first space and the first tank space are connected by the passage, so that one or more chemical fluids can flow from the first space to the first tank space through the passage. In an embodiment of the present invention, a second tank is formed in the peripheral area of ​​the upper cavity, and the second tank is formed above the first tank. In an embodiment of the present invention, an elastic member is attached between the first tank and the second tank, and the elastic member can prevent one or more chemical fluids from flowing from the first space to the first tank space.

[0031] In the semiconductor processing system 300 according to one or a combination of embodiments of the present invention, the semiconductor processing system 300 includes a controller 330. The controller 330 can communicate with and control the semiconductor processing equipment 310 and the material storage equipment 320. For example, the controller 330 can control the movement of the upper cavity between a first position where the wafer is loaded or unloaded and a second position where the upper cavity and the lower cavity are coupled to process the wafer. The controller 330 can also control the flow rate and flow direction of one or more chemical fluids. The controller 330 can detect the flow rate, flow direction, and state of the one or more chemical fluids and failures of the semiconductor processing equipment 310. In an embodiment of the present invention, the controller can include a PLC, a control unit, a sensor, and a storage device (e.g., a memory, a hard disk drive, an SSD, etc.).

[0032] 4 illustrates an exemplary method 400 for processing an edge area of ​​a semiconductor wafer 100 in a semiconductor processing apparatus according to an embodiment of the present invention. The method may utilize the semiconductor processing systems illustrated in FIGS. 2a-2f and 3.

[0033] In step 402 of FIG. 4 according to an embodiment of the present invention, the semiconductor processing equipment 200 mounts the input wafer on the first support area of ​​the lower cavity. In step 404, the semiconductor processing equipment fixes the wafer between the first support area and the second support area of ​​the upper cavity by coupling the upper cavity with the lower cavity. In step 406, a first passage is formed in the edge area of ​​the first support area or the second support area, and a first space is formed by the first passage. In step 408, the semiconductor processing equipment abuts a protrusion against the edge area of ​​the wafer to make the central axis of the wafer overlap the central axis of the second support area. In step 410, the semiconductor processing equipment injects one or more chemical fluids into the first space to etch the edge area of ​​the wafer.

[0034] In step 402 of the method 400 according to one embodiment or a combination of embodiments of the present invention, a wafer is transferred by a wafer transfer device onto a first support area of ​​a lower cavity of the semiconductor processing apparatus 200. An upper surface of the first support area faces the wafer. When the wafer transfer device transfers the wafer onto the upper surface of the first support area, a part of the lower surface of the wafer is covered by the upper surface of the first support area. In an embodiment of the present invention, when the upper cavity of the semiconductor processing apparatus 200 is located at a first position, a wafer can be loaded onto or removed from the first support area. That is, the wafer can be transferred from the wafer transfer device onto the upper surface of the first support area.

[0035] In step 404 of the method 400 according to one embodiment or a combination of embodiments of the present invention, the semiconductor processing apparatus 200 couples the upper cavity and the lower cavity to fix the wafer between the first support area and the second support area of ​​the upper cavity. When the upper cavity is located in the second position, the coupling of the upper cavity and the lower cavity allows the wafer to be fixed between the first support area and the second support area, thereby allowing the edge area of ​​the wafer to be processed. The upper cavity includes a second support area facing the lower surface of the wafer. The coupling of the upper cavity and the lower cavity allows the wafer to be fixed between the first support area and the second support area. That is, the wafer can be fixed between the lower surface of the first support area and the upper surface of the second support area.

[0036] In step 406 of the method 400 according to one embodiment or a combination of embodiments of the present invention, a first passage is formed in the edge area of ​​the first support area or the second support area. The first passage can also be formed on the lower surface of the upper cavity. The opening of the first passage faces the wafer. In an embodiment of the present invention, the first passage forms a first space in which the edge area of ​​the wafer can be treated. For example, one or more chemical fluids are injected into the first space to etch the edge area of ​​the wafer. In an embodiment of the present invention, the first passage can be designed as a closed loop. In an embodiment of the present invention, the first passage can also be designed as a circle. The semiconductor processing device 200 or the wafer transport device can feed all or a part of the edge area of ​​the wafer into the first space for treatment. In an embodiment of the present invention, the first passage can be formed in an arc shape with an included angle of 360° or less. The semiconductor processing device 200 or the wafer transport device can feed a part of the edge area of ​​the wafer into the first space for treatment.

[0037] A protrusion is formed in the upper cavity or the lower cavity of the semiconductor processing device 200 used in step 408 of the method 400 according to one embodiment or a combination of embodiments of the present invention. The semiconductor processing device can abut the protrusion against the edge area of ​​the wafer. When the upper cavity moves from the first position to the second position, the protrusion contacts the edge of the wafer. Then, the wafer on the upper surface of the first support area of ​​the lower cavity can be moved by abutting the protrusion against the edge of the wafer. When the upper cavity and the lower cavity are combined, the wafer is fixed on the upper surface of the first support area, and the central axis XX of the wafer and the central axis X'-X' of the second support area are aligned parallel to each other. The distance between the central axis XX of the wafer and the central axis X'-X' of the second support area is 0 mm to 0.1 mm. In an embodiment of the present invention, the protrusion is adjacent to the second support area and extends in a direction toward the lower cavity. In an embodiment of the present invention, the protrusion is located near the first passage.

[0038] In an embodiment of the present invention, the convex portion includes an interior angle facing the central axis X'-X' of the second support region. The interior angle is formed by an inner surface of the convex portion and an inner surface of the first passage, and faces the central axis X'-X' of the second support region. In an embodiment of the present invention, the interior angle abuts the edge region of the wafer. When the upper cavity moves from the first position to the second position, the interior angle of the convex portion can contact the edge of the wafer and then abut against the edge of the wafer to move the wafer. In another embodiment, the inner surface of the convex portion can contact the edge of the wafer and then abut against the edge of the wafer to move the wafer.

[0039] In step 410 of the method 400 according to one embodiment or a combination of embodiments of the present invention, the semiconductor processing device 200 etches the edge area of ​​the wafer by injecting one or more chemical fluids into the first space. The one or more chemical fluids can flow around the edge of the wafer in the first space to etches the edge area of ​​the wafer exposed in the first space. In one embodiment of the present invention, the semiconductor processing device includes a through hole that communicates between the first space and the outside of the semiconductor processing device. The one or more chemical fluids can flow into the first space through the through hole. In one embodiment of the present invention, the one or more chemical fluids can flow from the first space to the outside of the semiconductor processing device through the through hole. In another embodiment, the semiconductor processing device includes two through holes, and the two through holes are respectively connected to the first space and the outside of the semiconductor processing device in a state of communication. The two through holes are spaced apart by a predetermined distance, and the one or more chemical fluids can flow into the first space through one through hole and flow out from the first space to the outside of the semiconductor processing device through the other through hole.

[0040] second part The method for determining the position of the cavity center shown in FIG. 2a to FIG. 2f is adopted. That is, the cavity structure, the convex portion, etc. ensure that the center of the wafer and the cavity overlap. However, when the wafer is clamped by the convex portion 240, the part of the wafer abutting the convex portion 240 may not be corroded. Therefore, it is necessary to provide a new wafer positioning method. In the new wafer positioning method, the convex portion 240 for determining the wafer position may not be formed, but forming the convex portion 240 may support the wafer positioning.

[0041] FIG. 5 is a block diagram showing a wafer positioning system of the present invention. As shown in FIG. 5, the wafer positioning system includes a semiconductor processing device 610, an image edge detection device 500, a positioning and calibration module 620, and a wafer transport device 630. The semiconductor processing device 610 is the semiconductor processing device 200 of the part, and the edge of the wafer 100 can be etched by the semiconductor processing device 610. The semiconductor processing device 610 can be a modified version of the semiconductor processing device 200. For example, the semiconductor processing device 200 can be a semiconductor processing device that does not have a protrusion for determining the position of the wafer 100. In an embodiment of the present invention, the positioning and calibration module 620 can be integrated with the image edge detection device 500, or the positioning and calibration module 620 can be integrated with the wafer transport device. In another embodiment, the positioning and calibration module 620, the image edge detection device 500, and the wafer transport device 630 can be integrated with each other.

[0042] The image edge detection device 500 can quickly detect the etching effect of the edge of the wafer 100 on which etching has been performed by capturing an image of the edge of the wafer 100, thereby evaluating the etching effect of the edge of the wafer 100. A wafer transfer device 630 can transfer the wafer 100 in the semiconductor processing device 610 on which etching has been performed to the image edge detection device 500.

[0043] FIG. 6 is a perspective view showing an image edge detection device 500 according to one embodiment of the present invention, FIG. 7 is a side view showing the image edge detection device 500 of FIG. 6, and FIG. 8 is a diagram showing the results obtained by recognizing the wafer edge (hereinafter referred to as edge recognition) for a collected image.

[0044] As shown in Figures 6 and 7, the image edge detection device 500 includes a line scanning camera 510, a light source 520, a rotation device 530, a positioning device 540, an alignment device (not shown) and an image processing unit (not shown).

[0045] The rotating device 530 supports the wafer 100 and can drive the wafer 100 to rotate around a rotating axis. The alignment device ensures that the center of the wafer and the center of rotation of the rotating device are overlapped. The line scan camera 510 is applied to the edge of the wafer 100. When the wafer 100 rotates, the line scan camera 510 captures an image of the wafer in a line scan manner, and stops capturing the image when the captured image reaches a preset height. The image processing unit is electrically connected to the line scan camera 510, and obtains a first line indicating the edge of the etched thin film layer and a second line indicating the edge of the wafer by edge recognition in a specific area of ​​the captured image. The image processing unit can recognize the edge of the wafer by adopting various methods in the prior art. In FIG. 8, P2 is the thin film layer (area where etching is not performed) and P1 is the substrate (area where the edge is etched). As shown in Fig. 8, when the gray scale of the corrosion edge (i.e., the corroded area and the non-corroded area) changes suddenly, the first line L1 and the second line L2 can be recognized by the sudden change in gray scale. In the present invention, the Plane Rectangular Coordinate System of the imaging data is converted into a Polar coordinate system by the line scanning method, thereby simplifying the image processing algorithms of the image processing unit.

[0046] The light source 520 is a light source that supplies a light beam toward the scanning of the line scan camera 510. The positioning device 540 determines the position of the wafer by recognizing the positioning notch and wafer flat of the wafer. The line scan camera 510 can collect images of the wafer at various positions. For example, it can collect images after rotating 90 degrees, 120 degrees, 180 degrees, etc. from the positioning notch or wafer flat of the wafer. Thus, sampling at a fixed position or sampling at a random position can be performed.

[0047] When the rotating device 530 rotates, it outputs a synchronous pulse signal to the line scan camera 510, so that the line scan camera 510 can scan and sample. The preset height is 1 / N of the circumference of the wafer 100, where N can be a value greater than or equal to 1, such as 20. The length of the captured image can be set by setting N. To accelerate the detection speed, N can be set to a large value.

[0048] The image processing unit can detect the distance between the first line L1 and the second line L2 and the roughness of the first line L1. The distance indicates the corrosion width, and the roughness of the first line L1 indicates the smoothness of the corrosion edge. The roughness of the first line L1 can be indicated by the root mean square error of the first line L1.

[0049] The image processing unit further recognizes a third line L3. The second line L2 and the third line L3 are both edges of the wafer. The edge of the wafer is not composed of a straight line but is composed of an arc line, so the image processing unit may detect two lines. In this case, it is usually determined that only the third line L3 is the outermost edge of the wafer. In another embodiment, either the second line L2 or the third line L3 can be recognized by adjusting the light source or by other means. For example, the distance between the third line L3 and the first line L1 can represent the etching width of the edge of the wafer. In this case, either the second line L2 or the third line L3 can be recognized. The first line L1, the second line L2, and the third line L3 can be straight lines or curves similar to straight lines. After the enlargement, most pixel points are not arranged in a straight line, but are arranged in a curve similar to a straight line. That is, the pixel points on one row are arranged in a curve similar to a straight line.

[0050] The embodiments of the present invention will now be described in more detail.

[0051] For a 12-inch wafer, after the etching process of the wafer edge is completed, information collection and measurement are required to understand the formation of the oxide layer and the etching edge on the wafer edge, so as to determine whether the stability of the wafer support structure and the final processing process meet the required requirements. In the processing of the entire wafer (wafer disk or wafer), the visual inspection of the edge corrosion result plays a very important role, which can provide a strong calibration reference for the processing process of the entire equipment and improve the function of the processing equipment. If an abnormality occurs during the process, the processing process can be stopped, so as to avoid a large number of wafers being damaged due to equipment abnormalities.

[0052] A 12-inch wafer is processed with a camera and light source, and a three-level gray scale image is formed by taking pictures of the edge of the wafer. That is, a three-level gray scale image is formed, which consists of the etched layer, substrate, and bevel of the wafer. The edge contour can be detected by fitting the edge of each layer with an image algorithm. The width of each layer of the wafer that has been processed can vary within a certain range, and the range of fluctuation should not exceed the maximum allowable error of the processing process.

[0053] The ideal minimum detection value of the current image edge detection device 500 can reach 3.5 micrometers, but due to distortions caused when using industrial cameras and nozzles contaminating the image when taking an image, the actual minimum detection value of the image edge detection device 500 can reach ±10 micrometers. The ideal image edge detection device 500 can detect one wafer per minute, but the detection time of the image edge detection device 500 can be shorter.

[0054] The line scan camera 510 can capture clear and large amplitude image content in a very short time. After the image capture is completed, noise reduction and enhancement are performed on the captured image by using a dedicated Visual Processing Library. Next, the main contour is detected and key points are detected on the detected clear contour. The required boundary lines are fitted by least square method on the detected key points. Finally, three lines L1, L2, and L3 are obtained by fitting.

[0055] third part However, for wafers with different specifications, whether the surface of the substrate is polished or not has a large impact on the grayscale value of the single channel. For example, the grayscale value of the corroded area of ​​a wafer that is not polished can reach 120-180, and the grayscale value of the corroded area of ​​another wafer that is not polished can reach 70-100. Since the grayscale value of the corroded area of ​​a wafer that is polished can reach 200-255, a method of inspecting the edge with the grayscale value can be adopted. Since the upper and lower limits of different wafers are different, inspection cannot be performed without manually setting parameters, which leads to increased costs.

[0056] In an embodiment of the present invention, there is further provided a further improved method 700 for measuring the eroded edge of a wafer. The eroded edge detection method 700 can measure a wafer whose edge is eroded. The eroded edge measurement method 700 is implemented in an image processing unit of the image edge detection device 500. Figure 11 is a flow chart showing the method 700 for measuring the eroded edge of a wafer according to an embodiment of the present invention. As shown in Figure 11, the method includes the following steps:

[0057] In step 710, an image is captured of the edge etched wafer.

[0058] In step 720, the captured image of the wafer is converted to an HLS image.

[0059] In HLS, H stands for color tone, L stands for brightness, and S stands for saturation.

[0060] Regardless of whether the wafer is polished or not, the corroded area of ​​the wafer has a certain color tone value, and the entire corroded area of ​​the wafer is biased to green (similar to green). Figure 9 is a comparison diagram comparing the captured image of an etched wafer with its HLS image. The image on the left is the captured image (i.e., the original image), and the image on the right is the HLS image. The corroded area in the HLS image is biased to green. In this embodiment, the corroded area of ​​the wafer can be determined by H (color tone) and L (brightness). This method can determine the corroded area of ​​the wafer more accurately than the method using only grayscale values.

[0061] In step 730, pixel points in the HLS image whose brightness value L is less than or equal to the preset brightness threshold and whose color tone value H is less than or equal to the preset color tone threshold are detected, and then the pixel points are connected and denoised to obtain the bevel area and the contour lines on both sides of the bevel area. As shown in FIG. 10, L11 is the outer edge contour line of the bevel area, and L12 is the inner edge contour line of the bevel area. When the brightness value and color tone value range from 0 to 255, the preset brightness threshold can be, for example, 10, and the preset color tone threshold can be, for example, 8 or 0.

[0062] In step 740, the bevel area of ​​the HLS image is roughly defined into a bevel area A1, a corroded area A2 and an uncorroded area A3 according to the brightness value. As shown in Fig. 10, an area having a preset size in the corroded area is selected as a corroded area sample, and the upper limit value and the lower limit value of the brightness L and the upper limit value and the lower limit value of the color tone H are obtained according to the corroded area sample. As shown in Fig. 10, the line L13 is the corroded area sample.

[0063] In step 750, the HLS image is binarized according to the upper and lower limits of the luminance L and the upper and lower limits of the color tone H, and then the final contour of the corroded area is obtained by dilation and connection. The final contour includes the corrosion boundary line located between the corroded area and the non-corroded area. As shown in FIG. 10, L14 is the corrosion boundary line.

[0064] The corrosion boundary line can be used to perform various calculations, such as calculation of corrosion width and calculation of corrosion roughness.

[0065] In the embodiment of the present invention, after determining the upper and lower limits of H (hue) and L (brightness) of the corroded area by the automatic sampling method, an accurate contour of the corroded area can be obtained. That is, the present invention can obtain an appropriate grayscale value without manually setting parameters. In addition, compared with using a single channel, using two channels can obtain a more accurate contour.

[0066] Fourth part 12, FIG. 12 is a plan view showing a 6-inch wafer with an etched edge. As shown in FIG. 12, the wafer includes a wafer flat 810, an outer edge contour 820 located at the outermost edge, and an erosion boundary line 830 located inside. The erosion boundary line 830 can be obtained by image recognition and is the erosion boundary line L14 shown in FIG. 10, and the outer edge contour line 820 can be obtained by image recognition and is the outer edge contour line L11 shown in FIG. 10. Although the entire outer edge contour line 820 and the entire erosion boundary line 830 of the wafer are shown in FIG. 12, in a specific embodiment, the image edge detection device can detect only a part of the outer edge contour line 820 and a part of the erosion boundary line 830 by image recognition means. As shown in FIG. 12, when the center of the wafer is accurately located and the entire edge of the wafer is evenly eroded, i.e., when the erosion widths of the ten measurement points 1 to 10 in FIG. 12 are consistent, it can be determined whether the wafer position is accurately determined by detecting the erosion widths of each measurement point.

[0067] As can be seen, the wafer positioning system includes a positioning and calibration module 620 and a wafer transport device 630 .

[0068] The wafer transport device 630 includes a manipulator and a control device, and the control device sets or updates a current position setting parameter, and the positioning and calibration module transfers the wafer to a predetermined position on the first support area of ​​the lower cavity of the semiconductor processing device 610, i.e., a position corresponding to the current position setting parameter, according to the set or updated current position setting parameter. As described above, the semiconductor processing device 610 can etch the edge of the wafer loaded in the semiconductor processing device. As described above, the image edge detection device 500 can obtain the etched edge of the wafer by performing image collection and image recognition on the wafer loaded at a predetermined position and etched according to the current position setting parameter. The etched edge can be determined by an outer edge contour and an etched boundary line, or by other factors.

[0069] The positioning and calibration module 620 calculates a position deviation parameter of a current position setting parameter according to the etched edge information of the wafer obtained by image recognition. The control device of the wafer transport device 630 updates the current position setting parameter with the position deviation parameter to obtain an updated current position setting parameter, and controls the manipulator to transport the wafer to a predetermined position on the first support area of ​​the lower cavity according to the updated current position setting parameter, i.e., a position corresponding to the updated current position setting parameter.

[0070] In an embodiment of the present invention, the positioning and calibration module 620 calculates the position deviation parameter of the current position setting parameter, and then judges whether the position deviation parameter is within a preset position deviation range. If the position deviation parameter is within the preset position deviation range, the update of the current position setting parameter is stopped; if the position deviation parameter is not within the preset position deviation range, the current position setting parameter is updated by the position deviation parameter. Then, after re-acquiring the etched edge of the wafer with the updated current position setting parameter, the position deviation parameter of the updated current position setting parameter is calculated again, and the above steps are repeated until the position deviation parameter corresponding to the updated current position setting parameter is within the preset position deviation range.

[0071] In an embodiment of the present invention, the positioning and calibration module 620 calculates the erosion width of a plurality of measurement points of the wafer according to the erosion edge information of the wafer obtained by image recognition, and calculates the position deviation parameter according to the erosion width of the plurality of measurement points. As shown in FIG. 12, FIG. 12 is a plan view of a 6-inch wafer with eroded edge. As shown in FIG. 13, FIG. 13 is a plan view of an 8-inch or larger than 8-inch wafer with eroded edge. Ten measurement points, i.e., measurement points 1-10, are shown in FIG. 12, and eight measurement points, i.e., measurement points 1-8, are shown in FIG. 13. As shown in FIG. 12, the wafer has a wafer flat 810, and as shown in FIG. 13, the wafer has a positioning notch 850.

[0072] The position deviation parameters include a distance deviation Δx in a first direction and a distance deviation Δy in a second direction, and the current position setting parameters include a position coordinate x1 in the first direction and a position coordinate y1 in the second direction, and the first direction and the second direction are perpendicular to each other. In this embodiment, the first direction may be the X-axis direction, and the second direction may be the Y-axis direction. Specifically, the distance deviation Δx in the first direction of the position deviation parameters represents a positioning deviation in which the center of the wafer and the center of the first support area are misaligned in the first direction (hereinafter, abbreviated as the positioning deviation in the first direction), and the distance deviation Δy in the second direction of the position deviation parameters represents a positioning deviation in which the center of the wafer and the center of the first support area are misaligned in the second direction (hereinafter, abbreviated as the positioning deviation in the second direction). The position coordinate in the first direction of the updated current position setting parameters can be obtained by the position coordinate x1 in the first direction of the current position setting parameters and the distance deviation Δx in the first direction of the position deviation parameters. The position coordinate in the second direction of the updated current position setting parameters can be obtained by the position coordinate y1 in the second direction of the current position setting parameters and the distance deviation Δy in the second direction of the position deviation parameters.

[0073] The plurality of measurement points includes a plurality of pairs of measurement points. As shown in Fig. 12, measurement points 4 and 8 form a pair, measurement points 5 and 9 form a pair, measurement points 2 and 7 form a pair, and measurement points 6 and 10 form a pair. As shown in Fig. 13, measurement points 1 and 5 form a pair, measurement points 2 and 6 form a pair, measurement points 3 and 7 form a pair, and measurement points 4 and 8 form a pair. A straight line connecting a pair of measurement points passes through the center of the wafer. That is, a pair of measurement points is located at both ends of the wafer.

[0074] The first-direction distance deviation Δx of the position deviation parameter corresponds to one or more pairs of measurement points. A straight line connecting the pairs of measurement points corresponding to the first-direction distance deviation Δx passes through the center of the wafer. In the example of FIG. 12, the three pairs of measurement points corresponding to the first-direction distance deviation Δx may be 4 and 8, 5 and 9, and 6 and 10, respectively. In another example, the first-direction distance deviation Δx may correspond only to a pair of measurement points. For example, it may correspond only to any one of the pairs of measurement points 4 and 8, 5 and 9, and 6 and 10. A plurality of first-direction distance deviations Δx may correspond to a plurality of pairs of measurement points. Similarly, in FIG. 13, the first-direction distance deviation Δx also corresponds to three pairs of measurement points, which will not be described again here. The first-direction distance deviation Δx is calculated according to the difference value of the corrosion width of each pair of measurement points in the pair of measurement points or the plurality of pairs of measurement points.

[0075] JPEG2025511692000002.jpg24170 is the corrosion width at point 6, and w10 is the corrosion width at measurement point 10. The distance deviation Δx in the first direction can also be calculated using w5 and w9, w4 and w8, and w6 and w10. In this embodiment, the distance deviation Δx in the first direction is a positive number, and the first direction position coordinate x1 d =x1±Δx. In other words, when the distance deviation Δx in the first direction is inclined in one direction of the X axis, x1 d =x1+Δx, and when the distance deviation Δx in the first direction is inclined in the other direction of the X axis, x1 d=x1-Δx. The second direction distance deviation Δy of the position deviation parameter corresponds to one or more pairs of measurement points, and a straight line connecting the pair of measurement points corresponding to the second direction distance deviation Δy passes through the center of the wafer. In the example of FIG. 12, the three pairs of measurement points corresponding to the second direction distance deviation Δy may be 4 and 8, 2 and 7, and 6 and 10, respectively. In another example, the second direction distance deviation Δy may correspond only to a pair of measurement points. For example, it may correspond only to any one of the pair of measurement points 4 and 8, 2 and 7, and 6 and 10. A plurality of second direction distance deviations Δy may correspond to a plurality of pairs of measurement points. Similarly, in FIG. 13, the second direction distance deviation Δy also corresponds to three pairs of measurement points, which will not be described again here. The second direction distance deviation Δy is calculated according to the difference value of the corrosion width of each pair of measurement points in the pair of measurement points or the plurality of pairs of measurement points. w10 is the corrosion width at measurement point 10. The distance deviation Δy in the second direction can be calculated by w2 and w7, w4 and w8, and w6 and w10. In this embodiment, the distance deviation Δy in the second direction is a positive number, and the second direction position coordinate y1 of the updated current position setting parameters is d y1 d =y1±Δy. In other words, when the distance deviation Δy in the second direction is inclined in one direction of the Y axis, y1 d =y1+Δy, and when the distance deviation Δy in the second direction is inclined in the other direction of the Y axis, y1 d =y1-Δy.

[0076] In another embodiment, the distance deviation Δx in the first direction and the distance deviation Δy in the second direction can be positive or negative. For example, the tilt in one direction can be a positive number and the tilt in the other direction can be a negative number. In this case, y1 d = y1 ± Δy, x1 d =x1±Δx.

[0077] One or more pairs of measurement points corresponding to the distance deviation Δx in the first direction and one or more pairs of measurement points corresponding to the distance deviation Δy in the second direction are overlapped. Since measurement point 4 is located at a position of 45 degrees, measurement point 8 is located at a position of 225 degrees, measurement point 6 is located at a position of 315 degrees, and measurement point 10 is located at a position of 135 degrees, the distance deviation Δx in the first direction or the distance deviation Δy in the second direction can be calculated based on the difference between the corrosion width at measurement point 4 and the corrosion width at measurement point 8 and / or the difference between the corrosion width at measurement point 6 and the corrosion width at measurement point 10.

[0078] In an embodiment of the present invention, the position deviation parameters further include a positioning angle deviation Δθ, and the current position setting parameters further include a positioning angle θ. The positioning angle of the updated current position setting parameters can be obtained by the positioning angle θ of the current position setting parameters and the positioning angle deviation Δθ of the position deviation parameters. For example, the positioning angle of the updated current position setting parameters can be θ+Δθ. The positioning angle deviation Δθ of the position deviation parameters refers to the positioning angle deviation between the wafer and the first support area. For example, as shown in FIG. 12, a 6-inch wafer has a positioning edge 810, and the positioning angle θ of the wafer and the positioning angle of the first support area do not match, so that the erosion width of the positioning edge 810 is different. The positioning angle deviation Δθ of the position deviation parameters corresponds to a number of measurement points. As shown in FIG. 12, the three measurement points corresponding to the positioning angle deviation Δθ are measurement point 1, measurement point 2, and measurement point 3. In another embodiment, the positioning angle deviation Δθ can be calculated only by two measurement points, for example, measurement point 1 and measurement point 3. The slope of the fitting straight line of the plurality of measurement points is calculated according to the difference value of the corrosion width of a predetermined plurality of measurement points and the distance between the plurality of measurement points, and the positioning angle deviation Δθ can be obtained according to the slope of the fitting straight line. For example, the distance between measurement point 1 and measurement point 3 is D1, and the slope of the fitting straight line is K=(w1-w2) / D1=tanα. In the formula, w1 is the corrosion width of measurement point 1, and w2 is the corrosion width of measurement point 2.

[0079] When 8-inch and larger wafers are used, a positioning notch 850 can be formed on the wafer without forming a wafer flat (see FIG. 13). When the positioning notch 850 is formed on the wafer, a positioning pillar can be formed at a predetermined position of the upper cavity 220 or the lower cavity 210 of the semiconductor processing device 200. The positioning pillar can be coupled to the positioning notch 850 to determine the angle of the wafer. If the angle of the wafer cannot be accurately determined by the positioning pillar, the positioning angle deviation Δθ can also be determined by the erosion width of the measurement point. Specifically, the positioning angle deviation Δθ of the position deviation parameter corresponds to one or more pairs of measurement points, and each pair of measurement points corresponding to the positioning angle deviation Δθ is located on both sides of the positioning notch 850 of the wafer, and the positioning angle deviation Δθ can be calculated by the difference value of the erosion width of each pair of measurement points in one or more pairs of measurement points. The larger the positioning angle deviation Δθ, the larger the difference value of the erosion width of the measurement points located on both sides of the positioning notch 850.

[0080] The manipulator of the present invention performs one calibration including: setting a current position setting parameter; mounting the wafer at a position corresponding to the current position setting parameter, and then etching the edge of the wafer; acquiring the etching edge and etching width of the wafer by performing image recognition on the wafer on which etching has been performed; calculating a position deviation parameter of the setting parameter of the current wafer mounting position according to the etching edge of the wafer; determining whether the position deviation parameter is within a preset position deviation range; and updating or calibrating the current position setting parameter according to the position deviation parameter if the position deviation parameter is not within the preset position deviation range. In the present invention, the position deviation parameter is made to fall within the preset position deviation range by performing multiple calibrations, and when the position deviation parameter falls within the preset position deviation range, the positioning of the wafer is stopped. When performing multiple calibrations, the process of each calibration is the same, and will not be described again here.

[0081] The position of the wafer can be accurately determined by calibrating the current position setting parameters, but after a certain time, the quality of the erosion edge of the wafer may not meet the predetermined requirement due to the temperature change, the size of the wafer changes due to different wafer production batches, or other factors change, at which time the position of the wafer can be determined again by recalibrating the current position setting parameters, so that the quality of the erosion edge of the wafer meets the predetermined requirement and the position deviation parameters are within the preset position deviation range.

[0082] The present invention can determine the position of the wafer by continuously calibrating the current positioning parameters of the manipulator. The present invention can determine the position of the wafer 100 by using the calibration method together with the protrusions of the semiconductor processing device 200, or can determine the position of the wafer 100 by the calibration method alone.

[0083] The step of the manipulator transferring the wafer to a position corresponding to the current position setting parameter according to the current position setting parameter can be performed by a conventional technique. For example, the manipulator is manually controlled so that the manipulator transfers the wafer to a predetermined position on the first support area of ​​the lower cavity of the semiconductor processing device 200 after picking up the wafer from the wafer storage unit. At that time, the control device can obtain the current position setting parameter corresponding to the predetermined position. In another embodiment, the current position setting parameter can be directly set in the control device.

[0084] In an embodiment of the present invention, a wafer positioning method is provided. Figure 14 is a flow chart showing a wafer positioning method 900 according to an embodiment of the present invention. As shown in Figure 14, the wafer positioning method 900 includes the following steps:

[0085] In step 902, the manipulator transfers the wafer to a predetermined position on the first support area of ​​the lower cavity of the semiconductor processing equipment according to the set or updated current position setting parameters, ie, a position corresponding to the current position setting parameters.

[0086] In step 904, the semiconductor processing equipment etches the edge area of ​​the wafer. The specific etching process can be seen in the above part.

[0087] In step 906, the wafer is mounted at a predetermined position according to the current position setting parameters and etched, and then image acquisition and image recognition are performed to obtain the etching edge information (e.g., etching width, etching edge line) of the wafer. For the specific process of image recognition, please refer to the items in the second and third parts.

[0088] In step 908, the positioning and calibration module calculates position deviation parameters of the current position setting parameters according to the acquired etched edge information of the wafer.

[0089] In step 910, the control device obtains an updated current position setting parameter by updating the current position setting parameter with the position deviation parameter, and controls the manipulator to transfer the wafer to a predetermined position on the first support area of ​​the lower cavity according to the updated current position setting parameter, i.e., a position corresponding to the updated current position setting parameter.

[0090] In an embodiment of the present invention, after calculating the position deviation parameter of the current position setting parameter, the positioning and calibration module further determines whether the position deviation parameter is within a preset position deviation range. If the position deviation parameter is within the preset position deviation range, the update of the current position setting parameter is stopped; if the position deviation parameter is not within the preset position deviation range, the current position setting parameter is updated by the position deviation parameter. Then, after re-acquiring the etched edge of the wafer with the updated current position setting parameter, the position deviation parameter of the updated current position setting parameter is calculated again, and the above steps are repeated until the position deviation parameter corresponding to the updated current position setting parameter is within the preset position deviation range.

[0091] Other details of the wafer positioning method 900 can be referred to certain details described in the wafer positioning system, and will not be described again here.

[0092] Although specific embodiments of the present invention have been described above, the embodiments are merely illustrative of the present invention and do not limit the present invention. The specific embodiments are merely illustrative of the present invention, and the present invention is not limited to the embodiments. The scope of the present invention is defined by the claims of this application and the equivalents of the claims.

[0093] In this specification, "one embodiment" or "embodiment" refers to a feature, structure, or characteristic of the embodiment being included in at least one embodiment of the present invention. When the term "in one embodiment" is used in various places in this specification, it does not refer to only the same embodiment, nor does it refer to only one embodiment or a specific embodiment that excludes other embodiments. In the present invention, the terms "multiple" and "plural" refer to two or more items. In the present invention, the term "and / or" refers to a relationship of "and" or "alternative." In the present invention, terms with "first," "second," "third," "fourth," etc., are used to distinguish between different items, and are not intended to limit the order of each item. In the present invention, each term is used to describe a specific item, and is not intended to limit the order of each item.

[0094] It should be noted that in other embodiments, the functions / acts of the invention may be performed out of the order shown in the figures. For example, functions / acts shown in two figures may be performed simultaneously or in a conflicting order.

[0095] It should be noted that although the steps of the method of the present invention have been described in a specific order, other steps can be added between any two steps. The steps of the method of the present invention can be adjusted so that each step takes a different time to be performed or each step is performed by different systems, which can perform multiple steps simultaneously.

[0096] When a person skilled in the art implements various modifications and other embodiments of the present invention, it is assumed that the person skilled in the art has common knowledge and some basic data in the art. It should be noted that the present invention is not limited to the above-described embodiment, but may further include other embodiments within the scope of the present invention. Although the above-described embodiment and specific drawings have been used to describe elements and functions related to the specific embodiment, it is obvious that other elements and functions included in the claims of the present application are also included in the present invention. The claims of the present application may further include not only the elements and items clearly described above, but also other elements, items, and combinations thereof that are different from them. Although specific terms have been used in this specification, they are for describing the present invention, and do not limit the present invention.

Claims

1. a semiconductor processing device, an image edge detection device, a wafer transport device, and a positioning and calibration module; The semiconductor processing apparatus includes a lower cavity in which a first support area is formed and an upper cavity in which a second support area is formed, and when the upper cavity and the lower cavity are joined, a wafer is placed between the first support area and the second support area, a first passage is formed in an edge area of ​​the first support area and / or the second support area, a first space is formed by the first passage, and one or more chemical fluids are injected into the first space to corrode the edge area of ​​the wafer; The wafer transport device includes a manipulator and a control device, the control device sets or updates a current position setting parameter, and the manipulator transports the wafer to a predetermined position on a first support area of ​​a lower cavity of the semiconductor processing device according to the set or updated current position setting parameter, i.e., a position corresponding to the current position setting parameter; the image edge detection device acquires an etching edge of the wafer by collecting and recognizing images of the wafer that is mounted at a predetermined position according to the current position setting parameters and that has been subjected to etching; The positioning and calibration module calculates a position deviation parameter of a current position setting parameter according to the etching edge information of the wafer obtained by image recognition; the control device obtains an updated current position setting parameter by updating a current position setting parameter with the position deviation parameter, and controls the manipulator to transfer the wafer to a predetermined position on the first support area of ​​the lower cavity, i.e., a position corresponding to the updated current position setting parameter, using the updated current position setting parameter.

2. 2. The wafer positioning system of claim 1 , wherein the positioning and calibration module, after calculating a position deviation parameter of a current position setting parameter, judges whether the position deviation parameter is within a preset position deviation range, stops updating the current position setting parameter if the position deviation parameter is within the preset position deviation range, updates the current position setting parameter by the position deviation parameter if the position deviation parameter is not within the preset position deviation range, then re-acquires the etched edge of the wafer with the updated current position setting parameter, and then re-calculates the position deviation parameter of the updated current position setting parameter, and repeats the steps until the position deviation parameter corresponding to the updated current position setting parameter is within the preset position deviation range.

3. 2. The wafer positioning system of claim 1 , wherein the positioning and calibration module calculates the corrosion widths of a plurality of measurement points on the wafer according to the corrosion edge information of the wafer obtained by image recognition, and calculates the position deviation parameters according to the corrosion widths of the plurality of measurement points.

4. The position deviation parameters include a distance deviation in a first direction and a distance deviation in a second direction, the current position setting parameters include a position coordinate in the first direction and a position coordinate in the second direction, and the first direction and the second direction are perpendicular to each other; 4. The wafer positioning system of claim 3, wherein the updated position coordinate in the first direction of the current position setting parameters is obtained based on the position coordinate in the first direction of the current position setting parameters and the distance deviation in the first direction of the position deviation parameters, and the updated position coordinate in the second direction of the current position setting parameters is obtained based on the position coordinate in the second direction of the current position setting parameters and the distance deviation in the second direction of the position deviation parameters.

5. a distance deviation in a first direction of the position deviation parameter represents a positioning deviation in which a center of the wafer and a center of the first support area are misaligned in a first direction; 5. The wafer positioning system of claim 4, wherein the distance deviation in the second direction of the position deviation parameter represents a positioning deviation in which the center of the wafer and the center of the first support area are misaligned in the second direction.

6. 5. The wafer positioning system of claim 4, wherein the plurality of measurement points include a plurality of pairs of measurement points, the distance deviation in the first direction of the position deviation parameter corresponds to one or more pairs of measurement points, a straight line connecting the pair of measurement points corresponding to the distance deviation in the first direction passes through the center of the wafer, and the distance deviation in the first direction is calculated based on a difference value of the corrosion width of each pair of measurement points for the pair of measurement points or the plurality of pairs of measurement points; or the distance deviation in the second direction of the position deviation parameter corresponds to one or more pairs of measurement points, a straight line connecting the pair of measurement points corresponding to the distance deviation in the second direction passes through the center of the wafer, and the distance deviation in the second direction is calculated based on a difference value of the corrosion width of each pair of measurement points for the pair of measurement points or the plurality of pairs of measurement points.

7. 7. The wafer positioning system of claim 6, wherein one or more pairs of measurement points corresponding to the distance deviation in the first direction and one or more pairs of measurement points corresponding to the distance deviation in the second direction overlap.

8. 5. The wafer positioning system of claim 4, wherein the position deviation parameters further include a positioning angle deviation, the current position setting parameters further include a positioning angle, the positioning angle of the updated current position setting parameters is obtained according to the positioning angle of the current position setting parameters and the positioning angle deviation of the position deviation parameters, and the positioning angle deviation of the position deviation parameters refers to the positioning angle deviation between the wafer and the first support area.

9. The positioning angle deviation of the position deviation parameter corresponds to a plurality of measurement points, and a slope rate of a fitting line of the plurality of measurement points is calculated according to a difference value of corrosion width of a predetermined plurality of measurement points and a distance between the plurality of measurement points, and the positioning angle deviation is obtained according to the slope rate of the fitting line; or 9. The wafer positioning system of claim 8, wherein the positioning angle deviation of the position deviation parameter corresponds to one or more pairs of measurement points, each pair of measurement points corresponding to the positioning angle deviation is located on both sides of a positioning notch of the wafer, and the positioning angle deviation is calculated according to a difference value of the corrosion width of each pair of measurement points in the one or more pairs of measurement points.

10. A first passage is formed in the peripheral area of ​​the second support area, and one or more chemical fluids flow between the first space and the outside of the semiconductor processing device through a first through hole formed in the upper cavity; or 2. The wafer positioning system of claim 1, wherein a first passage is formed in the peripheral area of ​​the first support area, the lower cavity includes a first through hole, and one or more chemical fluids flow between the first space and the outside of the semiconductor processing device through the first through hole formed in the lower cavity.

11. the manipulator transfers the wafer to a predetermined position on the first support area of ​​the lower cavity of the semiconductor processing device according to the set or updated current position setting parameters, i.e., a position corresponding to the current position setting parameters; The semiconductor processing equipment etches an edge area of ​​the wafer; acquiring etching edge information of the wafer by performing image acquisition and image recognition on the wafer that has been mounted at a predetermined position according to the current position setting parameters and has been etched; The positioning and calibration module calculates a position deviation parameter of a current position setting parameter according to the acquired etching edge information of the wafer; a control device updating a current position setting parameter with the position deviation parameter to obtain an updated current position setting parameter, and controlling the manipulator to transfer the wafer to a predetermined position on the first support area of ​​the lower cavity using the updated current position setting parameter, i.e., a position corresponding to the updated current position setting parameter.

12. 12. The method of claim 11, further comprising: after calculating a position deviation parameter of a current position setting parameter, determining whether the position deviation parameter is within a preset position deviation range, stopping updating the current position setting parameter if the position deviation parameter is within the preset position deviation range; updating the current position setting parameter by the position deviation parameter if the position deviation parameter is not within the preset position deviation range; then re-acquiring the eroded edge of the wafer with the updated current position setting parameter, re-calculating the position deviation parameter of the updated current position setting parameter, and repeating the steps until the position deviation parameter corresponding to the updated current position setting parameter is within the preset position deviation range.

13. 12. The wafer positioning method of claim 11, wherein the positioning and calibration module calculates corrosion widths of a plurality of measurement points on the wafer according to corrosion edge information of the wafer obtained by image recognition, and calculates the position deviation parameter according to the corrosion widths of the plurality of measurement points.

14. The position deviation parameters include a distance deviation in a first direction and a distance deviation in a second direction, the current position setting parameters include a position coordinate in the first direction and a position coordinate in the second direction, and the first direction and the second direction are perpendicular to each other; 14. The wafer positioning method according to claim 13, further comprising: obtaining an updated position coordinate in the first direction of the current position setting parameter based on a position coordinate in the first direction of the current position setting parameter and a distance deviation in the first direction of the position deviation parameter; and obtaining an updated position coordinate in the second direction of the current position setting parameter based on a position coordinate in the second direction of the current position setting parameter and a distance deviation in the second direction of the position deviation parameter.

15. 15. The method of claim 14, wherein the plurality of measurement points include a plurality of pairs of measurement points, the distance deviation in a first direction of the position deviation parameter corresponds to one or more pairs of measurement points, a straight line connecting the pair of measurement points corresponding to the distance deviation in the first direction passes through the center of the wafer, and the distance deviation in the first direction is calculated according to a difference value of the corrosion width of each pair of measurement points for the pair of measurement points or the plurality of pairs of measurement points; or the distance deviation in a second direction of the position deviation parameter corresponds to one or more pairs of measurement points, a straight line connecting the pair of measurement points corresponding to the distance deviation in the second direction passes through the center of the wafer, and the distance deviation in the second direction is calculated according to a difference value of the corrosion width of each pair of measurement points for the pair of measurement points or the plurality of pairs of measurement points.

16. the position deviation parameters further include a positioning angle deviation, the current position setting parameters further include a positioning angle, and a positioning angle of the updated current position setting parameters is obtained according to the positioning angle of the current position setting parameters and the positioning angle deviation of the position deviation parameters, and the positioning angle deviation of the position deviation parameters refers to a positioning angle deviation between the wafer and the first supporting area; The positioning angle deviation of the position deviation parameter corresponds to a plurality of measurement points, and a slope rate of a fitting line of the plurality of measurement points is calculated according to a difference value of corrosion width of a predetermined plurality of measurement points and a distance between the plurality of measurement points, and the positioning angle deviation is obtained according to the slope rate of the fitting line; or 15. The wafer positioning method according to claim 14, wherein the positioning angle deviation of the position deviation parameter corresponds to one or more pairs of measurement points, each pair of measurement points corresponding to the positioning angle deviation is located on both sides of a positioning notch of a wafer, and the positioning angle deviation is calculated according to a difference value of the corrosion width of each pair of measurement points in the one or more pairs of measurement points.

17. 12. The wafer positioning method of claim 11, wherein the semiconductor processing apparatus includes a lower cavity in which a first support area is formed and an upper cavity in which a second support area is formed, and when the upper cavity and the lower cavity are coupled, the wafer is loaded between the first support area and the second support area, a first passage is formed in an edge area of ​​the first support area or the second support area, a first space is formed by the first passage, and the edge area of ​​the wafer is etched by one or more chemical fluids injected into the first space.

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