Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes an insulating layer, a circuit layer disposed on the insulating layer, and a protective layer disposed on the insulating layer, the circuit layer including a 1-1 pad and a 1-2 pad spaced apart from each other in a first horizontal direction, the protective layer surrounding at least a portion of the side surfaces of the 1-1 pad and the 1-2 pad, a first protective pattern provided between the 1-1 pad and the 1-2 pad, and a second protective pattern surrounding the first protective pattern, an upper surface of the first protective pattern being located lower than upper surfaces of the 1-1 pad and the 1-2 pad, and an upper surface of the second protective pattern being located higher than upper surfaces of the 1-1 pad and the 1-2 pad, and the 1-1 pad and the 1-2 pad each having a width in the first horizontal direction and a width in a second horizontal direction perpendicular to the first horizontal direction that are different from each other.

Description

[Technical field]

[0001] The embodiments relate to a circuit board and a semiconductor package including the same. [Background technology]

[0002] 2. Description of the Related Art In general, a printed circuit board (PCB) is a laminated structure in which insulating layers and conductor layers are alternately laminated, and the conductor layers can be formed into a circuit pattern by patterning.

[0003] Such a printed circuit board is provided with a solder resist SR, which protects the circuit formed on the outermost layer of the laminate, prevents oxidation of the conductor layer, and acts as an insulator when electrically connecting to a chip mounted on the printed circuit board or to another board.

[0004] In general solder resist, an opening area SRO (Solder Resist Opening) is formed to be an electrical connection path when a connecting means such as solder or bump is combined, and as the performance and density of printed circuit boards increase, the I / O (Input / Output) performance is improved, so more opening areas are required in the solder resist, and therefore a small bump pitch is required in the opening area. At this time, the bump pitch of the opening area of ​​the solder resist means the center distance between adjacent opening areas.

[0005] Meanwhile, the solder resist opening region SRO includes a solder mask defined type (SMD) and a non-solder mask defined type (NSMD).

[0006] The NSMD type is characterized in that the width of the opening region SRO is smaller than the width of the pad exposed through the opening region SRO, whereby in the SMD type, at least a portion of the upper surface of the pad is covered by the solder resist.

[0007] In addition, the NSMD type is characterized in that the width of the opening region SRO is larger than the width of the pad exposed through the opening region SRO. Thus, in the NSMD type, the solder resist is disposed at a constant distance from the pad, thereby exposing both the top and side surfaces of the pad.

[0008] However, in the case of the SMD type, there is a problem that the solder balls are separated from the pads exposed through the opening region SRO during a solder ball joint reliability test for the bonding strength of the solder balls after the semiconductor package is attached to the main board. Also, in the case of the NSMD type, there is a problem that the pads on which the solder balls are placed are separated from the board. For this reason, the SMD type and the NSMD type have been appropriately combined and applied to one circuit board in the past.

[0009] At this time, the conventional circuit board provides a space in which a device such as a multi-layered ceramic capacitor (MLCC) is mounted. At this time, the solder resist in the space in the conventional circuit board in which the multi-layered ceramic capacitor is disposed is of an SMD type. As a result, a semiconductor package in which the multi-layered ceramic capacitor is mounted on the conventional circuit board has a problem in that the overall thickness is increased by the thickness of the solder resist.

[0010] To solve this problem, a conventional multilayer ceramic capacitor does not have a solder resist disposed in the space where the multilayer ceramic capacitor is disposed, and an adhesive member such as a solder ball has a structure that extends along the side of the pad, so that the structure without the solder resist has a short circuit problem in which the adhesive members disposed on the adjacent pads are interconnected.

[0011] (Patent Document 1) JP10-2013-0046726A

[0012] (Patent Document 2) JP10-1877963B Summary of the Invention [Problem to be solved by the invention]

[0013] The embodiments are intended to provide a slimmable circuit board and a semiconductor package including the same.

[0014] Also, the embodiments provide a circuit board capable of reducing the spacing between adjacent pads and a semiconductor package including the same.

[0015] Also, the embodiments provide a circuit board and a semiconductor package including the same that can solve the short-circuit problem between adhesive members disposed on pads.

[0016] Also, the embodiments provide a circuit board and a semiconductor package including the same with improved physical reliability and electrical reliability.

[0017] Also, the embodiments provide a circuit board and a semiconductor package including the same that can solve the problem of an adhesive material penetrating between an insulating layer and a pad.

[0018] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the art to which the proposed embodiments pertain from the following description. [Means for solving the problem]

[0019] A circuit board according to an embodiment includes an insulating layer, a circuit layer disposed on the insulating layer, and a protective layer disposed on the insulating layer, the circuit layer including a 1-1 pad and a 1-2 pad spaced apart from each other in a first horizontal direction, the protective layer surrounding at least a portion of the side surfaces of the 1-1 pad and the 1-2 pad, a first protective pattern provided between the 1-1 pad and the 1-2 pad, and a second protective pattern surrounding the first protective pattern, an upper surface of the first protective pattern is located lower than upper surfaces of the 1-1 pad and the 1-2 pad, an upper surface of the second protective pattern is located higher than upper surfaces of the 1-1 pad and the 1-2 pad, and the 1-1 pad and the 1-2 pad have different widths in the first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction.

[0020] The thickness of the first protection pattern is in the range of 40% to 90% of the thickness of at least one of the 1-1 pad and the 1-2 pad.

[0021] At least one of the 1-1 pad and the 1-2 pad has a thickness in the range of 10 μm to 25 μm, and the first protection pattern has a thickness in the range of 3 μm to 21 μm.

[0022] In addition, the vertical distance between the upper surface of at least one of the 1-1 pad and the 1-2 pad and the upper surface of the first protection pattern satisfies 3 μm to 10 μm.

[0023] In addition, an upper surface of at least one of the 1-1 pad and the 1-2 pad includes a curved surface, and the vertical distance is the vertical distance from the uppermost end of the upper surface of at least one of the 1-1 pad and the 1-2 pad to the uppermost end of the first protection pattern.

[0024] The thickness of the second protection pattern falls within the range of 17 μm to 45 μm.

[0025] Moreover, the width in the second horizontal direction of each of the 1-1 pad and the 1-2 pad is in the range of 125% to 220% of the width in the first horizontal direction of each of the 1-1 pad and the 1-2 pad.

[0026] Moreover, the interval between the 1-1 pad and the 1-2 pad satisfies the range of 70% to 120% of the width of each of the 1-1 pad and the 1-2 pad in the first horizontal direction.

[0027] In addition, an inner wall of the second protection pattern is spaced apart from a side surface of at least one of the 1-1 pad and the 1-2 pad by a distance of 15 μm to 23 μm.

[0028] The first protection pattern is provided to partially surround side surfaces of the 1-1 pad and the 1-2 pad, and at least a portion of the second protection pattern is in contact with a side surface of the 1-1 pad or a side surface of the 1-2 pad.

[0029] In addition, the 1-1 pad includes a 1-1 side facing the 1-2 pad and a 1-2 side excluding the 1-1 side, the 1-2 pad includes a 2-1 side facing the 1-1 side and a 2-2 side excluding the 2-1 side, and the second protection pattern is in direct contact with at least a portion of the 1-2 side of the 1-1 pad and the 2-2 side of the 1-2 pad.

[0030] The circuit layer further includes a second pad and a second trace, the second pad having a width in the range of 3 μm to 30 μm, the second trace having a width in the range of 1 μm to 10 μm, and a spacing between the second pad and the second trace in the range of 1 μm to 10 μm.

[0031] Further, the second pads are provided in plurality, the second traces are provided in plurality, and the protective layer has a through hole vertically overlapping the plurality of second pads, the plurality of second traces, and an area between the plurality of second pads and the plurality of second traces.

[0032] Further, the second pads are provided in plurality, the second traces are provided in plurality, and the protective layer further includes a third protective pattern provided between the plurality of second pads and the plurality of second traces, and the third protective pattern does not vertically overlap the second pads and the second traces.

[0033] Additionally, the top surface of the third protection pattern is located lower than the top surfaces of the second pads and the second traces.

[0034] Moreover, the circuit layer further includes a plurality of third pads and a plurality of third traces, the width of the third pads being within a range of 30 μm to 70 μm, and the spacing between the third pads and the third traces being within a range of 10 μm to 40 μm.

[0035] The protective layer further includes a fourth protective pattern having a width smaller than a width of the third pad and overlapping the third pad in a vertical direction. Effect of the Invention

[0036] The circuit board of the embodiment includes a first region in which a first semiconductor element is disposed.

[0037] The circuit board also includes a 1-1 pad and a 1-2 pad. The 1-1 pad and the 1-2 pad are provided so as to vertically overlap the first semiconductor element. Exemplarily, the 1-1 pad and the 1-2 pad are provided in a first region of the circuit board. The embodiment also includes a protective layer. The protective layer is provided surrounding at least a part of the side surfaces of the 1-1 pad and the 1-2 pad, and includes a first protective pattern disposed between the 1-1 pad and the 1-2 pad. The protective layer also includes a second protective pattern provided surrounding the periphery of the first protective pattern.

[0038] The first protective pattern contacts at least a part of the side of the 1-1 pad and the 1-2 pad without contacting the upper surfaces of the 1-1 pad and the 1-2 pad. For example, the upper surface of the first protective pattern is located lower than the upper surfaces of the 1-1 pad and the 1-2 pad. Therefore, the embodiment can reduce the thickness and width of the contact member disposed on the 1-1 pad and the 1-2 pad by using the first protective pattern.

[0039] For example, in the first comparative example, the thickness of the contact member was increased due to the provision of the protective layer, while in the second comparative example, the degree of expansion of the contact member was greater due to the absence of the protective layer, thereby increasing the width of the contact member.

[0040] In contrast, the embodiment may reduce the width of the contact member by reducing the degree of expansion of the contact member using a combination of the first and second protective patterns. Also, in the embodiment, only the first protective pattern is provided in the region vertically overlapping with the first semiconductor element. Exemplarily, the second protective pattern does not vertically overlap with the first semiconductor element. Therefore, the embodiment may prevent the contact member from increasing in height due to the height of the protective layer.

[0041] As a result, the embodiment can reduce the thickness of the semiconductor package, thereby achieving miniaturization. Furthermore, the embodiment can solve the short circuit problem caused by the connection between adjacent contact members by reducing the degree of expansion of the contact members. As a result, the embodiment can improve the electrical reliability and product reliability of the semiconductor package. Furthermore, by solving the short circuit problem in the embodiment, it is not necessary to increase the distance between the 1-1 pad and the 1-2 pad, thereby improving the circuit integration.

[0042] In addition, the embodiment can solve the problem of the adhesive material penetrating between the insulating layer and the pad by using the first protection pattern, thereby further improving product reliability. [Brief description of the drawings]

[0043] [Figure 1] 1 is a cross-sectional view of a semiconductor package according to a first comparative example. [Diagram 2] FIG. 11 is a cross-sectional view of a semiconductor package according to a second comparative example. [Diagram 3] 1 is a cross-sectional view showing an overall layer structure of a circuit board according to an embodiment of the present invention; [Figure 4] 4 is a diagram showing the structure of a second region of the circuit board in the first embodiment. FIG. [Diagram 5] FIG. 11 is a diagram showing the structure of a second region of a circuit board according to a second embodiment. [Figure 6] 6 is a diagram showing the structure of a third region of the circuit board in the embodiment. FIG. [Figure 7a] FIG. 2 is a plan view of a first region of the circuit board according to the first embodiment. [Figure 7b] FIG. 7b is a cross-sectional view taken along the CC' direction in FIG. 7a. [Figure 7c] FIG. 7b is a cross-sectional view taken along the direction DD' of FIG. 7a. [Figure 8] 1 is a perspective view showing a semiconductor element mounted in a first region of a circuit board according to an embodiment; [Figure 9] FIG. 11 is a plan view of a first region of a circuit board according to a second embodiment. [Figure 10a] FIG. 11 is a plan view of a first region of a circuit board according to a third embodiment. [Figure 10b] 10b is a cross-sectional view taken along the EE' direction in FIG. 10a. [Figure 10c] 10b is a cross-sectional view taken along the line FF' in FIG. 10b. [Figure 10d] FIG. 10c shows a variation of the structure of FIG. [Figure 11a] FIG. 13 is a plan view of a first region of a circuit board according to a fourth embodiment. [Figure 11b] 10b is a cross-sectional view taken along the direction GG' of FIG. 10a. [Figure 12] 1 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention. [Figure 13a] 13 is an enlarged view of a layout region of a first semiconductor element in FIG. 12 according to the first embodiment. [Figure 13b] 13 is an enlarged view of a layout region of a first semiconductor element in FIG. 12 according to a second embodiment. [Figure 14] 1A to 1C are diagrams showing a process for manufacturing a circuit board according to an embodiment of the present invention in order of steps. [Figure 15] 1A to 1C are diagrams showing a process for manufacturing a circuit board according to an embodiment of the present invention in order of steps. [Figure 16] 1A to 1C are diagrams showing a process for manufacturing a circuit board according to an embodiment of the present invention in order of steps. [Figure 17] 1A to 1C are diagrams showing a process for manufacturing a circuit board according to an embodiment of the present invention in order of steps. [Figure 18] 1A to 1C are diagrams showing a process for manufacturing a circuit board according to an embodiment of the present invention in order of steps. [Figure 19] 1A to 1C are diagrams showing a process for manufacturing a circuit board according to an embodiment of the present invention in order of steps. [Figure 20] 1A to 1C are diagrams showing a process for manufacturing a circuit board according to an embodiment of the present invention in order of steps. [Figure 21] 1A to 1C are diagrams showing a process for manufacturing a circuit board according to an embodiment of the present invention in order of steps. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0044] Hereinafter, the embodiments disclosed in the present specification will be described in detail with reference to the attached drawings. The same or similar components will be given the same reference numerals regardless of the drawing numbers, and the duplicated description thereof will be omitted. The suffixes "module" and "part" for components used in the following description are given or mixed to facilitate the preparation of the specification, and do not have a mutually distinguishing meaning or role by themselves. In addition, in the description of the embodiments disclosed in the present specification, if a detailed description of the related known technology is determined to interfere with the gist of the embodiments disclosed in the present specification, the detailed description thereof will be omitted. In addition, the attached drawings are provided to facilitate the understanding of the embodiments disclosed in the present specification, and the technical ideas disclosed in the present specification are not limited by the attached drawings, and it should be understood that the drawings include all modifications, equivalents, or alternatives included in the ideas and technical scope of the present invention.

[0045] Terms including ordinal numbers such as first, second, etc. may be used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another component.

[0046] When a component is referred to as being "coupled" or "connected" to another component, it should be understood that the component may be directly "coupled" or "connected" to the other component, and that there may be other components in between. On the other hand, when a component is referred to as being "directly coupled" or "directly connected" to another component, it should be understood that there are no other components in between.

[0047] A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0048] In this application, terms such as "comprise" or "have" are intended to specify the presence of any features, numbers, steps, operations, components, parts, or combinations thereof set forth in the specification, but are to be understood as not precluding the presence or additional possibility of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0049] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0050] -Comparative Example-

[0051] Prior to describing the embodiments, a comparative example to be compared with the circuit board of the embodiments of the present application will be described.

[0052] FIG. 1 is a cross-sectional view of a semiconductor package according to a first comparative example, and FIG. 2 is a cross-sectional view of a semiconductor package according to a second comparative example.

[0053] Referring to FIG. 1, a semiconductor package according to a first comparative example includes a circuit board and an element mounted on the circuit board.

[0054] The circuit board of the first comparative example includes an insulating layer 10, a circuit layer 20, and a protective layer 30.

[0055] The circuit layer 20 is disposed on the upper surface of the insulating layer 10. The circuit layer 20 may represent the outermost layer of multiple circuit layers disposed on a circuit board. For example, the circuit layer 20 represents the circuit layer in an area where a chip is mounted on the circuit board.

[0056] For example, the circuit layer 20 represents the pads on which the multilayer ceramic capacitors are placed.

[0057] A protective layer 30 is disposed on the insulating layer 10 .

[0058] At this time, the protective layer 30 is disposed on the insulating layer 10 with a constant thickness. Specifically, the protective layer 30 is disposed on the insulating layer 10 with a thickness that is greater than the thickness of the circuit layer 20.

[0059] The protective layer 30 includes an opening (not shown) that overlaps with the upper surface of the circuit layer 20 in the thickness direction. The planar area of ​​the opening of the protective layer 30 is smaller than the planar area of ​​the circuit layer 20. That is, the protective layer 30 is disposed so as to cover a portion of the upper surface of the circuit layer 20. The protective layer 30 overlaps with at least a portion of the upper surface of the circuit layer 20 in the thickness direction, and thus does not contact at least a portion of the upper surface of the circuit layer 20.

[0060] An adhesive member 50 is disposed in the opening of the protective layer 30. The adhesive member 50 may be a solder ball.

[0061] The element 40 may be mounted on the circuit layer 20 via an adhesive member 50. The element 40 has a structure in which a main body 41 and terminals 42 are formed on both sides of the main body 41. That is, the element 40 is a passive element. For example, the element 40 is a multilayer ceramic capacitor.

[0062] At this time, in the first comparative example, the protective layer 30 in the region where the element 40 is mounted is disposed higher than the upper surface of the circuit layer 20. As a result, in the first comparative example, there is a problem that the overall thickness of the semiconductor package increases by the protruding thickness of the protective layer 30.

[0063] That is, the circuit layer 20 includes a pad electrically connected to the element 40. The pad has a size corresponding to the terminal 42 of the element 40. For example, the width w1 of the pad in the first horizontal direction exceeds 140 μm. For example, the width w1 of the pad in the first horizontal direction exceeds 190 μm. For example, the width w1 of the pad in the first horizontal direction exceeds 300 μm. For example, the width w1 of the pad in the first horizontal direction exceeds 450 μm. The first horizontal direction refers to the spacing direction of the multiple terminals 42 of the element 40.

[0064] In addition, in the circuit board of the first comparative example, the interval w2 between the multiple pads connected to the element 40 exceeds 120 μm. For example, in the circuit board of the first comparative example, the interval w2 between the multiple pads connected to the element 40 exceeds 200 μm. For example, in the circuit board of the first comparative example, the interval w2 between the multiple pads connected to the element 40 exceeds 300 μm.

[0065] On the other hand, the maximum width w3 of the adhesive member 50 in the first horizontal direction has a level similar to the width w1 of the pad. For example, the maximum width w3 of the adhesive member 50 in the first horizontal direction has a level of 80% to 105% of the width of the pad.

[0066] On the other hand, the thickness t1 of the circuit layer 20 in the first comparative example is in the range of 10 μm to 20 μm. In addition, the thickness t2 of the portion of the protective layer 30 that protrudes above the upper surface of the circuit layer 20 is in the range of 7 μm to 20 μm.

[0067] At this time, the adhesive member 50 is disposed to have a certain thickness t3 from the upper surface of the protective layer 30. The thickness t3 is set based on the condition that allows the element 40 to be stably mounted on the circuit layer 20.

[0068] At this time, the thickness t3 in the first comparative example is set based on the upper surface of the protective layer 30, not the upper surface of the circuit layer 20. That is, if the thickness t3 is set based on the upper surface of the circuit layer 20, a problem may occur in which a part of the element 40 comes into contact with the upper surface of the protective layer 30 during the mounting process of the element 40. This may result in the element 40 being mounted in a misaligned state.

[0069] As a result, the thickness t4 from the upper surface of the insulating layer 10 to the upper surface of the element 40 in the first comparative example reflects not only the thickness t1 of the circuit layer 20 and the thickness t3 of the adhesive member 50, but also the thickness t2 of the protruding portion of the protective layer 30. Therefore, the first comparative example has a problem in that the overall thickness of the structure in which the element 40 is mounted increases by the thickness t2 of the protruding portion of the protective layer 30.

[0070] On the other hand, in the second comparative example in FIG. 2, in order to solve the problem of the first comparative example, the protective layer 30 is not disposed in the region where the element 40 is disposed.

[0071] At this time, the protective layer 30 may not be disposed in the region where the circuit layer 20 is disposed, and therefore, the circuit layer 20 has a structure in which no insulating member is provided between the pads. As a result, in the second comparative example, there is a problem that dendrites are generated between the pads. Exemplarily, a circuit board on which a semiconductor device is mounted is applied with a voltage corresponding to the driving power of the semiconductor device, and the metal forming the pads grows on the dendrites due to the applied voltage, causing an electrical problem in which two adjacent pads are shorted to each other, which means a short circuit due to the occurrence of migration. Exemplarily, when a certain level of voltage is applied to the circuit layer, metal ions may grow on the dendrites from the positive polarity pattern to the negative polarity pattern, causing an electrical problem in which the pads are shorted to each other.

[0072] In addition, the second comparative example can reduce the thickness of the semiconductor package by the thickness t2 of the protruding portion of the protective layer 30 in the first comparative example. The thickness t4' between the insulating layer 10 and the element 40 in the second comparative example may be smaller than the thickness t4 in the first comparative example by the thickness t2 of the protruding portion of the protective layer 30.

[0073] Furthermore, in the second comparative example, since the protective layer 30 is not present, there is a problem that the width of the adhesive member 50 becomes relatively large.

[0074] Specifically, the adhesive member 50 is disposed on the circuit layer 20. At this time, in a state in which the adhesive member 50 is disposed on the circuit layer 20, the adhesive member 50 has a structure in which it is disposed along the surface of the circuit layer 20, which is made of metal.

[0075] At this time, in the first comparative example, since the adhesive member 50 does not contact the side surface of the circuit layer 20, the width w3 of the adhesive member 50 was at the same level as the width w1 of the pad of the circuit layer 20.

[0076] In contrast, the second comparative example has a structure in which the side surfaces of the circuit layer 20 are entirely exposed. As a result, the adhesive member 50 of the second comparative example is disposed so as to cover not only the top surface of the circuit layer 20 but also the entire side surfaces.

[0077] That is, the width w3' of the adhesive member 50 in the second comparative example is larger than the width of the pad of the circuit layer 20. Specifically, the width w3' of the adhesive member 50 in the second comparative example is more than 130% of the width of the pad. More specifically, the width w3' of the adhesive member 50 in the second comparative example is more than 140% of the width of the pad.

[0078] At this time, the element 40 includes two terminals 42. In the second comparative example, the adhesive member 50 has a structure in which it is expanded along the side surface of the circuit layer 20, so that the gap between the two adhesive members contacting the two terminals is narrowed. The gap between the two adhesive members is narrowed as the thickness or width of the circuit layer 20 increases. As a result, the structure in the second comparative example in which the protective layer 30 is not disposed has a problem of the gap between the two contact members being narrowed. Furthermore, in the second comparative example, there is a problem of a short circuit occurring in which the two adhesive members come into contact with each other depending on the degree of expansion of the adhesive member 50. In the second comparative example, the gap w2 between the two pads is made larger than that in the first comparative example to solve the short circuit problem. As a result, the semiconductor package in the second comparative example can be made thinner than the semiconductor package in the first comparative example, but has a problem of a large horizontal size due to a problem of a decrease in circuit integration density.

[0079] Recently, as the performance of electric / electronic products has improved, research has been conducted into technologies for mounting more devices on a board of limited size, which has led to a demand for finer widths and spacing between circuit layers. However, in the case of the semiconductor packages of the first and second comparative examples, it is difficult to reduce the overall thickness, or there is a limit to reducing the spacing between circuit layers due to the problem of short circuits. In addition, the increase in functions processed by an application processor (AP) has made it difficult to realize this as a single chip. However, in the comparative example, it can be difficult to mount two application processors (APs) or multiple passive elements that perform different functions within a limited space.

[0080] The embodiment is intended to solve the problem of the comparative example, and divides the circuit board into a plurality of regions, and the protective layers in the plurality of regions have different open structures. As a result, the embodiment makes it possible to reduce the distance between pads on which elements are mounted without increasing the overall thickness of the semiconductor package. Through this, the embodiment makes it possible to improve the integration of the circuit board and mount a plurality of chips on one circuit board. For example, the embodiment makes it possible to provide a circuit board with a new structure in which a plurality of processor chips and memory chips performing different functions can all be mounted on one circuit board, and a semiconductor package including the same.

[0081] -Electronic Devices-

[0082] Prior to the description of the embodiment, an electronic device including a semiconductor package of the embodiment will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiment. Various chips may be mounted on the semiconductor package. The semiconductor package may mainly include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory, central processors (e.g., CPUs), graphic processors (e.g., GPUs), antenna chips, digital signal processors, encryption processors, microprocessors, and microcontrollers, logic chips such as analog-to-digital converters and application-specific ICs (ASICs), and passive chips.

[0083] Specifically, at least one chip may be mounted in the semiconductor package of the embodiment, and the chip may include at least one of a processor chip, a passive chip, and an active chip. Specifically, electronic components such as chips may be mounted in the semiconductor package. The chip may be either an active chip or a passive chip. An active chip is a chip that actively uses a nonlinear part of the signal characteristics. Note that a passive chip means a chip that does not use a nonlinear signal characteristic even if both a linear signal and a nonlinear signal characteristic exist. For example, an active chip may include a transistor, an IC semiconductor chip, etc., and a passive chip may include a capacitor, a resistor, an inductor, etc. A passive chip may increase the signal processing speed of a semiconductor chip that is an active chip, or perform a filtering function, etc. In addition, the chip may be a wireless communication chip that can be used for wi-fi or 5G communication.

[0084] On the other hand, the product group to which the semiconductor package of the embodiment is applied may be any of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited to these.

[0085] In addition, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the electronic device is not limited to these, and may be any other electronic device that processes data.

[0086] --Example--

[0087] FIG. 3 is a cross-sectional view showing the overall layer structure of a circuit board according to an embodiment.

[0088] Referring to FIG. 3, a circuit board includes multiple insulating layers.

[0089] In this case, the circuit board may be a core board including a core layer, but the embodiment is not limited thereto, and the circuit board of the embodiment may be a coreless board not including a core layer.

[0090] However, in the following, for the sake of convenience, the circuit board of the embodiment will be described as a core board including a core layer.

[0091] In addition, although the circuit board of the embodiment is shown in the drawings as having a five-layer structure based on the number of insulating layers, the present invention is not limited thereto. For example, the circuit board of the embodiment may have four or less insulating layers, or may have six or more insulating layers.

[0092] In the following, as an example of the embodiment, a circuit board having a five-layer insulating layer structure including a core layer will be described.

[0093] The insulating layer 110 of the embodiment includes a first insulating layer 111. The first insulating layer 111 may be an insulating layer having copper foil laminated on both sides. Preferably, the first insulating layer 111 may be a copper clad lamination (CCL).

[0094] In particular, the copper foil laminate is a disk from which a circuit board is generally manufactured, and is a laminate in which copper foil is laminated on an insulating layer. The copper foil laminate may include glass / epoxy copper foil laminate, heat-resistant resin copper foil laminate, paper / phenol copper foil laminate, high-frequency copper foil laminate, flexible copper foil laminate (e.g., polyimide film), and composite copper foil laminate, etc., depending on the application. In this case, the first insulating layer 111 of the embodiment may be a glass / epoxy copper foil laminate for manufacturing a double-sided circuit board and a multi-layer circuit board, but is not limited thereto.

[0095] The first insulating layer 111 may have a thickness in the range of 100 μm to 500 μm. Preferably, the first insulating layer 111 may have a thickness in the range of 120 μm to 480 μm. More preferably, the first insulating layer 111 may have a thickness in the range of 150 μm to 450 μm.

[0096] If the thickness of the first insulating layer 111 is less than 100 μm, the rigidity and warpage characteristics of the circuit board may be reduced, and if the thickness of the first insulating layer 111 is more than 500 μm, the thickness of the circuit layer disposed on the first insulating layer 110, the line width of the circuit layer, the interval between the circuit layers, and the thickness of the through electrodes may be increased.

[0097] The insulating layer 110 may include a plurality of insulating layers respectively stacked on the upper and lower sides of the first insulating layer 111. For example, the insulating layer 110 may include a second insulating layer 112 disposed on the upper surface of the first insulating layer 111, a third insulating layer 113 disposed on the upper surface of the second insulating layer 112, a fourth insulating layer 114 disposed on the lower surface of the first insulating layer 111, and a fifth insulating layer 115 disposed on the lower surface of the fourth insulating layer 114.

[0098] The second to fifth insulating layers 115 may include a prepreg PPG. The prepreg may be formed by impregnating a fiber layer in the form of a fabric sheet, such as a glass fabric woven with glass fiber yarn, with an epoxy resin or the like, and then performing thermocompression bonding. However, the embodiment is not limited thereto, and the prepreg constituting the second to fifth insulating layers 115 may include a fiber layer in the form of a fabric sheet woven with carbon fiber yarn.

[0099] At least one of the second to fifth insulating layers 115 may be rigid or flexible. For example, at least one of the second to fifth insulating layers 115 may include RCC (Resin Coated Copper), ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc.

[0100] Each of the second to fifth insulating layers 115 may have a thickness in the range of 10 μm to 60 μm. Preferably, each of the second to fifth insulating layers 115 may have a thickness in the range of 12 μm to 50 μm. More preferably, each of the second to fifth insulating layers 115 may have a thickness in the range of 15 μm to 40 μm.

[0101] If the thickness of each of the second to fifth insulating layers 115 is less than 10 μm, the circuit layer included in the circuit board may not be stably protected. If the thickness of each of the second to fifth insulating layers 115 exceeds 60 μm, the thickness of the circuit board and the semiconductor package including the same may increase. If the thickness of each of the second to fifth insulating layers 115 exceeds 60 μm, the thickness of the circuit layer and the through electrode may increase accordingly. Furthermore, if the thickness of the circuit layer and the through electrode increase, the signal transmission loss may increase.

[0102] An example circuit board includes a circuit layer.

[0103] A circuit layer may be disposed on each surface of the insulating layer 110. For example, the circuit layers may include a first circuit layer 121 disposed on an upper surface of the first insulating layer 111, a second circuit layer 122 disposed on an upper surface of the second insulating layer 112, a third circuit layer 123 disposed on an upper surface of the third insulating layer 113, a fourth circuit layer 124 disposed on a lower surface of the first insulating layer 111, a fifth circuit layer 125 disposed on a lower surface of the fourth insulating layer 114, and a sixth circuit layer 126 disposed on a lower surface of the fifth insulating layer 115.

[0104] At least one of the first circuit layer 121, the second circuit layer 122, the third circuit layer 123, the fourth circuit layer 124, the fifth circuit layer 125, and the sixth circuit layer 126 can have a thickness of 10 μm to 25 μm. Preferably, at least one of the first circuit layer 121, the second circuit layer 122, the third circuit layer 123, the fourth circuit layer 124, the fifth circuit layer 125, and the sixth circuit layer 126 can have a thickness of 12 μm to 23 μm. More preferably, at least one of the first circuit layer 121, the second circuit layer 122, the third circuit layer 123, the fourth circuit layer 124, the fifth circuit layer 125, and the sixth circuit layer 126 can have a thickness of 15 μm to 20 μm.

[0105] The first circuit layer 121, the second circuit layer 122, the third circuit layer 123, the fourth circuit layer 124, the fifth circuit layer 125, and the sixth circuit layer 126 may include a conductive material. For example, the first circuit layer 121, the second circuit layer 122, the third circuit layer 123, the fourth circuit layer 124, the fifth circuit layer 125, and the sixth circuit layer 126 may include at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the first circuit layer 121, the second circuit layer 122, the third circuit layer 123, the fourth circuit layer 124, the fifth circuit layer 125, and the sixth circuit layer 126 may be formed of copper (Cu), which has high conductivity and is relatively inexpensive.

[0106] The first circuit layer 121, the second circuit layer 122, the third circuit layer 123, the fourth circuit layer 124, the fifth circuit layer 125, and the sixth circuit layer 126 can be manufactured using typical circuit board manufacturing processes such as an additive process, a subtractive process, a modified semi-additive process (MSAP), or a semi-additive process (SAP), and detailed explanations thereof will be omitted here.

[0107] The circuit board includes a through electrode, for example, a through electrode that penetrates an insulating layer and electrically connects circuit layers arranged on different layers.

[0108] For example, the through electrodes include a first through electrode 131 that penetrates the first insulating layer 111. The first through electrode 131 may electrically connect the first circuit layer 121 and the fourth circuit layer 124.

[0109] The through electrodes include a second through electrode 132 that penetrates the second insulating layer 112. The second through electrode 132 may electrically connect the first circuit layer 121 and the second circuit layer 122 to each other.

[0110] In addition, the through electrodes include a third through electrode 133 that penetrates the third insulating layer 113. The third through electrode 133 may electrically connect the second circuit layer 122 and the third circuit layer 123 to each other.

[0111] In addition, the through electrodes include a fourth through electrode 134 that penetrates the fourth insulating layer 114. The fourth through electrode 134 may electrically connect the fourth circuit layer 124 and the fifth circuit layer 125 to each other.

[0112] In addition, the through electrodes include a fifth through electrode 135 that penetrates the fifth insulating layer 115. The fifth through electrode 135 may electrically connect the fifth circuit layer 125 and the sixth circuit layer 126 to each other.

[0113] The circuit board also includes a protective layer. The protective layer may be disposed on the top or bottom side of the circuit board. The protective layer may protect the surface of a circuit layer or an insulating layer disposed on the top or bottom side of the circuit board.

[0114] Preferably, the protective layer may include a first protective layer 140 disposed on an upper surface of the third insulating layer 113. The first protective layer 140 may protect the upper surface of the third insulating layer 113 and the upper surface of the third circuit layer 123. The first protective layer 140 may also include a first opening (not shown) overlapping in the thickness direction with at least a portion of the upper surface of the third circuit layer 123. The first opening may be formed corresponding to a mounting position of an electronic element or a contact position with an external board.

[0115] The protective layer may also include a second protective layer 150 disposed on the lower surface of the fifth insulating layer 115. The second protective layer 150 may protect the lower surface of the fifth insulating layer 115 and the lower surface of the sixth circuit layer 126. The second protective layer 150 may also include a second opening (not shown) overlapping in the thickness direction with at least a portion of the lower surface of the sixth circuit layer 126. The second opening may be formed corresponding to a mounting position of an electronic element or a connection position with an external board.

[0116] In this case, the first protective layer 140 and the second protective layer 150 may be a solder resist, but are not limited to this.

[0117] Meanwhile, the circuit board of the embodiment may include multiple regions. For example, the circuit board may include a first region R1, a second region R2, and a third region R3. For example, the insulating layer 110 may include a first region R1, a second region R2, and a third region R3. For example, the circuit layer 120 may include a first region R1, a second region R2, and a third region R3. For example, the first protective layer 140 may include a first region R1, a second region R2, and a third region R3.

[0118] At this time, the first protective layer 140 in the embodiment may have a structure different from each other in each region. For example, the first protective layer 140 in the embodiment may have a height or an open structure different from each other in the first region R1, the second region R2, and the third region R3. The outermost insulating layer, the outermost circuit layer, and the outermost protective layer will be described below. Preferably, the insulating layer arranged on the uppermost side of the circuit board, the circuit layer arranged on the uppermost side, and the protective layer arranged on the uppermost side will be described below. The insulating layer, the circuit layer, and the protective layer described below may mean, but are not limited to, the insulating layer, the circuit layer, and the protective layer arranged on the uppermost side of the circuit board. For example, the insulating layer, the circuit layer, and the protective layer described below may mean the insulating layer, the circuit layer, and the protective layer arranged on the lowermost side of the circuit board.

[0119] Therefore, in the following, the third insulating layer 113 arranged on the top side of the circuit board will be referred to as insulating layer 110, the third circuit layer 123 arranged on the top side will be referred to as circuit layer 120, and the first protective layer 140 arranged on the top side will be referred to as protective layer 140.

[0120] The first region R1, the second region R2, and the third region R3 may be divided based on the difference in the structure of the open region of the protective layer 140. The first region R1, the second region R2, and the third region R3 may be divided according to the type of configuration disposed on the circuit board. The first region R1, the second region R2, and the third region R3 may be divided based on the line width and spacing of the pads and traces of the circuit layer 120 disposed on the insulating layer 110.

[0121] The first region R1 may refer to a region where chips such as passive elements are mounted on the circuit board. The second region R2 may refer to a region where application chips are mounted on the circuit board. The third region R3 may refer to a region where another upper substrate (e.g., a memory substrate) is attached on the circuit board. Thus, the structures of the openings of the protective layer 140 in the first region R1, the second region R2, and the third region R3 may be different from each other.

[0122] The first region R1, the second region R2, and the third region R3 of the embodiment will be specifically described below.

[0123] For convenience of explanation, the structures of the second region R2 and the third region R3 will be explained first, and then the structure of the third region R3 will be explained last.

[0124] FIG. 4 is a diagram showing the structure of the second region of the circuit board according to the first embodiment, and FIG. 5 is a diagram showing the structure of the second region of the circuit board according to the second embodiment.

[0125] 4, a second pattern portion 120-2 of a circuit layer 120 is disposed on a second region R2 of an insulating layer 110. Fig. 4(a) is a plan view of the second region of a circuit board according to a first embodiment, and Fig. 4(b) is a cross-sectional view taken along the A-A' direction of Fig. 4(a).

[0126] In this case, the second region R2 may refer to a region where fine circuits are required for mounting a processor chip or a driver IC. In the following description, it is assumed that the chip mounted in the second region R2 is a processor chip.

[0127] The second pattern unit 120-2 may refer to a circuit pattern disposed in a second chip mounting region where a processor chip is mounted in the circuit layer 120. The second pattern unit 120-2 includes second pads 120-21 corresponding to terminals of the processor chip and second traces 120-22 connected to the second pads 120-21.

[0128] The second pattern unit 120-2 is required to be finely detailed. For example, in the second region R2, pads all connected to the terminals of the processor chip should be arranged within a limited space, and traces connected to the pads connected to the terminals should be arranged. Thus, the second pattern unit 120-2 may include a fine pattern.

[0129] Furthermore, recently, the number of functions processed by a processor chip has been increasing. This makes it difficult to realize all the functions with one processor chip. Therefore, there is a demand for mounting two or more processor chips that perform different functions on one circuit board.

[0130] Therefore, when the processor chip includes a first and a second processor chip, miniaturization of the second pattern portion 120-2 is required in order to connect all the wiring between the first processor chip and the second processor chip within a limited space.

[0131] In addition, the number of terminals in the first processor chip and the second processor chip is gradually increasing due to reasons such as 5G, Internet of Things (IOT), improved image quality, and increased communication speed, etc. As a result, the connection wiring between the first processor chip and the second processor chip may be more than two times, three times, or even ten times larger than before.

[0132] As a result, in order to mount the first processor chip and the second processor chip on a single circuit board while minimizing the gap between them and to connect the first processor chip and the second processor chip to each other within a limited space, ultra-fine construction of the second pattern portion 120-2 is required.

[0133] Second pads 120-21 of second pattern portion 120-2 correspond to terminals of a processor chip mounted on a circuit board, so that the number of second pads 120-21 corresponds to the number of terminals of the processor chip.

[0134] The second pad 120-21 may have a width in a first horizontal direction different from a width in a second horizontal direction perpendicular to the first horizontal direction. In this case, the width of the second pad 120-21 in the separation direction between adjacent pads or traces may be smaller than the width in the direction perpendicular to the separation direction. The width of the second pad 120-21 in the separation direction has a large effect on the circuit integration density.

[0135] That is, the second pad 120-21 may have an elliptical shape with a width in the spacing direction smaller than a width in a direction perpendicular to the spacing direction, but the embodiment is not limited thereto. For example, the second pad 120-21 may have a circular shape with a width in the spacing direction as a whole.

[0136] The width W1 of the second pad 120-21 may be 3 μm to 30 μm. For example, the width W1 of the second pad 120-21 may be 4 μm to 28 μm. For example, the width W1 of the second pad 120-21 may be 5 μm to 25 μm.

[0137] If the width W1 of the second pad 120-21 is less than 3 μm, it may be difficult to arrange an adhesive member that is stably connected to the terminal of the processor chip. If the width W1 of the second pad 120-21 is less than 3 μm, the connection reliability between the second pad 120-21 and the processor chip may decrease. If the width W1 of the second pad 120-21 is greater than 30 μm, it may be difficult to arrange all the patterns that are connected to the processor chip within a limited space. If the width W1 of the second pad 120-21 is greater than 30 μm, the size of the circuit board may increase. If the width W1 of the second pad 120-21 is greater than 30 μm, the spacing between adjacent patterns becomes narrow, which may cause reliability problems such as short circuits.

[0138] The second pattern unit 120-2 disposed in the second region R2 includes a second trace 120-22 connected to the second pad 120-21. The second trace 120-22 may refer to a thin and long signal line connected to the second pad 120-21. In addition, when two processor chips are mounted on the second pattern unit 120-2, the second trace 120-22 may include a signal line connecting the two chips.

[0139] The second trace 120-22 may include an ultra-fine pattern. For example, the line width W2 of the second trace 120-22 may satisfy the range of 1 μm to 10 μm. For example, the line width W2 of the second trace 120-22 may satisfy the range of 1.2 μm to 8 μm. For example, the line width W2 of the second trace 120-22 may satisfy the range of 1.5 μm to 7 μm. If the line width W2 of the second trace 120-22 is smaller than 1 μm, the resistance of the second trace 120-22 increases, which may make it difficult to properly communicate with the processor chip. Also, if the line width W2 of the second trace 120-22 is smaller than 1 μm, it may be difficult to apply a general circuit pattern manufacturing process. If the line width W2 of the second trace 120-22 is smaller than 1 μm, a physical reliability problem may occur in which the second trace 120-22 collapses due to various factors. If the line width W2 of the second trace 120-22 is greater than 10 μm, it may be difficult to arrange all the signal lines connected to the terminals of the processor within a limited space. For example, if the line width W2 of the second trace 120-22 is greater than 10 μm, it may be difficult to arrange all the traces for connecting multiple processor chips within a limited space. For example, if the line width W2 of the second trace 120-22 is greater than 10 μm, the area of ​​the second region R2 increases, which may increase the overall size of the circuit board and the semiconductor package.

[0140] Meanwhile, the second pattern units 120-2 may be spaced apart from each other at a constant distance W3 on the second region R2. The distance W3 may refer to the distance between the second pads 120-21 of the second pattern unit 120-2. Also, the distance W3 may refer to the distance between the second traces of the second pattern unit 120-2. Also, the distance W3 may refer to the distance between the second pads 120-21 and the second traces 120-22 adjacent to each other of the second pattern unit 120-2.

[0141] The spacing W3 may range from 1 μm to 10 μm. The spacing W3 may range from 1.2 μm to 8 μm. The spacing W3 may range from 1.5 μm to 7 μm. If the spacing W3 is smaller than 1 μm, there is a problem in that adjacent second traces or second pads are connected to each other, causing an electrical short circuit. For example, if the spacing W3 is larger than 10 μm, it may be difficult to arrange all the traces for connecting multiple processor chips within a limited space.

[0142] As described above, a relatively dense circuit pattern is arranged in the second region R2. For example, the second pattern portion 120-2, which has a smaller width and interval than the first region R1 and the third region R3, is arranged in the second region R2. In addition, with a general solder resist exposure resolution, it may be difficult to form an SRO on the second pad 120-21 of the second pattern portion 120-2. As a result, as shown in FIG. 4B, the protective layer 140 may not be arranged in the second region R2. In other words, the protective layer 140 may not vertically overlap the second region R2. That is, the second pattern portion 120-2 arranged in the second region R2 is a fine pattern, and due to the limit of resolution for forming the SRO of the protective layer 140, it may be difficult to form the SRO of the protective layer 140 corresponding to the fine pattern in the second region R2.

[0143] 5, the second trace 120-22 disposed in the second region R2 is a fine pattern and is a pattern disposed in the outermost layer. The second trace 120-22 has a structure protruding above the upper surface of the insulating layer 110. As a result, the second trace 120-22 may be damaged during subsequent manufacturing processes after it is formed. This may cause problems with the physical reliability of the second trace 120-22.

[0144] As a result, the third protection pattern 142 of the protection layer 140 may be formed in the second region R2a of the second embodiment.

[0145] In this case, the third protection pattern 142 may have the same height or thickness on the second region R2a as a whole. Here, the third protection pattern 142 having the same height or thickness on the whole may mean that the difference in height of the top surface of the third protection pattern 142 in the second region R2a is 3 μm or less, 2 μm or less, 1 μm or less, or 0.5 μm or less.

[0146] In this case, the thickness T1 of the second pattern portion 120-2 arranged in the second region R2a may be 10 μm to 25 μm.

[0147] Third protective pattern 142 of protective layer 140 may have a thickness T2 smaller than thickness T1 of second pattern portion 120-2. For example, thickness T2 of third protective pattern 142 may be in the range of 40% to 90% of thickness T1 of second pattern portion 120-2. Preferably, thickness T2 of third protective pattern 142 may be in the range of 45% to 85% of thickness T1 of second pattern portion 120-2. For example, thickness T2 of third protective pattern 142 may be in the range of 50% to 80% of thickness T1 of second pattern portion 120-2.

[0148] For example, the thickness T2 of the third protective pattern 142 can be 4 μm to 22 μm. For example, the thickness T2 of the third protective pattern 142 can be 4.5 μm to 21 μm. For example, the thickness T2 of the third protective pattern 142 can be 5 μm to 20 μm.

[0149] If the thickness T2 of the third protective pattern 142 is less than 40% of the thickness T1 of the second pattern unit 120-2, the effect of protecting the second pattern unit 120-2 by the third protective pattern 142 may be insufficient. If the thickness T2 of the third protective pattern 142 is more than 90% of the thickness T1 of the second pattern unit 120-2, residual resin of the protective layer 140 may remain on the upper surface of the second pattern unit 120-2. If residual resin exists, problems may occur in electrical reliability.

[0150] As in the first embodiment, the top surface and side surfaces of second pattern portion 120-2 in second region R2 may not be in contact with protective layer 140 as a whole.

[0151] Furthermore, in the second embodiment, the top surface of second pattern portion 120-2 in second region R2a may not be in contact with protective layer 140 as a whole. In addition, the side surface of second pattern portion 120-2 in second region R2a in the second embodiment may be partially covered with protective layer 140. For example, while at least a portion of the side surface of second pattern portion 120-2 is covered with protective layer 140, at least a remaining portion may not be in contact with protective layer 140.

[0152] That is, in the second embodiment, a step of thinning the thickness of the protective layer (e.g., a thinning step or a step of forming a protective layer in the first region described later) can be performed in a state where a protective layer that entirely covers the upper surface of the second pattern portion 120-2 is formed on the second region R2a. As a result, the protective layer 140 in the second embodiment can be disposed in the second region R2a, and a third protective pattern having a height that is entirely lower than the upper surface of the second pattern portion 120-2 can be formed.

[0153] FIG. 6 is a diagram showing a structure of a third region of the circuit board according to the embodiment.

[0154] FIG. 6(a) is a plan view of the third region of the circuit board of the embodiment, and FIG. 6(b) is a cross-sectional view taken along the line BB' of FIG. 6(a).

[0155] 6(a) and 6(b), third region R3 is provided with third pattern portion 120-3 that is relatively larger in width and spacing than second pattern portion 120-2 provided in second region R2.

[0156] The third region R3 refers to a region where pads or bumps to be connected to another package substrate such as a memory substrate are arranged.

[0157] Third pattern portion 120-3 includes a third pad 120-31 and a third trace 120-3.

[0158] The width W4 of the third pads 120 to 31 is in the range of 30 μm to 70 μm. For example, the width W4 of the third pads 120 to 31 is in the range of 35 μm to 65 μm. For example, the width W4 of the third region R3 is in the range of 35 μm to 50 μm.

[0159] Furthermore, the spacing W5 between adjacent patterns in the third region R3 is in the range of 10 μm to 40 μm. For example, the spacing W5 between adjacent patterns in the third region R3 is in the range of 12 μm to 30 μm. For example, the spacing W5 between adjacent patterns in the third region R3 is in the range of 13 μm to 25 μm.

[0160] Unlike the second region R2, the third traces 120-3 of the third pads 120-31 arranged in the third region R3 do not require fine line widths or fine intervals.

[0161] Therefore, in the third region R3, a protective layer 140 having a structure different from that in the second region R2 is formed.

[0162] For example, the protective layer 140 includes a fourth protective pattern 143 disposed in the third region R3.

[0163] The fourth protection pattern 143 is arranged in the third region R3 to have a thickness greater than the thickness of the third pad 120-31. In this case, the fourth protection pattern 143 may be arranged to cover at least a portion of the upper surface of the third pad 120-31. The fourth protection pattern 143 also includes an opening 143-1 that overlaps at least a portion of the upper surface of the third pad 120-31 in the thickness direction.

[0164] That is, the side surface of the third pad 120-31 may be entirely covered with the fourth protective pattern 143 of the protective layer 140.

[0165] And, the top surface of the third pad 120-31 may be partially covered with the fourth protective pattern 143 of the protective layer 140.

[0166] Specifically, the third pad 120-31 may include a first portion 120-31a overlapping with the opening 143-1 of the fourth protective pattern 143 of the protective layer 140 in the thickness direction, and a second portion 120-31b covered by the fourth protective pattern 143.

[0167] In addition, the top surface of the third trace 120-3 may be entirely covered with the fourth protective pattern 143 of the protective layer 140. However, the embodiment is not limited thereto, and a part of the top surface of the third trace 120-3 adjacent to the third pad 120-31 may not be in contact with the fourth protective pattern 143 of the protective layer 140.

[0168] In conclusion, the protective layer 140 in the third region R3 can have an SMD structure.

[0169] As described above, the protective layer 140 of the embodiment has different structures in the second region R2 and the third region R3.

[0170] For example, the protective layer 140 may not be disposed in the second region R2. Alternatively, the protective layer 140 may not be in full contact with the top surface of the second pattern portion 120-2 in the second region R2a. For example, the protective layer 140 may be located lower than the top surface of the second pattern portion 120-2 in the second region R2a.

[0171] In addition, protective layer 140 may be located higher than the upper surface of third pattern portion 120-3 in third region R3. For example, protective layer 140 may cover at least a portion of the upper surface of third pattern portion 120-3 in third region R3. For example, protective layer 140 may have an SMD structure in third region R3.

[0172] Meanwhile, the protective layer 140 in the first region R1 may have a different structure from the second region R2 and / or the third region R3. Here, the different structure may mean that the structure of the openings formed in the protective layer 140 is different, or may mean that the height or thickness is different.

[0173] 7a is a plan view of a first region of a circuit board according to the first embodiment, FIG. 7b is a cross-sectional view taken along the CC' direction of FIG. 7a, FIG. 7c is a cross-sectional view taken along the D-D' direction of FIG. 7a, and FIG. 8 is an oblique view showing an element mounted in the first region of a circuit board according to one embodiment.

[0174] Hereinafter, the first region of the circuit board according to the embodiment will be specifically described with reference to FIGS. 7a to 8. FIG.

[0175] In the first region R1, a first pattern unit 120-1 having a width and interval relatively larger than those of the pattern units arranged in the second region R2 and the third region R3 is arranged. In this case, the first pattern unit 120-1 includes a plurality of pads. In this case, the first region R1 may not include a trace. That is, the first pattern unit 120-1 may include only a plurality of pads. For example, the first region R1 may include a first pattern unit 120-1 including only an island pad that is not directly connected to other patterns arranged on the upper surface of the insulating layer 110. However, the embodiment is not limited thereto, and in some cases, a trace connected to the first pattern unit 120-1 may be arranged in the first region R1.

[0176] The first pattern unit 120-1 includes a first pad, for example, a 1-1 pad 120-11 and a 1-2 pad 120-12 connected to one first semiconductor element.

[0177] The 1-1 pad 120-11 may be a pad connected to a first terminal of a first semiconductor element, and the 1-2 pad 120-12 may be a pad connected to a second terminal of the first semiconductor element. Although the drawings show a first pad connected to one first semiconductor element, the present invention is not limited thereto. For example, a plurality of first pads each connected to at least two first semiconductor elements may be arranged in the first region R1. Each of the plurality of first pads may include a 1-1 pad and a 1-2 pad.

[0178] The first-1 pad 120-11 and the first-2 pad 120-12 may be large area pads. For example, the terminals of the first chip have a relatively large size. Here, having a relatively large size may mean that the size of each terminal of the first chip is larger than the size of each terminal of a second chip such as a processor chip.

[0179] The first-1 pad 120-11 and the first-2 pad 120-12 may be spaced apart from each other in a first horizontal direction, which may refer to the width direction, the x-axis direction, and the lateral direction in the drawing.

[0180] The 1-1 pad 120-11 and the 1-2 pad 120-12 may each have a width W6 in the second horizontal direction that is smaller than a width W7 in the first horizontal direction perpendicular to the first horizontal direction.

[0181] The width W6 in the second horizontal direction of each of the 1-1 pad 120-11 and the 1-2 pad 120-12 can be in the range of 125% to 220% of the width W7 in the first horizontal direction. The width W6 in the second horizontal direction of each of the 1-1 pad 120-11 and the 1-2 pad 120-12 can be in the range of 130% to 210% of the width W7 in the first horizontal direction. The width W6 in the second horizontal direction of each of the 1-1 pad 120-11 and the 1-2 pad 120-12 can be in the range of 140% to 200% of the width W7 in the first horizontal direction.

[0182] If the width W6 in the second horizontal direction of each of the 1-1 pad 120-11 and the 1-2 pad 120-12 is less than 125% of the width W7 in the first horizontal direction, it may be difficult to stably arrange the first semiconductor element. If the width W6 in the second horizontal direction of each of the 1-1 pad 120-11 and the 1-2 pad 120-12 is less than 125% of the width W7 in the first horizontal direction, the mountability of the first chip and the electrical reliability with the first semiconductor element may be reduced. If the width W6 in the second horizontal direction of each of the 1-1 pad 120-11 and the 1-2 pad 120-12 is more than 220% of the width W7 in the first horizontal direction, the arrangement space of the first pattern portion 120-1 increases, which may increase the size of the circuit board.

[0183] For example, the second horizontal width W6 of each of the 1-1 pad 120-11 and the 1-2 pad 120-12 may have a range of 210 μm±15 μm. If the second horizontal width W6 has a range of 210 μm±15 μm, the first horizontal width W7 may have a range of 140 μm±15 μm.

[0184] For example, the second horizontal width W6 of each of the 1-1 pad 120-11 and the 1-2 pad 120-12 may have a range of 310 μm±15 μm. If the second horizontal width W6 has a range of 310 μm±15 μm, the first horizontal width W7 may have a range of 190 μm±15 μm.

[0185] For example, the second horizontal width W6 of each of the 1-1 pad 120-11 and the 1-2 pad 120-12 may have a range of 660 μm±15 μm. If the second horizontal width W6 has a range of 660 μm±15 μm, the first horizontal width W7 may have a range of 450 μm±15 μm.

[0186] Preferably, the second horizontal width W6 of each of the 1-1 pad 120-11 and the 1-2 pad 120-12 can be greater than 195 μm. Preferably, the second horizontal width W6 of each of the 1-1 pad 120-11 and the 1-2 pad 120-12 can be greater than 295 μm. Preferably, the second horizontal width W6 of each of the 1-1 pad 120-11 and the 1-2 pad 120-12 can be greater than 645 μm.

[0187] Preferably, the first horizontal width W7 of each of the 1-1 pad 120-11 and the 1-2 pad 120-12 can be greater than 125 μm. Preferably, the first horizontal width W7 of each of the 1-1 pad 120-11 and the 1-2 pad 120-12 can be greater than 175 μm. Preferably, the first horizontal width W7 of each of the 1-1 pad 120-11 and the 1-2 pad 120-12 can be greater than 435 μm.

[0188] On the other hand, the interval W8 between the 1-1 pad 120-11 and the 1-2 pad 120-12 in the first region R1 can be in the range of 70% to 120% of the width W7 in the first horizontal direction of each of the 1-1 pad 120-11 and the 1-2 pad 120-12. The interval W8 between the 1-1 pad 120-11 and the 1-2 pad 120-12 in the first region R1 can be in the range of 75% to 115% of the width W7 in the first horizontal direction of each of the 1-1 pad 120-11 and the 1-2 pad 120-12. The interval W8 between the 1-1 pad 120-11 and the 1-2 pad 120-12 in the first region R1 can be in the range of 80% to 110% of the width W7 in the first horizontal direction of each of the 1-1 pad 120-11 and the 1-2 pad 120-12.

[0189] If the distance W8 between the 1-1 pad 120-11 and the 1-2 pad 120-12 in the first region R1 is less than 70% of the width W7 in the first horizontal direction of each of the 1-1 pad 120-11 and the 1-2 pad 120-12, a short circuit problem may occur due to the connection between the multiple adhesive members in the mounting process of the first chip. If the distance W8 between the 1-1 pad 120-11 and the 1-2 pad 120-12 in the first region R1 exceeds 120% of the width W7 in the first horizontal direction of each of the 1-1 pad 120-11 and the 1-2 pad 120-12, the connectivity with the first semiconductor element may be reduced.

[0190] As described above, the first pattern portion 120-1 having a relatively large width and a relatively large interval is arranged in the first region R1 of the circuit board. As a result, the open structure of the protective layer 140 in the first region R1 generally has an SMD structure. That is, as in the first comparative example, the protective layer 140 in the first region of a general circuit board has an SMD structure that covers at least a part of the upper surface of the first pattern portion.

[0191] In contrast, in the embodiment, the protective layer 140 is disposed in the first region R1, and a new open structure is provided so that the protective layer 140 does not affect the increase in thickness of the semiconductor package.

[0192] That is, the protective layer 140 includes a protective portion 141 disposed in the first region R1.

[0193] The protective portion 141 may have different heights depending on the position. Preferably, the protective portion 141 does not contact the top surface of the first pattern portion 120-1 but contacts at least a part of the side surface of the first pattern portion 120-1. Here, the protective portion 141 contacting at least a part of the side surface of the first pattern portion 120-1 means that at least a part of the side surface of the first pattern portion 120-1 does not contact the first protective layer 140.

[0194] Protection portion 141 includes first protection pattern 141-1 adjacent to first pattern portion 120-1 in first region R1, and second protection pattern 141-2 other than first protection pattern 141-1.

[0195] In this case, in the embodiment, a process of thinning the thickness of the protective layer 140 may be performed, so that the protective layer 140 is provided with a first protective pattern 141-1 and a second protective pattern 141-2. In this case, an inner wall of the second protective pattern 141-2 may have a slope along the thickness direction of the protective layer 140. Exemplarily, the inner wall of the second protective pattern 141-2 may have a slope whose width changes along the thickness direction. Preferably, the inner walls of the first protective pattern 141-1 and the second protective pattern 141-2 in the embodiment are provided by a process of selectively thinning the thickness of the protective layer 140, and thus may have a curved surface with a constant curvature whose width decreases along the thickness direction.

[0196] As a result, in the embodiment, the inner wall of the second protective pattern 141-2 may have a curved surface, thereby increasing the contact area between the second protective pattern 141-2 and the molding layer. Therefore, in the embodiment, the problem of the molding layer peeling off from the protective layer may be solved, and further, the semiconductor device may be more stably seated by the molding layer.

[0197] In addition, since the inner wall of the second protective pattern 141-2 has a curved surface, the embodiment may increase the distance between the upper surface of the protective layer 140 and the first pattern unit 120-1 corresponding to the curvature of the curved surface. In this case, the semiconductor package may be subjected to stress due to heat cycles such as expansion and / or contraction during the manufacturing process and / or the usage environment. In this case, the stress may be transferred to the first pattern unit 120-1, which may affect the electrical reliability of the first semiconductor element mounted on the first pattern unit 120-1. Exemplarily, if the stress is transferred to the interface between the first pattern unit 120-1 and the first semiconductor element, a crack may be generated, which may cause a reliability problem in which the first semiconductor element is electrically isolated from the first pattern unit 120-1. In response to this, the embodiment may be configured such that the inner wall of the second protective pattern 141-2 has a curved surface, thereby preventing the stress from being transferred to the interface between the first semiconductor element and the first pattern unit 120-1, thereby improving the electrical reliability and / or physical reliability of the semiconductor package.

[0198] The first protection pattern 141-1 may be disposed in a region adjacent to the first pattern portion 120-1 in the first region R1, and the second protection pattern 141-2 may be disposed in an edge region of the first region R1 excluding the first protection pattern 141-1.

[0199] For example, the first protection pattern 141-1 may be provided between the 1-1 pad and the 1-2 pad of the first pattern unit 120-1 by surrounding at least a portion of the side of the 1-1 pad and the 1-2 pad, and the second protection pattern 141-2 may be provided by surrounding the first protection pattern 141-1.

[0200] For example, the first protective pattern 141-1 may be disposed in a surrounding region of the side of the 1-1 pad 120-11 and the 1-2 pad 120-12. Also, the first protective pattern 141-1 may be disposed in a region between the 1-1 pad 120-11 and the 1-2 pad 120-12. For example, the first protective pattern 141-1 includes a first portion 141-11 disposed between the 1-1 pad 120-11 and the 1-2 pad 120-12. Also, the first protective pattern 141-1 includes a second portion 141-12 disposed to surround the side of the 1-1 pad 120-11, the side of the 1-2 pad 120-12, and the side of the first portion 141-11.

[0201] That is, the first protection pattern 141-1 may be disposed on the first region R1 to surround the peripheral region of the first pattern portion 120-1 including the region between the 1-1 pad 120-11 and the 1-2 pad 120-12.

[0202] An upper surface of the first protection pattern 141-1 may be located lower than an upper surface of the first pattern unit 120-1, that is, a thickness T2 of the first protection pattern 141-1 may be smaller than a thickness T1 of the first pattern unit 120-1.

[0203] The thickness T1 of first pattern portion 120-1 may be 10 μm to 25 μm. Preferably, the thickness T1 of first pattern portion 120-1 may be 12 μm to 23 μm. More preferably, the thickness T1 of first pattern portion 120-1 may be 12 μm to 20 μm.

[0204] The thickness T2 of the first protection pattern 141-1 may be 3 μm to 21 μm. The thickness T2 of the first protection pattern 141-1 may be 4 μm to 19 μm. The thickness T2 of the first protection pattern 141-1 may be 5 μm to 16 μm.

[0205] According to the embodiment, if the thickness T2 of the first protective pattern 141-1 is 3 μm or less, the effect of the first protective pattern 141-1 may be insufficient. For example, if the thickness T2 of the first protective pattern 141-1 is 3 μm or less, the effect of preventing short circuits between the plurality of adhesive members disposed on the 1-1 pad 120-11 and the 1-2 pad 120-12 may be insufficient. For example, if the thickness T2 of the first protective pattern 141-1 is 3 μm or less, there may be a limit to reducing the distance between the 1-1 pad 120-11 and the 1-2 pad 120-12. For example, if the thickness T2 of the first protective pattern 141-1 exceeds 21 μm, a problem may occur in which residual resin of the protective layer 140 remains on the 1-1 pad 120-11 or the 1-2 pad 120-12. For example, if the thickness T2 of the first protection pattern 141-1 exceeds 21 μm, a reliability problem may occur in which at least a portion of the top surface of the 1-1 pad 120-11 or the 1-2 pad 120-12 is covered by the first protection pattern 141 due to a process error.

[0206] Furthermore, thickness T2 of first protective pattern 141-1 may be in the range of 40% to 90% of thickness T1 of first pattern portion 120-1. Preferably, thickness T2 of first protective pattern 141-1 may be in the range of 45% to 85% of thickness T1 of first pattern portion 120-1. For example, thickness T2 of first protective pattern 141-1 may be in the range of 50% to 80% of thickness T1 of first pattern portion 120-1.

[0207] Meanwhile, in the embodiment, the height difference TΔ between the top surface of the first pattern unit 120-1 and the top surface of the first protection pattern 141-1 is set to be 3 μm or more. The height difference TΔ may refer to the vertical distance between the top surface of the first pattern unit 120-1 and the top surface of the first protection pattern 141-1.

[0208] In the embodiment, the height difference TΔ between the upper surface of first pattern unit 120-1 and the upper surface of first protection pattern 141-1 is 3.5 μm or more. More preferably, in the embodiment, the height difference TΔ between the upper surface of first pattern unit 120-1 and the upper surface of first protection pattern 141-1 is 4 μm or more. In this case, the upper surface of first pattern unit 120-1 may not be flat, and the upper surface of protection unit 141 may not be flat either. This may refer to the height difference.

[0209] If the height difference TΔ between the top surface of first pattern portion 120-1 and the top surface of first protective pattern 141-1 is less than 3 μm, there may be a problem that residual resin remains on the top surface of first pattern portion 120-1, or that at least a portion of the top surface of first pattern portion 120-1 is covered by first protective pattern 141-1 due to process errors.

[0210] Preferably, the height difference TΔ between the upper surface of first pattern unit 120-1 and the upper surface of first protective pattern 141-1 is set to 3 μm to 10 μm. This makes it possible to provide first protective pattern 141-1 with an optimal height regardless of the thickness of first pattern unit 120-1. That is, if the height difference TΔ exceeds 10 μm, the effect provided by first protective pattern 141-1 may be insufficient.

[0211] Meanwhile, the protection unit 141 includes a second protection pattern 141-2 disposed around the first protection pattern 141-1. The second protection pattern 141-2 may have a thickness greater than that of the first protection pattern 141-1. Also, the second protection pattern 141-2 may have a thickness greater than that of the first pattern unit 120-1.

[0212] Preferably, the upper surface of the second protection pattern 141-2 may be located higher than the upper surface of the first protection pattern 141-1. Furthermore, the upper surface of the second protection pattern 141-2 may be located higher than the upper surface of the first pattern portion 120-1.

[0213] The thickness T3 of the second protective pattern 141-2 may be 17 μm to 45 μm. Preferably, the thickness T3 of the second protective pattern 141-2 may be 19 μm to 43 μm. More preferably, the thickness T3 of the second protective pattern 141-2 may be 19 μm to 40 μm.

[0214] Second protection pattern 141-2 is disposed to surround the periphery of first protection pattern 141-1.

[0215] In this case, width W9 between first pattern portion 120-1 and second protection pattern 141-2 of first protection pattern 141-1 may be in the range of 13 μm to 25 μm. Preferably, width W9 between first pattern portion 120-1 and second protection pattern 141-2 of first protection pattern 141-1 may be in the range of 15 μm to 23 μm. Width W9 between first pattern portion 120-1 and second protection pattern 141-2 of first protection pattern 141-1 may be in the range of 16 μm to 20 μm.

[0216] Specifically, the 1-1 pad 120-11 includes a plurality of side surfaces. The plurality of side surfaces of the 1-1 pad 120-11 include a 1-1 side surface facing a side surface of the 1-2 pad 120-12 and a 1-2 side surface other than the 1-1 side surface. The width W9 may refer to the horizontal distance between the 1-2 side surface of the 1-1 pad 120-11 and an inner wall of the second protection pattern 141-2 adjacent to the 1-2 side surface.

[0217] In addition, the 1-2 pad 120-12 includes a plurality of side surfaces. The plurality of side surfaces of the 1-2 pad 120-12 include a 2-1 side surface facing the 1-1 side surface of the 1-1 pad 120-11, and a 2-2 side surface excluding the 2-1 side surface. The width W9 may refer to the horizontal distance between the 2-2 side surface of the 1-2 pad 120-12 and an inner wall of the second protective pattern 141-2 of the first protective layer 140 adjacent to the 2-2 side surface.

[0218] If the width W9 is less than 13 μm, a problem may occur in which the second protective pattern 141-2 of the protective layer 140 overlaps with the first chip in the thickness direction due to manufacturing process errors. For example, the design of the 1-1 pad 120-11 and the 1-2 pad 120-12 is performed in consideration of process errors in the arrangement process of the first semiconductor element. For example, the first semiconductor element may be arranged on the 1-1 pad 120-11 and the 1-2 pad 120-12 with a certain degree of error range. The width W9 may be determined in consideration of the error range. In this case, if the width W9 is less than 13 μm, a problem may occur in which the error range cannot be sufficiently covered, and thus a problem may occur in which at least a part of the first chip contacts the second protective pattern 141-2 in the mounting process of the first chip. Also, if the width W9 exceeds 25 μm, the area of ​​the first region R1 increases, which may increase the overall size of the circuit board.

[0219] 8, the design of the first region R1 is determined based on the size of the first semiconductor element 200 disposed on the 1-1 pad 120-11 and the 1-2 pad 120-12. The first semiconductor element 200 may be a variety of elements, and may be, for example, a multilayer ceramic capacitor.

[0220] The first semiconductor device 200 includes a body 210. The first semiconductor device 200 also includes a first terminal 220 disposed on one side of the body 210 and connected to the 1-1 pad 120-11. The first semiconductor device 200 also includes a second terminal 230 disposed on the other side of the body 210 and connected to the 1-2 pad 120-12. The first terminal 220 and the second terminal 230 may be disposed spaced apart in a second horizontal direction, which is a spaced direction between the 1-1 pad 120-11 and the 1-2 pad 120-12.

[0221] The first semiconductor element 200 may have a width L in the second horizontal direction larger than a width W in the first horizontal direction perpendicular to the second horizontal direction.

[0222] The width L of the first semiconductor element 200 in the second horizontal direction may be in the range of 125% to 220% of the width W in the first horizontal direction. The width L of the first semiconductor element 200 in the second horizontal direction may be in the range of 130% to 210% of the width W in the first horizontal direction. The width L of the first semiconductor element 200 in the second horizontal direction may be in the range of 140% to 200% of the width W in the first horizontal direction.

[0223] For example, the width W of the first semiconductor element 200 in the first horizontal direction may be in the range of 200 μm±15 μm, the width L of the second horizontal direction may be in the range of 400 μm±15 μm, and the thickness T of the first semiconductor element 200 may be in the range of 200 μm±50 μm.

[0224] As another example, the first horizontal width W of the first semiconductor element 200 may range from 300 μm±15 μm, the second horizontal width L may range from 600 μm±15 μm, and the thickness T of the first semiconductor element 200 may range from 400 μm±100 μm.

[0225] As another example, the width W of the first semiconductor element 200 in the first horizontal direction may be in the range of 500 μm±15 μm, the width L of the second horizontal direction may be in the range of 1000 μm±15 μm, and the thickness T of the first semiconductor element 200 may be in the range of 450 μm±250 μm.

[0226] As another example, the width W of the first semiconductor device 200 in the first horizontal direction may be in the range of 800 μm±15 μm, and the width L of the second horizontal direction may be in the range of 1500 μm±15 μm.

[0227] As another example, the width W of the first semiconductor device 200 in the first horizontal direction may be in the range of 1300 μm±15 μm, and the width L of the second horizontal direction may be in the range of 2000 μm±15 μm.

[0228] As another example, the width W of the first semiconductor device 200 in the first horizontal direction may be in the range of 2000 μm±15 μm, and the width L of the second horizontal direction may be in the range of 2500 μm±15 μm.

[0229] As another example, the width W of the first semiconductor device 200 in the first horizontal direction may be in the range of 1500 μm±15 μm, and the width L of the second horizontal direction may be in the range of 3000 μm±15 μm.

[0230] As another example, the width W of the first semiconductor device 200 in the first horizontal direction may be in the range of 2500 μm±15 μm, and the width L of the second horizontal direction may be in the range of 3200 μm±15 μm.

[0231] As another example, the width W of the first semiconductor device 200 in the first horizontal direction may be in the range of 1600 μm±15 μm, and the width L of the second horizontal direction may be in the range of 4500 μm±15 μm.

[0232] As another example, the width W of the first semiconductor device 200 in the first horizontal direction may be in the range of 3000 μm±15 μm, and the width W of the second horizontal direction may be in the range of 4600 μm±15 μm.

[0233] As another example, the width W of the first semiconductor device 200 in the first horizontal direction may be in the range of 250 μm±15 μm, and the width L of the second horizontal direction may be in the range of 5000 μm±15 μm.

[0234] As another example, the width W of the first semiconductor device 200 in the first horizontal direction may be in the range of 3200 μm±15 μm, and the width L of the second horizontal direction may be in the range of 6300 μm±15 μm.

[0235] As another example, the width W of the first semiconductor device 200 in the first horizontal direction may be in the range of 6300 μm±15 μm, and the width W of the second horizontal direction may be in the range of 6900 μm±15 μm.

[0236] As another example, the width W of the first semiconductor device 200 in the first horizontal direction may be in the range of 5100 μm±15 μm, and the width L of the second horizontal direction may be in the range of 7400 μm±15 μm.

[0237] The circuit board of the embodiment includes a first region in which a first semiconductor element is disposed.

[0238] The circuit board also includes a 1-1 pad and a 1-2 pad. The 1-1 pad and the 1-2 pad are provided so as to vertically overlap the first semiconductor element. Exemplarily, the 1-1 pad and the 1-2 pad are provided in a first region of the circuit board. The embodiment also includes a protective layer. The protective layer is provided surrounding at least a part of the side surfaces of the 1-1 pad and the 1-2 pad, and includes a first protective pattern disposed between the 1-1 pad and the 1-2 pad. The protective layer also includes a second protective pattern provided surrounding the periphery of the first protective pattern.

[0239] The first protective pattern contacts at least a part of the side of the 1-1 pad and the 1-2 pad without contacting the upper surfaces of the 1-1 pad and the 1-2 pad. For example, the upper surface of the first protective pattern is located lower than the upper surfaces of the 1-1 pad and the 1-2 pad. Therefore, the embodiment can reduce the thickness and width of the contact member disposed on the 1-1 pad and the 1-2 pad by using the first protective pattern.

[0240] For example, in the first comparative example, the thickness of the contact member was increased due to the provision of the protective layer, while in the second comparative example, the degree of expansion of the contact member was greater due to the absence of the protective layer, thereby increasing the width of the contact member.

[0241] In contrast, the embodiment may reduce the width of the contact member by reducing the degree of expansion of the contact member using a combination of the first and second protective patterns. Also, in the embodiment, only the first protective pattern is provided in the region vertically overlapping with the first semiconductor element. Exemplarily, the second protective pattern does not vertically overlap with the first semiconductor element. Therefore, the embodiment may prevent an increase in the contact member due to the height of the protective layer.

[0242] As a result, the embodiment can reduce the thickness of the semiconductor package, thereby achieving miniaturization. Furthermore, the embodiment can solve the short circuit problem caused by connection between adjacent contact members by reducing the degree of expansion of the contact members. As a result, the embodiment can improve the electrical reliability and product reliability of the semiconductor package. Furthermore, by solving the short circuit problem in the embodiment, it is not necessary to increase the distance between the 1-1 pad and the 1-2 pad, thereby improving the circuit integration.

[0243] In addition, the embodiment can solve the problem of the adhesive material penetrating between the insulating layer and the pad by using the first protection pattern, thereby further improving the reliability of the product.

[0244] On the other hand, in the first embodiment, the vertical cross-section of first pattern portion 120-1 has been described as having a rectangular shape, and therefore the top surface of first pattern portion 120-1 is flat and at least a portion of the side surface of first pattern portion 120-1 does not contact first protective pattern 141 of protective layer 140.

[0245] FIG. 9 is a plan view of a first region of a circuit board according to the second embodiment.

[0246] 9, the first pattern unit 120-1a may be deformed during the process of forming the circuit pattern. For example, the top surface of the first pattern unit 120-1a may have a curved surface rather than a flat surface.

[0247] This allows the height of the upper surfaces of first pad 120-11a and second pad 120-12a of first pattern portion 120-1a to vary in the horizontal direction.

[0248] When the upper surfaces of the first pad 120-11a and the second pad 120-12a have curved surfaces as in FIG. 9, it may be difficult to confirm exactly how far the upper surfaces of the first pad 120-11a and the second pad 120-12a extend.

[0249] In this case, the upper surfaces of the first pad 120-11a and the second pad 120-12a in the second embodiment may refer to the start and end portions of the curved surfaces.

[0250] As a result, the first protective pattern 141-1 of the protective layer 140 can cover the entire side surfaces of the first pad 120-11a and the second pad 120-12a, or alternatively, can cover only a portion of the side surfaces.

[0251] However, the uppermost end UM2 of the first protection pattern 141-1 may be located lower than the uppermost end UM1 of the first pad 120-11a and the second pad 120-12a.

[0252] 10a is a plan view of a first region of a circuit board according to the third embodiment, FIG. 10b is a cross-sectional view taken along the E-E' direction of FIG. 10a, FIG. 10c is a cross-sectional view taken along the F-F' direction of FIG. 10a, and FIG. 10d is a diagram of a modified example of the structure of FIG. 10c.

[0253] The first region of the circuit board according to the third embodiment will be specifically described below with reference to FIGS. 10a to 10d.

[0254] In the first region R1a of the third embodiment, a first pattern portion 120-1 is disposed. The first pattern portion 120-1 includes a 1-1 pad 120-11 and a 1-2 pad 120-12.

[0255] In the first region R1a, the protective portion 141a of the protective layer 140 is disposed.

[0256] Protective portion 141a may have different heights depending on the position. Preferably, protective portion 141a does not contact the top surface of first pattern portion 120-1 but contacts at least a part of the side surface of first pattern portion 120-1. Here, protective portion 141 contacting at least a part of the side surface of first pattern portion 120-1 means that at least a part of the side surface of first pattern portion 120-1 does not contact first protective layer 140.

[0257] Protection portion 141a includes first protection pattern 141-1a adjacent to first pattern portion 120-1 in first region R1a and second protection pattern 141-2a other than first protection pattern 141-1a.

[0258] For example, the first protective pattern 141-1a may be disposed in at least a portion of the peripheral region of the side of the 1-1 pad 120-11 and the 1-2 pad 120-12. In this case, the first protective pattern 141-1 of the previous embodiment is disposed to entirely surround the peripheral region of the first pad 120-11 and the second pad 120-12. The first protective pattern 141-1 of the previous embodiment is disposed to surround the peripheral region of the first pad 120-11 and the second pad 120-12 in a closed loop shape.

[0259] In contrast, the first protection pattern 141-1a in the third embodiment may be disposed in at least a portion of the surrounding area of ​​the side surface of the 1-1 pad 120-11 and the 1-2 pad 120-12. That is, the first protection pattern 141-1a does not have to be disposed in at least a portion of the surrounding area of ​​the first pad 120-11 and the second pad 120-12. For example, the first protection pattern 141-1a is disposed to surround the surrounding area of ​​the first pad 120-11 and the second pad 120-12 in a closed loop shape.

[0260] 10b, the first protective pattern 141-1a includes a first portion 141-11a disposed between the 1-1 pad 120-11 and the 1-2 pad 120-12. The first protective pattern 141-1a also includes a second portion 141-12a disposed to surround the side of the 1-1 pad 120-11, the side of the 1-2 pad 120-12, and the side of the first portion 141-11a. The second portion 141-12a may not contact at least a part of the side of the 1-1 pad 120-11 and the side of the 1-2 pad 120-12.

[0261] Meanwhile, second protection pattern 141-2a is disposed around first protection pattern 141-1a. Second protection pattern 141-2a may have a thickness greater than that of first protection pattern 141-1a. Second protection pattern 141-2a may have a thickness greater than that of first pattern portion 120-1a.

[0262] Second protection pattern 141-2a is disposed to surround the periphery of first protection pattern 141-1a.

[0263] Furthermore, at least a portion of the second protection pattern 141-2a may be in direct contact with the side surface of the 1-1 pad 120-11 and the side surface of the 1-2 pad 120-12.

[0264] For example, the 1-1 pad 120-11 includes a plurality of side surfaces. The plurality of side surfaces of the 1-1 pad 120-11 include a 1-1 side surface facing the side surface of the 1-2 pad 120-12 and a 1-2 side surface opposite to the 1-1 side surface. The second protection pattern 141-2a may be in direct contact with at least a portion of the 1-2 side surface of the 1-1 pad 120-11.

[0265] The 1-2 pad 120-12 also includes a plurality of side surfaces. The plurality of side surfaces of the 1-2 pad 120-12 include a 2-1 side surface facing the 1-1 side surface of the 1-1 pad 120-11 and a 2-2 side surface opposite the 2-1 side surface. The second protection pattern 141-2a may be in direct contact with at least a portion of the 2-2 side surface of the 1-2 pad 120-12.

[0266] As a result, in the embodiment, the second protective pattern 141-2a can be used to prevent the adhesive member from coming off to the outside of the 1-1 pad 120-11 and the 1-2 pad 120-12, thereby improving reliability. However, although the second protective pattern 141-2a is in direct contact with a part of the side surface of the 1-1 pad 120-11 and the 1-2 pad 120-12, in this structure, when a first semiconductor element is mounted on the 1-1 pad 120-11 and the 1-2 pad 120-12, the second protective pattern 141-2a has a structure that does not overlap the first semiconductor element in the thickness direction.

[0267] Meanwhile, as shown in FIG. 10d, the second protection pattern 141-2a may be in contact with one side of the 1-1 pad 120-11 and the 1-2 pad 120-12 but not in contact with the other side.

[0268] That is, the second protection pattern 141-2a may include a first portion 141-22a that directly contacts at least a portion of the 1-2 side of the 1-1 pad 120-11.

[0269] In addition, the second protection pattern 141-2a may include a second portion 141-21a disposed around the first protection pattern 141-1a without contacting the entire side surface of the 1-2 pad 120-12.

[0270] FIG. 11a is a plan view of a first region of a circuit board according to a fourth embodiment, and FIG. 11b is a cross-sectional view taken along the line GG' in FIG. 10a.

[0271] The first region of the circuit board according to the fourth embodiment will be specifically described below with reference to FIGS. 11a and 11b.

[0272] In the fourth embodiment, a first pattern portion 120-1 is disposed in the first region R1b. The first pattern portion 120-1 includes a 1-1 pad 120-11 and a 1-2 pad 120-12.

[0273] In the first region R1b, the protective portion 141b of the protective layer 140 is disposed.

[0274] The protective portions 141b may have different heights depending on the positions. Preferably, the protective portion 141b includes a first protective pattern 141-1b adjacent to the first pattern portion 120-1 in the first protective pattern first region R1b and a second protective pattern 141-2b other than the first protective pattern 141-1b.

[0275] For example, the first protective pattern 141-1b may be disposed in at least a portion of the peripheral region of the side of the 1-1 pad 120-11 and the 1-2 pad 120-12. In this case, the first protective pattern 141-1 of the previous embodiment is disposed to entirely surround the peripheral region of the first pad 120-11 and the second pad 120-12. The first protective pattern 141-1 of the previous embodiment is disposed to surround the peripheral region of the first pad 120-11 and the second pad 120-12 in a closed loop shape.

[0276] In contrast, the first protection pattern 141-1b in the fourth embodiment may be disposed in at least a portion of the surrounding area of ​​the side surface of the 1-1 pad 120-11 and the 1-2 pad 120-12. That is, the first protection pattern 141-1b may not be disposed in at least a portion of the surrounding area of ​​the first pad 120-11 and the second pad 120-12. For example, the first protection pattern 141-1b may be disposed to surround the surrounding area of ​​the first pad 120-11 and the second pad 120-12 in a closed loop shape.

[0277] That is, as shown in FIGS. 11a and 11b, the first protection pattern 141-1b is disposed between the 1-1 pad 120-11 and the 1-2 pad 120-12.

[0278] Furthermore, the first protection pattern 141-1b may come into contact with at least a part of the side surface of the 1-1 pad 120-11 and the side surface of the 1-2 pad 120-12.

[0279] Meanwhile, the second protection pattern 141-2b may have a thickness greater than that of the first protection pattern 141-1b. Also, the second protection pattern 141-2b may have a thickness greater than that of the first pattern portion 120-1b.

[0280] Second protection pattern 141-2b is disposed to surround the periphery of first protection pattern 141-1b.

[0281] Furthermore, at least a portion of the second protection pattern 141-2b may be in direct contact with the upper surface and side surface of the 1-1 pad 120-11 and the upper surface and side surface of the 1-2 pad 120-12.

[0282] For example, the 1-1 pad 120-11 includes a plurality of side surfaces. The plurality of side surfaces of the 1-1 pad 120-11 include a 1-1 side surface facing a side surface of the 1-2 pad 120-12 and a 1-2 side surface S12 opposite to the 1-1 side surface S11. The second protection pattern 141-2b may contact the 1-2 side surface S12 of the 1-1 pad 120-11 and a portion of the upper surface of the 1-1 pad 120-11 adjacent to the 1-2 side surface S12.

[0283] The 1-2 pad 120-12 also includes a plurality of side surfaces. The plurality of side surfaces of the 1-2 pad 120-12 include a 2-1 side surface S21 that faces the 1-1 side surface S11 of the 1-1 pad 120-11, and a 2-2 side surface S22 that is opposite to the 2-1 side surface S21. The second protection pattern 141-2b may come into contact with the 2-2 side surface S22 of the 1-2 pad 120-12 and a portion of the upper surface of the 1-2 pad 120-12 adjacent to the 2-2 side surface S22.

[0284] As a result, in the embodiment, the adhesive member can be prevented from coming off to the outside of the 1-1 pad 120-11 and the 1-2 pad 120-12 by using the second protective pattern 141-2b. This can improve reliability. However, although the second protective pattern 141-2b is in direct contact with the upper surface and part of the side surface of the 1-1 pad 120-11 and the 1-2 pad 120-12, when the first semiconductor element is mounted on the 1-1 pad 120-11 and the 1-2 pad 120-12 in such a structure, the second protective pattern 141-2b has a structure that does not overlap with the first semiconductor element in the thickness direction.

[0285] FIG. 12 is a cross-sectional view showing a semiconductor package according to an embodiment, FIG. 13a is an enlarged view of the arrangement area of ​​the first semiconductor element in FIG. 12 according to the first embodiment, and FIG. 13b is an enlarged view of the arrangement area of ​​the first semiconductor element in FIG. 12 according to the second embodiment.

[0286] The semiconductor package of the embodiment can have a structure in which a semiconductor element is mounted on at least one of the circuit boards described above.

[0287] For example, the semiconductor package may include a first connection portion 310 disposed on the first pattern portion 121 of the circuit layer 120 .

[0288] The first connecting portion 310 may include a spherical shape. For example, the cross section of the first connecting portion 310 may include a circular or semicircular shape. For example, the cross section of the first connecting portion 310 may include a partially or entirely rounded shape. The cross section of the first connecting portion 310 may have a flat surface on one side and a curved surface on the other side. The first connecting portion 310 may be, but is not limited to, a solder ball.

[0289] Alternatively, the first connecting portion 310 may have a hexahedral shape. For example, the cross section of the first connecting portion 310 may include a quadrangular shape. The cross section of the first connecting portion 310 may include a rectangular shape or a square shape.

[0290] The first semiconductor element 200 may be mounted on the first connection portion 310. The first semiconductor element 200 may be a passive chip. For example, the first semiconductor element 200 may be, but is not limited to, a multilayer ceramic capacitor. Meanwhile, although the drawings show one first semiconductor element 200 disposed in the semiconductor package, a plurality of first semiconductor elements may actually be disposed in the first region of the embodiment.

[0291] The semiconductor package also includes a second connection portion 320 disposed on the second pattern portion 122 of the circuit layer 120 .

[0292] The second semiconductor device 400 is disposed on the second connection portion 320. The second chip 420 may be a processor chip. For example, the second semiconductor device 400 may be any one of an application processor (AP) of a central processor (e.g., CPU), a graphic processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller.

[0293] At this time, the bottom surface of the second semiconductor element 400 may include a terminal 425, and the terminal 425 may be electrically connected to the second pattern unit 120-2 of the circuit board via the second connection unit 320.

[0294] Meanwhile, the semiconductor package of the embodiment may have a plurality of second semiconductor elements arranged on a single circuit board at regular intervals, for example, the second semiconductor elements may include a 2-1 semiconductor element and a 2-2 semiconductor element spaced apart from each other.

[0295] The 2-1 semiconductor device and the 2-2 semiconductor device may be different types of application processor (AP) chips.

[0296] Meanwhile, the 2-1 semiconductor element and the 2-2 semiconductor element may be spaced apart at a fixed distance on the circuit board. For example, the separation width between the 2-1 semiconductor element and the 2-2 semiconductor element may be 150 μm or less. For example, the separation width between the 2-1 semiconductor element and the 2-2 semiconductor element may be 120 μm or less. For example, the separation width between the 2-1 semiconductor element and the 2-2 semiconductor element may be 100 μm or less.

[0297] Preferably, for example, the interval between the 2-1 semiconductor element and the 2-2 semiconductor element may be in the range of 60 μm to 150 μm. For example, the interval between the 2-1 semiconductor element and the 2-2 semiconductor element may be in the range of 70 μm to 120 μm. For example, the interval between the 2-1 semiconductor element and the 2-2 semiconductor element may be in the range of 80 μm to 110 μm. For example, if the interval between the 2-1 semiconductor element and the 2-2 semiconductor element is smaller than 60 μm, interference between the 2-1 semiconductor element and the 2-2 semiconductor element may cause problems in the operational reliability of the 2-1 semiconductor element and the 2-2 semiconductor element. For example, if the interval between the 2-1 semiconductor element and the 2-2 semiconductor element is larger than 150 μm, the signal transmission loss may increase as the distance between the 2-1 semiconductor element and the 2-2 semiconductor element increases.

[0298] The semiconductor package further includes a third connection portion 330 disposed in the third region R3. The third connection portion 330 may be disposed on the third pattern portion 120-3 of the circuit layer 120 of the embodiment. The third connection portion 330 may be a connection portion for coupling to another external board (e.g., a memory board).

[0299] The semiconductor package may also include a molding layer 500. The molding layer 500 may be disposed to cover the first semiconductor element 200 and the second chip 400. For example, the molding layer 500 may be, but is not limited to, an epoxy mold compound (EMC) formed to protect the mounted first semiconductor element 200 and the second chip 400. The molding layer 500 may include an opening that exposes an upper surface of the third connection portion 330. For example, the upper surface of the third connection portion 330 may not be in contact with the molding layer 500. The third connection portion 330 may be a solder ball, or alternatively, may be a post bump.

[0300] At this time, the molding layer 500 may have a low dielectric constant in order to enhance heat dissipation characteristics. For example, the dielectric constant (Dk) of the molding layer 500 may be 0.2 to 10. For example, the dielectric constant (Dk) of the molding layer 500 may be 0.5 to 8. For example, the dielectric constant (Dk) of the molding layer 500 may be 0.8 to 5. Thus, in the embodiment, the molding layer 500 has a low dielectric constant, so that the heat dissipation characteristics for heat generated in the first semiconductor element 200 and the second chip 400 can be enhanced.

[0301] Meanwhile, the package substrate may include a fourth connection portion 340 disposed on the bottom side of the circuit board. The fourth connection portion 340 may be for bonding between the semiconductor package and an external substrate (e.g., a main substrate of an external device).

[0302] Similar to FIG. 13a, in the embodiment, the first connection portion 310 is disposed on the 1-1 pad 120-11 and the 1-2 pad 120-12 of the first pattern portion 120-1.

[0303] At this time, the first connection portion 310 contacts at least a part of the side surfaces of the 1-1 pad 120-11 and the 1-2 pad 120-12. The first connection portion 310 does not contact at least a part of the side surfaces of the 1-1 pad 120-11 and the 1-2 pad 120-12. For example, the first connection portion 310 may contact the upper surface of the first protective pattern 141-1 of the protective layer 140.

[0304] As a result, the bottom end of first connection portion 310 in the embodiment can be located higher than the upper surface of insulating layer 110. Also, the bottom end of first connection portion 310 in the embodiment is located higher than the lower surface of first pattern portion 120-1 but lower than the upper surface.

[0305] Therefore, in the embodiment, the width W10 of the first connection portion 310 can be reduced compared to the comparative example. For example, the width W10 of the first connection portion 310 can be 125% or less of the width in the second horizontal direction of the 1-1 pad 120-11 and the 1-2 pad 120-12. For example, the width W10 of the first connection portion 310 can be 120% or less of the width in the second horizontal direction of the 1-1 pad 120-11 and the 1-2 pad 120-12. As a result, in the embodiment, the distance W11 between the first connection portion arranged on the 1-1 pad 120-11 and the first connection portion arranged on the 1-2 pad 120-12 can be increased compared to the comparative example.

[0306] For example, when the spacing between pads 1-1 and 1-2 in the comparative example and the embodiment is equal, the spacing W11 between the multiple first connection parts in the embodiment can be 90% or less, 80% or less, or even 70% or less of the spacing between the multiple first connection parts in the comparative example.

[0307] On the other hand, the first connection portion 310 in FIG. 13a had the shape of a circular solder ball.

[0308] Alternatively, as shown in Fig. 13b, the first connection portion 310B of the second embodiment may have the shape of a solder fillet. For example, the first connection portion 310B of the second embodiment may be a paste.

[0309] In addition, the first connection portion 310B may form a solder fillet that expands to a side surface of the first semiconductor element 200B as the first semiconductor element 200B is seated in a state in which the first connection portion 310B is disposed on the 1-1 pad 120-11 and the 1-2 pad 120-12.

[0310] In addition, when the first semiconductor element 200B is mounted by applying the first connection portion 310B of the second embodiment, the distance (e.g., the distance in the vertical direction or thickness direction) between the first pattern portion 120-1 and the first semiconductor element 200B can be further reduced compared to the first embodiment. In this case, when the first connection portion 310B of the second embodiment is applied, the first protection pattern 141-1 of the protection layer 140 between the 1-1 pad 120-11 and the 1-2 pad 120-12 can be omitted. However, even when the first connection portion 310B of the second embodiment is applied, a problem may occur in that the first connection portion 310B penetrates between the insulating layer and the first pattern portion. Furthermore, a short circuit problem may occur in which the 1-1 pad 120-11 and the 1-2 pad 120-12 are electrically connected to each other by the first connection portion 310B. Therefore, in the second embodiment, the first protection pattern 141-1 of the protection layer 140 is disposed between the 1-1 pad 120-11 and the 1-2 pad 120-12, thereby making it possible to solve the reliability problem caused by the flow of the first connection portion 310B.

[0311] The circuit board of the embodiment includes a first region in which a first semiconductor element is disposed.

[0312] The circuit board also includes a 1-1 pad and a 1-2 pad. The 1-1 pad and the 1-2 pad are provided so as to vertically overlap the first semiconductor element. Exemplarily, the 1-1 pad and the 1-2 pad are provided in a first region of the circuit board. The embodiment also includes a protective layer. The protective layer is provided surrounding at least a part of the side surfaces of the 1-1 pad and the 1-2 pad, and includes a first protective pattern disposed between the 1-1 pad and the 1-2 pad. The protective layer also includes a second protective pattern provided surrounding the periphery of the first protective pattern.

[0313] The first protective pattern contacts at least a part of the side of the 1-1 pad and the 1-2 pad without contacting the upper surfaces of the 1-1 pad and the 1-2 pad. For example, the upper surface of the first protective pattern is located lower than the upper surfaces of the 1-1 pad and the 1-2 pad. Therefore, the embodiment can reduce the thickness and width of the contact member disposed on the 1-1 pad and the 1-2 pad by using the first protective pattern.

[0314] For example, in the first comparative example, the thickness of the contact member was increased due to the provision of the protective layer, while in the second comparative example, the degree of expansion of the contact member was greater due to the absence of the protective layer, thereby increasing the width of the contact member.

[0315] In contrast, the embodiment may reduce the expansion degree of the contact member by using a combination of the first and second protective patterns, thereby reducing the width of the contact member. Also, in the embodiment, only the first protective pattern is provided in the region vertically overlapping with the first semiconductor element. Exemplarily, the second protective pattern does not vertically overlap with the first semiconductor element. Therefore, the embodiment may prevent an increase in the contact member due to the height of the protective layer.

[0316] As a result, the embodiment can reduce the thickness of the semiconductor package, thereby achieving miniaturization. Furthermore, the embodiment can reduce the degree of expansion of the contact members, thereby solving the short circuit problem caused by the connection between adjacent contact members. As a result, the embodiment can improve the electrical reliability and product reliability of the semiconductor package. Furthermore, by solving the short circuit problem in the embodiment, it is not necessary to increase the distance between the 1-1 pad and the 1-2 pad, thereby improving the circuit integration.

[0317] In addition, the embodiment can solve the problem of the adhesive material penetrating between the insulating layer and the pad by using the first protection pattern, thereby further improving product reliability.

[0318] 14 to 21 are cross-sectional views showing the manufacturing process of the circuit board according to the embodiment in the order of steps.

[0319] 14, in an embodiment, a first insulating layer 111 based on the manufacture of a circuit board is prepared. The first insulating layer 111 can be, but is not limited to, a core layer.

[0320] Next, in the embodiment, a first through electrode 131 is formed to penetrate the first insulating layer 111. Then, in the embodiment, in addition to forming the first through electrode 131, a process of forming a first circuit layer 121 on the upper surface of the first insulating layer 111 and forming a fourth circuit layer 124 on the lower surface of the first insulating layer 111 is performed.

[0321] Next, referring to FIG. 15, in this embodiment, a second insulating layer 112 is laminated on an upper surface of a first insulating layer 111, and a fourth insulating layer 114 is laminated on a lower surface of the first insulating layer 111.

[0322] Thereafter, in the embodiment, a step of forming the second through electrode 132 and the second circuit layer 122 in the second insulating layer 112 is performed. In addition, in the embodiment, a step of forming the fourth through electrode 132 and the fifth circuit layer 125 in the fourth insulating layer 114 is performed.

[0323] Next, referring to FIG. 16, in this embodiment, a third insulating layer 113 is laminated on the upper surface of the second insulating layer 112, and a fifth insulating layer 115 is laminated on the lower surface of the fourth insulating layer 114.

[0324] Thereafter, in the embodiment, a step of forming a third through electrode 133 and a third circuit layer 123 in the third insulating layer 113 is performed. In addition, in the embodiment, a step of forming a fifth through electrode 135 and a sixth circuit layer 126 in the fifth insulating layer 115 is performed.

[0325] 17, in the embodiment, a first solder resist layer 140L is formed on the third insulating layer 113, and a second solder resist layer 150L is formed under the fifth insulating layer 115. At this time, the first solder resist layer 140L is disposed on the third insulating layer 113 so as to entirely cover the third circuit layer 123. In addition, the second solder resist layer 150L is disposed under the fifth insulating layer 115 so as to entirely cover the sixth circuit layer 126.

[0326] Next, referring to FIG. 18, in the embodiment, a process may be performed in which the first solder resist layer 140L and the second solder resist layer 150L are each partially exposed to light and cured.

[0327] As a result, the first solder resist layer 140L in the embodiment can be subjected to sectionwise exposure and curing in the first region R1, the second region R2, and the third region R3. As a result, the first region R1 can include a cured region 140L1 and an uncured region 140L2. At this time, the cured region 140L1 in the first region R1a does not vertically overlap the third circuit layer 123 arranged in the first region R1a.

[0328] The second region R2 may include only the uncured region 140L2, and the third region R3 may include the cured region 140L1 and the uncured region 140L2.

[0329] 19, in an embodiment, a thinning process may be performed to develop the uncured region 140L2. The height of the uncured region 140L2 may be reduced by the thinning process. In this case, the height of the uncured region 140L2 may be freely adjusted by adjusting the thinning process conditions (e.g., process time).

[0330] The thinning process may include a process of thinning the uncured region 140L2 using an organic alkaline compound containing tetramethylammonium hydroxide (TMAH) or trimethyl-2-hydroxyethylammonium hydroxide (choline), etc.

[0331] 20, in the embodiment, a process of curing the uncured region 140L2 in the first region R1 can be performed. At this time, according to the first embodiment, the second region R2 has a structure in which the protective layer 140 is not disposed, so the uncured region 140L2 in the second region R2 may not be cured. However, since the third protective pattern 142 remains in the second region R2 in the second embodiment, a process of curing the uncured region in the second region R2 can be performed.

[0332] Next, referring to FIG. 21, in an embodiment, a process may be performed in which the uncured area of ​​the second region R2 is thinned to remove all of the protective layer 140 present in the second region R2.

[0333] Meanwhile, when the circuit board having the above-mentioned inventive features is used in IT devices and home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when the circuit board having the features of the present invention functions as a semiconductor package, it can safely protect the semiconductor chip from external moisture and contaminants, and can solve the problems of leakage current or electrical short circuit between terminals, or electrical open of terminals supplying power to the semiconductor chip. In addition, when it functions as a signal transmission, it can solve the noise problem. Through this, the circuit board having the above-mentioned inventive features can maintain stable functions of IT devices and home appliances, and the entire product and the circuit board to which the present invention is applied can form functional unity or technical interrelationship with each other.

[0334] When the circuit board having the above-mentioned features of the present invention is used in a transportation device such as a vehicle, it can solve the problem of distortion of signals transmitted to the transportation device, safely protect the semiconductor chip that controls the transportation device from the outside, and solve the problems of leakage current or electrical short circuit between terminals, or electrical open of terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board to which the present invention is applied can be functionally integrated or technically linked with each other.

[0335] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person having ordinary skill in the art to which the embodiment belongs. Therefore, the contents related to such combinations and modifications should be interpreted as being included in the scope of the embodiment.

[0336] The above description focuses on the embodiments, but these are merely illustrative and do not limit the embodiments. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically illustrated in the embodiments can be modified and implemented. Differences related to such modifications and applications should be interpreted as being included in the scope of the embodiments defined in the appended claims.

Claims

1. An insulating layer; a circuit layer disposed on the insulating layer; a protective layer disposed on the insulating layer; the circuit layer includes a first-1 pad and a first-2 pad spaced apart from each other in a first horizontal direction; The protective layer is a first protection pattern disposed along side surfaces of the first-1 pad and the first-2 pad and between the first-1 pad and the first-2 pad; a second protection pattern surrounding the first protection pattern, an upper surface of the first protection pattern is located lower than upper surfaces of the 1-1 pad and the 1-2 pad; an upper surface of the second protection pattern is located higher than upper surfaces of the 1-1 pad and the 1-2 pad; The first-1 pad and the first-2 pad have different widths in the first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction.

2. The thickness of the first protection pattern is 2. The circuit board according to claim 1, wherein the thickness of at least one of the first-1 pad and the first-2 pad is in the range of 40% to 90%.

3. At least one of the first-1 pad and the first-2 pad has a thickness in the range of 10 μm to 25 μm; 3. The circuit board according to claim 1, wherein the first protection pattern has a thickness in the range of 3 μm to 21 μm.

4. 3. The circuit board according to claim 1, wherein the vertical distance between an upper surface of at least one of the 1-1 pad and the 1-2 pad and an upper surface of the first protection pattern is in the range of 3 μm to 10 μm.

5. At least one of the first-1 pad and the first-2 pad has a curved upper surface; The vertical distance is:

5. The circuit board of claim 4, wherein the distance is a vertical distance from a top end of an upper surface of at least one of the first-1 pad and the first-2 pad to a top end of the first protection pattern.

6. The circuit board according to claim 3 , wherein the second protection pattern has a thickness ranging from 17 μm to 45 μm.

7. The width of each of the first-1 pad and the first-2 pad in the second horizontal direction is 2. The circuit board of claim 1, wherein the width of each of the first-1 pad and the first-2 pad is in the range of 125% to 220% of the width in the first horizontal direction.

8. The first horizontal distance between the first-1 pad and the first-2 pad is:

8. The circuit board according to claim 7, wherein the first horizontal width of each of the first-1 pad and the first-2 pad is in the range of 70% to 120%.

9. 2. The circuit board of claim 1, wherein an inner wall of the second protection pattern is spaced apart from a side surface of at least one of the first pad and the second pad by a distance of 15 μm to 23 μm.

10. the first protection pattern is provided to partially surround side surfaces of the first-1 pad and the first-2 pad, 2. The circuit board according to claim 1, wherein at least a portion of the second protection pattern contacts a side surface of the first-1 pad or a side surface of the first-2 pad.

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