Large area gap filling using volume expansion

Abstract

An exemplary method of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed in the processing region of the semiconductor processing chamber. The substrate may define one or more features along the substrate. The method may include depositing a silicon-containing material on the substrate. The silicon-containing material may extend along the substrate into the one or more features. The method may include providing an oxygen-containing precursor. The method may include annealing the silicon-containing material with the oxygen-containing precursor. The annealing may cause the silicon-containing material to expand within the one or more features. The method may include repeating one or more of the steps to iteratively fill one or more features on the substrate.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. patent application Ser. No. 17 / 737,340, entitled "LARGE AREA GAPFILL USING VOLUMETRIC EXPANSIONS," filed May 5, 2022, which is incorporated by reference in its entirety into this specification.

[0002]

[0002] The present technology relates to methods and components for semiconductor processing. In particular, the present technology relates to systems and methods for depositing silicon-containing materials with reduced void or seam formation. [Background technology]

[0003]

[0003] Integrated circuits are made possible by processes that produce intricately patterned layers of material on a substrate surface. Producing patterned materials on a substrate requires controlled methods for forming and removing materials. As devices become smaller, features in integrated circuits become smaller and the aspect ratios of structures can become larger, making it difficult to maintain the dimensions of these structures during processing steps. Some processing can produce voids or seams in the material, which can result in undesirable or undesirable effects in further processing. Developing materials that can suppress void or seam formation can become more difficult as devices become smaller.

[0004]

[0004] Thus, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. These and other needs are addressed by the present technology. Summary of the Invention

[0005]

[0005] An exemplary method of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed in the processing region of the semiconductor processing chamber. The substrate may define one or more features along the substrate. The method may include depositing a silicon-containing material on the substrate. The silicon-containing material may extend along the substrate into the one or more features. The method may include providing an oxygen-containing precursor. The method may include annealing the silicon-containing material with the oxygen-containing precursor. The annealing may cause the silicon-containing material to expand within the one or more features. The method may include repeating one or more of the steps to iteratively fill one or more features on the substrate.

[0006]

[0006] In some embodiments, one or more features along the substrate may be characterized by tapered sidewalls. The silicon-containing material deposited on the substrate may define a seam or void prior to being annealed with the oxygen-containing precursor. A temperature within the semiconductor processing chamber may be maintained at about 300° C. or greater while depositing the silicon-containing material on the substrate. A pressure within the semiconductor processing chamber may be maintained at about 100 Torr or greater while depositing the silicon-containing material on the substrate. Annealing the silicon-containing material may be performed at a temperature of about 600° C. or greater. The annealing may be performed for a time period of about 30 minutes or greater.

[0007]

[0007] Some embodiments of the present technology may include a semiconductor processing method. The method may include providing a first silicon-containing precursor in a processing region of a semiconductor processing chamber. A substrate may be disposed in the processing region of the semiconductor processing chamber. The substrate may define one or more features along the substrate. The method may generate a plasma of the first silicon-containing precursor. The method may include depositing a first silicon-containing material on the substrate. The first silicon-containing material may extend into the one or more features along the substrate. The method may include providing a second silicon-containing precursor. The method may include depositing a second silicon-containing material on the first silicon-containing material. The second silicon-containing material may extend into the one or more features along the substrate. The method may include providing an oxygen-containing precursor. The method may include annealing the second silicon-containing material with the oxygen-containing precursor. The annealing may cause the second silicon-containing material to expand in the one or more features.

[0008]

[0008] In some embodiments, the first silicon-containing precursor may be or may include tetraethyl orthosilicate. The second silicon-containing precursor may be or may include disilane. Depositing the second silicon-containing material may be performed in a semiconductor processing chamber separate from the semiconductor processing chamber in which the first silicon-containing material was deposited. Annealing the second silicon-containing material may increase the thickness of the second silicon-containing material by about 50% or more. A temperature may be maintained at about 300° C. or greater during depositing the second silicon-containing material on the substrate. Depositing the second silicon-containing material on the first silicon-containing material may be performed as a plasma-free process. The oxygen-containing precursor may be or may include a vapor. Annealing the second silicon-containing material may be performed at a temperature of about 600° C. or greater.

[0009]

[0009] Some embodiments of the present technology may include a semiconductor processing method. The method may include generating a plasma of a first silicon-containing precursor. The method may include depositing a first silicon-containing material on a substrate defining one or more features along the substrate. The first silicon-containing material may extend into the one or more features along the substrate. The method may include providing a second silicon-containing precursor. The method may include depositing a second silicon-containing material on the first silicon-containing material. The second silicon-containing material may extend into the one or more features along the substrate. The method may include providing an oxygen-containing precursor. The method may include generating a plasma of the oxygen-containing precursor. The method may include treating a second silicon-containing material with plasma effluents of the oxygen-containing precursor. The plasma effluents of the oxygen-containing precursor may expand the second silicon-containing material on the substrate.

[0010]

[0010] In some embodiments, generating a plasma of the oxygen-containing precursor can be performed at a temperature of about 450°C or higher. The plasma of the oxygen-containing precursor can be generated at a plasma power of about 800W or higher. The oxygen-containing precursor can be or can include nitrous oxide, diatomic oxygen, or a combination of both. The first silicon-containing precursor can be or can include tetraethyl orthosilicate. The second silicon-containing precursor can be or can include disilane. Treating the second silicon-containing material with the plasma effluent of the oxygen-containing precursor can reduce seams or voids defined within the second silicon-containing material.

[0011]

[0011] Such techniques may provide numerous advantages over conventional systems and techniques. For example, embodiments of the present technique may reduce void or seam size applicable to some substrate features. Furthermore, the present technique may produce silicon-containing films for gap-fill applications, as well as any other application that may benefit from a deposited film characterized by reduced void or seam size. These and other embodiments, along with their many advantages and features, are described in more detail below and in the accompanying drawings.

[0012]

[0012] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings. [Brief description of the drawings]

[0013] [Figure 1]

[0013] A schematic cross-sectional view of an exemplary plasma system according to some embodiments of the present technique is shown. [Diagram 2]

[0014] 1 illustrates steps in a semiconductor processing method, in accordance with some embodiments of the present technique. [Figure 3A]

[0015] 3A-3F show schematic cross-sectional views of exemplary structures that may include layers of material and may be fabricated in accordance with some embodiments of the present technology. [Figure 3B] 3A-3F show schematic cross-sectional views of exemplary structures that may include layers of material and may be fabricated in accordance with some embodiments of the present technology. [Figure 3C] 3A-3F show schematic cross-sectional views of exemplary structures that may include layers of material and may be fabricated in accordance with some embodiments of the present technology. [Figure 3D] 3A-3F show schematic cross-sectional views of exemplary structures that may include layers of material and may be fabricated in accordance with some embodiments of the present technology. [Figure 3E] 3A-3F show schematic cross-sectional views of exemplary structures that may include layers of material and may be fabricated in accordance with some embodiments of the present technology. [Figure 3F]3A-3F show schematic cross-sectional views of exemplary structures that may include layers of material and may be fabricated in accordance with some embodiments of the present technology. [Figure 4]

[0016] 1 illustrates steps in a semiconductor processing method, in accordance with some embodiments of the present technique. [Figure 5A]

[0017] 5A-5D show schematic cross-sectional views of exemplary structures that may include layers of material and may be fabricated in accordance with some embodiments of the present technology. [Figure 5B] 5A-5D show schematic cross-sectional views of exemplary structures that may include layers of material and may be fabricated in accordance with some embodiments of the present technology. [Figure 5C] 5A-5D show schematic cross-sectional views of exemplary structures that may include layers of material and may be fabricated in accordance with some embodiments of the present technology. [Figure 5D] 5A-5D show schematic cross-sectional views of exemplary structures that may include layers of material and may be fabricated in accordance with some embodiments of the present technology. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014]

[0018] Some of the drawings are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes and should not be considered to scale unless expressly stated to be to scale. Moreover, as schematic diagrams, the drawings are provided to aid in understanding and may not include all aspects or information compared to a realistic depiction and may include material that is emphasized for illustrative purposes.

[0015]

[0019] In the accompanying drawings, similar components and / or features may have the same reference numbers. Furthermore, various components of the same type may be distinguished according to the reference numbers, with a letter distinguishing between the similar components. If only a first reference number is used in this specification, the description is applicable to any of the similar components having the same first reference number, regardless of the letter.

[0016]

[0020] As device sizes continue to shrink, many layers of materials may be reduced in thickness and size to scale the devices. Features within semiconductor structures may become smaller and the aspect ratios of the features may increase. As the aspect ratios of features increase, chemical vapor deposition processes may pinch off near the top of the feature before completely filling the feature, resulting in voids or seams within the feature.

[0017]

[0021] Conventional techniques, such as processes associated with 3D NAND, have struggled to produce films that fill high aspect ratio features in underlying structures that inhibit void or seam formation. Deposition of silicon-containing materials on underlying structures containing high aspect ratio trenches can be incomplete because many silicon-containing film depositions produce conformal films. The filling process can result in feature sealing near the top of the feature before filling within the feature. This can result in voids or seams in the fill material in the center of the feature. The voids or seams can extend to the top of the structure. In some fabrications, where a polishing process may follow, removal may expose the voids or seams and provide access into the feature. This can cause oxidation of materials exposed to the atmosphere as well as contamination of slurry or other materials along the voids or seams. Thus, many conventional techniques have limited ability to prevent structural defects in the final device.

[0018]

[0022] The present technology overcomes these problems by annealing the film on the underlying structure to reduce the presence or size of any voids or seams in the film. By annealing the film with an oxygen-containing precursor, the present technology alters the film on the underlying structure, expanding a portion of the film to reduce voids or seams in the film. This allows for subsequent deposition of silicon-containing material to gradually fill the feature while minimizing the formation of voids or seams. By filling the feature or high aspect ratio structure with silicon-containing material with reduced or eliminated voids or seams, the present technology may prevent problems in any subsequent integration process and / or defects in the final device. The remaining disclosure routinely identifies specific deposition processes utilizing the disclosed technology and describes one type of semiconductor processing chamber, but it will be readily understood that the described processes may be performed in any number of semiconductor processing chambers. Thus, the present technology should not be considered limited to use with these specific deposition processes or chambers alone. This disclosure will describe one possible chamber that may be used to carry out processes according to embodiments of the present technology before methods of semiconductor processing according to the present technology are described.

[0019]

[0023] FIG. 1 illustrates a cross-sectional view of an exemplary semiconductor processing chamber 100 according to some embodiments of the present technology. The diagram may provide an overview of a system that may be specifically configured to incorporate one or more aspects of the present technology and / or perform one or more processes according to some embodiments of the present technology. Further details of the chamber 100 or the method performed may be further described below. Although the chamber 100 may be utilized to form a film layer according to some embodiments of the present technology, it should be understood that the method may be similarly performed in any chamber in which film formation may occur. The semiconductor processing chamber 100 may include a chamber body 102, a substrate support 104 disposed within the chamber body 102, and a lid assembly 106 coupled to the chamber body 102 and enclosing the substrate support 104 within a processing space 120. The substrate 103 may be provided to the processing space 120 through an opening 126, which may be conventionally sealed for processing using a slit valve or door. The substrate 103 may be placed on a surface 105 of the substrate support 104 during processing. The substrate support 104 may be rotatable along an axis 147 about which the shaft 144 of the substrate support 104 may be positioned, as indicated by arrow 145. Alternatively, the substrate support 104 may be elevated and rotated as needed during the deposition process.

[0020]

[0024] A plasma profile modulator 111 may be disposed within the semiconductor processing chamber 100 to control the distribution of plasma across the substrate 103 disposed on the substrate support 104. The plasma profile modulator 111 may include a first electrode 108. The first electrode 108 may be disposed adjacent to the chamber body 102 and may separate the chamber body 102 from other components of the lid assembly 106. The first electrode 108 may be part of the lid assembly 106 or may be a separate sidewall electrode. The first electrode 108 may be an annular or ring-shaped member and may be a ring electrode. The first electrode 108 may be a continuous loop around the periphery of the semiconductor processing chamber 100 surrounding the processing space 120 or may be discontinuous at selected locations, if desired. The first electrode 108 may also be a perforated electrode, such as a perforated ring or mesh electrode, or may be a flat electrode, such as a secondary gas distributor.

[0021]

[0025] One or more insulators 110a, 110b, which may be, for example, a dielectric material such as a ceramic or metal oxide, such as aluminum oxide and / or aluminum nitride, may contact the first electrode 108 and electrically and thermally isolate the first electrode 108 from the gas distributor 112 and from the chamber body 102. The gas distributor 112 may define an opening 118 for distributing process precursors into the processing space 120. The gas distributor 112 may be coupled to a first power source 142, such as an RF generator, an RF power source, a DC power source, a pulsed DC power source, a pulsed RF power source, or any other power source that may be coupled to the semiconductor processing chamber 100. In some embodiments, the first power source 142 may be an RF power source.

[0022]

[0026] The gas distributor 112 may be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 may also be formed of conductive and non-conductive components. For example, the body of the gas distributor 112 may be conductive while the faceplate of the gas distributor 112 may be non-conductive. The gas distributor 112 may be powered, such as by a first power source 142 as shown in FIG. 1, or in some embodiments, the gas distributor 112 may be coupled to ground.

[0023]

[0027] The first electrode 108 may be coupled to a first tuned circuit 128 that may control the ground path of the semiconductor processing chamber 100. The first tuned circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be or may include a variable capacitor or other circuit element. The first tuned circuit 128 may be or may include one or more inductors 132. The first tuned circuit 128 may be any circuit that allows for a variable or controllable impedance under the plasma conditions present in the processing space 120 during processing. In some embodiments as shown, the first tuned circuit 128 may include a first circuit leg and a second circuit leg coupled in parallel between ground and the first electronic sensor 130. The first circuit leg may include a first inductor 132A. The second circuit leg may include a second inductor 132B coupled in series with the first electronic controller 134. The second inductor 132B may be disposed between the first electronic controller 134 and a node coupling both the first and second circuit legs to the first electronic sensor 130. The first electronic sensor 130 may be a voltage or current sensor and may be coupled to the first electronic controller 134. The first electronic controller 134 may allow some closed-loop control of the plasma conditions inside the process space 120.

[0024]

[0028] A second electrode 122 may be coupled to the substrate support 104. The second electrode 122 may be embedded in the substrate support 104 or may be coupled to a surface 105 of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a wire screen, or other distributed arrangement of conductive elements. The second electrode 122 may be a tuning electrode and may be coupled to a second tuning circuit 136 by a conduit 146, such as a cable having a selected resistance, such as 50 ohms, disposed in a shaft 144 of the substrate support 104. The second tuning circuit 136 may include a second electronic sensor 138 and a second electronic controller 140. The second electronic controller 140 may be a second variable capacitor. The second electronic sensor 138 may be a voltage or current sensor and may be coupled to the second electronic controller 140 to further control the plasma conditions in the process space 120.

[0025]

[0029] A third electrode 124, which may be a bias electrode and / or an electrostatic chuck electrode, may be coupled to the substrate support 104. The third electrode may be coupled to a second power source 150 through a filter 148. The filter 148 may be an impedance matching circuit. The second power source 150 may be a DC power source, a pulsed DC power source, an RF bias power source, a pulsed RF source or a bias power source, or a combination or other power source. In some embodiments, the second power source 150 may be an RF bias power source. The substrate support 104 may also include one or more heating elements configured to heat the substrate to a processing temperature, which may be between about 25° C. and about 800° C. or above.

[0026]

[0030] The lid assembly 106 and substrate support 104 of FIG. 1 may be used with any processing chamber for plasma or thermal processing. During operation, the semiconductor processing chamber 100 may allow real-time control of plasma conditions within the processing space 120. The substrate 103 may be placed on the substrate support 104, and process gases may be flowed through the lid assembly 106 using the inlet 114 according to any desired flow plan. The gases may exit the semiconductor processing chamber 100 through the outlet 152. A power source may be coupled to the gas distributor 112 to establish a plasma within the processing space 120. In some embodiments, the substrate may be electrically biased using a third electrode 124.

[0027]

[0031] Upon exciting the plasma in the process space 120, a potential difference may be established between the plasma and the first electrode 108. Also, a potential difference may be established between the plasma and the second electrode 122. The electronic controllers 134, 140 may then be used to adjust the flow characteristics of the ground paths represented by the two tuned circuits 128, 136. Set points may be provided for the first tuned circuit 128 and the second tuned circuit 136 to provide independent control of the deposition rate and independent control of the center-to-edge plasma density uniformity. In embodiments where the electronic controllers can both be variable capacitors, the electronic sensors may independently adjust the variable capacitors to maximize the deposition rate and minimize the thickness non-uniformity.

[0028]

[0032] Each of the tuning circuits 128, 136 may have a variable impedance that may be adjusted using the respective electronic controller 134, 140. If the electronic controller 134, 140 is a variable capacitor, the capacitance range of each of the variable capacitors and the inductance of the first inductor 132A and the second inductor 132B may be selected to provide a range of impedances. This range depends on the frequency and voltage characteristics of the plasma, and there may be a minimum value in the capacitance range of each variable capacitor. Thus, when the capacitance of the first electronic controller 134 is at a minimum or maximum, the impedance of the first tuning circuit 128 may be high, resulting in a plasma shape with a minimum aerial or lateral coverage over the substrate support 104. When the capacitance of the first electronic controller 134 approaches a value that minimizes the impedance of the first tuning circuit 128, the aerial coverage of the plasma may grow to a maximum, effectively covering the entire working area of ​​the substrate support 104. When the capacitance of the first electronic controller 134 is moved away from the minimum impedance setting, the plasma shape may shrink from the chamber walls, reducing the air coverage of the substrate support 104. The second electronic controller 140 has a similar effect, and as the capacitance of the second electronic controller 140 can be altered, the air coverage of the plasma on the substrate support 104 can be increased or decreased.

[0029]

[0033] The electronic sensors 130, 138 may be used to tune the respective circuits 128, 136 in a closed loop. Depending on the type of sensor used, a current or voltage set point may be provided for each sensor, and the sensors may be provided with control software that determines adjustments to each respective electronic controller 134, 140 to minimize deviations from the set point. As a result, the plasma shape may be selected and dynamically controlled during processing. Although the above description is based on the electronic controller 134, 140 being a variable capacitor, it will be appreciated that any electronic component having adjustable characteristics may be used to provide the tuned circuits 128, 136 with adjustable impedance.

[0030]

[0034] FIG. 2 illustrates exemplary steps in a processing method 200 according to some embodiments of the present technique. Method 200 may be performed in a variety of processing chambers, including the semiconductor processing chamber 100 described above, as well as any other chambers, including non-plasma chambers, in which steps may be performed. Method 200 may include one or more steps prior to the start of method 200, including front-end processing, deposition, etching, polishing, cleaning, or any other steps that may be performed prior to the steps described. Method 200 may include several optional steps that may or may not be specifically associated with some embodiments of the method according to some embodiments of the present technique. For example, many of the steps are described to provide a broader scope of the processes performed, but are not essential to the present technique, or may be performed by alternative methods as described further below. Method 200 may describe steps shown generally in FIGS. 3A-3F, which will be described in conjunction with the steps of method 200. It should be understood that the figures are partial schematic representations only and that the substrate may include any number of additional materials and features having various properties and aspects as shown.

[0031]

[0035] The method 200 may or may not include optional steps for developing the semiconductor structure into a particular manufacturing process. It will be understood that the method 200 may be performed on any number of semiconductor structures or substrates 305, as shown in FIG. 3A. They include an exemplary structure 300 in which one or more silicon-containing materials may be formed. As shown in FIG. 3A, the substrate 305 may be processed to form one or more features 315. The one or more features 315 may be recesses, such as trenches, openings, or any other structure in semiconductor processing. The substrate 305 may be any number of materials, such as a base wafer or substrate 305 made of silicon or silicon-containing materials, other substrate 305 materials, as well as one or more materials that may be formed overlying the substrate 305 during semiconductor processing. For example, in some embodiments, the substrate 305 may be processed to include one or more materials or structures for semiconductor processing. The substrate 305 may be or include a dielectric material, such as an oxide or nitride of any number of materials. In embodiments, one or more layers of material 310 may be deposited on the substrate 305. In embodiments, the one or more layers of material 310 may be or include a silicon-containing material. The silicon-containing material may be or include silicon, including amorphous silicon, doped silicon, silicon oxide, silicon nitride, or silicon carbide.

[0032]

[0036] As shown, one or more features 315, such as trenches, openings, or other recessed features, may be defined by one or more layers of material 310 and / or substrate 305. The feature 315 may be characterized by tapered sidewalls. In embodiments, the feature 315 may be characterized by a larger diameter or width at the top of the feature 315 than at the bottom of the feature 315. The aspect ratio of the feature 315, i.e., the ratio of the depth of the feature to the width or diameter of the formed feature, may be about 1:1 or more, and may be about 2:1 or more, about 3:1 or more, about 4:1 or more, about 5:1 or more, about 6:1 or more, about 7:1 or more, about 8:1 or more, about 9:1 or more, about 10:1 or more, or more. Although only one feature 315 is shown in the figures, it will be understood that the exemplary structure may have any number of features 315 defined along the structure in accordance with embodiments of the present technology.

[0033]

[0037] Method 200 may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber in step 205. The silicon-containing precursor may be provided to the same processing region of the semiconductor processing chamber for performing multiple steps prior to the start of method 200. The silicon-containing precursor that may be used in method 200 may be or include any number of silicon-containing precursors. For example, the silicon-containing precursor may be or include silane (SiH4), disilane (Si2H6), silicon tetrachloride (SiCl4), tetraethylorthosilicate (TEOS), or any other precursor capable of forming, for example, silicon oxide (SiO), silicon nitride (SiN), or silicon carbide (SiC) materials. In some embodiments, one or more additional precursors, such as a hydrogen-containing precursor, and one or more carrier gases or inert gases, such as, for example, argon or helium, may be provided along with the silicon-containing precursor. In embodiments of the present technique, higher order silanes can be used, which can increase the flowability of the deposited material, but can also increase the hydrogen content in the deposited material, which can lead to outgassing in subsequent processes.

[0034]

[0038] As shown in FIG. 3B, the method 200 may include depositing a silicon-containing material 320a on the substrate 305 (and one or more layers of material 310, if present) in step 210. A silicon-containing precursor may contact the substrate 305 (and one or more layers of material 310, if present). As shown in FIG. 3B, the silicon-containing material 320a extends along any and / or all exposed surfaces along the substrate 305 (when exposed), as well as along any other incorporated materials, such as the one or more layers of material 310. During step 225, growth may occur inwardly within the feature 315 from sidewalls that define the feature 315.

[0035]

[0039] In step 210, depositing the silicon-containing material 320a on the substrate 305 may be performed as a plasma-free process. By performing step 210 plasma-free, the deposition of the silicon-containing material 320a may be highly conformal. In some embodiments, the deposition of the silicon-containing material 320a may be characterized by a conformality of about 80% or more, about 85%, about 90%, about 95%, or more. This high level of conformality may be beneficial during the expansion of the silicon-containing material 320a in a subsequent annealing, as described further below, because the silicon-containing material 320a may expand to the full depth of the feature 315.

[0036]

[0040] As the feature 315 begins to close or fill with the silicon-containing material 320a, a void 330 and / or seam 335 may form in the silicon-containing material 320a. A void 330 may refer to a portion within the feature 315 between the silicon-containing material 320a deposited on the bottom and top of the feature 315. A void 330 may form due to a buildup or "breadloafing" of the silicon-containing material 320a deposited on the top of the feature 315. A seam 335 may refer to a gap or trench that extends into the silicon-containing material 320a at or near the bottom of the feature 315. Although a consistent opening is shown in the figures, the void 330 and / or seam 335 structure may further be characterized by a number of shapes. Some shapes may include wide at the top, wide at the bottom, as well as more irregular shapes, as can be readily understood by one of ordinary skill in the art. As the deposition time increases, the amount of deposition at the top of the feature 315 begins to completely seal the feature 315, thereby forming voids 330 or seams 335 that are covered by the silicon-containing material 320a. As the time increases, the voids 330 or seams 335 can no longer be filled with the silicon-containing material 320a. The technique can incorporate one or more annealing processes to expand the silicon-containing material 320a to reduce or eliminate any voids 330 and / or seams 335.

[0037]

[0041] During the above-mentioned deposition, the semiconductor processing chamber, pedestal, or substrate 305 may be maintained at various temperatures at which the deposition of the film may be performed. In some embodiments, the temperature of the semiconductor processing chamber, pedestal, or substrate 305 may be maintained at about 700° C. or less, about 650° C. or less, about 600° C. or less, about 550° C. or less, about 500° C. or less, or below. In some embodiments, the temperature of the semiconductor processing chamber, pedestal, or substrate 305 may be maintained at about 300° C. or more, about 350° C. or more, about 400° C. or more, about 450° C. or more, about 500° C. or more, or above. This facilitates thermal deposition of the precursors and allows plasma-free deposition to be performed.

[0038]

[0042] Also during the above-mentioned deposition, the semiconductor processing chamber may be maintained at various pressures at which the deposition may be performed. For example, the pressure in the semiconductor processing chamber may be maintained at about 100 Torr or more, about 150 Torr or more, about 200 Torr or more, about 250 Torr or more, about 300 Torr or more, about 350 Torr or more, about 400 Torr or more, or more during the deposition of the silicon-containing material 320a. Similarly, the pressure in the semiconductor processing chamber may be maintained at about 500 Torr or less, about 450 Torr or less, about 400 Torr or less, about 350 Torr or less, about 300 Torr or less, about 250 Torr or less, about 200 Torr or less, or less during the deposition of the silicon-containing material 320a.

[0039]

[0043] Following deposition of the silicon-containing material 320a, the method 200 may include providing an oxygen-containing precursor at step 215. In some embodiments, the method 200 may include stopping the flow of the silicon-containing precursor before step 215. Stopping the flow of the silicon-containing precursor may stop the deposition and allow processing such as annealing of the deposited film to be performed. The oxygen-containing precursor may be provided in the same processing region of the semiconductor processing chamber for depositing the silicon-containing material 320a and continue from the deposition step(s) as described above. In other embodiments, the structure 300 may be moved to a different chamber before step 215. The oxygen-containing precursor that may be used in the method 200 may be or may include any number of oxygen-containing precursors. For example, the oxygen-containing precursor may be or may include nitrous oxide (N2O), water (H2O), dioxygen (O2), ozone (O3), a combination of one or more thereof, or any other oxygen-containing material.

[0040]

[0044] In some embodiments, the method 200 may include generating a plasma of the oxygen-containing precursor in step 220. The plasma power may affect the depth of oxygen penetration, reduce the temperature required to expand the silicon-containing material 320a, and / or increase the amount of voids 330 and / or seams 335 that are removed. Thus, in some embodiments, the plasma power applied when generating the plasma of the oxygen-containing precursor may be about 800 W or more, about 850 W or more, about 900 W or more, about 1000 W or more, or more. However, higher plasma powers may increase collisions and may cause sputtering and / or etching of the silicon-containing material 320a, and thus, in some embodiments, the plasma power may be about 1500 W or less, about 1400 W or less, about 1300 W or less, about 1200 W or less, about 1000 W or less, or less. During generation of the oxygen-containing precursor plasma, the temperature within the semiconductor processing chamber may be maintained at about 450° C. or greater, about 500° C. or greater, about 550° C. or greater, about 600° C. or greater, or greater. During generation of the oxygen-containing precursor plasma, the temperature may be maintained at about 650° C. or less, about 600° C. or less, about 550° C. or less, about 500° C. or less, or less. In embodiments in which a plasma of an oxygen-containing precursor is generated, the oxygen-containing precursor may include one or both of N2O and O2.

[0041]

[0045] As shown in FIG. 3C, the method 200 may include annealing the silicon-containing material 320a with an oxygen-containing precursor or plasma effluents of the oxygen-containing precursor in step 225. As previously mentioned, when depositing the silicon-containing material 320a, voids 330 and / or seams 335 may form in the silicon-containing material 320a due to increased sidewall deposition that may close and encapsulate the feature 315 inward before the feature 315 is completely filled. To reduce or eliminate these voids 330 or seams 335, the present technique may expand the silicon-containing material 320a by annealing the film. The oxygen-containing precursor or plasma effluents of the oxygen-containing precursor, when generated, may cause the silicon-containing material 320a to expand inward from the sidewalls of the feature 315 due to incorporation of oxygen into the silicon-containing material 320a.

[0042]

[0046] The annealing may cause the silicon-containing material 320a to expand within one or more features 315. As the silicon-containing material 320a expands within the feature 315, the material may expand in all directions across the feature 315, reducing any unfilled spaces between the silicon-containing material 320a deposited on the sidewalls of the feature 315. Without being bound by any particular theory, during annealing, the silicon-containing material 320a may expand inwardly and bond across the feature 315 during expansion and annealing. Thus, treating the silicon-containing material 320a with an oxygen-containing precursor (such as a plasma effluent of an oxygen-containing precursor) may reduce any voids 330 or seams 335 defined within the silicon-containing material 320a.

[0043]

[0047] During step 225, the temperature may be elevated compared to the temperature used during the preceding deposition step. The temperature in the semiconductor processing chamber in which the annealing may be performed may be maintained at about 600° C. or higher, about 650° C. or higher, about 700° C. or higher, about 750° C. or higher, about 800° C. or higher, about 850° C. or higher, about 900° C. or higher, or higher, during the annealing of the silicon-containing material 320a. However, at higher temperatures, the substrate 305 and / or one or more layers of material 310 (if present) may also be affected by the annealing. For example, in embodiments using a substrate 305 that is or includes silicon, the substrate 305 may begin to oxidize as well. Thus, the temperature in the semiconductor processing chamber may be maintained at about 1000° C. or lower, about 950° C., about 900° C., about 850° C., about 800° C., about 750° C., about 700° C., or lower, during the annealing of the silicon-containing material 320a. In embodiments in which the silicon-containing material 320a is treated with a plasma effluent of an oxygen-containing precursor, the temperature for performing the annealing and expanding the silicon-containing material 320a may be lower than the temperature for thermally induced oxidation. In such embodiments, the temperature within the semiconductor processing chamber may be maintained at about 600° C. or below, about 575° C., about 550° C., or below, while annealing the silicon-containing material 320a.

[0044]

[0048] In step 225, annealing the silicon-containing material 320a with the oxygen-containing precursor or plasma effluents of the oxygen-containing precursor (if present) may continue for a time sufficient to expand the silicon-containing material 320a in the feature 315 by a desired amount. This time may depend on various factors, including, but not limited to, the depth of the feature 315, the aspect ratio of the feature 315, and / or the thickness of the silicon-containing material 320a. In some embodiments, the annealing may be performed for a time of about 30 minutes or more, and may be about 45 minutes or more, about 60 minutes or more, about 75 minutes or more, about 90 minutes or more, about 105 minutes or more, about 120 minutes or more, about 150 minutes or more, about 180 minutes or more, about 210 minutes or more, about 240 minutes or more, or more. For longer times, treating the silicon-containing material 320a with the oxygen-containing precursor or plasma effluents of the oxygen-containing precursor (if present) may increase the expansion of the silicon-containing material 320a. Thus, in some embodiments, the treatment may be carried out for about 180 minutes or less, about 150 minutes or less, about 120 minutes or less, or less.

[0045]

[0049] During step 225, the thickness of the silicon-containing material 320a may increase depending on the length of time the silicon-containing material 320a is annealed. This may be due, at least in part, to oxygen being incorporated into the film, converting the silicon film to a silicon oxide film. A shorter annealing process may result in a smaller increase in thickness of the silicon-containing material 320a. A longer annealing process may result in a larger increase in thickness of the silicon-containing material 320a. In some embodiments, annealing the silicon-containing material 320a may increase the thickness of the silicon-containing material 320a by about 50% or more, about 60% or more, about 70% or more, about 80% or more, about 90% or more, about 100% or more, about 110% or more, or more. Annealing the silicon-containing material 320a may increase the thickness of the silicon-containing material 320a by about 120% or less, may increase the thickness of the silicon-containing material 320a by about 110%, about 100%, or less.

[0046]

[0050] As shown in Figures 3D-3E, to fill the features 315 while reducing or eliminating the voids 330 and / or seams 335, the method 200 may include sequentially depositing a silicon-containing material (such as an additional silicon-containing material 320b) followed by annealing the additional silicon-containing material 320b with an oxygen-containing precursor. After annealing, the additional silicon-containing material 320b may be combined with the previously annealed silicon-containing material 320a to form a combined silicon-containing material 320c, which may be consistent with the previously annealed silicon-containing material 320a. This process may be repeated for any number of cycles. As shown in Figure 3F, when cycling deposition and annealing of silicon-containing materials, one or more features 315 may be repeatedly filled higher in a bottom-up gap fill, such as toward the top of the feature 315 during each deposition and annealing sequence. As previously described, annealing the silicon-containing material 320b with an oxygen-containing precursor or plasma effluent of an oxygen-containing precursor can cause the silicon-containing material 320b to expand. By repeatedly depositing and annealing the silicon-containing material, the material expands and the voids 330 and / or seams 335 can be reduced or eliminated entirely.

[0047]

[0051] The number of iterations of sequentially depositing and annealing films may depend on various factors, including, but not limited to, the depth of the feature 315, the aspect ratio of the feature 315, the amount of silicon-containing material deposited, and / or the presence of voids 330 and / or seams 335 within the silicon-containing material. In some embodiments, the method 200 of depositing and annealing a silicon-containing material is repeated at least twice and may include depositing and annealing a silicon-containing material at least three times, at least four times, at least five times, at least six times, at least seven times, or more times.

[0048]

[0052] In some embodiments where silicon-containing material 320 is repeatedly deposited in a feature 315 and subsequently annealed, earlier films may expand more than later films. This may be due to the thinner thickness of the subsequently deposited films in the feature 315 to control the expansion. Additionally, as previously described, one or more features 315 along the substrate 305 may be characterized by tapered sidewalls. Due to the conformal deposition previously described, this sidewall profile may challenge gap filling without voids 330 and / or seams 335. However, the present technique may overcome any number of topographies and / or feature shapes to provide reduced or void-free filling of void space.

[0049]

[0053] Some embodiments of the present technique may also provide a non-cyclic loading that may improve throughput. FIG. 4 illustrates exemplary steps in a processing method 400 according to some embodiments of the present technique. The method 400 may be performed in a variety of processing chambers, including the semiconductor processing chamber 100 described above, as well as any other chambers, including non-plasma chambers, in which the steps may be performed. The method 400 may include any of the aspects, materials, or characteristics of the method 200 as described above. The method 400 may include several optional steps that may or may not be specifically associated with some embodiments of the method according to some embodiments of the present technique. For example, many of the steps are described to provide a broader scope of the processes performed, but are not essential to the present technique, or may be performed by alternative methods as described further below. The method 400 may describe the steps shown generally in FIGS. 5A-5D, which will be described in conjunction with the method 400. It should be understood that the figures are only partially schematic and that the substrate may include any number of additional materials and features having various properties and aspects as shown.

[0050]

[0054] Method 400 may or may not include optional steps for developing the semiconductor structure into a particular manufacturing process. It should be understood that method 400 may be performed on any number of semiconductor structures or substrates 505, as shown in FIG. 5A, including exemplary structures 500 on which one or more silicon-containing materials may be formed. Substrate 505 may have any of a number of aspects, qualities, or characteristics as described with respect to substrate 305. Substrate 505 may also have features 515 similar to features 315 described with respect to substrate 305.

[0051]

[0055] In some embodiments, a first silicon-containing material may be deposited prior to depositing the silicon-containing material that may experience deposition expansion. For example, a first silicon oxide material may be formed in the feature to a first thickness. Silicon oxide may then be formed as described above. This may provide a final fill step that may produce a void-reduced or void-free fill. In step 405, method 400 may include providing a first silicon-containing precursor to a processing region of a semiconductor processing chamber, such as semiconductor processing chamber 100, in which substrate 505 may be housed. In some embodiments, an oxygen-containing precursor may be provided along with the silicon-containing precursor. The semiconductor processing chamber may be the same or a different chamber from the chamber in which pre-processing or previous processing steps may be performed. The first silicon-containing precursor may be or may include any of the silicon-containing precursors previously described with respect to step 205 of method 200, as well as any of the oxygen-containing precursors previously described. In some embodiments, a silicon- and oxygen-containing precursor may be used as the first silicon-containing precursor, and may be or include TEOS, for example.

[0052]

[0056] In step 410, the method 400 may include generating a plasma of the first silicon-containing precursor. The method 400 may also include generating a plasma of the oxygen-containing precursor or other deposition precursors (if included). The plasma power may affect the depth of silicon penetration, the degree of bond reorientation, and / or the amount of voids 530 and / or seams 535 that may subsequently result. Thus, in some embodiments, the plasma power applied when generating a plasma of the silicon-containing precursor, such as the first plasma power applied in the method 400, may be about 2000 W or less, about 1500 W or less, about 1250 W or less, about 1000 W or less, about 750 W or less, about 500 W or less, about 250 W or less, or less. However, at lower plasma powers, the plasma effluents of the silicon-containing precursor may not easily reach the full depth of the feature 515, and thus, in some embodiments, the plasma power may be about 250 W or more, about 500 W or more, about 750 W, about 1000 W or more, or more.

[0053]

[0057] As shown in FIG. 5B, the method 400 may include depositing a first silicon-containing material 517 on the substrate 505 and / or one or more layers of material 510 in step 415. In some embodiments, the deposited film may be a film desired for gap filling, such as silicon oxide, as one non-limiting example. A plasma effluent of the first silicon-containing precursor may contact the substrate 505 and may contact the one or more layers of material 510 (if present). As shown in FIG. 5B, the first silicon-containing material 517 extends along any and / or all exposed surfaces along the substrate 505 (when exposed), as well as along any other incorporated materials, such as the one or more layers of material 510. During step 415, growth may occur inwardly within the feature 515 from the sidewalls that define the feature 515. The first silicon-containing material 517 may be silicon or a silicon-containing film, and in some embodiments, the first silicon-containing material may be a silicon and oxygen-containing film.

[0054]

[0058] The deposition of the first silicon-containing material 517 may be substantially conformal, such that growth occurs inwardly into the feature 515 from the sidewalls that define the feature 515. In that case, the growth rate inwardly from the sidewalls may be equal to or less than the growth rate at the bottom and top of the feature 515. The amount of deposition may vary based on the amount of time that the deposition of the first silicon-containing material 517 occurs. Although the amount of deposition may vary, a greater amount of the first silicon-containing material 517 may be deposited at the bottom of the feature 515 than at the top of the feature 515 during deposition in step 415. Additionally, in some embodiments, a greater amount of the first silicon-containing material 517 may be deposited at the bottom and / or top of the feature 515 than at the sidewalls that define the feature 515.

[0055]

[0059] The deposition of the first silicon-containing material may be performed to fill the feature by a certain amount to reduce or limit repeated deposition of the second silicon-containing material. For example, in some embodiments, the first silicon-containing material may be deposited to fill about 10% or more of the width or diameter of the feature being filled, about 15% or more, about 20% or more, about 25% or more, about 30% or more, about 35% or more, about 40% or more, about 45% or more, about 50% or more, about 55% or more, about 60% or more, about 65% or more, about 70% or more, about 75% or more, about 80% or more, or more. However, as the amount of deposition increases, the possibility of void formation from pinch-off may increase. Thus, to help maintain access to the features, the first silicon-containing material may be deposited to fill about 85% or less, about 80% or less, about 75% or less, about 70% or less, about 65% or less, about 60% or less, about 55% or less, about 50% or less, or less than that, of the width or diameter of the feature being filled.

[0056]

[0060] In step 420, the method 400 may include providing a second silicon-containing precursor to a processing region of the second semiconductor processing chamber. The structure 500 may be moved to a different semiconductor processing chamber before step 420. In other embodiments, the second silicon-containing precursor may be provided to the same processing region of the semiconductor processing chamber for depositing the first silicon-containing material 517, continuing from the deposition step as described above. In embodiments, the first silicon-containing precursor may be or may include TEOS, as described above. The second silicon-containing precursor may be or may include Si2H6. However, as described above, any silicon-containing material may be used in embodiments of the present technology. As shown in FIG. 5C, the method 400 may include, in step 425, depositing a second silicon-containing material 520 on the substrate 505, the one or more layers of material 510 (if present), and / or the first silicon-containing material 517. The second silicon-containing precursor may contact the substrate 505, the one or more layers of material 510 (if present), and / or the first silicon-containing material 517. As shown in Figure 5C, the second silicon-containing material 520 extends along any and / or all exposed surfaces along the substrate 505 (when exposed), as well as along any other incorporated materials, such as the one or more layers of material 510 and / or the first silicon-containing material 517. The second silicon-containing precursor and the second silicon-containing material 520 may share any number of qualities, properties, or characteristics with the silicon-containing material 320 described above with respect to the method 200.

[0057]

[0061] While step 415 may include plasma-enhanced deposition, depositing the second silicon-containing material 520 on the substrate 505 or on the first silicon-containing material 517 in step 425 may be performed as a plasma-free step. By performing step 425 plasma-free, the deposition of the second silicon-containing material 520 may be highly conformal. In some embodiments, the deposition of the second silicon-containing material 520 may be characterized by a conformality of about 80% or more, about 85% or more, about 90% or more, about 95% or more, or more. This high level of conformality may be beneficial during the expansion of the second silicon-containing material 520 in a subsequent anneal, as described further below, because the second silicon-containing material 520 may expand to the full depth of the feature 515. Similar to method 200 , as the features 515 begin to close or fill with the silicon-containing material 520 , voids 530 and / or seams 535 may form in the silicon-containing material 520 .

[0058]

[0062] During the above-mentioned depositions, the semiconductor processing chamber, pedestal, or substrate 505 may be maintained at a temperature as described above with respect to method 200. Similarly, the semiconductor processing chamber may be maintained at a pressure as described above with respect to method 200. Based on the amount of the first silicon-containing material deposited within the feature, the second silicon-containing material may be deposited to perform a single expansion step. However, as described above, multiple cycles may be performed. For example, the second silicon-containing material may be deposited to a thickness of about 50% or less of the remaining width or diameter of the feature to be filled after depositing the first silicon-containing material to any of the thicknesses described above for the feature size.

[0059]

[0063] After depositing the silicon-containing material 520, the method 400 may include providing an oxygen-containing precursor to a second processing region of the second semiconductor processing chamber to treat the silicon-containing material 520, at step 430. In some embodiments, the method 400 may include generating a plasma of the oxygen-containing precursor, at step 435. As shown in FIG. 5D, the method 400 may include annealing the silicon-containing material 520 with the oxygen-containing precursor or plasma effluents of the oxygen-containing precursor, at step 440. Treating the silicon-containing material 520 may be similar to steps 215-225 described above with respect to method 200 and may share any properties.

[0060]

[0064] In embodiments in which silicon-containing material is deposited and annealed only once, some voids 530 and / or seams 535 may remain in the feature 515 based on the degree of expansion throughout the feature and the amount of material deposited, but the presence of voids 530 and / or seams 535 may be reduced in such embodiments compared to the prior art.

[0061]

[0065] In the foregoing description, for purposes of explanation, numerous details are presented in order to facilitate an understanding of various embodiments of the present technology. However, it will be apparent to one of ordinary skill in the art that certain embodiments may be practiced without some of these details, or with additional details.

[0062]

[0066] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Moreover, some well-known processes and elements have not been described to avoid unnecessarily obscuring the technology. Thus, the above description should not be construed as limiting the scope of the technology.

[0063]

[0067] Where a range of values ​​is given, each intervening value between the upper and lower limits of that range is specifically disclosed to the smallest unit of the lower limit, unless the context clearly indicates otherwise. Any smaller ranges between any stated or unstated intervening value in a stated range, as well as any other stated or intervening value in that stated range, are also included. The upper and lower limits of these smaller ranges may be individually included or excluded from the range, and each range in which either, neither or both limits are included in the smaller ranges is also encompassed within the scope of this technology, subject to any specifically excluded limits in the stated range. Where a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0064]

[0068] As used in the specification and claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to a "silicon-containing precursor" includes a plurality of such precursors, reference to a "silicon-containing material" includes reference to one or more layers and equivalents thereof known to those skilled in the art, and so forth.

[0065]

[0069] Additionally, the terms "comprises," "comprising," "containing," "containing," "including," and "including," when used in this specification and claims, are intended to specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, operations, or groups.

Claims

1. i) providing a silicon-containing precursor to a processing region of a semiconductor processing chamber, the substrate being disposed in the processing region of the semiconductor processing chamber, the substrate defining one or more features along the substrate; ii) depositing a silicon-containing material onto the substrate, the silicon-containing material extending along the substrate and into the one or more features; iii) providing an oxygen-containing precursor; iv) annealing the silicon-containing material with the oxygen-containing precursor, the annealing causing the silicon-containing material to expand within the one or more features; and repeating steps i through iv to iteratively fill said one or more features on said substrate.

2. The semiconductor processing method of claim 1 , wherein the one or more features along the substrate are characterized by tapered sidewalls.

3. 10. The semiconductor processing method of claim 1, wherein the silicon-containing material deposited on the substrate defines seams or voids prior to being annealed with the oxygen-containing precursor.

4. 10. The semiconductor processing method of claim 1, wherein a temperature within the semiconductor processing chamber is maintained at or above about 300[deg.] C. while depositing the silicon-containing material on the substrate.

5. 10. The semiconductor processing method of claim 1, wherein a pressure in said semiconductor processing chamber is maintained at or above about 100 Torr while depositing said silicon-containing material on said substrate.

6. The semiconductor processing method of claim 1 , wherein annealing the silicon-containing material is performed at a temperature of about 600° C. or greater.

7. 10. The semiconductor processing method of claim 1, wherein said annealing is performed for a time period of about 30 minutes or more.

8. providing a first silicon-containing precursor to a processing region of a semiconductor processing chamber, the first silicon-containing precursor defining one or more features along the substrate, the first silicon-containing precursor being disposed in the processing region of the semiconductor processing chamber; generating a plasma of the first silicon-containing precursor; depositing a first silicon-containing material onto the substrate, the first silicon-containing material extending along the substrate and into the one or more features; providing a second silicon-containing precursor; depositing a second silicon-containing material onto the first silicon-containing material, the second silicon-containing material extending along the substrate and into the one or more features; Providing an oxygen-containing precursor; and annealing the second silicon-containing material with the oxygen-containing precursor, the annealing causing the second silicon-containing material to expand within the one or more features.

9. 9. The semiconductor processing method of claim 8, wherein the first silicon-containing precursor comprises tetraethylorthosilicate and the second silicon-containing precursor comprises disilane.

10. 10. The semiconductor processing method of claim 8, wherein depositing the second silicon-containing material is performed in a semiconductor processing chamber separate from the semiconductor processing chamber in which the first silicon-containing material was deposited.

11. 10. The semiconductor processing method of claim 8, wherein annealing the second silicon-containing material increases a thickness of the second silicon-containing material by about 50% or more.

12. 9. The semiconductor processing method of claim 8, wherein a temperature is maintained at or above about 300 degrees Celsius while depositing the second silicon-containing material on the substrate.

13. 13. The semiconductor processing method of claim 12, wherein depositing the second silicon-containing material on the first silicon-containing material is performed as a plasma-free process.

14. the oxygen-containing precursor comprises steam; 13. The semiconductor processing method of claim 12, wherein annealing the second silicon-containing material is performed at a temperature of about 600° C. or greater.

15. generating a plasma of a first silicon-containing precursor; depositing a first silicon-containing material on a substrate defining one or more features along the substrate, the first silicon-containing material extending along the substrate and into the one or more features; providing a second silicon-containing precursor; depositing a second silicon-containing material onto the first silicon-containing material, the second silicon-containing material extending along the substrate and into the one or more features; Providing an oxygen-containing precursor; generating a plasma of the oxygen-containing precursor; and 16. A semiconductor processing method comprising: treating the second silicon-containing material with plasma effluents of the oxygen-containing precursor, the plasma effluents of the oxygen-containing precursor expanding the second silicon-containing material on the substrate.

16. 16. The semiconductor processing method of claim 15, wherein generating the plasma of the oxygen-containing precursor is performed at a temperature of about 450° C. or greater.

17. 20. The semiconductor processing method of claim 15, wherein the plasma of the oxygen-containing precursor is generated at a plasma power of about 800 W or greater.

18. 16. The semiconductor processing method of claim 15, wherein the oxygen-containing precursor comprises nitrous oxide, diatomic oxygen, or a combination of both.

19. the first silicon-containing precursor comprises tetraethyl orthosilicate; 16. The semiconductor processing method of claim 15, wherein the second silicon-containing precursor comprises disilane.

20. 16. The semiconductor processing method of claim 15, wherein treating the second silicon-containing material with the plasma effluents of the oxygen-containing precursor reduces seams or voids defined within the second silicon-containing material.

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