Bias current receiver with selective coupling circuitry.

Abstract

1. An integrated circuit (IC) comprising: a current mirror including a first field effect transistor (FET) including a first drain, a first gate, and a first source, the first FET having a first drain, a first gate, and a first source, the first FET having a first source coupled to a first voltage rail; and a second FET having a second drain, a second gate, and a second source, the second gate being coupled to the first gate of the first FET and the second source being coupled to the first voltage rail; and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS)

[0001] This patent application claims priority to pending U.S. non-provisional application No. 17 / 831,306, filed on June 2, 2022, assigned to the assignee of this patent application, and expressly incorporated by reference herein as if fully set forth below and for all applicable purposes.

[0002] Aspects of the present disclosure relate generally to a bias current receiver, and more particularly to a bias current receiver with a selective coupling circuit. [Background technology]

[0003]

[0003] An integrated circuit (IC) typically includes several functional cores that perform various operations. In some cases, the functional cores may each include a bias current receiver that receives a reference current and generates therefrom one or more sets of bias currents for use in achieving the various operations of the functional core. The reference currents may be generated by a process-voltage-temperature (PVT) stable (e.g., bandgap) current generator. During IC fabrication, metal traces may be formed to couple the reference current generator to the current mirror as part of the bias current receiver. If the metal traces are directly coupled to the gates of the current mirror field effect transistors (FETs), damage to the FETs may occur as a result of the gate antenna effect. That is, charge accumulated on the metal traces during IC processing may discharge through the gate oxide / insulator of the FET, causing the FET to fail. Summary of the Invention

[0004]

[0004] The following presents a simplified summary of one or more implementations to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations, and is not intended to identify key or critical elements of all implementations or to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the Detailed Description presented later.

[0005]

[0005] Certain aspects of the present disclosure relate to an integrated circuit (IC) that includes a current mirror including a first field effect transistor (FET) including a first drain, a first gate, and a first source, the first FET having a first drain, a first gate, and a first source, the first FET having a first source coupled to a first voltage rail, and a second FET having a second drain, a second gate, and a second source, the second gate coupled to the first gate of the first FET and the second source coupled to the first voltage rail, and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET.

[0006] Another aspect of the disclosure relates to a method that includes selectively coupling a first drain of a first field effect transistor (FET) to a first gate of the first FET and a second gate of a second FET to achieve a current mirror operation of the first and second FETs in response to a voltage at a first drain of the first FET.

[0007] Another aspect of the disclosure relates to an apparatus including a first field effect transistor (FET), a second FET, and means for selectively coupling a first drain of the first FET to a first gate of the first FET and a second gate of the second FET to achieve a current mirror operation of the first and second FETs in response to a voltage at a first drain of the first FET.

[0008] Another aspect of the present disclosure relates to a wireless communication device, the wireless communication device includes a reference current generator, a bias current receiver coupled to the reference current generator, the bias current receiver including a current mirror including a first field effect transistor (FET) including a first drain, a first gate, and a first source, the first FET having a first drain, a first gate, and a first source, the first FET having a first source coupled to a first voltage rail, and a second FET including a second drain, a second gate, and a second source, the second gate coupled to the first gate of the first FET, and the second source coupled to the first voltage rail, and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET, and one or more signal processing cores coupled to the bias current receiver.

[0009]

[0009] To the accomplishment of the foregoing and related ends, the one or more implementations comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of the various implementations may be employed, and the described implementations are intended to include all such aspects and their equivalents. [Brief description of the drawings]

[0010] [Figure 1]

[0010] FIG. 1 illustrates a schematic diagram of an example integrated circuit (IC) including an example bias current receiver in accordance with an aspect of the present disclosure. [Diagram 2]

[0011] 1 shows a schematic diagram of another example integrated circuit (IC) including another example bias current receiver in accordance with another aspect of the disclosure. [Diagram 3]

[0012] 1 shows a schematic diagram of another example integrated circuit (IC) including another example bias current receiver in accordance with another aspect of the disclosure. [Figure 4]

[0013] 1 shows a schematic diagram of another example integrated circuit (IC) including another example bias current receiver in accordance with another aspect of the disclosure. [Diagram 5]

[0014] 1 shows a schematic diagram of another example integrated circuit (IC) including another example bias current receiver in accordance with another aspect of the disclosure. [Figure 6]

[0015] 1 shows a schematic diagram of another exemplary bias current receiver in accordance with another aspect of the present disclosure. [Figure 7]

[0016] 1 shows a schematic diagram of another example integrated circuit (IC) including another example bias current receiver in accordance with another aspect of the disclosure. [Figure 8]

[0017] 1 shows a schematic diagram of another exemplary bias current receiver in accordance with another aspect of the present disclosure. [Figure 9]

[0018] 9 illustrates a schematic diagram of an example transmission gate of the example voltage rail collapse control circuit of the bias current receiver of FIG. 8 in accordance with another aspect of the present disclosure. [Figure 10]

[0019] 9 illustrates a schematic diagram of an example inverter of the example voltage rail collapse control circuit of the bias current receiver of FIG. 8 in accordance with another aspect of the disclosure. [Figure 11]

[0020] 9 illustrates a schematic diagram of an example voltage level shifter of the example voltage rail collapse control circuit of the bias current receiver of FIG. 8 in accordance with another aspect of the present disclosure. [Figure 12]

[0021] 13 shows a schematic diagram of another exemplary selective coupling circuit according to another aspect of the present disclosure. [Figure 13A]

[0022] 1 illustrates a side view of an exemplary integrated circuit (IC) that eliminates the gate antenna effect associated with bonding metal traces to the bulk of a field effect transistor (FET) in accordance with another embodiment of the present disclosure. [Figure 13B]1 illustrates a side view of an exemplary integrated circuit (IC) that eliminates the gate antenna effect associated with bonding metal traces to the bulk of a field effect transistor (FET) in accordance with another embodiment of the present disclosure. [Figure 14]

[0023] 4 illustrates a flow diagram of an exemplary method for generating a bias current according to another aspect of the present disclosure. [Figure 15]

[0024] 1 illustrates a block diagram of an exemplary wireless communication device according to another aspect of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011]

[0025] The detailed description of the present invention, described below in connection with the accompanying drawings, is intended as an illustration of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description of the present invention includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0012]

[0026] An integrated circuit (IC) typically includes several functional cores or circuits that perform various operations. As some examples, an IC may include a display serial interface (DSI), a serial data bus interface, a double data rate (DDR) memory interface, a physical controller messaging interface, and / or others. In some cases, these functional cores or circuits may incorporate bias current receivers that receive a reference current and generate therefrom one or more sets of bias currents for use in achieving various operations of the functional cores or circuits. The reference currents may be generated by process voltage temperature (PVT) stable (e.g., bandgap) current generators.

[0013]

[0027] 1 illustrates a schematic diagram of an example integrated circuit (IC) 100 in accordance with an aspect of the present disclosure. The IC 100 includes a reference current generator 110 and a bias current receiver 120. The reference current generator 110 generates a reference current I REF The bias current receiver 120 is configured to generate a reference current I REF or the reference current I REF Based on, one or more bias currents I B1 ~I BN The bias current receivers 120 are configured to generate a set of bias currents I B1 ~I BN The set of functional cores or circuits may be associated with or co-located with one or more functional cores or functional circuits.

[0014]

[0028] Specifically, the reference current generator 110 includes a first p-channel metal oxide semiconductor field effect transistor (PMOS FET) M11 coupled in series with a current source 112 (e.g., a PVT stable or bandgap current source) between a first upper voltage rail VDD1 and a lower voltage rail VSS (e.g., ground). That is, the PMOS FET M11 includes a source coupled to the first upper voltage rail VDD1 and a gate and a drain coupled together. The current source 112 is coupled between the gate and drain of the PMOS FET M11 and the lower voltage rail VSS. The current source 112 generates a PVT stable or bandgap current I BG is configured to generate

[0015]

[0029] The reference current generator 110 further includes a second PMOS FET M12 having a source coupled to the first upper voltage rail VDD1, a gate coupled to the gate and drain of the first PMOS FET M11 to form a current mirror, and a drain serving as a current output of the reference current generator 110. Thus, the reference current generator 110 outputs a reference current I through the PMOS FET M12. REF and a reference current I REF is the current I generated by the current source 112. BG or the current I BG (For example, the current gain of a current mirror (I REF / I BG ) based on the current gain I REF / I BG is the channel width-to-length ratio (W / L) of the first PMOS FET M11. 1 ) of the channel width to length ratio (W / L 2 ) based on the ratio of the reference current I REF is provided to the bias current receiver 120 via a metal trace represented as a resistor R.

[0016]

[0030] The bias current receiver 120 includes a first n-channel metal oxide semiconductor field effect transistor (NMOS FET) M13 coupled between a current input (Vin) of the bias current receiver 120 and a lower voltage rail VSS. As used herein, the term (Vin) in parentheses refers to the current input, and the term Vin without parentheses refers to the voltage at the current input. As shown, a metal trace R is coupled between the output of the reference current generator 110 and the current input (Vin) of the bias current receiver 120. The first NMOS FET M13 includes a drain coupled to or serving as the current input (Vin) of the bias current receiver 120, a gate coupled to its drain, and a source coupled to the lower voltage rail VSS.

[0017]

[0031] The bias current receiver 120 further includes a PMOS FET M15 coupled in series with the second NMOS FET M14 between the second upper voltage rail VDD2 and the lower voltage rail VSS. That is, the PMOS FET M15 includes a source coupled to the second upper voltage rail VDD2 and a gate and a drain coupled together. The second NMOS FET M14 includes a drain coupled to the gate and drain of the PMOS FET M15, a gate coupled to the gate and drain of the first NMOS FET M13, and a source coupled to the lower voltage rail VSS. In such a configuration, the first and second NMOS FETs M13 and M14 are connected to the PMOS FET M15 and the reference current I REF or the reference current I REF (For example, the current gain of a current mirror (I MRR / I REF ) the mirrored current I through the second NMOS FET M14 MMR That is, a current mirror is formed to generate a received reference current I REF is the mirrored current I through the NMOS FET M14. MMR The voltage VMRR is generated at the gates of the NMOS FETs M13 and M14. The current gain I MRR / I REF is the channel width-to-length ratio (W / L) of the first NMOS FET M13. 3 ) to the channel width-to-length ratio (W / L 4 ) may be based on the ratio of

[0018]

[0032] The bias current receiver 120 receives the mirrored current I MMR A current I related to or mirrored by MMR Based on, one or more bias currents I B1 ~I BN That is, the set of one or more PMOS FETs MB1-MBN each having a source coupled to the second upper voltage rail VDD2, a gate coupled to the gate / drain of the PMOS FET M15, and a corresponding bias current I to achieve their operation. B1 ~I BN and a drain coupled to one or more functional cores or circuits requiring the

[0019]

[0033] In such a configuration, the PMOS FET M15 and the PMOS FETs MB1 to MBN receive the mirrored current I MRR A current I related to or mirrored by MRR (e.g., one or more sets of current gains of the current mirror (I B1 / I MRR ~I BN / I MRR ) based on one or more bias currents I B1 ~I BN A current mirror is formed to generate a set of one or more current gains I B1 / I MRR ~IBN / I MRR The set of PMOS FET M15 channel width to length ratio (W / L 5 ) the channel width to length ratio W / L of the set of one or more second PMOS FETs MB1 to MBN B1 ~W / L BN The set of one or more current gains may each be based on a set of one or more ratios of a reference current I REF to effectively multiply and / or divide one or more bias currents I B1 ~I BN can be used to generate a set of

[0020]

[0034] In IC100, the metal trace R that couples the reference current generator 110 to the bias current receiver 120 is directly coupled to the gates of NMOS FETs M13 and M14. Thus, NMOS FETs M13 and M14 may be susceptible to the gate antenna effect. That is, during fabrication of IC100, specifically during the plasma etching to form the metal trace R, significant charge may build up on the metal trace R, especially if the metal trace R is relatively long (e.g., 10-15 millimeters (mm)). Because the gate oxide or insulator of NMOS FETs M13 and M14 may be relatively thin, the charge on the metal trace R may discharge through the gate oxide or insulator of NMOS FETs M13 and M14 to the lower voltage rail VSS. This discharge may cause damage or failure of NMOS FETs M13 and M14, resulting in reduced yield in fabrication of IC100.

[0021]

[0035] 2 illustrates a schematic diagram of another example integrated circuit (IC) 200 including another example bias current receiver 220 according to another aspect of the disclosure. IC 200 is similar to IC 100, including a reference current generator 210 coupled to bias current receiver 220 via a metal trace R.

[0022]

[0036] Similarly, reference current generator 210 includes first and second PMOS FETs M21 and M22 and a PVT stable or bandgap current source 212 in the same configuration as first and second PMOS FETs M11 and M12 and PVT stable or bandgap current source 112 of reference current generator 110. Similarly, bias current receiver 220 includes first and second NMOS FETs M23 and M24 and a PMOS FET M25 in the same configuration as first and second NMOS FETs M13 and M14 and PMOS FET M15 of bias current receiver 120. Although not explicitly shown, bias current receiver 220 also includes a bias current I B1 ~I BN . . , respectively, may include a set of one or more PMOS FETs MB1 through MBN coupled to a PMOS FET M25 in a current mirror configuration to generate a set of PMOS FETs M1 through M25.

[0023]

[0037] To address potential gate antenna effects, the bias current receiver 220 further includes a reverse-biased diode D1 with its cathode coupled to the gates of the NMOS FETs M23 and M24 and its anode coupled to the low-side voltage rail VSS. The reverse-biased diode D1 provides a path for charge built up on the metal trace R to discharge to the low-side voltage rail VSS. Thus, the charge does not discharge through the thin gate oxide / insulator of the NMOS FETs M23 and M24, thereby eliminating or reducing the possibility of damage to the NMOS FETs M23 and M24. During normal operation of the IC100, the reverse-biased diode D1 does not turn on and does not affect the operation of the IC100. A drawback of such an approach is that the reverse-biased diode D1 occupies a significant IC area, which is generally undesirable.

[0024]

[0038] 3 illustrates a schematic diagram of another example integrated circuit (IC) 300 including another example bias current receiver 320 according to another aspect of the disclosure. IC 300 is similar to IC 100, including a reference current generator 310 coupled to bias current receiver 320 via a metal trace R.

[0025]

[0039] Similarly, reference current generator 310 includes first and second PMOS FETs M31 and M32 and a PVT stable or bandgap current source 312 of the same configuration as first and second PMOS FETs M11 and M12 and PVT stable or bandgap current source 112 of reference current generator 110. Also similarly, bias current receiver 320 includes first and second NMOS FETs M33 and M34 and a PMOS FET M35 of the same configuration as first and second NMOS FETs M13 and M14 and PMOS FET M15 of bias current receiver 120, except that the drain of NMOS FET M33 is not directly coupled to its gate, as discussed further herein. Although not explicitly shown, bias current receiver 320 may include one or more bias currents I B1 ~I BN .MBN respectively coupled to PMOS FET M35 in a current mirror configuration to generate a set of one or more PMOS FETs MB1-MBN.

[0026]

[0040] To address potential gate antenna effects, the bias current receiver 320 further includes a selective coupling circuit 322 that includes an input (current input (Vin) of the bias current receiver 320) coupled to the metal trace R and an output coupled to the gates of the NMOS FETs M33 and M34. In this configuration, the gates of the NMOS FETs M33 and M34 are not directly coupled to the metal trace R, and therefore the NMOS FETs M33 and M34 are protected from gate antenna effects from the metal trace R. Also, in this example, there are no other gate antenna effects with respect to the metal trace R, since the metal trace R does not terminate at the gate of any device.

[0027]

[0041] In this example, the selective coupling circuit 322 includes an NMOS FET M36 coupled between a current input (Vin) of the bias current receiver 320 (e.g., to which an end of the metal trace R is coupled) and the gates of the NMOS FETs M33 and M34. That is, the NMOS FET M36 includes a drain coupled to the current input (Vin) of the bias current receiver 320, a source coupled to the gates of the NMOS FETs M33 and M34, and a gate configured to receive a non-complementary enable signal (en). The selective coupling circuit 322 further includes an NMOS FET M37 coupled between the gates of the NMOS FETs M33 and M34 and the lower voltage rail VSS. That is, the NMOS FET M37 includes a drain coupled to the gates of the NMOS FETs M33 and M34, a source coupled to the lower voltage rail VSS, and a gate configured to receive a complementary enable signal (enb). The enable signals en and enb may be associated with enabling / disabling the bias current receiver 320 including the functional core or functional circuit to which the bias current receiver 320 is coupled and / or associated.

[0028]

[0042] In operation, when the enable signal is asserted (e.g., en=high (H) (e.g., substantially at VDD2 potential) and enb=low (L) (e.g., substantially at VSS potential)), NMOS FET M36 is turned on and NMOS FET M37 is turned off. Thus, the turned-on NMOS FET M36 electrically couples the drain of NMOS FET M33 to the gates of NMOS FETs M33 and M34, thereby causing a reference current I REF By achieving mirroring of the mirrored current I MMR 3. Enables the current mirror action of NMOS FETs M33 and M34 to generate I. The turned off NMOS FET M37 electrically isolates the gates of NMOS FETs M33 and M34 from the lower voltage rail VSS.

[0029]

[0043] When the enable signal is not asserted (deasserted) (e.g., en=L, enb=H), NMOS FET M36 is turned off and NMOS FET M37 is turned on. Thus, the turned off NMOS FET M36 electrically isolates the drain of NMOS FET M33 from the gates of NMOS FETs M33 and M34, and the turned on NMOS FET M37 electrically couples the gates of NMOS FETs M33 and M34 to the lower voltage rail VSS. This disables the current mirror action of NMOS FETs M33 and M34.

[0030]

[0044] A drawback of bias current receiver 320 is that when it is enabled (en=H, enb=L), the turned-on NMOS FET M36 must provide a voltage V MRR In general, it may not be possible to transfer the voltage Vin completely across the NMOS FET M36 to generate a threshold voltage V T Therefore, the voltage V at the gates of the NMOS FETs M33 and M34 is MRR To achieve accurate current mirroring, use Vin-V instead of Vin. T which is the mirrored current I MRR The reference current I REF This results in an inaccurate mirroring of one or more bias currents I B1 ~I BN Through the use of a current mirror coupled to a PMOS FET M35 to generate a mirrored current I MRR is multiplied, the error in current mirroring increases by the multiplication factor.

[0031]

[0045] 4 illustrates a schematic diagram of another example integrated circuit (IC) 400 including another example bias current receiver 420 according to another aspect of the disclosure. IC 400 is similar to IC 100, including a reference current generator 410 coupled to bias current receiver 420 via a metal trace R.

[0032]

[0046] Similarly, reference current generator 410 includes first and second PMOS FETs M41 and M42 and a PVT stable or bandgap current source 412 of the same configuration as first and second PMOS FETs M11 and M12 and PVT stable or bandgap current source 112 of reference current generator 110. Similarly, bias current receiver 420 also includes first and second NMOS FETs M43 and M44 and a PMOS FET M45 of the same configuration as first and second NMOS FETs M13 and M14 and PMOS FET M15 of bias current receiver 120, except that the drain of NMOS FET M43 is not directly coupled to its gate, as discussed further herein. Although not explicitly shown, bias current receiver 420 may include one or more bias currents I B1 ~I BN .MBN respectively coupled to PMOS FET M45 in a current mirror configuration to generate a set of one or more PMOS FETs MB1-MBN.

[0033]

[0047] To address potential gate antenna effects, the bias current receiver 420 further includes a selective coupling circuit 422 that includes an input (current input (Vin) of the bias current receiver 420) coupled to the metal trace R and an output coupled to the gates of the NMOS FETs M43 and M44. In this configuration, the gates of the NMOS FETs M43 and M44 are not directly coupled to the metal trace R, and therefore the NMOS FETs M43 and M44 are protected from gate antenna effects from the metal trace R. Also, in this example, there are no other gate antenna effects with respect to the metal trace R, since the metal trace R does not terminate at the gate of any device.

[0034]

[0048] In this example, the selective coupling circuit 422 includes a transmission gate 424 (including parallel-coupled NMOS FET M46 and PMOS FET M47) coupled between the current input (Vin) of the bias current receiver 420 (e.g., to which the ends of the metal trace R are coupled) and the gates of the NMOS FETs M43 and M44. That is, the NMOS FET M46 of the transmission gate 424 includes a drain coupled to the current input (Vin) of the bias current receiver 420, a source coupled to the gates of the NMOS FETs M43 and M44, and a gate configured to receive a non-complementary enable signal (en). The PMOS FET M47 of the transmission gate 424 includes a source coupled to the current input (Vin) of the bias current receiver 420, a drain coupled to the gates of the NMOS FETs M43 and M44, and a gate configured to receive a complementary enable signal (enb).

[0035]

[0049] The selective coupling circuit 422 further includes an NMOS FET M48 coupled between the gates of the NMOS FETs M43 and M44 and the lower voltage rail VSS. That is, the NMOS FET M48 includes a drain coupled to the gates of the NMOS FETs M43 and M44, a source coupled to the lower voltage rail VSS, and a gate configured to receive a complementary enable signal enb. The enable signals en and enb may be associated with enabling / disabling the bias current receiver 420 including the functional core or functional circuit with which the bias current receiver 420 is coupled and / or associated.

[0036]

[0050] In operation, when the enable signal is asserted (e.g., en=H, enb=L), the transmission gate 424 is turned on and the NMOS FET M48 is turned off. Thus, the turned-on transmission gate 424 electrically couples the drain of the NMOS FET M43 to the gates of the NMOS FETs M43 and M44, thereby causing the reference current I REF By achieving mirroring of the mirrored current I MMR3. Enables the current mirror action of NMOS FETs M43 and M44 to generate I. The turned off NMOS FET M48 electrically isolates the gates of NMOS FETs M43 and M44 from the lower voltage rail VSS.

[0037]

[0051] When the enable signals en and enb are deasserted (e.g., en=L, enb=H), the transmission gate 424 is turned off and the NMOS FET M48 is turned on. Thus, the turned off transmission gate 424 electrically isolates the drain of the NMOS FET M43 from the gates of the NMOS FETs M43 and M44, and the turned on NMOS FET M48 electrically couples the gates of the NMOS FETs M43 and M44 to the lower voltage rail VSS. This disables the current mirror action of the NMOS FETs M43 and M44.

[0038]

[0052] A drawback of bias current receiver 420 is that due to differences in the voltage domains (VDD1 vs. VDD2) in which reference current generator 410 and bias current receiver 420 operate, PMOS FET M47 of transmission gate 424 may not be turned off completely, which may result in leakage current when bias current receiver 420 is disabled (e.g., en=L, enb=H). For example, the supply voltage at the upper voltage rail VDD1 of reference current generator 410 may be 1.2 volts (V) and the supply voltage at the upper voltage rail VDD2 of bias current receiver 420 may be 0.8 V. Thus, the high voltage of the complementary enable signal enb applied to the gate of PMOS FET M47 is 0.8 V. When transmission gate 424 is turned off, reference current I REF is relatively small, so the voltage Vin at the current input of the bias current receiver 420 is about 1.2 V. When the voltage Vin is applied to the source of the PMOS FET M47, the PMOS FET M47 may experience a source-gate voltage (Vsg) of about 0.4 V. This Vsg may not be small enough to completely turn off the PMOS FET M47, thus causing leakage current through the transmission gate 424.

[0039]

[0053] 5 illustrates a schematic diagram of another exemplary integrated circuit (IC) 500 including an exemplary bias current receiver 520 according to another aspect of the disclosure. In this implementation, the bias current receiver 520 includes a selective coupling circuit 522 including a control input coupled to the current input of the bias current receiver 520 to selectively couple the current input to the gate of a current mirroring NMOS FET in response to a voltage at the current input and an enable signal. More specifically, when the bias current receiver 520 is disabled, the control input receives a voltage Vin at the current input of the bias current receiver 520, and the selective coupling circuit uses the voltage Vin to decouple the current input of the bias current receiver 520 from the gate of the current mirror NMOS FET. As discussed further herein with reference to the exemplary implementation, the selective coupling circuit may include a PMOS FET with a source coupled to the current input of the bias current receiver 520 and a gate selectively driven by Vin. Thus, in this case, since Vsg is substantially 0 (0)V, such a PMOS FET may be completely turned off, thereby preventing leakage current through the PMOS FET.

[0040]

[0054] Specifically, IC 500 includes a reference current generator 510 coupled to a bias current receiver 520 via a metal trace R. Reference current generator 510 includes first and second PMOS FETs M51 and M52 and a PVT stable or bandgap current source 512 of the same configuration as first and second PMOS FETs M11 and M12 and PVT stable or bandgap current source 112 of reference current generator 110. Bias current receiver 520 includes first and second NMOS FETs M53 and M54 and a PMOS FET M55 of the same configuration as first and second NMOS FETs M13 and M14 and PMOS FET M15 of bias current receiver 120, except that the drain of NMOS FET M53 is not directly coupled to its gate, as discussed further herein. Although not explicitly shown, bias current receiver 520 may include one or more bias currents I B1 ~IBN .MBN respectively coupled to PMOS FET M55 in a current mirror configuration to generate a set of one or more PMOS FETs MB1-MBN.

[0041]

[0055] To address potential gate antenna effects, the bias current receiver 520 further includes a selective coupling circuit 522 that includes an input (current input (Vin) of the bias current receiver 520) coupled to the metal trace R and an output coupled to the gates of the NMOS FETs M53 and M54. In this configuration, the gates of the NMOS FETs M53 and M54 are not directly coupled to the metal trace R, and therefore the NMOS FETs M53 and M54 are protected from gate antenna effects from the metal trace R. Also, in this example, there are no other gate antenna effects with respect to the metal trace R, since the metal trace R does not terminate at the gate of any device.

[0042]

[0056] In this implementation, the selective coupling circuit 522 includes a first control input coupled to the current input (Vin) of the bias current receiver 520 to receive the input voltage Vin therefrom. The selective coupling circuit 522 further includes a second control input configured to receive at least one of a non-complementary enable signal (en) and / or a complementary enable signal (enb). As an example, via the second control input, the selective coupling circuit 522 can receive the non-complementary enable signal en and internally generate the complementary enable signal enb using an inverter, or receive the complementary enable signal enb and internally generate the non-complementary enable signal en using an inverter, or receive both the non-complementary signal en and the complementary enable signal enb. Also, as shown, the selective coupling circuit 522 can include a third control input coupled to the lower voltage rail VSS.

[0043]

[0057] As discussed further herein with respect to an exemplary implementation of the selective coupling circuit 522, the selective coupling circuit 522 decouples the current input (Vin) of the bias current receiver 520 from the gates of the NMOS FETs M53 and M54 based on the input voltage Vin and the deasserted enable signal en / enb (e.g., en=L, enb=H). The decoupling of the current input (Vin) of the bias current receiver 520 from the gates of the NMOS FETs M53 and M54 is performed to substantially eliminate leakage current. Additionally, the selective coupling circuit 522 couples the current input (Vin) of the bias current receiver 520 to the gates of the NMOS FETs M53 and M54 based on the potential at the lower voltage rail VSS (e.g., 0V) and the asserted enable signal en / enb (e.g., en=H, enb=L).

[0044]

[0058] 6 illustrates a schematic diagram of another exemplary bias current receiver 600 according to another aspect of the disclosure. The bias current receiver 600 may be an exemplary implementation of the bias current receiver 520 of the IC 500. Similarly, the bias current receiver 600 includes first and second NMOS FETs M61 and M62 and a PMOS FET M63 in a configuration similar to the first and second NMOS FETs M13 and M14 and PMOS FET M15 of the bias current receiver 120, except that the drain of the NMOS FET M61 is not directly coupled to its gate, as discussed further herein. Although not explicitly shown, the bias current receiver 600 may include one or more bias currents I B1 ~I BN , M63 respectively.

[0045]

[0059] The bias current receiver 600 includes a selective coupling circuit 622 including an input coupled to or also serving as the current input (Vin) of the bias current receiver 600 and an output coupled to the gates of NMOS FETs M61 and M62. The selective coupling circuit 622 includes a first PMOS FET M67, a second PMOS FET M65, an NMOS FET M64, and an NMOS FET M66. In addition, the selective coupling circuit 622 includes an inverter 626 including a PMOS FET M68, an NMOS FET M69, and an NMOS FET M70 coupled in series between the current input (Vin) of the bias current receiver 600 and the lower voltage rail VSS.

[0046]

[0060] More specifically, PMOS FET M67 includes a source coupled to the current input (Vin) of the bias current receiver 600, a drain coupled to the source of PMOS FET M65, and a gate coupled to the output of the inverter 626. NMOS FET M64 includes a drain coupled to the current input (Vin), a source coupled to the drain of PMOS FET M65, and a gate configured to receive a non-complementary enable signal (en). PMOS FET M65 includes a gate configured to receive a complementary enable signal (enb). NMOS FET M66 includes a drain coupled to the source / drain of NMOS FET M64 / PMOS FET M65 (as well as the gates of NMOS FETs M61 and M62), a source coupled to the lower voltage rail VSS, and a gate configured to receive a complementary enable signal enb.

[0047]

[0061] The PMOS FET M68 of the inverter 626 includes a source coupled to the current input (Vin) of the bias current receiver 600. The NMOS FET M69 of the inverter 626 includes a drain coupled to the drain of the PMOS FET M68. The gates of the PMOS FET M68 and the NMOS FET M69 are coupled together and to the source / drain of the NMOS FET M64 / PMOS FET M65 (as well as the drain of the NMOS FET M66 and the gates of the NMOS FETs M61 and M62). The gates of the PMOS FET M68 and the NMOS FET M69 serve as the input of the inverter 626, and the drains of the PMOS FET M68 and the NMOS FET M69 serve as the output of the inverter 626, which is coupled to the gate of the PMOS FET M67, as discussed. NMOS FET M70 of inverter 626 includes a drain coupled to the source of NMOS FET M69, a source coupled to the lower voltage rail VSS, and a gate configured to receive a non-complementary enable signal en.

[0048]

[0062] In operation, when the bias current receiver 600 is enabled by asserting the enable signal (en=H, enb=L), the NMOS FET M64 and the PMOS FET M65 are turned on, the NMOS FET M66 is turned off, and the NMOS FET M70 of the inverter 626 is turned on. Thus, a small reference current I flows into the selective coupling circuit 622. REF , which causes the voltage Vin at the current input (Vin) of the bias current receiver 600 to be approximately 0.8V (e.g., ∼VDD1-I REF * Initially, the voltage V at the input of inverter 626 (and the gates of current mirror NMOS FETs M61 and M62) can be MRR to about 0.6V (for example, Vin-V T , where V T (V is the threshold voltage of NMOS FET M64) A small voltage drop will exist across NMOS FET M64. This voltage V MRRIn response, PMOS FET M68 is turned off and NMOS FET M69 is turned on. Thus, inverter 626 outputs a voltage substantially at the VSS potential (e.g., 0V) that is provided to the gate of PMOS FET M67. This turns PMOS FET M67 fully on, increasing the voltage VSS at the gates of the current mirror NMOS FETs M61 and M62. MRR is effectively raised to Vin for accurate current mirror action.

[0049]

[0063] When the bias current receiver 600 is disabled by deasserting the enable signal (en=L, enb=H), the NMOS FET M64 and the PMOS FET M65 are turned off, the NMOS FET M66 is turned on, and the NMOS FET M70 of the inverter 626 is turned off. Thus, the reference current I REF is relatively small due to the turned off NMOS FET M64 / PMOS FET M65, so the voltage Vin at the current input (Vin) of the bias current receiver 600 is about 1.2 V (e.g., .about.VDD1). The voltage V MRR is substantially at the VSS potential (e.g., 0V) due to the turned-on NMOS FET M66. MRR In response, PMOS FET M68 is turned on and NMOS FET M69 is turned off. Thus, inverter 626 outputs a voltage substantially at the Vin potential (e.g., 1.2V) which is supplied to the gate of PMOS FET M67. This turns PMOS FET M67 completely off since its Vsg is substantially 0V, thereby preventing leakage current through it.

[0050]

[0064] A further problem arises when the supply voltage VDD2 collapses to VSS potential or 0V. At this point, the enable signals en and enb also collapse to VSS potential or 0V. Thus, referring again to FIG. 6, PMOS FET M65 will be turned on and, if the output of inverter 626 is at VSS potential or 0V, PMOS FET M67 will also be turned on. Because the supply voltage VDD1 is present in the reference current generator, the reference current I REF flows into the selective coupling circuit 622. As a result, there will be significant current that latches onto the gates of the current mirror NMOS FETs M61 and M62. As discussed further herein, in the following exemplary implementation of the selective coupling circuit, circuitry is provided to prevent or reduce latching current into the current mirror NMOS FETs in response to a VDD2 collapse.

[0051]

[0065] 7 illustrates a schematic diagram of another example integrated circuit (IC) 700 including an example reference current generator 710 and an example bias current receiver 720 in accordance with another aspect of the disclosure. In this implementation, the bias current receiver 720 includes circuitry that responds to a collapse of the bias current receiver 720 supply voltage VDD2 when the reference current generator 710 supply voltage VDD1 is present.

[0052]

[0066] More specifically, IC 700 includes a reference current generator 710 coupled to a bias current receiver 720 via metal trace R. Reference current generator 710 includes first and second PMOS FETs M71 and M72 and a PVT stable or bandgap current source 712 of the same configuration as first and second PMOS FETs M11 and M12 and PVT stable or bandgap current source 112 of reference current generator 110. Bias current receiver 720 includes first and second NMOS FETs M73 and M74 and a PMOS FET M75 of the same configuration as first and second NMOS FETs M13 and M14 and PMOS FET M15 of bias current receiver 120, except that the drain of NMOS FET M73 is not directly coupled to its gate, as discussed further herein. Although not explicitly shown, bias current receiver 720 may include one or more bias currents I B1 ~I BN , M75 respectively.

[0053]

[0067] To address potential gate antenna effects, the bias current receiver 720 further includes a selective coupling circuit 722 that includes an input (current input (Vin) of the bias current receiver 720) coupled to the metal trace R and an output coupled to the gates of the NMOS FETs M73 and M74. In this configuration, the gates of the NMOS FETs M73 and M74 are not directly coupled to the metal trace R, and therefore the NMOS FETs M73 and M74 are protected from gate antenna effects from the metal trace R. Also, in this example, there are no other gate antenna effects with respect to the metal trace R, since the metal trace R does not terminate at the gate of any device.

[0054]

[0068] In this implementation, the selective coupling circuit 722 includes a first control input coupled to the current input (Vin) of the bias current receiver 720 and receiving the input voltage Vin therefrom. The selective coupling circuit 722 further includes a second control input configured to receive at least one of a non-complementary enable signal (en) and / or a complementary enable signal (enb). Similarly, via the second control input, the selective coupling circuit 722 can receive the non-complementary enable signal en and internally generate a complementary enable signal enb using an inverter, or receive a complementary enable signal enb and internally generate a non-complementary enable signal en using an inverter, or receive both the non-complementary signal en and the complementary enable signal enb. The selective coupling circuit 722 also includes a third control input configured to receive a supply voltage VDD2. Also, as shown, the selective coupling circuit 722 can also be coupled to a lower voltage rail VSS.

[0055]

[0069] As discussed further herein with respect to an exemplary implementation of the selective coupling circuit 722, the selective coupling circuit 722 decouples the current input (Vin) of the bias current receiver 720 from the gates of the NMOS FETs M73 and M74 based on the input voltage Vin and in response to the supply voltage VDD2 including the collapsed enable signals en / enb (e.g., all at VSS potential or 0V). The decoupling of the current input (Vin) of the bias current receiver 720 from the gates of the NMOS FETs M73 and M74 is performed to substantially eliminate leakage or latching currents. Additionally, the selective coupling circuit 722 couples the current input (Vin) of the bias current receiver 720 to the gates of the NMOS FETs M73 and M74 based on the potential at the lower voltage rail VSS (e.g., 0V) and the asserted enable signals en / enb (e.g., en=H, enb=L) when VDD2 is not collapsing.

[0056]

[0070] 8 illustrates a schematic diagram of another exemplary bias current receiver 800 according to another aspect of the disclosure. The bias current receiver 800 may be an exemplary implementation of the bias current receiver 720 of the IC 700. Similarly, the bias current receiver 800 includes first and second NMOS FETs M81 and M82 and PMOS FET M83 in a configuration similar to the first and second NMOS FETs M13 and M14 and PMOS FET M15 of the bias current receiver 120, except that the drain of the NMOS FET M81 is not directly coupled to its gate, as discussed further herein. Although not explicitly shown, the bias current receiver 800 may include one or more bias currents I B1 ~I BN .MBN respectively coupled to PMOS FET M83 in a current mirror configuration to generate a set of one or more PMOS FETs MB1-MBN.

[0057]

[0071] The bias current receiver 800 includes a selective coupling circuit 822 including an input coupled to or serving as a current input (Vin) of the bias current receiver 800 and an output coupled to the gates of NMOS FETs M81 and M82. The selective coupling circuit 822 includes a first PMOS FET M92, a second PMOS FET M88, a third PMOS FET M85, a first NMOS FET M84, a second NMOS FET M86, and a third NMOS FET M87. In addition, the selective coupling circuit 822 includes an inverter 826 including a PMOS FET M89, an NMOS FET M90, and an NMOS FET M91 coupled in series between the current input (Vin) of the bias current receiver 800 and the lower voltage rail VSS. Furthermore, the selective coupling circuit 822 includes a supply voltage (VDD2) collapse control circuit 830.

[0058]

[0072] More specifically, the first PMOS FET M92 has a source coupled to the current input (Vin) of the bias current receiver 800, a drain coupled to the source of the second PMOS FET M88, and a drain coupled thereto from which the first control voltage V CPThe second PMOS FET M88 includes a drain coupled to the source of the third PMOS FET M85 and a gate coupled to the output of the inverter 826. The third PMOS FET M85 includes a gate configured to receive the complementary enable signal (enb). The first NMOS FET M84 includes a drain coupled to the current input (Vin) of the bias current receiver 800, a source coupled to the drain of the third PMOS FET M85, and a gate configured to receive the non-complementary enable signal (en).

[0059]

[0073] The second NMOS FET M86 includes a drain coupled to the source / drains of NMOS FET M84 / PMOS FET M85 (and the gates of NMOS FETs M81 and M82), a source coupled to the lower voltage rail VSS, and a gate configured to receive the complementary enable signal enb. The third NMOS FET M87 also includes a drain coupled to the source / drains of NMOS FET M84 / PMOS FET M85 (and the gates of NMOS FETs M81 and M82), a source coupled to the lower voltage rail VSS, and a gate configured to receive a second control voltage V CN and a gate coupled to a second control output of the VDD2 decay control circuit 830 to receive the

[0060]

[0074] The PMOS FET M89 of the inverter 826 includes a source coupled to the current input (Vin) of the bias current receiver 800. The NMOS FET M90 of the inverter 826 includes a drain coupled to the drain of the PMOS FET M89. The gates of the PMOS FET M89 and the NMOS FET M90 are coupled together and to the source / drain of the NMOS FET M84 / PMOS FET M85 (as well as to the drains of the second and third NMOS FETs M86 and M87 and the gates of the current mirror NMOS FETs M81 and M82). The gates of the PMOS FET M89 and the NMOS FET M90 serve as the input of the inverter 826, and the drains of the PMOS FET M89 and the NMOS FET M90 serve as the output of the inverter 826, which is coupled to the gate of the second PMOS FET M88, as discussed. NMOS FET M91 of inverter 826 includes a drain coupled to the source of NMOS FET M90, a source coupled to the lower voltage rail VSS, and a gate configured to receive a non-complementary enable signal en.

[0061]

[0075] The VDD2 decay control circuit 830 includes a first control input coupled to a current input (Vin) of the bias current receiver 800 for receiving a voltage Vin therefrom. The VDD2 decay control circuit 830 includes a second control input coupled to an upper voltage rail VDD2 of the bias current receiver 800 for receiving a supply voltage VDD2 therefrom. As also shown, the VDD2 decay control circuit 830 may include a third control input coupled to a lower voltage rail VSS. The VSS potential is connected to a control voltage V CP and V CN This is called the control input because it is used to generate

[0062]

[0076] In operation, when the supply voltage VDD2 is not collapsing, the selective coupling circuit 822 operates similarly to the selective coupling circuit 622 discussed above. That is, when VDD2 is not collapsing, the VDD2 collapse control circuit 830 couples VSS potential (e.g., 0V) to keep the first PMOS FET M92 on.CP , and V is also at the VSS potential (for example, 0V) to keep the third NMOS FET M87 off. CN As described above, the VDD2 collapse control circuit 830 uses its third control input to generate a control voltage V CP and V CN Generate.

[0063]

[0077] Thus, when the bias current receiver 800 is enabled by the enable signal being asserted (en=H, enb=L), the first NMOS FET M84 and the third PMOS FET M85 are turned on, the second NMOS FET M86 is turned off, and the NMOS FET M91 of the inverter 826 is turned on. Thus, some reference current I flows into the selective coupling circuit 822. REF VDD1-I, which reduces the voltage Vin at the current input (Vin) of the bias current receiver 800 to approximately 0.8 V (e.g., REF * Initially, there will be a small voltage drop across the first NMOS FET M84, causing the voltage V MRR to about 0.6V (for example, Vin-V T ). This voltage V MRR In response, PMOS FET M89 is turned off and NMOS FET M90 is turned on. Thus, inverter 826 outputs a voltage substantially at the VSS potential (e.g., 0V) which is supplied to the gate of the second PMOS FET M88. This turns PMOS FET M88 fully on, increasing the voltage VSS at the gates of the current mirror NMOS FETs M81 and M82. MRR is effectively raised to Vin for accurate current mirror action.

[0064]

[0078] When the bias current receiver 800 is disabled by deasserting the enable signal (en=L, enb=H), the first NMOS FET M84 and the third PMOS FET M85 are turned off, the second NMOS FET M86 is turned on, and the NMOS FET M91 of the inverter 826 is turned off. Thus, the reference current I REF is relatively small due to the turned off NMOS FET M84 / PMOS FET M85, so the voltage Vin at the current input (Vin) of the bias current receiver 800 is about 1.2V (e.g., .about.VDD1). The voltage V MRR is substantially at the VSS potential (e.g., 0V) due to the second NMOS FET M86 being turned on. MRR In response, PMOS FET M89 is turned on and NMOS FET M90 is turned off. Thus, inverter 826 outputs a voltage substantially at the Vin potential (e.g., 1.2 V) which is supplied to the gate of the second PMOS FET M88. Because the Vsg of PMOS FET M88 is substantially 0 V, this turns PMOS FET M88 completely off, thereby preventing leakage or latching current to the gates of the current mirror NMOS FETs M81 and M82.

[0065]

[0079] When the supply voltage VDD2 collapses as sensed by the VDD2 collapse control circuit 830, as discussed in more detail further herein with reference to an exemplary implementation of the VDD2 collapse control circuit 830, the VDD2 collapse control circuit 830 controls a first control voltage V substantially at Vin to turn off the first PMOS FET M92. CP , effectively creating a Vin-V T The second control voltage V CN The VDD2 decay control circuit 830 uses its coupling to the current input (Vin) of the bias current receiver 800 to generate substantially Vin and Vin-V T The control signal VCP and V CN The first PMOS FET M92 being turned off and the third NMOS FET M87 being turned on prevent leakage or latching currents to the gates of the current mirror NMOS FETs M81 and M82.

[0066]

[0080] 9 shows a schematic diagram of an exemplary transmission gate 900 according to another embodiment of the disclosure. The transmission gate 900 may be an exemplary implementation of the second control input circuit of the VDD2 collapse control circuit 830. As discussed further herein, the transmission gate 900 is coupled between a second upper voltage rail VDD2 and the input (gate) of an inverter, as discussed further herein. Because there may be a relatively long metal trace between the VDD2 voltage rail and the gate of the inverter, the transmission gate 900 isolates the gate from the metal trace to eliminate or reduce the possibility of gate antenna effect damage to the FET of the inverter.

[0067]

[0081] More specifically, the transmission gate 900 includes a parallel-coupled NMOS FET M95 and a PMOS FET M96, each including a drain and a source coupled together, that serves as a second control input of the VDD2 decay control circuit 830. The NMOS FET M95 and the PMOS FET M96 each include a source and a drain coupled together that are configured to generate a voltage VDD2' that is related to (e.g., substantially the same as) the supply voltage VDD2. The NMOS FET M95 is configured to convert a voltage V at the current input of the bias current receiver 800 to a threshold voltage V of the NMOS FET, as discussed further herein. T The PMOS FET M96 includes a gate configured to receive a voltage Vin' that may be substantially equal to the lower voltage rail VSS minus VSS.

[0068]

[0082] In operation, when the supply voltage VDD2 does not collapse (e.g., VDD2=0.8V), the PMOS FET M96 of the transmission gate 900 operates to substantially pass the supply voltage VDD2 to generate the voltage VDD2'. When the supply voltage VDD2 collapses (e.g., VDD2=0V), the NMOS FET M95 of the transmission gate 900 operates to substantially pass the supply voltage VDD2 to generate the voltage VDD2'.

[0069]

[0083] 10 illustrates a schematic diagram of an exemplary inverter 1000 according to another embodiment of the present disclosure. The inverter 1000 applies a second control voltage V CN 1 is an example of a circuit for generating

[0070]

[0084] Specifically, inverter 1000 includes PMOS FET M101, diode-connected NMOS FET M102, PMOS FET M103, and NMOS FET M104 coupled in series between the current input (Vin) of bias current receiver 800 and the lower voltage rail VSS. More specifically, PMOS FET M101 includes a source coupled to the current input (Vin) of bias current receiver 800, a gate coupled to the lower voltage rail VSS, and a drain coupled to the drain and gate of diode-connected NMOS FET M102. Diode-connected NMOS FET M102 includes a source coupled to the source of PMOS FET M103. NMOS FET M104 includes a gate coupled to the gate of PMOS FET M103, a drain coupled to the drain of PMOS FET M103, and a source coupled to the lower voltage rail VSS.

[0071]

[0085] The gates of PMOS FET M103 and NMOS FET M104 are coupled to the output of the transmission gate 900 for receiving voltage VDD2' therefrom. The sources of diode-connected NMOS FET M102 and PMOS FET M103 are coupled to the gate of NMOS FET M95 of the transmission gate 900 for providing voltage Vin' thereto. A second control voltage V CN is generated at the drains of PMOS FET M103 and NMOS FET M104.

[0072]

[0086] In operation, the diode-connected NMOS FET M102 is connected to the gate of the NMOS FET M102 through a threshold voltage V T This is because inverter 1000 reduces voltage Vin by the logic lower control voltage V CN For example, inverter 1000 generates a logic low control voltage V when voltage VDD2′ is logic high (e.g., when supply voltage VDD2 is not collapsing). CN When not collapsing, the voltage VDD2' may be approximately 0.8V. If Vin (e.g., 1.2V) were applied directly to the source of PMOS FET M103, PMOS FET M103 would have a Vsg of approximately 0.4V, which may not be enough to turn off PMOS FET M103, resulting in leakage current through PMOS FET M103. Thus, the diode-connected NMOS FET M102 reduces the voltage Vin' at the source of PMOS FET M103, reducing the Vsg of PMOS FET M103 and reducing or preventing leakage current through it.

[0073]

[0087] Thus, when the supply voltage VDD2 is not collapsing, the voltage VDD2' is logic high (e.g., 0.8V), which causes the inverter 1000 to output a logic low at the VSS potential and a control voltage V CNGenerates a control voltage VSS potential. CN turns off the third NMOS FET M87 of the selective coupling circuit 822, which causes the gates of the current mirroring NMOS FETs M81 and M82 to receive the reference current I REF Depending on the gate voltage V MRR When the supply voltage VDD2 collapses, the voltage VDD2' is logic low (e.g., 0V), which causes the inverter 1000 to generate Vin-V T A logic high at the control voltage V CN Generate Vin-V T Control voltage V CN turns on the third NMOS FET M87 of the selective coupling circuit 822, thereby grounding the gates of the current mirroring NMOS FETs M81 and M82 and disabling the current mirroring operation.

[0074]

[0088] 11 shows a schematic diagram of an example voltage level shifter 1100 according to another aspect of the present disclosure. The voltage level shifter 1100 receives the voltage VDD2′ generated by the transmission gate 900 and the second control voltage V CN In response to this, a first control voltage V CP This is an example of a circuit that generates the input voltages VDD2' and V CN varies substantially according to the VDD2 voltage domain (e.g., between 0 and 0.8 V), and the first control voltage V CP Since V Vdd1 effectively varies according to the VDD1 voltage domain (eg, between 0 and 1.2 V), the circuit 1100 is referred to as a voltage level shifter.

[0075]

[0089] Specifically, the voltage level shifter 1100 includes a first PMOS FET M111, a second PMOS FET M112, and a first NMOS FET M113 coupled in series between the current input (Vin) of the bias current receiver 800 and the lower voltage rail VSS. That is, the first PMOS FET M111 includes a source coupled to the current input (Vin) of the bias current receiver 800 and a drain coupled to the source of the second PMOS FET M112. The second PMOS FET M112 includes a gate and a drain coupled together and to the drain of the first NMOS FET M113. The first NMOS FET M113 includes a source coupled to the lower voltage rail VSS and a gate coupled to the output of the transmission gate 900 to receive the voltage VDD2'.

[0076]

[0090] The voltage level shifter 1100 includes a third PMOS FET M114, a fourth PMOS FET M115, and a second NMOS FET M116 coupled in series between the current input (Vin) of the bias current receiver 800 and the lower voltage rail VSS. That is, the third PMOS FET M114 includes a source coupled to the current input (Vin) of the bias current receiver 800, a gate coupled to the gate and drain of the second PMOS FET M112, and a drain coupled to the source of the fourth PMOS FET M115. The fourth PMOS FET M115 includes a gate and a drain coupled together and to the gate of the first PMOS FET M111 and the drain of the second NMOS FET M116. The second NMOS FET M116 includes a source coupled to the lower voltage rail VSS and a drain coupled to the second control voltage VSS. CN and a gate coupled to the output of inverter 1000 to receive

[0077]

[0091] In addition, the voltage level shifter 1100 includes a fifth PMOS FET M117 and a third NMOS FET M118 coupled in series between the current input (Vin) of the bias current receiver 800 and the lower voltage rail VSS. That is, the fifth PMOS FET M117 includes a source coupled to the current input (Vin) of the bias current receiver 800, a gate coupled to the drain of the third PMOS FET M114 and the source of the fourth PMOS FET M115, and a drain coupled to the drain of the third NMOS FET M118. The NMOS FET M118 includes a gate coupled to the gate / drain of the fourth PMOS FET M115 (as well as the gate of the first PMOS FET M111 and the drain of the second NMOS FET M116). The NMOS FET M118 includes a source coupled to the lower voltage rail VSS. The first control voltage V CP is generated at the drains of PMOS FET M117 and NMOS FET M118.

[0078]

[0092] In operation, when the supply voltage VDD2 is not collapsing, the voltage VDD2' is logically high and the second control voltage V CN is logic low. The logic high voltage VDD2' turns on the first NMOS FET M113. As a result, the gate of the third PMOS FET M114 is driven to the VSS potential (e.g., 0V), turning on the third PMOS FET M114. The turned-on third PMOS FET M114 applies Vin to the gate of the fifth PMOS FET M117, turning off the fifth PMOS FET M117. The turned-on third PMOS FET M114 also applies Vin to the source of the diode-connected fourth PMOS FET M115. Thus, the voltage at the gate / drain of the diode-connected fourth PMOS FET M115 is Vin-V T This is applied to the gate of the third NMOS FET M118 to turn on the NMOS FET M118. This causes the first control voltage V CPfalls to the VSS potential, turning on the PMOS FET M92 of the selective coupling circuit 822.

[0079]

[0093] When the supply voltage VDD2 collapses, the voltage VDD2' is logic low and the second control voltage V CN is logically high. Logic high voltage V CN This turns on the second NMOS FET M116. As a result, the gate of the first PMOS FET M111 is driven to the VSS potential (e.g., 0V), turning on the first PMOS FET M111. The turned-on first PMOS FET M111 applies Vin to the source of the diode-connected second PMOS FET M112. Thus, the voltage at the gate / drain of the diode-connected second PMOS FET M112 is Vin-V T , which is applied to the gate of the third PMOS FET M114 to turn off the PMOS FET M114. The gate of the third NMOS FET M118 is driven to the VSS potential, thereby turning off the NMOS FET M118. Also, the gate of the fourth PMOS FET M115 is driven to the VSS potential (e.g., 0V) to turn on the fourth PMOS FET M115. The fourth PMOS FET M115 that has been turned on has a potential V T A potential is applied to the gate of the fifth PMOS FET M117 to turn on the PMOS FET M117. The turned-on PMOS FET M117 is connected to the first control voltage V CP Vin to turn off the PMOS FET M92 of the selective coupling circuit 822.

[0080]

[0094] 12 illustrates a schematic diagram of another exemplary selective coupling circuit 1200 according to another aspect of the disclosure. The selective coupling circuit 1200 may be an exemplary more detailed implementation of the selective coupling circuit 822 of the bias current receiver 800 discussed above. Although not shown, the selective coupling circuit 1200 may include a VDD2 collapse control circuit 830.

[0081]

[0095] The selective coupling circuit 1200 includes first, second, and third PMOS FETs M121, M122, and M124, first, second, and third NMOS FETs M123, M125, and M126, and an inverter 1220 including a PMOS FET M127 and NMOS FETs M128 and M129. These devices correspond to the first, second, and third PMOS FETs M92, M88, and M85, first, second, and third NMOS FETs M84, M86, and M87, and an inverter 826 including a PMOS FET M89 and NMOS FETs M90 and M91, respectively, of the selective coupling circuit 822 discussed in detail above.

[0082]

[0096] In the selective coupling circuit 1200, the bulk (n-well) of each of the PMOS FETs M121, M122, M124, and M127 is coupled to the current input (Vin) of the associated bias current receiver to prevent leakage current through the corresponding source / n-well junction when the bulk (n-well) is biased with the supply voltage VDD2 of the bias current receiver. For example, a voltage Vin (e.g., 1.2V) may be applied to the sources of the PMOS FETs M121, M122, M124, and M127, and when a supply voltage VDD2 (e.g., 0.8V) is applied to the bulk (n-well) of these FETs, the p-doped sources and n-wells form pn-junctions that are forward biased based on such voltage. As a result, leakage current occurs through the source / n-well junctions of the PMOS FETs M121, M122, M124, and M127. Therefore, in the selective coupling circuit 1200, the bulk (n-well) of each of the PMOS FETs M121, M122, M124, and M127 is coupled to the current input (Vin) to prevent such leakage currents.

[0083]

[0097] 13A illustrates a side view of an exemplary integrated circuit (IC) 1300 that eliminates the gate antenna effect associated with coupling a metal trace to the bulk of a field effect transistor (FET) according to another embodiment of the disclosure. As previously discussed with respect to IC 100, metal trace R may have a length (e.g., 10-15 mm) that may cause a gate antenna effect if it were terminated at the gate of the FET. Also, as previously discussed, metal trace R of ICs 100, 200, 300, 400, 500, and 700 terminate at the current input (Vin) of the corresponding bias current receivers 120, 220, 320, 420, 520, and 720, respectively.

[0084]

[0098] Thus, for selective coupling circuit 1200, such metal traces R may terminate in the bulk (n-well) of each of PMOS FETs M121, M122, M124, and M127. Because the bulk (n-well) directly couples to the gate oxide or insulator of the corresponding PMOS FET, the gate oxide or insulator may suffer gate antenna effect damage due to the direct coupling of metal trace R to the bulk (n-well) of the corresponding PMOS FET. IC1300 includes layout techniques to eliminate the gate antenna effect due to the coupling of metal trace R to the bulk (n-well) of the PMOS FET.

[0085]

[0099] Specifically, IC 1300 includes a first n-well 1310 that may be associated with a reference current generator. IC 1300 includes a second n-well 1330 that may be associated with a bias current receiver, such as a bias current receiver that includes selective coupling circuit 1200. For example, second n-well 1330 may be the bulk (n-well) of any of PMOS FETs M121, M122, M124, and M127 of selective coupling circuit 1200. IC 1300 further includes a metal trace 1320 that electrically couples first n-well 1310 to second n-well 1330.

[0086]

[0100] More specifically, one end of the metal trace 1320 (on the left as shown) may be coupled to the first n-well 1310 by an upper metallized via hole 1318, a lower metal layer 1316, and a lower metallized via hole 1314. Similarly, the other end of the metal trace 1320 (on the right as shown) may be coupled to the second n-well 1330 by an upper metallized via hole 1338, a lower metal layer 1336, and a lower metallized via hole 1334. In this configuration, the metal trace 1320 is coupled to the pin of the cell that includes the n-wells 1310 and 1330. Thus, if the metal trace 1320 is at or above the metal layer that includes ends that, when formed, couple to both n-wells 1310 and 1330, charge stored on the metal trace 1320 may discharge through multiple paths and a relatively large area, preventing discharge of high concentrations of charge through the gate oxide or insulator that may damage the corresponding FET. The gate antenna effect may not be an issue.

[0087]

[0101] FIG. 13B illustrates a side view of another exemplary integrated circuit (IC) 1350 that eliminates the gate antenna effect associated with coupling of metal traces to the bulk of a field effect transistor (FET) in accordance with another embodiment of the present disclosure.

[0088]

[0102] The IC 1350 includes a first n-well 1360 that may be associated with a reference current generator. The IC 1350 includes a second n-well 1380 that may be associated with a bias current receiver, such as the bias current receiver that includes the selective coupling circuit 1200. Similarly, the second n-well 1380 may be the bulk (n-well) of any of the PMOS FETs M121, M122, M124, and M127 of the selective coupling circuit 1200. The IC 1350 further includes a metal trace 1374 that electrically couples the first n-well 1360 to the second n-well 1380. Unlike the metal trace 1320, the metal trace 1374 underlies a metal layer that directly couples to the pins of the cells incorporating the n-wells 1360 and 1380, respectively. In such a case, the order of fabrication of the IC 1350 should be considered to prevent gate antenna effects on the devices associated with the n-well 1380.

[0089]

[0103] For example, metal trace 1374 may be formed on the same metal layer as metal contacts 1366 and 1386 coupled to n-wells 1360 and 1380 by metallized via holes 1364 and 1384, respectively. Jumpers 1370 and 1390 may then be formed that are coupled to metal trace 1374 through metallized via holes 1372 and 1392, respectively. Jumpers 1370 and 1390 may be coupled to metal contacts 1366 and 1386 by metallized via holes 1368 and 1388, respectively. Thus, during fabrication, metal trace 1374 is electrically coupled to n-wells 1360 and 1380 simultaneously through jumpers 1370 and 1390, allowing charge built up on metal trace 1374 to discharge through multiple paths and a relatively large area, preventing discharge of high concentrations of charge through the gate oxide or insulator, which may damage the corresponding FET.

[0090]

[0104] 14 illustrates a flow diagram of an exemplary method 1400 for generating a bias current according to another embodiment of the disclosure. The method 1400 includes selectively coupling a first drain of a first field effect transistor (FET) to a first gate of the first FET and a second gate of the second FET to achieve a current mirror operation of the first and second FETs in response to a voltage at a first drain of the first FET (block 1410). Examples of means for selectively coupling a first drain of a first FET to a first gate of the first FET and a second gate of the second FET to achieve a current mirror operation of the first and second FETs in response to a voltage at a first drain of the first FET include the selective coupling circuits 522, 622, 722, 822, including subcircuits 900, 1000, and 1100 described herein.

[0091]

[0105] With respect to selectively coupling the first drain of the first FET to the first and second gates of the first and second FETs, respectively, method 1400 may further include selectively coupling the first drain of the first FET to the first and second gates of the first and second FETs, respectively, in response to an enable signal. Examples of means for selectively coupling the first drain of the first FET to the first and second gates of the first and second FETs, respectively, in response to an enable signal include any of the selective coupling circuits described herein.

[0092]

[0106] Additionally, the method 1400 may include generating a current through the second FET based on the supply voltage, where selectively coupling the first drain of the first FET to the first and second gates of the first and second FETs, respectively, further includes decoupling the first drain of the first FET from the first and second gates of the first and second FETs in response to a supply voltage collapse. An example of a means for generating a current through the second FET based on the supply voltage includes PMOS FETs M15, M25, M35, M45, M55, M63, M75, and M83 coupled in series with NMOS FETs M14, M24, M34, M44, M54, M62, M74, and M82, respectively, between the upper voltage rail VDD2 and the lower voltage rail VSS. Examples of means for decoupling the first drain of the first FET from the first and second gates of the first and second FETs in response to a supply voltage collapse include selective coupling circuits 722 and 822, which include subcircuits 900, 1000, and 1100 described herein.

[0093]

[0107] 15 illustrates a block diagram of an exemplary wireless communication device 1500 according to another aspect of the disclosure. The wireless communication device 1500 may be a smartphone, a desktop computer, a laptop computer, a tablet device, an Internet of Things (IoT), a wearable wireless device (e.g., a wireless watch), and other types of wireless devices.

[0094]

[0108] Specifically, the wireless communication device 1500 includes an integrated circuit (IC) that may be implemented as a system on chip (SOC) 1510. The SOC 1510 includes a reference current generator 1520, a bias current receiver 1530, and one or more signal processing cores 1540. For example, the reference current generator 1520 generates a reference current I REF to the bias current receiver 1530. The bias current receiver 1530 receives a reference current I REF Based on this, one or more bias currents IB1 and I BN to the one or more signal processing cores 1540. The one or more signal processing cores 1540 may generate transmit baseband (BB) signals and process receive baseband (BB) signals by using one or more bias currents I B1 and I BN A set of

[0095]

[0109] The wireless communication device 1500 may further include a transceiver 1550 and at least one antenna 1560 (e.g., an antenna array). The transceiver 1550 is coupled to the one or more signal processing cores 1540 to receive transmitted BB signals from the one or more signal processing cores 1540 and provide received BB signals thereto. The transceiver 1550 is configured to convert transmitted BB signals to transmitted radio frequency (RF) signals and convert received RF signals to received BB signals. The transceiver 1550 is coupled to the at least one antenna 1560 to provide transmitted RF signals to the at least one antenna for electromagnetic radiation to a wireless medium for wireless transmission and to receive received RF signals electromagnetically picked up from the wireless medium by the at least one antenna 1560.

[0096]

[0110] The following provides a summary of aspects of the disclosure.

[0097]

[0111] Aspect 1: An integrated circuit (IC) comprising: a current mirror including a first field effect transistor (FET) including a first drain, a first gate, and a first source, the first FET including a first drain, a first gate, and a first source, the first FET having a first source coupled to a first voltage rail; and a second FET including a second drain, a second gate, and a second source, the second gate being coupled to the first gate of the first FET and the second source being coupled to the first voltage rail; and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET.

[0098]

[0112] Aspect 2: The IC of aspect 1, wherein the selective coupling circuit includes: a third FET including a third source, a third gate, and a third drain, the third source coupled to the first drain of the first FET, the third FET; and an inverter coupled between the first drain of the first FET and the first voltage rail, the inverter including an input coupled to the third drain of the third FET and an output coupled to the third gate of the third FET.

[0099]

[0113] Aspect 3: The IC of aspect 2, wherein the inverter includes: a fourth FET including a fourth source, a fourth gate, and a fourth drain, where the fourth source is coupled to the first drain of the first FET; and a fifth FET including a fifth drain, a fifth gate, and a fifth source, where the fifth drain is coupled to the fourth drain of the fourth FET, the fifth gate is coupled to the fourth gate of the fourth FET, and the fifth source is coupled to the first voltage rail.

[0100]

[0114] Aspect 4: The IC of aspect 3, wherein the first, second, and fifth FETs each include an n-channel metal-oxide-semiconductor field effect transistor (NMOS FET), and the third and fourth FETs each include a p-channel metal-oxide-semiconductor field effect transistor (PMOS FET).

[0101]

[0115] Example 5: The IC of example 4, wherein the third and fourth FETs each include an n-well coupled to the first drain of the first FET.

[0102]

[0116] Example 6: The IC of example 5, wherein the n-well is coupled to a metal trace via a jumper.

[0103]

[0117] Aspect 7: An IC as described in any one of aspects 1 to 6, wherein the selective coupling circuit is further configured to couple a first drain of the first FET to first and second gates of the first and second FETs based on a first enable signal.

[0104]

[0118] Aspect 8: The IC of Aspect 7, wherein the selective coupling circuit includes: a first NMOS FET including a third drain, a third gate, and a third source, where the third drain is coupled to the first drain of the first FET, the third gate is configured to receive a first enable signal, and the third source is coupled to the first and second gates of the first and second FETs; and a first PMOS FET including a fourth source, a fourth gate, and a fourth drain, where the fourth source is coupled to the third drain of the first NMOS FET, the fourth gate is configured to receive a second enable signal, where the second enable signal is complementary to the first enable signal, and the fourth drain is coupled to the third source of the first NMOS FET.

[0105]

[0119] Aspect 9: The IC of aspect 8, wherein the selective coupling circuit further includes a second NMOS FET including a fifth drain, a fifth gate, and a fifth source, the fifth drain coupled to the first and second gates of the first and second FETs, the fifth gate configured to receive a second enable signal, and the fifth source coupled to the first voltage rail.

[0106]

[0120] Aspect 10: The IC of Aspect 9, wherein the selective coupling circuit further includes: a second PMOS FET including a sixth source, a sixth gate, and a sixth drain, where the sixth source is coupled to the first drain of the first FET and the sixth drain is coupled to the fourth source of the first PMOS FET; and an inverter coupled between the first drain of the first FET and the first voltage rail, the inverter including an input coupled to the first and second gates of the first and second FETs and an output coupled to the sixth gate of the second PMOS FET.

[0107]

[0121] Example 11: The IC of example 10, wherein the first and second PMOS FETs each include an n-well coupled to the first drain of the first FET.

[0108]

[0122] Example 12: The IC of any one of examples 1 to 11, further comprising a third FET coupled in series with the second FET between the second voltage rail and the first voltage rail.

[0109]

[0123] Aspect 13: The IC of aspect 12, wherein the selective coupling circuit is further configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a supply voltage at the second voltage rail.

[0110]

[0124] Aspect 14: The IC of aspect 13, wherein the selective coupling circuit includes: a control circuit including a first control input coupled to the first drain of the first FET, a second control input coupled to the second voltage rail, and a third control input coupled to the first voltage rail, a first control output, and a second control output; a PMOS FET including a fourth source, a fourth gate, and a fourth drain, where the fourth source is coupled to the first drain of the first FET, the fourth gate is coupled to the first control output of the control circuit, and the fourth drain is coupled to the first and second gates of the first and second FETs; and an NMOS FET including a fifth drain, a fifth gate, and a fifth source, where the fifth drain is coupled to the first and second gates of the first and second FETs, the fifth gate is coupled to the second control output of the control circuit, and the fifth source is coupled to the first voltage rail.

[0111]

[0125] Aspect 15: The IC of aspect 14, wherein the control circuit sets a first control signal at the first control output to turn on the PMOS FET and sets a second control signal at the second control output to turn off the NMOS FET based on the supply voltage not collapsing, and sets the first control signal at the first control output to turn off the PMOS FET and sets the second control signal at the second control output to turn on the NMOS FET based on the supply voltage collapsing.

[0112]

[0126] Example 16: The IC of example 15, wherein the control circuit further includes an inverter configured to generate the second control signal in response to the supply voltage.

[0113]

[0127] Aspect 17: An IC as described in aspect 16, wherein the control circuit includes a transmission gate including an input coupled to or serving as the second control input and an output coupled to the input of the inverter.

[0114]

[0128] Aspect 18: An IC as described in any one of aspects 15 to 17, wherein the control circuit further includes a voltage level shifter configured to generate the first control signal in response to the supply voltage and the second control signal.

[0115]

[0129] Aspect 19: A method comprising selectively coupling a first drain of a first field effect transistor (FET) to a first gate of the first FET and a second gate of the second FET to achieve current mirror operation of the first and second FETs in response to a voltage at a first drain of the first FET.

[0116]

[0130] Aspect 20: The method of aspect 19, wherein selectively coupling the first drain of the first FET to the first and second gates of the first and second FETs, respectively, further comprises selectively coupling the first drain of the first FET to the first and second gates of the first and second FETs, respectively, in response to an enable signal.

[0117]

[0131] Aspect 21: The method of aspect 19 or 20, further comprising generating a current through the second FET based on a supply voltage, and wherein selectively coupling the first drain of the first FET to the first and second gates of the first and second FETs, respectively, further comprises decoupling the first drain of the first FET from the first and second gates of the first and second FETs in response to a supply voltage collapse.

[0118]

[0132] Example 22: An apparatus comprising: a first field effect transistor (FET); a second FET; and means for selectively coupling a first drain of the first FET to a first gate of the first FET and a second gate of the second FET to achieve current mirror operation of the first and second FETs in response to a voltage at a first drain of the first FET.

[0119]

[0133] Example 23: The apparatus of example 22, wherein the means for selectively coupling the first drain of the first FET to the first and second gates of the first and second FETs, respectively, comprises means for selectively coupling the first drain of the first FET to the first and second gates of the first and second FETs, respectively, in response to an enable signal.

[0120]

[0134] Aspect 24: The apparatus of aspect 22 or 23, further comprising: means for generating a current through the second FET based on a supply voltage, wherein the means for selectively coupling the first drain of the first FET to the first and second gates of the first and second FETs, respectively, comprises means for decoupling the first drain of the first FET from the first and second gates of the first and second FETs in response to a supply voltage collapse.

[0121]

[0135] Aspect 25: A wireless communication device including: a reference current generator; a bias current receiver coupled to the reference current generator, the bias current receiver including a current mirror including a first field effect transistor (FET) including a first drain, a first gate, and a first source, the first FET including a first drain, a first gate, and a first source, the first FET having a first source coupled to a first voltage rail, and a second FET including a second drain, a second gate, and a second source, the second gate coupled to the first gate of the first FET and the second source coupled to the first voltage rail; and a selective coupling circuit configured to selectively couple a first drain of the first FET to first and second gates of the first and second FETs based on a voltage at a first drain of the first FET; and one or more signal processing cores coupled to the bias current receiver.

[0122]

[0136] Aspect 26: The wireless communication device of aspect 25, wherein the selective coupling circuit includes: a third FET including a third source, a third gate, and a third drain, where the third source is coupled to the first drain of the first FET; and an inverter coupled between the input and the first voltage rail, where the inverter includes an input coupled to the third drain of the third FET and the output, and an output coupled to the third gate of the third FET.

[0123]

[0137] Aspect 27: The wireless communication device of aspect 25 or 26, wherein the selective coupling circuit includes a second control input configured to receive an enable signal, and a transmission gate coupled between the first drain and the first and second gates of the first FET, the transmission gate being coupled to the second control input.

[0124]

[0138] Aspect 28: The bias current receiver further includes a third FET coupled in series with the second FET between the second voltage rail and the first voltage rail, and the selective coupling circuit further includes a control circuit including a first control input coupled to the first drain of the first FET, a second control input coupled to the second voltage rail, and a third control input coupled to the first voltage rail, a first control output, and a second control output; and a fourth FET including a fourth source, a fourth gate, and a fourth drain, the fourth source being coupled to the first drain of the first FET. 28. The wireless communication device of any one of aspects 25-27, comprising: a fourth FET having a fourth drain coupled to the first voltage rail, a fourth gate coupled to a first control output of the control circuit and a fourth drain coupled to the first and second gates; and a fifth FET including a fifth drain, a fifth gate, and a fifth source, the fifth drain coupled to the first and second gates, the fifth gate coupled to a second control output of the control circuit and the fifth source coupled to the first voltage rail.

[0125]

[0139] Aspect 29: An integrated circuit (IC) including a bias current receiver including a current mirror including a first field effect transistor (FET) including a first drain, a first gate, and a first source, the first FET having a first drain, a first gate, and a first source, the first source coupled to a first voltage rail and the first drain coupled to a current input of the bias current receiver, and a second FET having a second drain, a second gate, and a second source, the second gate coupled to the first gate of the first FET and the second source coupled to the first voltage rail, and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET.

[0126]

[0140] Aspect 30: The IC of aspect 1, wherein the selective coupling circuit is further configured to selectively couple a first drain of the first FET to first and second gates of the first and second FETs based on a first enable signal received at a second control input of the selective coupling circuit, and the voltage at the first drain of the first FET is received via a first control input of the selective coupling circuit coupled to a current input of the bias current receiver.

[0127]

[0141] Aspect 31: A method comprising selectively coupling a first drain of a first field effect transistor (FET) to a first gate of a first FET and a second gate of a second FET of a bias current receiver to mirror a first current received at an input of the bias current receiver to produce a mirrored current through the second FET based on a voltage generated at the input of the bias current receiver in response to the first current.

[0128]

[0142] Aspect 32: An apparatus including a bias current receiver including a first field effect transistor (FET), a second FET, and means for selectively coupling a first drain of the first FET to a first gate of the first FET and a second gate of the second FET to mirror a first current received at an input of the bias current receiver to produce a mirrored current through the second FET based on a voltage generated at the input of the bias current receiver in response to the first current.

[0129]

[0143] Aspect 33: A wireless communications device comprising: a reference current generator; a bias current receiver coupled to the reference current generator via a metal trace, the bias current receiver comprising: a first field effect transistor (FET) including a first drain, a first gate, and a first source, the first source coupled to a first voltage rail and the first drain coupled to a current input of the bias current receiver; and a second FET including a second drain, a second gate, and a second source, the second gate coupled to the first gate of the first FET and the second source coupled to the first voltage rail; and a selective coupling circuit having an output coupled to a current input of the bias current receiver and to gates of the first and second FETs, the selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET; and one or more signal processing cores coupled to the bias current receiver.

[0130]

[0144] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. a first field effect transistor (FET) including a first drain, a first gate, and a first source, the first FET being coupled to a first voltage rail; a second FET including a second drain, a second gate, and a second source, the second gate coupled to the first gate of the first FET and the second source coupled to the first voltage rail; a current mirror including: a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET; An integrated circuit (IC).

2. The selective coupling circuit comprises: a third FET including a third source, a third gate, and a third drain, the third source coupled to the first drain of the first FET; an inverter coupled between the first drain of the first FET and the first voltage rail, the inverter having an input coupled to the third drain of the third FET and an output coupled to the third gate of the third FET; The IC of claim 1 .

3. The inverter is a fourth FET including a fourth source, a fourth gate, and a fourth drain, the fourth source coupled to the first drain of the first FET; a fifth FET including a fifth drain, a fifth gate, and a fifth source, the fifth drain coupled to the fourth drain of the fourth FET, the fifth gate coupled to the fourth gate of the fourth FET, and the fifth source coupled to the first voltage rail; The IC of claim 2 .

4. 4. The IC of claim 3, wherein the first, second, and fifth FETs each comprise an n-channel metal-oxide-semiconductor field effect transistor (NMOS FET), and the third and fourth FETs each comprise a p-channel metal-oxide-semiconductor field effect transistor (PMOS FET).

5. The IC of claim 4 , wherein the third and fourth FETs each include an n-well coupled to the first drain of the first FET.

6. The IC of claim 5, wherein the n-well is coupled to a metal trace through a jumper.

7. 2. The IC of claim 1 , wherein the selective coupling circuitry is further configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a first enable signal.

8. The selective coupling circuit comprises: a first NMOS FET including a third drain, a third gate, and a third source, the third drain coupled to the first drain of the first FET, the third gate configured to receive the first enable signal, and the third source coupled to the first and second gates of the first and second FETs; a first PMOS FET including a fourth source, a fourth gate, and a fourth drain, the fourth source being coupled to the third drain of the first NMOS FET, the fourth gate being configured to receive a second enable signal complementary to the first enable signal, and the fourth drain being coupled to the third source of the first NMOS FET; The IC of claim 7 .

9. 9. The IC of claim 8, wherein the selective coupling circuit further comprises a second NMOS FET including a fifth drain, a fifth gate, and a fifth source, the fifth drain coupled to the first and second gates of the first and second FETs, the fifth gate configured to receive the second enable signal, and the fifth source coupled to the first voltage rail.

10. The selective coupling circuit comprises: a second PMOS FET including a sixth source, a sixth gate, and a sixth drain, the sixth source coupled to the first drain of the first FET and the sixth drain coupled to the fourth source of the first PMOS FET; an inverter coupled between the first drain of the first FET and the first voltage rail, the inverter having an input coupled to the first and second gates of the first and second FETs and an output coupled to the sixth gate of the second PMOS FET; The IC of claim 9 , further comprising:

11. The IC of claim 10 , wherein the first and second PMOS FETs each include an n-well coupled to the first drain of the first FET.

12. 2. The IC of claim 1, further comprising a third FET coupled in series with the second FET between a second voltage rail and the first voltage rail.

13. 13. The IC of claim 12, wherein the selective coupling circuitry is further configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a supply voltage at the second voltage rail.

14. The selective coupling circuit comprises: a control circuit including a first control input coupled to the first drain of the first FET, a second control input coupled to the second voltage rail, and a third control input coupled to the first voltage rail, a first control output, and a second control output; a PMOS FET including a fourth source, a fourth gate, and a fourth drain, the fourth source coupled to the first drain of the first FET, the fourth gate coupled to the first control output of the control circuit, and the fourth drain coupled to the first and second gates of the first and second FETs; an NMOS FET including a fifth drain, a fifth gate, and a fifth source, the fifth drain being coupled to the first and second gates of the first and second FETs, the fifth gate being coupled to the second control output of the control circuit, and the fifth source being coupled to the first voltage rail; and The IC of claim 13 .

15. The control circuit, setting a first control signal at the first control output to turn on the PMOS FET and setting a second control signal at the second control output to turn off the NMOS FET based on the supply voltage not collapsing; setting the first control signal at the first control output to turn the PMOS FET off and setting the second control signal at the second control output to turn the NMOS FET on based on the supply voltage collapsing.

15. The IC of claim 14, configured as follows:

16. 16. The IC of claim 15, wherein the control circuit further comprises an inverter configured to generate the second control signal in response to the supply voltage.

17. 17. The IC of claim 16, wherein the control circuit includes a transmission gate having an input coupled to or serving as the second control input and an output coupled to an input of the inverter.

18. 16. The IC of claim 15, wherein the control circuit further comprises a voltage level shifter configured to generate the first control signal in response to the supply voltage and the second control signal.

19. 1. A method comprising: selectively coupling a first drain of a first field effect transistor (FET) to a first gate of the first FET and a second gate of a second FET to achieve a current mirror operation of the first and second FETs in response to a voltage at a first drain of the first FET.

20. 20. The method of claim 19, wherein selectively coupling the first drain of the first FET to the first and second gates of the first and second FETs, respectively, further comprises selectively coupling the first drain of the first FET to the first and second gates of the first and second FETs, respectively, in response to an enable signal.

21. 20. The method of claim 19, further comprising generating a current through the second FET based on a supply voltage, and wherein selectively coupling the first drain of the first FET to the first and second gates of the first and second FETs, respectively, further comprises decoupling the first drain of the first FET from the first and second gates of the first and second FETs in response to the supply voltage collapse.

22. a first field effect transistor (FET); a second FET; and means for selectively coupling the first drain of the first FET to a first gate of the first FET and to a second gate of the second FET to achieve a current mirror operation of the first and second FETs in response to a voltage at a first drain of the first FET; 13. An apparatus comprising:

23. 23. The apparatus of claim 22, wherein the means for selectively coupling the first drain of the first FET to the first and second gates of the first and second FETs, respectively, comprises means for selectively coupling the first drain of the first FET to the first and second gates of the first and second FETs, respectively, in response to an enable signal.

24. 23. The apparatus of claim 22, further comprising: means for generating a current through the second FET based on a supply voltage, wherein the means for selectively coupling the first drain of the first FET to the first and second gates of the first and second FETs, respectively, comprises means for decoupling the first drain of the first FET from the first and second gates of the first and second FETs in response to the supply voltage collapse.

25. A reference current generator; a bias current receiver coupled to the reference current generator, a first field effect transistor (FET) including a first drain, a first gate, and a first source, the first FET being coupled to a first voltage rail; a second FET including a second drain, a second gate, and a second source, the second gate coupled to the first gate of the first FET and the second source coupled to the first voltage rail; a current mirror including: a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET; Includes a bias current receiver; one or more signal processing cores coupled to the bias current receiver; 2. A wireless communication device comprising:

26. The selective coupling circuit comprises: a third FET including a third source, a third gate, and a third drain, the third source coupled to the first drain of the first FET; an inverter coupled between the first drain of the first FET and the first voltage rail, the inverter having an input coupled to the third drain of the third FET and the output, and an output coupled to the third gate of the third FET; 26. The wireless communication device of claim 25, comprising:

27. The selective coupling circuit comprises: a second control input configured to receive an enable signal; a transmission gate coupled between the first drain and the first and second gates of the first FET, the transmission gate being coupled to the second control input; 26. The wireless communication device of claim 25, comprising:

28. the bias current receiver further includes a third FET coupled in series with the second FET between a second voltage rail and the first voltage rail, and the selective coupling circuitry comprises: a control circuit including a first control input coupled to the first drain of the first FET, a second control input coupled to the second voltage rail, and a third control input coupled to the first voltage rail, a first control output, and a second control output; a fourth FET including a fourth source, a fourth gate, and a fourth drain, the fourth source coupled to the first drain of the first FET, the fourth gate coupled to the first control output of the control circuit, and the fourth drain coupled to the first and second gates; a fifth FET including a fifth drain, a fifth gate, and a fifth source, the fifth drain being coupled to the first and second gates, the fifth gate being coupled to the second control output of the control circuit, and the fifth source being coupled to the first voltage rail; 26. The wireless communication device of claim 25, comprising:

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