System and method for detecting particles using a detector during inspection

Abstract

The systems, devices, and methods include a detector including a detection element (400) comprising a portion of a silicon substrate (402), the portion of the silicon substrate (402) including a front surface (410) of the portion of the silicon substrate including a PIN diode including a p-type region (404 a) and an n-type region (403 a), a back surface (420) of the portion of the silicon substrate opposite the front surface, the back surface (420) including a substantially uniform surface, and a layer (421) on the back surface of the portion of the silicon substrate, wherein the region between the p-type region and the n-type region is configured to form a depletion region (407) when a reverse bias is applied between the p-type region (404 a) and the n-type region (403 a), and the PIN diode is configured to detect electrons that enter the back surface of the portion of the silicon substrate and travel through the portion of the silicon substrate to the depletion region.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Patent Application No. 63 / 403,534, filed September 2, 2022, which is incorporated herein by reference in its entirety.

[0002] TECHNICAL FIELD

[0002] The description herein relates to the field of inspection systems, and more particularly to systems that use detectors to detect particles during inspection. [Background technology]

[0003]

[0003] During the integrated circuit (IC) manufacturing process, unfinished and finished circuit components are inspected to ensure they are manufactured according to design and are free of defects. Inspection systems based on optical microscopes typically have a resolution down to a few hundred nanometers, with resolution limited by the wavelength of light. As the physical size of IC components continues to decrease down to sub-100 nanometers, or even sub-10 nanometers, inspection systems capable of higher resolution than those based on optical microscopes are needed.

[0004]

[0004] Charged particle (e.g., electron) beam microscopes, such as scanning electron microscopes (SEMs) or transmission electron microscopes (TEMs), capable of resolution down to less than 1 nanometer, serve as practical tools for inspecting IC components with feature sizes that are sub-100 nanometers. With an SEM, electrons from a single primary electron beam, or from multiple primary electron beams, can be focused onto a location of interest on a wafer under inspection. The primary electrons interact with the wafer and can be backscattered or can cause the wafer to emit secondary electrons. The intensity of the electron beam, including the backscattered and secondary electrons, can vary based on the characteristics of the wafer's internal and external structure, thereby indicating whether the wafer has defects. Summary of the Invention

[0005]

[0005] Embodiments of the present disclosure provide devices, systems, and methods for detecting particles with a detector. In some embodiments, the systems and methods may include a silicon substrate thinned to a thickness of 30 μm or less, a front surface of the silicon substrate including a p-type implant and an n-type implant, a region between the p-type implant and the n-type implant configured to form a depletion region when a reverse bias is applied between the p-type implant and the n-type implant, a back surface of the silicon substrate opposite the front surface including a substantially uniform surface, and a protective layer on the substantially uniform surface on the back surface of the silicon substrate, wherein the lateral PIN diode is configured to detect electrons entering the back surface of the silicon substrate and traveling through the silicon substrate to the depletion region.

[0006]

[0006] In some embodiments, the detector may include a plurality of detection elements, each of the plurality of detection elements including a portion of a silicon substrate, the portion of the silicon substrate including a surface of the portion of the silicon substrate including a PIN diode including a p-type region and an n-type region, a back surface of the portion of the silicon substrate opposite the surface including a substantially uniform surface, and a layer on the back surface of the portion of the silicon substrate, the region between the p-type region and the n-type region being configured to form a depletion region when a reverse bias is applied between the p-type region and the n-type region, and the PIN diode being configured to detect electrons that enter the back surface of the portion of the silicon substrate and travel through the portion of the silicon substrate to the depletion region.

[0007]

[0007] In some embodiments, the detector may include a plurality of detection elements, each of the plurality of detection elements comprising a portion of a silicon substrate, the portion of the silicon substrate comprising a surface of the portion of the substrate comprising a PIN diode including a p-type region and an n-type region, a back surface of the portion of the substrate opposite the surface comprising a substantially uniform surface, and a layer on the back surface of the portion of the substrate, wherein the region between the p-type region and the n-type region is configured to form a depletion region when a reverse bias is applied between the p-type region and the n-type region, and the PIN diode is configured to receive electrons incident on the back surface of the portion of the substrate.

[0008]

[0008] In some embodiments, the detector may include a plurality of detection elements, each of the plurality of detection elements comprising a portion of a substrate, the portion of the substrate comprising a surface of the portion of the substrate comprising a p-type region and an n-type region, wherein the p-type region and the n-type region form a PIN diode, and a back surface of the portion of the substrate opposite the surface comprising a substantially uniform surface, the region between the p-type region and the n-type region being configured to form a depletion region when a reverse bias is applied between the p-type region and the n-type region, and the PIN diode being configured to receive electrons passing through the portion of the substrate from the back surface of the portion of the substrate.

[0009]

[0009] In some embodiments, a method of forming a detection element of a detector may include forming a PIN diode on a surface of the silicon substrate by implanting p-type dopants to form a p-type region and implanting n-type dopants to form an n-type region in the silicon substrate, wherein a region between the p-type region and the n-type region is configured to form a depletion region when a reverse bias is applied between the p-type region and the n-type region, forming the PIN diode; thinning a back surface of the silicon substrate opposite the front surface, wherein the back surface comprises a substantially uniform surface; and forming a layer on the back surface of the silicon substrate, wherein the PIN diode is configured to detect electrons that enter the back surface of the silicon substrate and pass through the silicon substrate to the depletion region. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a schematic diagram illustrating an exemplary electron beam inspection (EBI) system consistent with embodiments of the present disclosure. [Figure 2A]

[0011] 2 is a schematic diagram illustrating an example multi-beam system that is part of the example charged particle beam inspection system of FIG. 1, consistent with an embodiment of the present disclosure. [Figure 2B]

[0012] 2 is a schematic diagram illustrating an example single beam system that is part of the example charged particle beam inspection system of FIG. 1, consistent with an embodiment of the present disclosure. [Figure 3A]

[0013] 1 is a schematic representation of an exemplary structure of a detector consistent with embodiments of the present disclosure. [Figure 3B]

[0014] 1 is a schematic diagram of a cross-sectional structure of a substrate of a detector consistent with an embodiment of the present disclosure. [Figure 3C]

[0015] 1 is a schematic diagram of a cross-sectional structure of a substrate of a detector consistent with an embodiment of the present disclosure. [Figure 3D]

[0016] FIG. 1 is a schematic diagram of an individual sensing element consistent with an embodiment of the present disclosure. [Figure 4]

[0017] FIG. 1 is a schematic diagram of an individual sensing element consistent with an embodiment of the present disclosure. [Figure 5]

[0018] FIG. 1 is a schematic diagram of an individual sensing element consistent with an embodiment of the present disclosure. [Figure 6A]

[0019] FIG. 1 is a schematic diagram of the metal geometry of an individual sensing element consistent with an embodiment of the present disclosure. [Figure 6B]

[0019] FIG. 2 is a schematic diagram of the metal geometry of an individual sensing element consistent with an embodiment of the present disclosure. [Figure 6C]

[0019] FIG. 2 is a schematic diagram of the metal geometry of an individual sensing element consistent with an embodiment of the present disclosure. [Figure 7]

[0020] FIG. 1 is a schematic diagram of a detector consistent with an embodiment of the present disclosure. [Figure 8A]

[0021] 1 is a flowchart illustrating an exemplary process for forming a sensing element consistent with embodiments of the present disclosure. [Figure 8B] 1 is a flowchart illustrating an exemplary process for forming a sensing element consistent with embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011]

[0022] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, in which like numbers in different drawings represent the same or similar elements unless otherwise noted. The implementations described in the following description of exemplary embodiments do not represent all implementations consistent with the present disclosure. Instead, they are merely examples of apparatus and methods consistent with aspects related to the subject matter recited in the appended claims. For example, while some embodiments are described in the context of utilizing electron beams, the disclosure is not so limited. Other types of charged particle beams may be similarly applicable. Furthermore, other imaging systems, such as optical imaging, light detection, x-ray detection, extreme ultraviolet inspection, deep ultraviolet inspection, etc., may be used, which produce corresponding types of images.

[0012]

[0023] Electronic devices consist of circuits formed on a piece of silicon called a substrate. Many circuits can be formed together on the same piece of silicon and are called integrated circuits, or ICs. The dimensions of these circuits have been dramatically reduced so that many more circuits can fit on a substrate. For example, the IC chip in a smartphone can be as small as a thumbnail, but can contain over 2 billion transistors, each smaller than 1 / 1000 the size of a human hair.

[0013]

[0024] Fabricating these extremely small ICs is a complex, time-consuming, and expensive process, often involving hundreds of individual steps. An error in just one step can result in a defect in the finished IC, rendering it unusable. Therefore, one of the goals of a manufacturing process is to avoid such defects and maximize the number of functional ICs produced in the process, i.e., to improve the overall yield of the process.

[0014]

[0025] One component of improving yield is monitoring the chip fabrication process to ensure that a sufficient number of functional integrated circuits are being produced. One way to monitor the process is to inspect the chip circuit structures at various stages in their formation. Inspection may be performed using a scanning electron microscope (SEM). An SEM can be used to image these very small structures, essentially taking a "picture" of them on the wafer. This image can be used to determine whether the structures were formed properly and whether they were formed in the proper location. If the structures are defective, the process can be adjusted to reduce the likelihood of the defect recurring. Defects can occur during various stages of semiconductor processing. For the reasons stated above, it is important to find defects as quickly, accurately, and efficiently as possible.

[0015]

[0026] The operating principle of an SEM is similar to that of a camera. A camera takes a picture by receiving and recording the brightness and color of light reflected or emitted from a person or object. An SEM takes a "photo" by receiving and recording the energy or quantity of electrons reflected or emitted from a structure. Before taking such a "photo," an electron beam may be directed onto the structure. As electrons reflect or emit (emit) from the structure, the SEM's detector receives and records the energy or quantity of those electrons, generating an image. To take such a "photo," some SEMs use a single electron beam (called a "single-beam SEM"), while others use multiple electron beams (called a "multi-beam SEM") to take multiple "photos" of the wafer. By using multiple electron beams, the SEM can provide more electron beams onto the structure to obtain these multiple "photos," resulting in more electrons exiting the structure. Thus, the detector simultaneously receives more exiting electrons, allowing for more efficient and faster generation of images of the wafer's structures.

[0016]

[0027] For example, a typical detector (e.g., including multiple detector elements) may be pixelated such that each detector element may receive particles (e.g., charged particles such as photons, electrons, protons, etc.) projected from the sample and output a detection signal. The detection signal may be used to reconstruct an image of the sample structure under inspection, for example, to reveal defects within the sample.

[0017]

[0028] However, typical detection systems face challenges due to limitations. A typical inspection system may include a detection element having a horizontal or vertical PIN diode on a substrate that detects particles by front-side illumination. That is, the detection element detects particles by receiving particles on the front side of the detection element through the PIN diode rather than on the back side of the detection element through the substrate. Detection elements that detect particles by front-side illumination, particularly low-energy particles (e.g., electrons less than 5 keV), exhibit low responsivity and low response speed due to carrier loss at the surface of the PIN diode. For example, carrier loss may occur due to the PIN diode's surface passivation layer, heavily doped region, surface metal layer, or surface electrical contacts. For example, carrier loss may occur due to the PIN diode's surface metal layer or surface electrical contacts absorbing some electrons. Detection elements with vertical PIN diodes also suffer from limitations, such as the need to incorporate complex through-substrate vias to integrate the PIN diode into a readout integrated circuit.

[0018]

[0029] Furthermore, detector substrates are typically too thick to feasibly detect particles with backside illumination. Detectors with pure boron layers can achieve higher responsivity using either frontside or backside illumination, but these detectors operate at low response speeds to low-energy particles due to the high sheet resistance of the thin bonding layer.

[0019]

[0030] Some of the disclosed embodiments provide systems and methods that address some or all of these shortcomings by providing a detector having a detection element that includes a lateral PIN diode on a thin substrate and uses backside illumination. The disclosed embodiments may include providing a silicon substrate having a PIN diode on a front side of the substrate, a back side of the silicon substrate that includes a substantially uniform surface (e.g., a surface without implant dopants, a material with zero implant dopant concentration, zero PIN diode, zero cathode, zero anode, etc.), and a passivation layer on the back side of the silicon substrate, where the PIN diode is configured to detect electrons that enter the back side of the silicon substrate and travel through the silicon substrate to a depletion region of the PIN diode, thereby improving detection response speed, responsivity, and fill factor with acceptable levels of parasitic capacitance, and being easily integrated with readout integrated circuits.

[0020]

[0031] The relative dimensions of components in the drawings may be exaggerated for clarity. In the following description of the drawings, the same or similar reference numerals refer to the same or similar components or entities, and only the differences with respect to the individual embodiments are described.

[0021]

[0032] As used herein, unless otherwise stated, the term "or" includes all possible combinations unless impracticable. For example, if a component is described as being able to include A or B, the component can include A, or B, or A and B, unless otherwise stated or impracticable. As a second example, if a component is described as being able to include A, B, or C, the component can include A, or B, or C, or A and B, or A and C, or B and C, or A, B, and C, unless otherwise stated or impracticable.

[0022]

[0033] Without limiting the scope of the present disclosure, some embodiments may be described in the context of providing detectors and detection methods in systems utilizing electron beams. However, the disclosure is not so limited. Other types of charged particle beams may be similarly applied. Furthermore, the systems and methods for detection may be used in other imaging systems, such as optical imaging, photon detection, x-ray detection, ion detection, etc.

[0023]

[0034] FIG. 1 illustrates an exemplary electron beam inspection (EBI) system 100 consistent with embodiments of the present disclosure. The EBI system 100 can be used for imaging. As shown in FIG. 1, the EBI system 100 includes a main chamber 101, a load / lock chamber 102, an electron beam tool 104, and an equipment front-end module (EFEM) 106. The electron beam tool 104 is disposed inside the main chamber 101. The EFEM 106 includes a first load port 106a and a second load port 106b. The EFEM 106 may include additional load ports. The first load port 106a and the second load port 106b receive wafer front-opening unified pods (FOUPs) containing wafers (e.g., semiconductor wafers or wafers made of other materials) or samples (wafers and samples may be used interchangeably) to be inspected. A "lot" is a plurality of wafers that can be loaded for processing as a batch.

[0024]

[0035] One or more robot arms (not shown) in the EFEM 106 can transfer wafers to the load / lock chamber 102. The load / lock chamber 102 is connected to a load / lock vacuum pumping system (not shown), which removes gas molecules from the load / lock chamber 102 to reach a first pressure lower than atmospheric pressure. After the first pressure is reached, one or more robot arms (not shown) can transfer the wafers from the load / lock chamber 102 to the main chamber 101. The main chamber 101 is connected to a main chamber vacuum pumping system (not shown), which removes gas molecules from the main chamber 101 to reach a second pressure lower than the first pressure. After the second pressure is reached, the wafers are subjected to inspection by the electron beam tool 104. The electron beam tool 104 can be a single beam system or a multi-beam system.

[0025]

[0036] The controller 109 is electronically connected to the electron beam tool 104. The controller 109 may be a computer configured to control various aspects of the EBI system 100. While the controller 109 is shown in FIG. 1 as being external to the structure that includes the main chamber 101, the load / lock chamber 102, and the EFEM 106, it will be understood that the controller 109 may also be part of this structure.

[0026]

[0037] In some embodiments, controller 109 may include one or more processors (not shown). A processor may be a general-purpose or specialized electronic device capable of manipulating or processing information. For example, a processor may include any number and combination of central processing units (i.e., "CPUs"), graphics processing units (i.e., "GPUs"), optical processors, programmable logic controllers, microcontrollers, microprocessors, digital signal processors, intellectual property (IP) cores, programmable logic arrays (PLAs), programmable array logic (PALs), general-purpose array logic (GALs), complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), systems-on-chips (SoCs), application-specific integrated circuits (ASICs), and any type of circuitry capable of processing data. A processor may also be a virtual processor, including one or more processors distributed across multiple machines or devices coupled via a network.

[0027]

[0038] In some embodiments, controller 109 may further include one or more memories (not shown). Memory may be a general-purpose or specialized electronic device capable of storing code and data accessible to a processor (e.g., via a bus). For example, memory may include any combination of any number of random access memories (RAMs), read-only memories (ROMs), optical disks, magnetic disks, hard drives, solid-state drives, flash drives, security digital (SD) cards, memory sticks, compact flash (CF) cards, or any type of storage device. Code may include an operating system (OS) and one or more application programs (i.e., "apps") for specific tasks. Memory may also be virtual memory, including one or more memories distributed across multiple machines or devices coupled via a network.

[0028]

[0039] Embodiments of the present disclosure may provide a single charged particle beam imaging system ("single beam system"). In comparison to a single beam system, a multiple charged particle beam imaging system ("multi-beam system") may be designed to optimize throughput for different scanning modes. Embodiments of the present disclosure provide a multi-beam system that has the ability to optimize throughput for different scanning modes by using beam arrays with different geometries and accommodating different throughput and resolution requirements.

[0029]

[0040] 2A, which is a schematic diagram illustrating an exemplary electron beam tool 104 including a multi-beam inspection tool that is part of the EBI system 100 of FIG. 1, consistent with embodiments of the present disclosure. In some embodiments, the electron beam tool 104 can be operated as a single-beam inspection tool that is part of the EBI system 100 of FIG. 1. The multi-beam electron beam tool 104 (also referred to herein as apparatus 104) includes an electron source 201, a Coulomb aperture plate (or "gun aperture plate") 271, a condenser lens 210, a source conversion unit 220, a primary projection system 230, a motorized stage 209, and a sample holder 207 supported by the motorized stage 209 for holding a sample 208 (e.g., a wafer or photomask) to be inspected. The multi-beam electron beam tool 104 can further include a secondary projection system 250 and an electron detection device 240. The primary projection system 230 can include an objective lens 231. The electronic detection device 240 may include a number of detection elements 241, 242, and 243. A beam separator 233 and a deflection scanning unit 232 may be arranged inside the primary projection system 230.

[0030]

[0041] The electron source 201, the Coulomb aperture plate 271, the condenser lens 210, the radiation source conversion unit 220, the beam separator 233, the deflection scanning unit 232, and the primary projection system 230 may be aligned with a primary optical axis 204 of the apparatus 104. The secondary projection system 250 and the electron detection device 240 may be aligned with a secondary optical axis 251 of the apparatus 104.

[0031]

[0042] The electron source 201 may include a cathode (not shown) and an extractor or anode (not shown), and in operation the electron source 201 is configured to emit primary electrons from the cathode, which are extracted or accelerated by the extractor and / or anode to form a primary electron beam 202 that forms a (virtual or real) primary beam crossover 203. The primary electron beam 202 may be visible as it is emitted from the primary beam crossover 203.

[0032]

[0043] The source conversion unit 220 may include an image-forming element array (not shown), an aberration compensator array (not shown), a beam-limiting aperture array (not shown), and a pre-bend micro-deflector array (not shown). In some embodiments, the pre-bend micro-deflector array deflects multiple primary beamlets 211, 212, 213 of the primary electron beam 202 so that they properly enter the beam-limiting aperture array, the image-forming element array, and the aberration compensator array. In some embodiments, the apparatus 104 can be operated as a single-beam system so that a single primary beamlet is generated. In some embodiments, the condenser lens 210 is designed to focus the primary electron beam 202 into a parallel beam and at normal incidence on the source conversion unit 220. The imaging element array may include a plurality of micro-deflectors or micro-lenses for influencing the plurality of primary beamlets 211, 212, and 213 of the primary electron beam 202 and for forming a plurality of (virtual or real) parallel images of the primary beam crossover 203, one for each of the primary beamlets 211, 212, and 213. In some embodiments, the aberration compensator array may include a field curvature compensator array (not shown) and an astigmatism compensator array (not shown). The field curvature compensator array may include a plurality of micro-lenses for compensating for field curvature aberration of the primary beamlets 211, 212, and 213. The astigmatism compensator array may include a plurality of micro-stigmators for compensating for astigmatism of the primary beamlets 211, 212, and 213. The beam-limiting aperture array may be configured to limit the diameter of each of the primary beamlets 211, 212, and 213. 2A shows three primary beamlets 211, 212, and 213 by way of example, it will be understood that the source conversion unit 220 may be configured to form any number of primary beamlets. The controller 109 may be connected to various parts of the EBI system 100 of FIG. 1, such as the source conversion unit 220, the electron detection device 240, the primary projection system 230, or the motorized stage 209. In some embodiments, the controller 109 may perform various image and signal processing functions, as described in more detail below.The controller 109 may also generate various control signals to govern the operation of the charged particle beam inspection system.

[0033]

[0044] The condenser lens 210 is configured to focus the primary electron beam 202. The condenser lens 210 may be further configured to adjust the current of the primary beamlets 211, 212, and 213 downstream of the radiation source conversion unit 220 by changing the focusing power of the condenser lens 210. Alternatively, the current can be changed by changing the radial size of a beam-limiting aperture in a beam-limiting aperture array corresponding to each primary beamlet. The current can be changed by changing both the radial size of the beam-limiting aperture and the focusing power of the condenser lens 210. The condenser lens 210 may be an adjustable condenser lens that may be configured such that the position of its first-principles plane is movable. The adjustable condenser lens may be configured to be magnetic, which may result in the off-axis beamlets 212 and 213 irradiating the radiation source conversion unit 220 with a rotation angle. The rotation angle varies depending on the focusing power or the position of the first-principles plane of the adjustable condenser lens. Collector lens 210 may be an anti-rotation collector lens that may be configured to not change its rotation angle when the focusing power of collector lens 210 is changed. In some embodiments, collector lens 210 may be an adjustable anti-rotation collector lens that does not change its rotation angle when its focusing power and the position of its first-principles plane are changed.

[0034]

[0045] The objective lens 231 may be configured to focus the beamlets 211, 212, and 213 onto the sample 208 for inspection, which in the current embodiment may form three probe spots 221, 222, and 223 on the surface of the sample 208. The Coulomb aperture plate 271 is operatively configured to block peripheral electrons of the primary electron beam 202 to reduce the Coulomb effect, which can increase the size of the probe spots 221, 222, and 223 of the primary beamlets 211, 212, and 213, respectively, thereby degrading inspection resolution.

[0035]

[0046] The beam separator 233 may be, for example, a Wien filter including electrostatic deflectors that generate electrostatic and magnetic dipole fields (not shown in FIG. 2A ). In operation, the beam separator 233 may be configured to exert an electrostatic force due to the electrostatic dipole field on individual electrons of the primary beamlets 211, 212, and 213. This electrostatic force is equal in magnitude but opposite in direction to the magnetic force exerted on the individual electrons by the magnetic dipole field of the beam separator 233. Thus, the primary beamlets 211, 212, and 213 may pass at least approximately straight through the beam separator 233 with at least approximately zero deflection angle.

[0036]

[0047] The deflection scanning unit 232 is operatively configured to deflect the primary beamlets 211, 212, and 213 to scan the probe spots 221, 222, and 223 over respective scan areas within a section of the surface of the sample 208. In response to the incidence of the primary beamlets 211, 212, and 213 or the probe spots 221, 222, and 223 on the sample 208, electrons emerge from the sample 208 and generate three secondary electron beams 261, 262, and 263. Each of the secondary electron beams 261, 262, and 263 typically includes secondary electrons (having an electron energy of 50 eV or less) and backscattered electrons (having an electron energy between 50 eV and the landing energy of the primary beamlets 211, 212, and 213). The beam separator 233 is configured to deflect the secondary electron beams 261, 262, and 263 towards the secondary projection system 250. The secondary projection system 250 then focuses the secondary electron beams 261, 262, and 263 onto detector elements 241, 242, and 243 of the electron detection device 240. The detector elements 241, 242, and 243 are arranged to detect corresponding secondary electron beams 261, 262, and 263 and generate corresponding signals that are sent to the controller 109 or a signal processing system (not shown), for example, to construct an image of a corresponding scanned area of ​​the sample 208.

[0037]

[0048] In some embodiments, detector elements 241, 242, and 243 detect corresponding secondary electron beams 261, 262, and 263, respectively, and generate corresponding intensity signal outputs (not shown) to an image processing system (e.g., controller 109). In some embodiments, each detector element 241, 242, and 243 may include one or more pixels. The intensity signal output of a detector element may be the sum of signals generated by all of the pixels in the detector element.

[0038]

[0049] In some embodiments, the controller 109 may include an image processing system including an image acquirer (not shown) and storage (not shown). The image acquirer may include one or more processors. For example, the image acquirer may include a computer, a server, a mainframe host, a terminal, a personal computer, any type of mobile computing device, etc., or a combination thereof. The image acquirer may be communicatively coupled to the electronic detection device 240 of the apparatus 104 by a medium such as electrical conductors, a fiber optic cable, a portable storage medium, IR, Bluetooth, the Internet, a wireless network, a wireless radio, or a combination thereof, among others. In some embodiments, the image acquirer may receive signals from the electronic detection device 240 and construct an image. The image acquirer may thus acquire an image of the sample 208. The image acquirer may also perform various post-processing functions, such as generating contours and superimposing indicators on the acquired image. The image acquirer may be configured to adjust the brightness and contrast of the acquired image, etc. In some embodiments, the storage may be a storage medium, such as a hard disk, a flash drive, cloud storage, random access memory (RAM), or other types of computer-readable memory. A storage may be coupled to the image acquirer and can be used to store raw scanned image data as original images and to store post-processed images.

[0039]

[0050] In some embodiments, the image acquirer may acquire one or more images of the sample based on an imaging signal received from the electronic detection device 240. The imaging signal may correspond to a scanning motion for performing charged particle imaging. The acquired image may be a single image including multiple imaging areas. The single image may be stored in storage. The single image may be an original image that may be divided into multiple regions. Each of these regions may include an imaging area that includes a feature of the sample 208. The acquired image may include multiple images of a single imaging area of ​​the sample 208 sampled multiple times over a time series. The multiple images may be stored in storage. In some embodiments, the controller 109 may be configured to perform image processing steps using multiple images of the same location on the sample 208.

[0040]

[0051] In some embodiments, the controller 109 may include measurement circuitry (e.g., an analog-to-digital converter) to obtain a distribution of detected secondary electrons. The electron distribution data collected during the detection time window may be used in combination with the corresponding scan path data for each of the primary beamlets 211, 212, and 213 incident on the wafer surface to reconstruct an image of the wafer structure under inspection. The reconstructed image may be used to reveal various features of the internal or external structure of the sample 208, and thereby reveal any defects that may be present in the wafer.

[0041]

[0052] In some embodiments, the controller 109 may control the motorized stage 209 to move the sample 208 during inspection of the sample 208. In some embodiments, the controller 109 may enable the motorized stage 209 to continuously move the sample 208 in one direction at a constant velocity. In other embodiments, the controller 109 may enable the motorized stage 209 to vary the speed of movement of the sample 208 over time depending on the steps in the scanning process.

[0042]

[0053] 2A shows that the apparatus 104 uses three primary electron beams, it will be understood that the apparatus 104 can use one, two, or more primary electron beams. This disclosure does not limit the number of primary electron beams used in the apparatus 104. In some embodiments, the apparatus 104 can be an SEM used for lithography. In some embodiments, the electron beam tool 104 can be a single beam system or a multi-beam system.

[0043]

[0054] For example, as shown in FIG. 2B , electron beam tool 100B (also referred to herein as apparatus 100B) may be a single-beam inspection tool for use in EBI system 10 consistent with embodiments of the present disclosure. Apparatus 100B includes a wafer holder 136 supported by a motorized stage 134 for holding a wafer 150 to be inspected. Electron beam tool 100B includes an electron emitter, which may include a cathode 103, an anode 121, and a gun aperture 122. Electron beam tool 100B further includes a beam-limiting aperture 125, a condenser lens 126, a column aperture 135, an objective lens assembly 132, and a detector 144. In some embodiments, objective lens assembly 132 may be a modified SORIL lens, which includes a pole piece 132a, a control electrode 132b, a deflector 132c, and an excitation coil 132d. In the imaging process, an electron beam 161 emanating from the tip of the cathode 103 is accelerated by the voltage on the anode 121, passes through the gun aperture 122, the beam-limiting aperture 125, the condenser lens 126, and may be focused by a modified SORIL lens to a probe spot 170, impinging on the surface of the wafer 150. The probe spot 170 may be scanned across the surface of the wafer 150 by a deflector, such as the deflector 132c of the SORIL lens or other deflectors. Secondary particles or scattered primary particles, such as secondary electrons or scattered primary electrons emanating from the wafer surface, may be collected by a detector 144 to determine the intensity of the beam and so that an image of the area of ​​interest on the wafer 150 may be reconstructed.

[0044]

[0055] An image processing system 199 may also be provided, including the image acquirer 120, the storage 130, and the controller 109. The image acquirer 120 may include one or more processors. For example, the image acquirer 120 may include a computer, a server, a mainframe host, a terminal, a personal computer, any type of mobile computing device, etc., or a combination thereof. The image acquirer 120 may be connected to the detector 144 of the electron beam tool 100B through a medium such as electrical conductors, a fiber optic cable, a portable storage medium, IR, Bluetooth, the Internet, a wireless network, a wireless radio, or a combination thereof. The image acquirer 120 may receive signals from the detector 144 and construct an image. The image acquirer 120 may thus acquire an image of the wafer 150. The image acquirer 120 may also perform various post-processing functions, such as generating contours and superimposing indicators on the acquired image. The image acquirer 120 may be configured to adjust the brightness and contrast of the acquired image, etc. The storage 130 may be a storage medium such as a hard disk, random access memory (RAM), cloud storage, or other types of computer-readable memory. The storage 130 may be coupled to the image acquirer 120 and may be used to store raw scanned image data as original images and to store post-processed images. The image acquirer 120 and the storage 130 may be connected to the controller 109. In some embodiments, the image acquirer 120, the storage 130, and the controller 109 may be integrated together as one electronic control unit.

[0045]

[0056] In some embodiments, the image acquirer 120 may acquire one or more images of the sample based on an imaging signal received from the detector 144. The imaging signal may correspond to a scanning motion for performing charged particle imaging. The acquired image may be a single image including multiple imaging areas that may include various features of the wafer 150. The single image may be stored in the storage 130. The imaging may be performed on an imaging frame-by-frame basis.

[0046]

[0057] The condenser and illumination optics of the electron beam tool may include or be assisted by electromagnetic quadrupole electron lenses. For example, as shown in FIG. 2B , electron beam tool 100B may include a first quadrupole lens 148 and a second quadrupole lens 158. In some embodiments, the quadrupole lenses are used to control the electron beam. For example, first quadrupole lens 148 may be controlled to adjust the beam current, and second quadrupole lens 158 may be controlled to adjust the beam spot size and beam shape.

[0047]

[0058] 2B illustrates a charged particle beam device in which the inspection system may use a single primary beam that may be configured to generate secondary electrons by interacting with the wafer 150. The detector 144 may be positioned along the optical axis 105, as in the embodiment shown in FIG. 2B. The primary electron beam may be configured to travel along the optical axis 105. Thus, the detector 144 may include a hole in its center to allow the primary electron beam to pass through and reach the wafer 150.

[0048]

[0059] Reference is now made to Figure 3A, which shows a schematic representation of an exemplary structure of a detector 300, consistent with embodiments of the present disclosure. Detector 300 may be provided as detector 144 or electron detection device 240 in connection with Figures 2A and 2B. While one array is shown in Figure 3A, it should be understood that detector 300 may include multiple arrays, such as one array for each secondary electron beam.

[0049]

[0060] Detector 300 may include an array of detector elements, including detector elements 311, 312, and 313. The detector elements may be arranged in a planar, two-dimensional array, with the plane of the array approximately perpendicular to the direction of incidence of the incoming charged particles. In some embodiments, detector 300 may be arranged so that it is tilted relative to the direction of incidence.

[0050]

[0061] The detector 300 may include a substrate 310. The substrate 310 may be a semiconductor substrate that may include a detector element. The detector element may be a diode. The detector element may also be a diode-like element that can convert incident energy into a measurable signal. The detector element may include, for example, a PIN diode, an avalanche diode, an electron multiplier tube (EMT), or the like, or a combination thereof. Additionally, the term "detector element" may include or cover a "sensing element," "sensor element," "detector cell," or "detector segment," etc. In some embodiments, a pixel on a detector may be a detector element.

[0051]

[0062] Area 325 may be provided between adjacent detector elements. Area 325 may be an isolation area for isolating sides or corners of adjacent detector elements from each other. Area 325 may include an insulating material that is a different material from other areas of the detector surface of detector 300. Area 325 may be provided as a cross-shaped area as seen in the plan view of FIG. 3A. Area 325 may be provided as a rectangle. In some embodiments, area 325 may not be provided between adjacent sides of detector elements. For example, in some embodiments, there may be no isolation area provided on the detector surface.

[0052]

[0063] The detector element may generate an electrical signal proportional to the charged particles received at the active area of ​​the detector element. For example, the detector element may generate a current signal proportional to the energy of the received electrons. A pre-processing circuit may convert the generated current signal into a voltage that may represent the intensity of the electron beam spot or a portion thereof. The pre-processing circuit may include, for example, a pre-amplifier circuit. The pre-amplifier circuit may include, for example, a charge transfer amplifier (CTA), a transimpedance amplifier (TIA), or an impedance conversion circuit coupled to the CTA or TIA. In some embodiments, a signal processing circuit may be provided that provides an output signal at any time interval. One or more substrates, such as dies, may be provided that may form circuit layers for processing the output of the detector element. The dies may be stacked across the thickness of the detector. Other circuits for other functions may also be provided. For example, a switch actuation circuit may be provided that may control switch elements for connecting the detector elements to each other.

[0053]

[0064] Reference is now made to FIG. 3B , which illustrates a schematic diagram of a cross-sectional structure of a substrate 310 consistent with embodiments of the present disclosure. The substrate 310 may be an example of a structure included in a PIN detector. The substrate 310 may include one or more layers. For example, the substrate 310 may be configured to have multiple layers stacked in a thickness direction, with the thickness direction being approximately parallel to the direction of incidence of the electron beam. In some embodiments, the substrate 310 may have multiple layers stacked in a direction perpendicular to the direction of incidence of the electron beam. The substrate 310 may be provided with a sensor surface 301 for receiving incident charged particles. Detecting elements (e.g., detecting elements 311, 312, and 313) may be provided in a sensing layer of the substrate 310. An area 325 may be provided between adjacent detecting elements. For example, the substrate 310 may include a trench or other structure made of or filled with an insulating material. In some embodiments, the area 325 may extend completely or partially through the substrate 310.

[0054]

[0065] As shown in FIG. 3C , in some embodiments, area 325 may not be provided between sensing elements, consistent with embodiments of the present disclosure. For example, there may be no insulating material provided between sides of adjacent sensing elements in a cross-sectional view. Multiple sensing elements may be contiguous in a cross-sectional view. Isolation between adjacent sensing elements may still be achieved by other means, such as by controlling an electric field. For example, an electric field may be controlled between each sensing element.

[0055]

[0066] Although the diagram may show the detector elements 311, 312, and 313 as separate units, in reality, such division may not exist. For example, the detector elements may be formed by semiconductor devices that constitute a PIN diode device. The PIN diode device may be fabricated as a substrate having multiple layers, including a p-type region, an intrinsic region, and an n-type region. One or more of such layers may be continuous in cross-section. However, in some embodiments, the detector elements may have physical separations between them. Also, in addition to the sensor layer, additional layers, such as a circuit layer and a readout layer, may be provided.

[0056]

[0067] As an example of additional layers, the detector 300 may include one or more circuit layers adjacent to the sensor layer. The one or more circuit layers may include electrical wires, interconnects, and various electronic circuit components. The one or more circuit layers may include a processing system. The one or more circuit layers may include signal processing circuitry. The one or more circuit layers may be configured to receive detected output currents from the sensing elements of the sensor layer. The one or more circuit layers and the sensor layer may be provided on the same or separate dies, for example.

[0057]

[0068] FIG. 3D shows a schematic diagram of an individual detector element consistent with an embodiment of the present disclosure, which may be an example of one of detector elements 311, 312, and 313. For example, FIG. 3D shows detector element 311A. Detector element 311A ​​may include a semiconductor structure of p-type layer 321, intrinsic layer 322, and n-type layer 323. Detector element 311A ​​may include two terminals, such as an anode and a cathode. Detector element 311A ​​may be reverse-biased, and a depletion region 330 may form spanning a portion of the length of p-type layer 321, substantially the entire length of intrinsic layer 322, and a portion of the length of n-type layer 323. Charge carriers may be removed in depletion region 330, and new charge carriers generated in depletion region 330 may be swept away according to their charge. For example, when an incoming charged particle reaches the sensor surface 301, an electron-hole pair may be created, and the hole 351 may be attracted towards the p-type layer 321 while the electron 352 may be attracted towards the n-type layer 323. In some embodiments, a protective layer may be provided on the sensor surface 301.

[0058]

[0069] During operation, the depletion region of the detector element can function as a capture region. Incoming charged particles can interact with the semiconductor material of the depletion region and generate new charges. For example, the detector element can be configured so that charged particles having an energy above a certain amount can remove electrons from the lattice of the semiconductor material, thereby creating electron-hole pairs. The resulting electrons and holes can be forced to travel in opposite directions, for example, due to the electric field in the depletion region. The generation of carriers traveling toward the terminals of the detector element can correspond to the flow of current through the detector element.

[0059]

[0070] In a comparative example, a photodiode can be configured to generate charge in response to receiving a photon. The photon can have an energy corresponding to its wavelength or frequency. Typically, a photon in the visible light spectrum can have an energy of about 1 eV. However, in a semiconductor photodiode, it can typically require about 3.6 eV to generate one electron-hole pair. Therefore, photodiodes can face the following current generation detection challenges:

[0060]

[0071] Generally, the energy level of a photon may be similar to the level required to generate an electron-hole pair in a semiconductor photodiode. Therefore, to reliably generate a current, high-energy photons may be required to be incident on the semiconductor photodiode. When the photon's frequency is above a certain level, it may have enough energy to generate one electron-hole pair.

[0061]

[0072] Furthermore, the current generated by the electron-hole pair in response to a photon arrival event may be relatively low. The current generated in response to a photon arrival event may not be sufficient to overcome background noise. Some diodes, such as photodiodes biased in avalanche or Geiger counting mode, may use amplification to generate higher levels of current so that a useful detection signal can be generated. In some embodiments, the photodiode may be biased in an avalanche mode of operation. In some embodiments, the amplification may be provided by a gain block attached to the photodiode. The avalanche effect may be generated from a strong internal electric field resulting from the bias voltage. The avalanche effect may be used to achieve amplification by impact ionization.

[0062]

[0073] FIG. 4 shows a schematic diagram of an individual detector element consistent with embodiments of the present disclosure, which may be an example of one of detector elements 311, 312, and 313. For example, FIG. 4 shows detector element 400. Detector element 400 may include a substrate (e.g., a silicon substrate) 401 having lateral PIN diodes, where a first PIN diode includes an n-type region 403a (e.g., an n-type dopant), a p-type region 404a (e.g., a p-type dopant), and an intrinsic region 405a, a second PIN diode includes an n-type region 403b, a p-type region 404a, and an intrinsic region 405b, and a third PIN diode includes an n-type region 403b, a p-type region 404b, and an intrinsic region 405c. While three PIN diodes are shown, it should be understood that detector element 400 may include any number of PIN diodes. The PIN diodes may be formed on a surface 410 of detector element 400. In some embodiments, a passivation layer 411 may be formed on the surface 410 .

[0063]

[0074] The detector element 400 may include terminals such as a cathode 413a on the n-type region 403a, an anode 414a on the p-type region 404a, a cathode 413b on the n-type region 403b, and an anode 414b on the p-type region 404b. The region between the n-type region 403a and the p-type region 404a may form a depletion region 407a when a reverse bias is applied between the n-type region 403a and the p-type region 404a. The depletion region 407a may span a portion of the length of the n-type region 403a, substantially the entire length of the intrinsic region 405a, and a portion of the length of the p-type region 404a. In the depletion region 407a, charge carriers may be removed, and new charge carriers generated in the depletion region 407a may be swept away according to their charge. For example, when incoming charged particles (e.g., electrons) reach surface 410, electron-hole pairs may be created, and the holes may be attracted toward p-type region 404a while the electrons may be attracted toward n-type region 403a. Similarly, depletion region 407b may form between n-type region 403b and p-type region 404a, and depletion region 407c may form between n-type region 403b and p-type region 404b.

[0064]

[0075] During operation, the depletion region of the detection element 400 can function as a capture region. Incoming charged particles can interact with the semiconductor material of the depletion region and generate new charges. For example, the detection element 400 can be configured so that charged particles having an amount of energy or greater can remove electrons from the lattice of the semiconductor material, thereby creating electron-hole pairs. The resulting electrons and holes can be caused to travel in opposite directions, for example, due to the electric field in the depletion region. The generation of carriers traveling toward the terminals of the detection element 400 can correspond to the flow of current through the detection element 400.

[0065]

[0076] In some embodiments, passivation layer 421 may be formed on backside 420 of substrate 401, opposite front side 410. Unlike front side 410, which includes n-type regions 403a-403b and p-type regions 404a-404b, backside 420 may include a substantially uniform surface (e.g., a surface without implant dopants, a material with zero implant dopant concentration, a zero PIN diode, a zero cathode, a zero anode, etc.). The substantially uniform surface of backside 420 may be between front side 410 and passivation layer 421.

[0066]

[0077] The substrate 401 may include a dopant concentration greater than zero, where the dopant is a non-implanted dopant. The non-implanted dopant may be added to the silicon substrate as it is formed. For example, the dopant may be added to the molten silicon and become part of the silicon substrate as the silicon crystal is grown to form the silicon substrate.

[0067]

[0078] To detect particles, the PIN diode of the detection element 400 may be configured to detect particles 422 (e.g., charged particles) that enter the backside surface 420 and travel through the silicon substrate 401 to the depletion region. In some embodiments, the passivation layer 421 may include a material (e.g., SiN, a thin metal, etc.) that is substantially transparent to electrons, such that particles 422 (electrons) can pass through the detection element 400 from the backside surface 420 and be detected by the PIN diode of the detection element 400. Thus, the passivation layer 421 does not include a material, such as SiO2, that is not transparent to electrons when the detection element 400 is used to detect electrons.

[0068]

[0079] Advantageously, the detection element 400 may use a lateral PIN diode with backside illumination to detect particles (e.g., the backside of the substrate may be exposed to secondary electrons, but the front side of the substrate may not be exposed to secondary electrons), thereby improving the responsivity, response speed, and fill factor of the detection element 400. The detection responsivity may be described as the ratio of the output to the input of the detection element (e.g., the output current to the input current). The detection response speed may be described as the time it takes for an electrical signal to be generated by the detection element when a particle lands on it. The detection fill factor may be described as the percentage of detection elements within a certain area of ​​the detector that generate a signal.

[0069]

[0080] Backside illuminated detection of detector element 400 may exhibit improved responsivity and response speed during detection by avoiding carrier losses typically resulting from frontside illuminated detection, such as carrier losses due to a surface passivation layer on the surface of the PIN diode, a heavily doped region on the surface, a surface metal layer, or electrical contacts on the surface. For example, carrier losses may occur due to a surface metal layer or electrical contacts on the surface of the PIN diode absorbing some electrons.

[0070]

[0081] Advantageously, sensing element 400 may use a thin substrate, which allows a PIN diode on front surface 410 to detect particles 422 entering back surface 420. For example, thickness 402 of substrate 402 may be less than 20 μm or less than 30 μm, which may allow particles 422 to reach surface 410 with high responsivity and high response speed. Thin substrate 402 also avoids the use of trenches and additional implants in sensing element 400, which are typically required for backside illuminated sensing using thicker substrates.

[0071]

[0082] Because the substrate 401 is thin (e.g., less than 20 μm or less than 30 μm), the depletion regions 407 a- 407 c may include the backside 420, thereby depleting the entire substrate 401. Advantageously, a fully depleted substrate 401 may result in high responsivity and a high response speed of the sensing element 400.

[0072]

[0083] In some embodiments, the thickness of substrate 402 can be adjusted or controlled to control the detection response speed of detection element 400. In some embodiments, the detection response, response speed, fill factor, and parasitics of detection element 400 can be adjusted or controlled by adjusting PIN diodes, such as the widths of n-type regions 403a-403b and p-type regions 404a-404b, the dopant concentrations of n-type regions 403a-403b and p-type regions 404a-404b, and the widths of intrinsic regions 405a-405c.

[0073]

[0084] Some typical sensing elements may use substrates with thicknesses greater than 30 μm, which can be limiting. For example, sensing elements with substrate thicknesses greater than 30 μm may exhibit low responsivity and low response speed due to particles being unable to reach the surface of the sensing element or particles reaching the surface of the sensing element slowly. Sensing elements with substrate thicknesses greater than 30 μm may also require more complex manufacturing by requiring additional trenches and implants to allow particles to reach the surface of the sensing element with high responsivity and high response speed. Embodiments of the present disclosure overcome these limitations by using substrates with thicknesses less than 20 μm or less than 30 μm.

[0074]

[0085] Some detectors may also include, and be limited by, implant dopants on the back surface of the detector (i.e., implant dopants on the particle-entering surface of the detector, implant dopants on both the front and back surfaces, etc.). For example, detectors with implant dopants on the back surface of the detector may exhibit poor responsivity and poor response speed due to carrier loss on the back surface of the detector. For example, carrier loss may occur due to the implant dopants on the back surface of the detector absorbing some electrons. Embodiments of the present disclosure overcome these limitations by using a back surface with a substantially uniform surface (e.g., a surface without implant dopants, a material with zero implant dopant concentration, zero PIN diode, zero cathode, zero anode, etc.).

[0075]

[0086] FIG. 5 shows a schematic diagram of an individual detector element, which may be an example of one of detector elements 311, 312, 313, and 400, and a readout integrated circuit, consistent with an embodiment of the present disclosure.

[0076]

[0087] As shown in FIG. 5 , detector element 500 may include a substrate (e.g., a silicon substrate) 501 (e.g., substrate 401 in FIG. 4 ) having a lateral PIN diode, the PIN diode including an n-type region 503 (e.g., an n-type dopant) (e.g., n-type regions 403a-403b in FIG. 4 ), a p-type region 504 (e.g., a p-type dopant) (e.g., p-type regions 404a-404b in FIG. 4 ), and an intrinsic region 505 (e.g., intrinsic regions 405a-405c in FIG. 4 ). The PIN diode may be formed on a surface 510 (e.g., surface 410 in FIG. 4 ) of detector element 500. In some embodiments, a passivation layer 511 (e.g., passivation layer 411 in FIG. 4 ) may be formed on surface 510.

[0077]

[0088] Detector element 500 may include terminals such as a cathode 513 (e.g., cathodes 413a-413b in FIG. 4) on n-type region 503 and an anode 514 (e.g., anodes 414a-414b in FIG. 4) on p-type region 504. The region between n-type region 503 and p-type region 504 may form a depletion region 507 (e.g., depletion regions 407a-407c in FIG. 4) when a reverse bias is applied between n-type region 503 and p-type region 504. Depletion region 507 may span a portion of the length of n-type region 503, substantially the entire length of intrinsic region 505, and a portion of the length of p-type region 504. Because substrate 501 is thin (e.g., less than 20 μm or less than 30 μm), depletion region 507 may include backside surface 520, thereby depleting the entire substrate 501. Advantageously, a fully depleted substrate 501 may result in high responsivity and high response speed of the sensing element 500.

[0078]

[0089] In some embodiments, a passivation layer 521 (e.g., passivation layer 421 in FIG. 4 ) may be formed on a back surface 520 (e.g., back surface 420 in FIG. 4 ) of substrate 501 opposite front surface 510. Unlike front surface 510, which includes n-type region 503 and p-type region 504, back surface 520 may include a substantially uniform surface (e.g., a surface without implant dopants, material with zero implant dopant concentration, zero PIN diode, zero cathode, zero anode, etc.). To detect particles, the PIN diode of detection element 500 may be configured to detect particles 522 (e.g., charged particles) (e.g., particle 422 in FIG. 4 ) that enter back surface 520 and travel through silicon substrate 501 to depletion region 507. In some embodiments, passivation layer 521 may include a material (e.g., SiN, a thin metal, etc.) that is substantially transparent to electrons, such that particles 522 (electrons) can pass through backside 520 to detection element 500 and be detected by a PIN diode of detection element 500. Thus, passivation layer 521 does not include a material, such as SiO, that is not transparent to electrons when detection element 500 is used to detect electrons.

[0079]

[0090] 5, because the cathode 513 and anode 514 are on the same surface 510, the sensing element 500 can be easily integrated directly into a readout integrated circuit 520 (e.g., a CMOS ASIC) without using through-wafer vias in the substrate 501. For example, the sensing element 500 can be attached to the readout integrated circuit 550 using an adhesive material 551 (e.g., solder bumps).

[0080]

[0091] 6A, 6B, and 6C show schematic diagrams of the metal geometry of an individual sensing element consistent with an embodiment of the present disclosure, where the sensing element may be an example of one of sensing elements 311, 312, 313, 400, and 500.

[0081]

[0092] As shown in FIG. 6A , sensing element 600a (e.g., sensing element 400 of FIG. 4 , sensing element 500 of FIG. 5 ) may include a cathode 613a (e.g., cathodes 413a-413b of FIG. 4 , cathode 513 of FIG. 5 ) and an anode 614a (e.g., anodes 414a-414b of FIG. 4 , anode 514 of FIG. 5 ) on its surface 610a (e.g., surface 410 of FIG. 4 , surface 510 of FIG. 5 ). In some embodiments, cathode 613a and anode 614a of sensing element 600a may be arranged to be interdigitated with each other. In some embodiments, the metal geometry of interdigitated sensing element 600a may be adjusted to control or adjust sensing responsivity, response speed, parasitics, or losses from surface 610a.

[0082]

[0093] As shown in FIG. 6B , sensing element 600b (e.g., sensing element 400 of FIG. 4 , sensing element 500 of FIG. 5 ) may include a cathode 613b (e.g., cathodes 413a-413b of FIG. 4 , cathode 513 of FIG. 5 ) and an anode 614b (e.g., anodes 414a-414b of FIG. 4 , anode 514 of FIG. 5 ) on its surface 610b (e.g., surface 410 of FIG. 4 , surface 510 of FIG. 5 ). In some embodiments, cathode 613b and anode 614b of sensing element 600b may be concentrically arranged. In some embodiments, the metal geometry of sensing element 600b may be adjusted to control or adjust sensing responsivity, response speed, parasitics, or losses from surface 610b.

[0083]

[0094] As shown in FIG. 6C , sensing element 600c (e.g., sensing element 400 of FIG. 4 or sensing element 500 of FIG. 5 ) may include a cathode 613c (e.g., cathodes 413a-413b of FIG. 4 or cathode 513 of FIG. 5 ) and an anode 614c (e.g., anodes 414a-414b of FIG. 4 or anode 514 of FIG. 5 ) on its surface 610c (e.g., surface 410 of FIG. 4 or surface 510 of FIG. 5 ). In some embodiments, the cathodes 613c and anodes 614c of sensing element 600c may be arranged in a concentric hexagonal shape. In some embodiments, the metal geometry of sensing element 600c may be tailored to control or adjust sensing responsivity, response speed, parasitics, or losses from surface 610c. In some embodiments, the metal geometry of sensing element 600c may be used to reduce the breakdown voltage of sensing element 600c.

[0084]

[0095] In some embodiments, the metallic geometry of the sensing elements 600a, 600b, and 600c may improve the uniformity and consistency of the sensing responsivity, response speed, and fill factor across the detector.

[0085]

[0096] Referring now to Figure 7, Figure 7 shows a schematic diagram of an exemplary structure of a detector 700 (e.g., detector 300 of Figure 3) consistent with embodiments of the present disclosure. Detector 700 may be provided as detector 144 or electron detection device 240 in relation to Figures 2A and 2B. Although one array is shown in Figure 7, it should be understood that detector 700 may include multiple arrays, such as one array for each secondary electron beam.

[0086]

[0097] Detector 700 may include an array of detector elements, including detector element 701 (e.g., 311, 312, 313, 400, 500, 600a, 600b, 600c). The detector elements may be arranged in a planar, two-dimensional array, with the plane of the array approximately perpendicular to the direction of incidence of incoming charged particles. In some embodiments, detector 700 may be arranged at an angle to the direction of incidence. The PIN diodes of the detector elements may be arranged in a lateral geometry to provide a greater density of PIN diodes per unit area. For example, the array may include any combination of any number of alternating p-type and n-type regions.

[0087]

[0098] 7, sensing element 701 may include a cathode 713 (e.g., cathodes 413a-413b in FIG. 4, cathode 513 in FIG. 5) and an anode 714 (e.g., anodes 414a-414b in FIG. 4, anode 514 in FIG. 5) on its surface 710 (e.g., surface 410 in FIG. 4, surface 510 in FIG. 5). While cathodes 713 and anodes 714 are arranged in an interdigitated manner (e.g., sensing element 600a in FIG. 6A), it should be understood that the metal geometry of sensing element 701 is not limited, and other metal geometries (e.g., sensing element 600b in FIG. 6B, sensing element 600c in FIG. 6C) may be used as well.

[0088]

[0099] 8A and 8B, flowcharts illustrate exemplary processes 800A and 800B for forming sensing elements (e.g., 311, 312, 313, 400, 500, 600a, 600b, 600c, 701) consistent with embodiments of the present disclosure. The steps of processes 800A and 800B may be performed by a system that executes on or otherwise uses features of a computing device (e.g., controller 109 of FIGS. 1, 2A, and 2B) for illustrative purposes. It should be understood that the illustrated processes 800A and 800B may be modified to modify the order of steps and include additional steps.

[0089]

[0100] For example, process 800A of Figure 8A shows that in step 801, a substrate 801a (e.g., silicon, SOI, etc.) (e.g., substrate 401 of Figure 4, substrate 501 of Figure 5) may be prepared for processing. In some embodiments, substrate 801a may be a thick substrate (e.g., 500-600 μm) that forms the intrinsic region of a PIN diode (e.g., intrinsic regions 405a-405c of Figure 4, intrinsic region 505 of Figure 5).

[0090]

[0101] In step 802, layer 802a may be used to implant p-type dopants into substrate 801a to form p-type region 802b (e.g., p-type regions 404a-404b in FIG. 4 and p-type region 504 in FIG. 5). In some embodiments, layer 802a (e.g., SiN, SiO, diazonaphthoquinone-based resist (DNQ-Novolak), etc.) may be capable of blocking ions from entering regions of substrate 801a outside of p-type region 802b. In some embodiments, p-type region 802b may be tuned to adjust the depletion region of the PIN diode. For example, p-type region 802b may be tuned by adjusting its depth, width, or dopant concentration. In some embodiments, layer 802a may be deposited and patterned photoresist. The photoresist may be deposited and patterned before the ion implant, and the photoresist may be removed after the ion implant. In some embodiments, layer 802a may include an insulator and photoresist. An insulator and photoresist may be deposited, and the photoresist may be patterned. Using the photoresist pattern, the insulator may be patterned using a selective etching process. The photoresist may be removed, and an ion implant may be performed. The insulator may then be removed.

[0091]

[0102] In step 803, layer 803a may be used to implant n-type dopants into substrate 801a to form n-type region 803b (e.g., n-type regions 403a-403b in FIG. 4 and n-type region 503 in FIG. 5). In some embodiments, layer 803a (e.g., SiN, SiO, diazonaphthoquinone-based resist (DNQ-Novolak), etc.) may be able to block ions from entering regions of substrate 801a outside of n-type region 803b. In some embodiments, n-type region 803b may be tuned to adjust the depletion region of the PIN diode. For example, n-type region 803b may be tuned by adjusting its depth, width, or dopant concentration.

[0092]

[0103] In step 804, a metal layer may be deposited and patterned on p-type region 802b to form anode 804a, and on n-type region 803b to form cathode 804b. For example, a metal layer may be selectively deposited on p-type region 802b and n-type region 803b through photolithographic patterning using a sacrificial mask, followed by metal fill or metal deposition. In some embodiments, anode 804a and cathode 804b may be made of alloys or pure metals (e.g., aluminum (Al), tungsten (W), silicides (TiSi2, MoSi2, PtSi, CoSi2, WSi2), etc.).

[0093]

[0104] In step 805, a first passivation layer 805a may be formed on the anode 804a and the cathode 804b, and a second passivation layer 805b may be formed on the first passivation layer 805a. In some embodiments, the passivation layers 805a and 805b may function as insulators. In some embodiments, the thicknesses of the passivation layers 805a and 805b may be adjusted. For example, the passivation layer 805b (e.g., 5-10 μm) may be thicker than the passivation layer 805a (e.g., 100 nm). In some embodiments, the passivation layer 805a may be used to reduce recombination loss from the surface of the substrate 801a, and the substrate 801a may be thin (e.g., less than 100 nm). In some embodiments, passivation layer 805b may optionally be included for mechanical support for the step of thinning substrate 801a (step 808), with thicker layers providing more support.

[0094]

[0105] As shown in process 800B of FIG. 8B, in step 806 following step 805 of FIG. 8A, via holes 806a and 806b may be patterned in passivation layers 805a and 805b such that the via holes 806a and 806b are aligned with the anode 804a and the cathode 804b, respectively, thereby exposing the anode 804a and the cathode 804b from the passivation layers 805a and 805b.

[0095]

[0106] In step 807, a carrier substrate 807a may be attached to the passivation layer 805b in preparation for substrate thinning.

[0096]

[0107] In step 808, the backside 808a of the substrate 801a may be thinned to reduce the thickness of the substrate 801a (e.g., to a thickness of 20 μm, 30 μm, etc.), and a carrier substrate 807a is attached to the passivation layer 805b. In some embodiments, the substrate 801a may be thinned through a chemical-based etching process (e.g., polishing by chemical mechanical polishing (CMP), dry etching, etc.) or grinding process. As described above, the thinned substrate allows the directionality of electrons to travel from the backside of the substrate 801a to the PIN diode without losing their energy or path direction within the intrinsic region.

[0097]

[0108] In step 809, layer 809a (e.g., layer 421 in FIG. 4, layer 521 in FIG. 5) may be deposited on backside 808a of thinned substrate 801a. In some embodiments, layer 809a may include a material that protects substrate 801a and is substantially transparent to electrons (e.g., SiN, a thin metal, etc.).

[0098]

[0109] The carrier substrate 807a may be removed in step 810. In some embodiments, a passivation layer 805b is included for mechanical support for the substrate thinning step, and the passivation layer 805b may remain in the final detector element or may be removed.

[0099]

[0110] The following clauses may be used to further describe the embodiments. 1. a silicon substrate thinned to a thickness of 30 μm or less; a surface of a silicon substrate containing a lateral PIN diode formed by p-type and n-type implants; a region between the p-type implant and the n-type implant configured to form a depletion region when a reverse bias is applied between the p-type implant and the n-type implant; a back surface of the silicon substrate opposite the front surface, the back surface including a substantially uniform surface; a protective layer on a substantially uniform surface on the back surface of the silicon substrate; a lateral PIN diode configured to detect electrons entering the backside of the silicon substrate and traveling through the silicon substrate to the depletion region; Detector. 2. The detector of clause 1, wherein the protective layer comprises a material that is substantially transparent to electrons. 3. The detector of any one of clauses 1-2, wherein the substantially uniform surface of the backside of the silicon substrate comprises an implant dopant concentration that is substantially zero. 4. The detector of clause 3, wherein the silicon substrate comprises a dopant concentration greater than zero, and the dopant of the dopant concentration is a non-implanted dopant. 5. The detector of clause 4, wherein the non-implanted dopant is added to the silicon substrate when the silicon substrate is formed. 6. A detector according to any one of clauses 1 to 5, wherein a substantially uniform surface on the back surface of the silicon substrate is between the front surface and the protective layer. 7. A detector according to any one of clauses 1 to 6, wherein the backside of the silicon substrate comprises a zero PIN diode. 8. A detector according to any one of clauses 1 to 7, wherein the backside of the silicon substrate comprises a zero anode and a zero cathode. 9. A detector according to any one of clauses 1 to 8, wherein the back surface of the silicon substrate is configured to be exposed to secondary electrons and the front surface of the silicon substrate is configured not to be exposed to secondary electrons. 10. A detector according to any one of clauses 1 to 9, wherein the lateral PIN diode comprises an anode on a p-type implant and a cathode on an n-type implant. 11. A detector according to clause 10, wherein the cathodes and anodes are arranged in an alternating interdigitated manner. 12. A detector according to clause 10, wherein the cathode and anode are arranged concentrically. 13. A detector as described in clause 10, wherein the cathodes and anodes are arranged in a concentric hexagonal configuration. 14. A detector according to clause 10, wherein the lateral PIN diode is bonded by its cathode and anode to a readout integrated circuit. 15. a plurality of detection elements, each of the detection elements including a portion of a silicon substrate; A part of the silicon substrate a surface of a portion of a silicon substrate including a PIN diode including a p-type region and an n-type region; a back surface of a portion of the silicon substrate opposite the front surface, the back surface including a substantially uniform surface; a layer on the backside of a portion of the silicon substrate; a region between the p-type region and the n-type region configured to form a depletion region when a reverse bias is applied between the p-type region and the n-type region; the PIN diode is configured to detect electrons entering the backside of the portion of the silicon substrate and traveling through the portion of the silicon substrate to the depletion region; Detector. 16. A detector according to clause 15, wherein the layer comprises a material that is substantially transparent to electrons. 17. A detector according to any one of clauses 15 to 16, wherein the thickness of a portion of the silicon substrate is 30 μm or less. 18. A detector according to any one of clauses 15 to 17, wherein the substantially uniform surface of the backside of the portion of the silicon substrate comprises an implant dopant concentration that is substantially zero. 19. The detector of clause 18, wherein a portion of the silicon substrate includes a dopant concentration greater than zero, and the dopant of the dopant concentration is a non-implanted dopant. 20. The detector of clause 19, wherein the non-implanted dopant is added to the portion of the silicon substrate as the portion of the silicon substrate is formed. 21. A detector according to any one of clauses 15 to 20, wherein a substantially uniform surface of a back surface of a portion of the silicon substrate is between the front surface and the layer. 22. A detector according to any one of clauses 15 to 21, wherein the backside of a portion of the silicon substrate comprises a zero PIN diode. 23. A detector according to any one of clauses 15 to 22, wherein the backside of a portion of the silicon substrate comprises a zero anode and a zero cathode. 24. A detector described in any one of clauses 15 to 23, wherein a rear surface of a portion of the silicon substrate is configured to be exposed to secondary electrons and a front surface of a portion of the silicon substrate is configured not to be exposed to secondary electrons. 25. A detector according to any one of clauses 15 to 24, wherein the PIN diode comprises an anode on the p-type region and a cathode on the n-type region. 26. A detector according to clause 25, wherein the cathodes and anodes are arranged in an alternating interdigitated fashion. 27. A detector according to clause 25, wherein the cathode and anode are arranged concentrically. 28. A detector as described in clause 25, wherein the cathodes and anodes are arranged in a concentric hexagonal configuration. 29. A detector according to clause 25, wherein the PIN diode is attached to the readout integrated circuit by its cathode and anode. 30. A detector comprising a plurality of detector elements, wherein a detector element of the plurality of detector elements comprises a portion of a silicon substrate; A part of the silicon substrate a surface of a portion of a substrate including a PIN diode including a p-type region and an n-type region; a backside of a portion of the substrate opposite the front side, the backside including a substantially uniform surface; a layer on the backside of a portion of the substrate; a region between the p-type region and the n-type region configured to form a depletion region when a reverse bias is applied between the p-type region and the n-type region; a PIN diode configured to receive electrons incident on a backside of a portion of the substrate; Detector. 31. A detector according to clause 30, wherein the layer comprises a material that is substantially transparent to electrons. 32. A detector according to any one of clauses 30-31, wherein a portion of the substrate has a thickness of 30 μm or less. 33. A detector according to any one of clauses 30 to 32, wherein a substantially uniform surface on a backside of a portion of the substrate comprises an implant dopant concentration that is substantially zero. 34. The detector of clause 33, wherein a portion of the substrate includes a dopant concentration greater than zero, and the dopant in the dopant concentration is a non-implanted dopant. 35. A detector as recited in clause 34, wherein the non-implant dopant is added to the portion of the substrate as the portion of the substrate is formed. 36. A detector according to any one of clauses 30 to 35, wherein a substantially uniform surface of a back surface of a portion of the substrate is between the front surface and the layer. 37. A detector according to any one of clauses 30 to 36, wherein the backside of a portion of the substrate comprises a zero PIN diode. 38. A detector according to any one of clauses 30 to 37, wherein the backside of a portion of the substrate comprises a zero anode and a zero cathode. 39. A detector according to any one of clauses 30 to 38, wherein a back surface of a portion of the substrate is configured to be exposed to secondary electrons and a front surface of a portion of the substrate is configured not to be exposed to secondary electrons. 40. A detector according to any one of clauses 30 to 39, wherein the PIN diode comprises an anode on the p-type region and a cathode on the n-type region. 41. A detector according to clause 40, wherein the cathodes and anodes are arranged in an alternating interdigitated manner. 42. A detector according to clause 40, wherein the cathode and anode are arranged concentrically. 43. A detector as described in clause 40, wherein the cathodes and anodes are arranged in a concentric hexagonal configuration. 44. A detector according to clause 40, wherein the PIN diode is attached to the readout integrated circuit by its cathode and anode. 45. A detector comprising a plurality of detector elements, wherein a detector element of the plurality of detector elements comprises a portion of a substrate; Part of the board is a surface of a portion of a substrate including a p-type region and an n-type region, the p-type region and the n-type region forming a PIN diode; a back surface of a portion of the substrate opposite the front surface, the back surface comprising a substantially uniform surface; a region between the p-type region and the n-type region configured to form a depletion region when a reverse bias is applied between the p-type region and the n-type region; the PIN diode is configured to receive electrons passing through the portion of the substrate from a backside of the portion of the substrate; Detector. 46. ​​A detector according to clause 45, wherein the thickness of a portion of the substrate is 30 μm or less. 47. A detector according to any one of clauses 45-46, wherein a substantially uniform surface on a backside of a portion of the substrate comprises an implant dopant concentration that is substantially zero. 48. The detector of clause 47, wherein a portion of the substrate includes a dopant concentration greater than zero, and the dopant in the dopant concentration is a non-implanted dopant. 49. A detector as recited in clause 48, wherein the non-implant dopant is added to the portion of the substrate as the portion of the substrate is formed. 50. A detector according to any one of clauses 45 to 49, wherein a substantially uniform surface of a back surface of a portion of the substrate is between the front surface and the layer. 51. A detector according to any one of clauses 45 to 50, wherein the backside of a portion of the substrate comprises a zero PIN diode. 52. A detector according to any one of clauses 45 to 51, wherein the backside of a portion of the substrate comprises a zero anode and a zero cathode. 53. A detector according to any one of clauses 45 to 52, wherein a back surface of a portion of the substrate is configured to be exposed to secondary electrons and a front surface of a portion of the substrate is configured not to be exposed to secondary electrons. 54. A detector according to any one of clauses 45 to 53, wherein the PIN diode comprises an anode on the p-type region and a cathode on the n-type region. 55. A detector according to clause 54, wherein the cathodes and anodes are arranged in an alternating interdigitated manner. 56. A detector according to clause 54, wherein the cathode and anode are arranged concentrically. 57. A detector according to clause 54, wherein the cathodes and anodes are arranged in a concentric hexagonal configuration. 58. A detector according to clause 54, wherein the PIN diode is bonded to the readout integrated circuit by its cathode and anode. 59. A method of forming a detector element of a detector, comprising: forming a PIN diode at a surface of a silicon substrate by implanting p-type dopants to form a p-type region and implanting n-type dopants to form an n-type region in the silicon substrate; forming a PIN diode, wherein a region between the p-type region and the n-type region is configured to form a depletion region when a reverse bias is applied between the p-type region and the n-type region; thinning a back surface of the silicon substrate opposite the front surface, the back surface comprising a substantially uniform surface; forming a layer on a backside of a silicon substrate, forming a layer, wherein the PIN diode is configured to detect electrons entering the backside of the silicon substrate and traveling through the silicon substrate to a depletion region; A method comprising: 60. The method of clause 59, further comprising implanting p-type and n-type dopants using photoresist. 61. The method of clause 60, further comprising depositing and patterning a metal layer on the p-type region to form an anode, and depositing and patterning a metal layer on the n-type region to form a cathode. 62. The method of clause 61, wherein the cathodes and anodes are arranged in alternating interdigitation. 63. The method of clause 61, wherein the cathode and anode are arranged concentrically. 64. The method of clause 61, wherein the cathodes and anodes are arranged in a concentric hexagonal configuration. 65. The method of any one of clauses 61-64, further comprising depositing a first passivation layer on the patterned metal layer and depositing a second passivation layer on the first passivation layer, wherein the second passivation layer is thicker than the first passivation layer. 66. The method of clause 65, further comprising patterning via holes in the first passivation layer and the second passivation layer, the via holes being aligned with the cathode and anode. 67. The method of clause 66, further comprising attaching the carrier substrate to a second passivation layer. 68. The method of clause 67, wherein thinning the backside of the silicon substrate comprises reducing the thickness of the silicon substrate to 30 μm or less while the carrier substrate is attached to the second passivation layer. 69. The method of any one of clauses 67-68, wherein thinning the back surface of the silicon substrate comprises grinding or dry etching the back surface of the silicon substrate. 70. The method of any one of clauses 59-69, further comprising depositing a layer on the back surface of the silicon substrate after thinning the back surface of the silicon substrate. 71. A method according to any one of clauses 59 to 70, wherein the layer comprises a material that is transparent to electrons. 72. The method of any one of clauses 67-71, further comprising removing the carrier substrate. 73. The method of any one of clauses 59-72, wherein the substantially uniform surface on the backside of the substrate comprises an implant concentration of zero. 74. The method of any one of clauses 72-73, further comprising bonding a PIN diode to the readout integrated circuit by means of a cathode and an anode. 75. A detector formed according to any one of clauses 59 to 74, the detector comprises a plurality of detector elements, each of the plurality of detector elements including a portion of a silicon substrate; A part of the silicon substrate a surface of a portion of a silicon substrate including a PIN diode including a p-type region and an n-type region; a back surface of a portion of the silicon substrate opposite the front surface, the back surface including a substantially uniform surface; a layer on the backside of a portion of the silicon substrate; a region between the p-type region and the n-type region configured to form a depletion region when a reverse bias is applied between the p-type region and the n-type region; the PIN diode is configured to detect electrons entering the backside of a portion of the silicon substrate and traveling through the silicon substrate to the depletion region; Detector.

[0100]

[0111] It should be understood that the embodiments of the present disclosure are not limited to the exact configurations described above and illustrated in the accompanying drawings, and that various modifications and changes can be made without departing from the scope thereof.

Claims

1. A detector comprising: a plurality of detection elements, each of the plurality of detection elements including a portion of a silicon substrate; a portion of the silicon substrate, a surface of the portion of the silicon substrate including a PIN diode including a p-type region and an n-type region; a back surface of the portion of the silicon substrate opposite the front surface, the back surface comprising a substantially uniform surface; a layer on the backside of the portion of the silicon substrate; a region between the p-type region and the n-type region configured to form a depletion region when a reverse bias is applied between the p-type region and the n-type region; the PIN diode is configured to detect electrons that enter the backside of the portion of the silicon substrate and travel through the portion of the silicon substrate to the depletion region. Detector.

2. The detector of claim 1 , wherein the layer comprises a material that is substantially transparent to electrons.

3. The detector of claim 1 , wherein the portion of the silicon substrate has a thickness of 30 μm or less.

4. The detector of claim 1 , wherein the substantially uniform surface of the backside of the portion of the silicon substrate includes a substantially zero implant dopant concentration.

5. 5. The detector of claim 4, wherein the portion of the silicon substrate includes a dopant concentration greater than zero, the dopants in the dopant concentration being non-implanted dopants.

6. The detector of claim 5 , wherein the non-implanted dopant is added to the portion of the silicon substrate as the portion of the silicon substrate is formed.

7. The detector of claim 1 , wherein the substantially uniform surface of the back surface of the portion of the silicon substrate is between the front surface and the layer.

8. The detector of claim 1 , wherein the backside of the portion of the silicon substrate includes a zero PIN diode.

9. The detector of claim 1 , wherein the backside of the portion of the silicon substrate includes a zero anode and a zero cathode.

10. The detector of claim 1 , wherein the back surface of the portion of the silicon substrate is configured to be exposed to secondary electrons and the front surface of the portion of the silicon substrate is configured not to be exposed to secondary electrons.

11. The detector of claim 1 , wherein the PIN diode includes an anode on the p-type region and a cathode on the n-type region.

12. The detector of claim 11 , wherein the cathodes and anodes are arranged in an interdigitated manner.

13. The detector of claim 11 , wherein the cathode and the anode are arranged concentrically.

14. The detector of claim 11 , wherein the cathodes and anodes are arranged in a concentric hexagonal configuration.

15. 1. A method of forming a detector element of a detector, comprising: forming a pin diode at a surface of a silicon substrate by implanting p-type dopants to form p-type regions and n-type dopants to form n-type regions in the silicon substrate; a region between the p-type region and the n-type region configured to form a depletion region when a reverse bias is applied between the p-type region and the n-type region; forming the PIN diode; thinning a back surface of the silicon substrate opposite the front surface, the back surface comprising a substantially uniform surface; forming a layer on the backside of the silicon substrate, the PIN diode is configured to detect electrons that enter the backside of the silicon substrate and travel through the silicon substrate to the depletion region. forming a layer; A method comprising:

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