Power management using thermal gradient information

Abstract

Power management using thermal gradient information is described. According to the described technique, temperature measurements of a component are obtained from two or more sensors of the component. A temperature of a hot spot of the component is predicted based on the temperature measurements obtained from the two or more sensors of the component. Operation of the component is adjusted based on the predicted temperature of the hot spot.

Description

[Technical Field]

[0001] (Related Applications) This application claims priority to U.S. Patent Application No. 18 / 148,098, filed December 29, 2022, which claims priority under 35 U.S.C. §119(e) to U.S. Provisional Patent Application No. 63 / 410,175, filed September 26, 2022, entitled "Power Management Using Temperature Gradient Information," the entire disclosure of which is incorporated herein by reference. [Background technology]

[0002] Typically, a computing system has a discrete number of sensors (e.g., thermal sensors) to sense one or more conditions of a portion of the computing system, e.g., one or more components of the computing system. In a scenario where the sensors are thermal sensors that sense the temperature of respective portions of the computing system, the system may use the sensed temperatures to control the operation of the computing system. [Brief explanation of the drawings]

[0003] [Figure 1] FIG. 1 is a block diagram of a non-limiting example system having a memory and a controller operable to implement power management using thermal gradient information. [Figure 2] FIG. 10 is a block diagram of a non-limiting example in which thermal hot spots on a component correspond to locations on the component that are different from the locations of the sensors. [Figure 3] FIG. 1 illustrates a procedure in an exemplary embodiment of power management using thermal gradient information. [Figure 4] FIG. 1 illustrates a non-limiting example of a printed circuit board architecture for a high-bandwidth memory system. DETAILED DESCRIPTION OF THE INVENTION

[0004] (overview) Typically, a computing system has a discrete number of sensors (e.g., thermal sensors) to sense one or more conditions of a portion of the computing system, e.g., one or more components of the computing system. However, in scenarios where the sensors are thermal sensors that sense the temperature of respective portions of the computing system, there may be thermal hot spots that are not reflected in the temperatures generated by the sensors. As an example, this occurs in scenarios where thermal hot spots are located in different portions of the computing system where the thermal sensors are located. Thus, in traditional approaches, a system manager uses the maximum temperature measured by the sensors to determine operating parameters (e.g., voltage and frequency), and the maximum temperature often does not correspond to the actual hottest portion of the computing system.

[0005] Due to local hot spot effects, where actual hot spots of components are in locations different from where sensors are located in the system, and therefore actual temperatures of those hot spots are not recorded, conventional approaches inherently rely on erroneous maximum temperatures. In some cases, conventional approaches add guard bands, for example, to the voltage curve, to account for this error. However, by adding too large a guard band, conventional techniques fail to optimize the performance and / or efficiency of the system. Furthermore, by adding an insufficient guard band to account for the actual temperatures of thermal hot spots, for example, by adding too little guard band to cover the actual maximum temperature, conventional approaches may cause loss of stability and / or component degradation of one or more components of the system.

[0006] To solve these problems, power management using thermal gradient information is described. In contrast to conventional approaches, a system manager receives data (e.g., temperatures) generated over time by multiple sensors and logs this data. The system manager predicts the location and / or temperature of one or more thermal hot spots in components and / or the system based on the data generated by the sensors. The system manager then adjusts the operation of components (e.g., processors, processor cores, memory, and / or portions of memory) based on the predicted temperatures. In particular, the predicted temperatures and locations of hot spots according to the described techniques are more accurate than conventional techniques that throttle operation based on the temperature of the hottest sensor. More accurate determination of system and / or component temperatures is particularly advantageous for overclocking, as temperatures affect whether higher system performance is achievable.

[0007] Furthermore, at least one exemplary advantage of the described techniques is that the number of sensors incorporated into a computing system can be reduced. For conventional approaches, which assume that the highest measured temperature corresponds to the maximum temperature of the system, to be more accurate, such techniques require increasing the density of sensors throughout the system. However, sensors consume system area or volume, and adding more of them occupies more area or volume, resulting in a physically larger system (e.g., a system-on-chip), which may be more expensive than a design with fewer sensors. In contrast, the described techniques achieve greater accuracy with fewer sensors than conventional approaches. Furthermore, some components, such as arithmetic logic units, are not configurable to include sensors. Therefore, conventional approaches that rely on the highest measured temperature from sensors are not suitable for determining the hottest part of a system that includes such components.

[0008] In some aspects, the techniques described herein relate to a system that includes a processor; a first thermal sensor disposed on a first portion of the processor; a second thermal sensor disposed on a second portion of the processor; and a system manager configured to obtain a first temperature measurement from the first thermal sensor, obtain a second temperature measurement from the second thermal sensor, predict a temperature of a hotspot on the processor based on the first temperature measurement and the second temperature measurement, and adjust one or more settings of the processor based on the predicted temperature of the hotspot.

[0009] In some aspects, the technology described herein relates to a system in which a predicted temperature at a hot spot is higher than the first and second temperature measurements.

[0010] In some aspects, the technology described herein relates to a system in which the hot spot is located in a portion of the processor that is different from where the first thermal sensor and the second thermal sensor are located.

[0011] In some aspects, the techniques described herein relate to a system in which a system manager is configured to predict a temperature of a hotspot by determining a temperature delta between a first temperature measurement and a second temperature measurement, determining a slope of the temperature delta, and predicting a temperature of the hotspot based on the slope of the temperature delta.

[0012] In some aspects, the technology described herein relates to a system in which a first thermal sensor and a second thermal sensor are located on a first portion and a second portion of a core of a processor.

[0013] In some aspects, the techniques described herein relate to a system, wherein the system manager is further configured to adjust one or more settings of the core to keep a temperature measurement from the first thermal sensor within a threshold of a temperature measurement from the second thermal sensor.

[0014] In some aspects, the technology described herein relates to a system in which a first thermal sensor is located on a first core of a processor and a second thermal sensor is located on a second core of the processor.

[0015] In some aspects, the techniques described herein relate to a system, wherein the system manager is further configured to adjust one or more settings of at least one of the first core or the second core to keep a temperature measurement from the first thermal sensor within a threshold of a temperature measurement from the second thermal sensor.

[0016] In some aspects, the technology described herein relates to a system, wherein the system is a system-on-chip.

[0017] In some aspects, the techniques described herein relate to a method that includes obtaining temperature measurements of a component from two or more sensors of the component, predicting a temperature of a hot spot of the component based on the temperature measurements obtained from the two or more sensors of the component, and adjusting operation of the component based on the predicted temperature of the hot spot.

[0018] In some aspects, the technology described herein relates to methods where hot spots are located in different parts of a component where two or more sensors are located.

[0019] In some aspects, the technology described herein relates to methods where the predicted temperature of a hot spot is higher than the acquired temperature measurement.

[0020] In some aspects, the technology described herein relates to a method in which the component includes a processor.

[0021] In some aspects, the technology described herein relates to methods in which the component includes a memory.

[0022] In some aspects, the techniques described herein relate to a method where predicting further includes determining a temperature delta between temperature measurements obtained from two or more sensors of the component, determining a gradient of the temperature delta between the two or more sensors of the component, and predicting a temperature of the hot spot of the component based on the gradient of the temperature delta between the two or more sensors of the component.

[0023] In some aspects, the techniques described herein relate to methods whereby the regulating keeps temperature measurements from two or more sensors within a threshold temperature difference.

[0024] In some aspects, the technology described herein relates to a device that includes a stacked memory having a plurality of memory dies; and a system manager configured to obtain temperature measurements from thermal sensors associated with different memory dies of the stacked memory, predict hot spots in the stacked memory based on differences between the temperature measurements from the thermal sensors, and adjust one or more settings of the stacked memory based on the predicted hot spots.

[0025] In some aspects, the techniques described herein relate to a device where predicting a hot spot predicts the temperature of the hot spot and the location of the hot spot within a stacked memory.

[0026] In some aspects, the techniques described herein relate to a device, wherein the predicted location of the hotspot corresponds to at least one memory die of a plurality of memory dies.

[0027] In some aspects, the technology described herein relates to a device, wherein a thermal sensor is disposed on at least one of a plurality of memory dies or between a plurality of memory dies.

[0028] 1 is a block diagram of a non-limiting exemplary system 100 having a memory and a controller operable to implement power management using thermal gradient information. In this example, system 100 includes a processor 102 and a memory module 104. Further, processor 102 includes cores 106 and a controller 108. Memory module 104 includes memory 110. In one or more embodiments, system 100 also includes a system manager 112, and memory module 104 includes in-memory processing components (not shown). In the illustrated example, system 100 is shown with additional components 114 (e.g., cache, secondary storage, semiconductor intellectual property cores, etc.), which indicates that in variations, system 100 includes one or more optional additional components 114. It should be understood that in at least one variation, system 100 may not include one or more of the illustrated components and / or may include different components without departing from the spirit or scope of the described technology.

[0029] According to the described technology, the processor 102 and the memory module 104 are coupled to each other via wired or wireless connections. Additionally, the cores 106 and the controller 108 are coupled to each other via one or more wired or wireless connections. Other components of the system 100 can be connected via wired and / or wireless connections. Exemplary wired connections include, but are not limited to, buses (e.g., data buses), interconnects, through-silicon vias, traces, and planes. Examples of devices in which the system 100 may be implemented include, but are not limited to, servers, personal computers, laptops, desktops, game consoles, set-top boxes, tablets, smartphones, mobile devices, virtual and / or augmented reality devices, wearables, medical devices, systems-on-chips, and other computing devices or systems.

[0030] Processor 102 is an electronic circuit that performs various operations on and / or using data in memory 110. Examples of processor 102 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an accelerated processing unit (APU), and a digital signal processor (DSP). Core 106 is a processing unit that reads and executes instructions (e.g., programs) including, for example, adding, moving, and branching data. While one core 106 is shown in the illustrated example, in variations, processor 102 includes two or more cores 106, e.g., processor 102 is a multi-core processor.

[0031] In one or more embodiments, memory module 104 is a circuit board (e.g., a printed circuit board) on which memory 110 is mounted. In variations, one or more integrated circuits of memory 110 are mounted on the circuit board of memory module 104. Examples of memory module 104 include, but are not limited to, TransFlash memory modules, single in-line memory modules (SIMMs), and dual in-line memory modules (DIMMs). In one or more embodiments, memory module 104 is a single integrated circuit device that incorporates memory 110 on a single chip or die. In one or more embodiments, memory module 104 is composed of multiple chips or dies that implement memory 110 stacked together vertically (3D), arranged side-by-side on an interposer or substrate, or assembled via a combination of vertical stacking or side-by-side arrangement.

[0032] Memory 110 is a device or system used to store information for immediate use within the device, such as by cores 106 and / or in-memory processing components of processor 102. In one or more embodiments, memory 110 corresponds to semiconductor memory in which data is stored in memory cells on one or more integrated circuits. In at least one example, memory 110 corresponds to or includes volatile memory, examples of which include random-access memory (RAM), dynamic random-access memory (DRAM), synchronous dynamic random-access memory (SDRAM), and static random-access memory (SRAM). Alternatively or additionally, memory 110 corresponds to or includes non-volatile memory, examples of which include ferroelectric RAM, magnetoresistive RAM, flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electronically erasable programmable read-only memory (EEPROM), and non-volatile dual in-line memory modules (DIMMs) (NVDIMMs).

[0033] In one or more embodiments, memory 110 is configured as a dual in-line memory module (DIMM). A DIMM contains an array of dynamic random access memory integrated circuits, and the module is mounted on a printed circuit board. Examples of DIMM types include, but are not limited to, synchronous dynamic random access memory (SDRAM), double data rate (DDR) SDRAM, double data rate 2 (DDR2) SDRAM, double data rate 3 (DDR3) SDRAM, double data rate 4 (DDR4) SDRAM, and double data rate 5 (DDR5) SDRAM. In at least one variation, memory 110 is configured as a small outline DIMM (SO-DIMM) according to any of the aforementioned SDRAM standards, e.g., DDR, DDR2, DDR3, DDR4, and DDR5. In one or more embodiments, memory 110 is low-power double data rate (LPDDR), also known as LPDDR SDRAM, a type of synchronous dynamic random access memory. In variations, LPDDR consumes less power than other types of memory and / or has a form factor suitable for devices such as mobile computers and mobile phones. Examples of LPDDR include, but are not limited to, low power double data rate 2 (LPDDR2), low power double data rate 3 (LPDDR3), low power double data rate 4 (LPDDR4), and low power double data rate 5 (LPDDR5). It should be understood that memory 110 can be configured in various manners without departing from the spirit or scope of the described technology.

[0034] The controller 108 is a digital circuit that manages the flow of data to and from the memory 110. By way of example, the controller 108 includes logic for reading and writing to the memory 110 and interfacing with the cores 106, and in variations, includes logic for interfacing with in-memory processing components. For example, the controller 108 receives instructions from the cores 106 that include accessing the memory 110, and the controller 108 provides data from the memory 110 to the cores 106, for processing by the cores 106, for example. In one or more embodiments, the controller 108 is communicatively and / or topologically located between the cores 106 and the memory module 104, such that the controller 108 interfaces with both the cores 106 and the memory module 104.

[0035] In one or more embodiments, system manager 112 includes or is otherwise configured to interface with one or more systems capable of updating the operation of various components of system 100; examples of such systems include, but are not limited to, an adaptive voltage scaling (AVS) system, an adaptive voltage frequency scaling (AVFS), and a dynamic voltage frequency system (DVFS). For example, system manager 112 uses such systems to adjust the settings (e.g., voltage, frequency, timing, etc.) at which various components of the system operate. In one or more embodiments, system manager 112 is configured as an on-die microcontroller that executes firmware to perform the various operations described above and below.

[0036] According to the described techniques, the system manager 112 is configured to dynamically adjust the operation of one or more components of the system, such as by communicating change signals to adjust the frequency, voltage, and / or timing at which the components of the system operate. While the system manager 112 is shown separate from the processor 102 and the memory module 104, in one or more embodiments, the system manager 112 is included as part of the processor 102, the memory module 104, or the additional components 114. Alternatively or additionally, one or more components of the system 100 include a component manager (not shown), which performs one or more of the operations described above and below as being performed by the system manager 112. By way of example and not limitation, the processor 102 and the memory module 104 each include a component manager operable to implement power management using thermal gradient information. While a firmware implementation is described above, in one or more variations, the system manager 112 is implemented using hardware in addition to or instead of firmware. In one example, for example, the system manager 112 is implemented using in-core hardware.

[0037] In accordance with the described technology, system 100 includes multiple sensors 116, e.g., multiple thermal sensors. While the sensors are shown as integral with various components of system 100, in one or more embodiments, only a single component includes multiple sensors 116, e.g., core 106 or memory module 104 or memory 110. Alternatively or additionally, any two or more components of system 100 include one or more of the multiple sensors 116. Indeed, multiple sensors 116 may be integrated throughout the system (or throughout individual components) in a variety of ways without departing from the spirit or scope of the described technology.

[0038] In conventional approaches, component operation is managed based on the temperature associated with the “hottest” sensor, and the temperature obtained from this sensor is used as the basis for throttling the voltage, frequency, etc., of various components of the system. However, during operation, the portion of the computing system having the highest temperature may not be at the location where the sensor, e.g., a thermal sensor, is located. Instead, the portion of the computing system having the highest temperature may be at a location on the computing system that is some distance away from where one or more of the sensors are located. As a result, conventional approaches often throttle the operation of one or more computing system components based on an erroneous maximum temperature, e.g., a temperature that is lower than the actual maximum temperature of the computing system or a temperature that is lower than the actual maximum temperature of a component of the computing system. This can lead to instability of the component during operation and / or degradation of the system component over time.

[0039] In contrast to conventional approaches, in one or more embodiments, the system manager 112 receives data (e.g., temperature) generated over time by multiple sensors 116 and logs this data. The system manager 112 estimates the location and / or temperature of one or more thermal hot spots in the component and / or system 100 based on the data generated over time and space by the sensors 116. In at least one variation, the system manager 112 determines a temperature delta between two or more of the sensors 116 using one or more algorithms that account for the temperature delta. For example, the system manager 112 determines a slope of the temperature delta (e.g., difference) between at least two of the sensors 116. By way of example, two or more of the sensors 116 measure differences (e.g., temperatures) within a particular core, differences between different cores on the same piece of silicon, differences between different pieces of silicon within a package, e.g., a component having a stacked configuration such as a Vcache and / or stacked DRAM. In at least one variation, the system 100 includes sensors 116 positioned between components, such as between different dies of components in a stacked configuration.

[0040] In one or more embodiments, at least one of the algorithms is based on information obtained during pre-silicon analysis and / or post-silicon thermal imaging / mapping. Alternatively or additionally, at least one of the algorithms is based on building one or more models from input thermal sensor information from one or more of the sensors 116 located throughout the system 100 to calculate (e.g., estimate) local thermal hot spots. In at least one variation, the input thermal sensor information is static and corresponds to a point in time. In at least one additional variation, the input thermal sensor information corresponds to measurements from the sensors over time, such as over a time interval. In one or more embodiments, the information obtained during analysis and / or thermal imaging / mapping indicates the locations of various components within the system 100, such as the locations of various logic units within the system 100 that generate more heat than other parts of the system. Thus, the algorithm takes into account the locations of such components, thereby enabling the algorithm to predict the locations of thermal hot spots using knowledge embedded in the algorithm of component locations. In one or more embodiments, the system manager 112 monitors activity (e.g., processing and / or local power density) associated with one or more logical units and uses this information when predicting the location and / or temperature of thermal hotspots.

[0041] Based on the gradient of one or more temperature differences, the system manager 112 predicts the actual hot spot temperature and / or determines a correction, for example, from a table and / or algorithmically. The system manager 112 applies a correction to at least one of the temperature measurements generated by one or more of the sensors 116 to generate a computationally corrected temperature. In scenarios where the algorithm predicts a maximum temperature, the output of the algorithm can be used as the computationally corrected temperature. This computationally corrected temperature is then used by the system manager 112 as a basis for adjusting component operation; for example, the system manager 112 uses the computationally corrected temperature to throttle one or more of the voltage, frequency, timing, etc., of one or more components of the system 100, rather than simply using the temperatures (and guard bands) generated by the sensors 116. In one or more embodiments, this includes determining optimal voltages for one or more components of the system 100 based on the computationally corrected temperature. The temperature and location of hot spots determined according to the described techniques are more accurate than conventional techniques that throttle operation based on the temperature of the hottest sensor. More accurate determination of system and / or component temperatures is particularly advantageous for overclocking, as temperature affects whether higher performance of the system 100 is achievable.

[0042] In one or more embodiments, the system manager 112 uses the temperature delta (e.g., between the sensors 116) to adjust the voltage and / or frequency operating point (or another aspect of the operating components) to maintain the temperature delta (e.g., between the sensors 116) within a threshold difference. By maintaining the delta between the sensors 116 within a range, the system manager 112 improves the accuracy of predicting the temperature and temperature of the actual hotspot location, for example, using extrapolation. This is because if the delta between the sensors 116 is too large, extrapolation error can be introduced into the prediction, causing an inaccurate prediction. Thus, in one or more embodiments, the system manager 112 monitors the delta, and if the delta meets (e.g., is greater than or equal to) a threshold difference, the system manager 112 takes one or more actions (e.g., adjusts voltage, frequency, timing, etc.) to bring the delta back within the threshold. In other words, through iterations of monitoring the delta and taking actions to adjust the operating aspects of the components, the system manager 112 is configured to control the delta (e.g., temperature delta) between the sensors 116.

[0043] Additionally or alternatively, system manager 112 may log data generated by sensors over time to generate a model of temperature changes throughout system 100 (or components) over time, which allows for filtering and further adjustments. By logging this data over time and generating such a model, for example, system manager 112 may determine how different workloads affect the temperature of portions of system 100 over time, so that system manager 112 can then preemptively "prime" one or more components of system 100 (e.g., throttle voltage, frequency, timing, etc.) to handle a given workload.

[0044] At least one exemplary advantage of the described techniques is that they can reduce the number of sensors incorporated into a computing system. To improve accuracy over conventional approaches that assume the highest measured temperature corresponds to the maximum system temperature, such techniques require an increased density of sensors throughout the system. However, sensors consume system area or volume, and adding more of them occupies more area or volume, resulting in a physically larger system (e.g., a system-on-chip), which may be more expensive than a design with fewer sensors. In contrast, the described techniques achieve greater accuracy with fewer sensors than conventional approaches. Furthermore, some components, such as arithmetic logic units, are not configurable to include sensors. Thus, conventional approaches that rely on the highest measured temperature from sensors are not suitable for determining the hottest part of a system that includes such components, which may correspond to components that cannot be configured to include sensors.

[0045] FIG. 2 is a block diagram of a non-limiting example 200 in which thermal hot spots on a component correspond to locations on the component that are different from the locations of the sensors.

[0046] The illustrated example 200 includes a component 202 corresponding to one or more components of system 100. In this example 200, component 202 includes at least a first sensor 204 and a second sensor 206, which are examples of sensors 116. Example 200 also shows a thermal hotspot 208 of component 202, e.g., the actual hottest portion of component 202. In this example 200, neither first sensor 204 nor second sensor 206 is located in thermal hotspot 208 corresponding to a first temperature. Instead, first sensor 204 is located in a portion 210 of component 202 corresponding to a second temperature, and second sensor 206 is located in a portion 212 of component 202 corresponding to a third temperature. In one or more scenarios, the second temperature at first portion 210 is lower than the first temperature at thermal hotspot 208, and the third temperature at second portion 212 is lower than the second temperature. This example 200 illustrates a scenario in which the actual temperature of component 202 increases in the direction of arrow 214 .

[0047] According to the described techniques, the system manager 112 obtains data (e.g., temperature measurements) from the first sensor 204 and the second sensor 206 and logs this data. The system manager 112 also determines a difference, e.g., a temperature difference, between the data generated by the first sensor 204 and the data generated by the second sensor 206. For example, the system manager 112 determines the difference between the data generated by the first sensor 204 and the second sensor 206 at substantially the same time, e.g., the system manager 112 calculates the difference in correspondence in the data.

[0048] In one or more embodiments, the system manager 112 calculates the difference between corresponding temperatures measured (e.g., substantially simultaneously) by the first sensor 204 and the second sensor 206. In other words, the system manager 112 calculates a “temperature delta” between the temperature measured by the first sensor 204 and the temperature measured by the second sensor 206. With reference to the illustrated example 200, for example, the system manager 112 determines the difference between the temperature measured by the first sensor 204, e.g., in portion 210, and the temperature measured by the second sensor 206, e.g., in portion 212.

[0049] In one or more embodiments, the system manager 112 determines the gradient of the difference (e.g., the temperature gradient) and applies a correction to the raw sensor data, e.g., the temperature measured by the first sensor 204 of the portion 210, based on the gradient. In variations, the system manager 112 calculates the temperature gradient over time between the various sensors 116 using one or more of a variety of algorithms. In at least one variation, the system manager 112 extrapolates the gradient to the opposite side of the sensor measuring a higher temperature, where the “opposite side” is the opposite side of the sensor measuring a lower temperature. In the context of the illustrated example 200, for example, the system manager 112 extrapolates the gradient from the second sensor 206 to the opposite side of the first sensor 204 (e.g., by continuing in the direction of the gradient). Based on this, the system manager 112 estimates or otherwise predicts the actual maximum temperature. In at least one variation, the system manager 112 estimates or otherwise predicts the location of the maximum temperature. In one or more scenarios, the system manager 112 simply uses this predicted temperature as the highest temperature. Alternatively or additionally, the system manager 112 corrects the raw sensor data by applying a correction to the highest measured temperature to obtain the predicted temperature. This predicted or corrected temperature is referred to herein as the computationally corrected temperature.

[0050] Based on the computationally corrected temperatures, system manager 112 manages or adjusts settings of system 100, such as by managing or adjusting the power, frequency, timing, etc., of components 202 and / or other components of system 100. In one or more embodiments, system manager 112 also determines the locations of thermal hotspots 208 based on the temperature gradient between various combinations of two or more of sensors 116, for example, by extrapolating the gradient. In one or more embodiments, system manager 112 determines the locations of one or more thermal hotspots on the same piece of silicon, e.g., the same hardware die. Alternatively or additionally, system manager 112 determines the locations of one or more thermal hotspots in a three-dimensional or 3D structure or component, such as between different dies in a stacked component, e.g., a Vcache or a stacked memory such as a DRAM. Thus, in one or more variations, the system manager manages the power, frequency, timing, etc. of components 202 and / or other components of system 100 based on the predicted (or estimated) locations and temperatures of the thermal hotspots.

[0051] While thermal sensors are discussed above and below, it should be understood that in variations, system 100 includes additional or different types of sensors. In such variations, system manager 112 is configured to determine (e.g., using one or more algorithms) differences between the data generated by such other types of sensors, add corrections to the sensor data generated by at least one of the sensors, and manage one or more of the components based on the computationally corrected data rather than using the raw sensor data.

[0052] FIG. 3 illustrates a procedure in an exemplary embodiment 300 of power management using thermal gradient information.

[0053] Temperature measurements of a component are obtained from two or more sensors of the component (block 302). A temperature of a hot spot of the component is predicted based on the temperature measurements obtained from the two or more sensors of the component (block 304). Operation of the component is adjusted based on the predicted temperature of the hot spot (block 306).

[0054] In one or more embodiments, memory module 104 corresponds to or otherwise includes stacked memory, e.g., DRAM. System 100 can utilize sensors 116 located throughout the 3D memory (e.g., DRAM) and use temperature deltas (e.g., gradients) to determine computationally corrected temperature refreshes, thus improving inter-process communication (IPC) by dynamically increasing (e.g., overclocking) the performance of portions of the stacked memory that can handle the increase.

[0055] High-bandwidth memory (HBM) provides increased bandwidth and memory density, allowing multiple layers (e.g., tiers) of DRAM dies (e.g., 8-12 dies) to be stacked on top of each other with one or more optional logic / memory interface dies. Such memory stacks can be connected to a processing unit (e.g., a CPU and / or GPU) via a silicon interposer, as described in more detail below in connection with FIG. 4. Alternatively or additionally, such memory stacks can be stacked on top of the processing unit (e.g., a CPU and / or GPU). In one or more embodiments, stacking memory stacks on top of a processing unit can provide additional connectivity and performance advantages over connection via a silicon interposer.

[0056] 4 shows a non-limiting example printed circuit board architecture 400 for a high-bandwidth memory system. The illustrated example is an exemplary architecture capable of implementing power management using thermal gradient information. Indeed, power management using thermal gradient information can be implemented using a variety of other architectures that include one or more of the components of the exemplary architecture without departing from the spirit or scope of the described technology.

[0057] The illustrated example 400 includes a printed circuit board 402, shown in this case as a multi-layer printed circuit board. In one example, the printed circuit board 402 is used to implement a graphics card. It should be understood that the printed circuit board 402 may be used to implement other computing systems, such as central processing units (CPUs), graphics processing units (GPUs), field programmable gate arrays (FPGAs), accelerated processing units (APUs), and digital signal processors (DSPs), to name a few, without departing from the spirit or scope of the described technology.

[0058] In the illustrated example 400, the layers of the printed circuit board 402 also include a package substrate 404, a silicon interposer 406, a processor chip 408, a memory die 410 (e.g., a DRAM die), and a controller die 412 (e.g., a high-bandwidth memory (HBM) controller die). The illustrated example 400 also shows a plurality of solder balls 414 between the various layers. Here, the example 400 shows the printed circuit board 402 as a first layer and the package substrate 404 as a second layer, with a first plurality of solder balls 414 disposed between the printed circuit board 402 and the package substrate 404. In one or more embodiments, this arrangement is formed by depositing the first plurality of solder balls 414 between the printed circuit board 402 and the package substrate 404. Additionally, the example 400 shows the silicon interposer 406 as a third layer, with a second plurality of solder balls 414 disposed between the package substrate 404 and the silicon interposer 406. In this example 400, the processor chip 408 and the controller die 412 are shown on a fourth layer, with a third plurality of solder balls 414 deposited between the silicon interposer 406 and the processor chip 408, and a fourth plurality of solder balls 414 deposited between the silicon interposer 406 and the controller die 412. In this example, the memory die 410 forms an additional layer (e.g., a fifth layer) disposed "above" the controller die 412. The illustrated example 400 also shows through-silicon vias 416 within each of the memory die 410 and within the controller die 412, such as for connecting these various components.

[0059] It should be understood that the system for power management using thermal gradient information may be implemented using different architectures in one or more variations without departing from the spirit or scope of the described techniques. For example, any of the components described above (e.g., printed circuit board 402, package substrate 404, silicon interposer 406, processor chip 408, memory die 410 (e.g., DRAM die), and controller die 412 (e.g., high-bandwidth memory (HBM) controller die)) may be arranged in different positions within a stack, side-by-side, or combinations thereof in accordance with the described techniques. Alternatively or additionally, the components may be configured differently than illustrated; for example, memory die 410 may include only a single die in one or more variations, the architecture may include one or more processor chips 408, etc. In at least one variation, one or more of the described components are not included in the architecture for implementing power management using thermal gradient information in accordance with the described techniques.

[0060] In this example 400, the processor chip 408 is shown to include a logic engine 418, a first controller 420, and a second controller 422. In variations, the processor chip 408 includes more, different, or fewer components without departing from the spirit or scope of the described technology. In one or more embodiments, such as a graphics card implementation, the logic engine 418 is configured as a three-dimensional (3D) engine. Alternatively or additionally, the logic engine 418 is configured to perform different logic operations, e.g., digital signal processing, machine learning-based operations, etc. In one or more embodiments, the first controller 420 corresponds to a display controller. Alternatively or additionally, the first controller 420 is configured to control different components, e.g., any input / output components. In one or more embodiments, the second controller 422 is configured to control memory, which in this example 400 includes a controller die 412 (e.g., a high-bandwidth memory controller die) and a memory die 410 (e.g., a DRAM die). Thus, one or more of second controller 422 and / or controller die 412, in one or more embodiments, corresponds to controller 108. With this in mind, in one or more embodiments, memory die 410 corresponds to memory 110.

[0061] The illustrated example 400 also includes multiple data links 424. In one or more embodiments, the data links 424 are configured as 1024 data links, used in connection with a high-bandwidth memory stack, and / or have a speed of 500 megahertz (MHz). In one or more variations, such data links are configured differently. Here, the data links 424 are shown linking memory (e.g., the controller die 412 and the memory die 410) to the processor chip 408, e.g., to interface with the second controller 422. In accordance with the described techniques, the data links 424 can be used to link various components of the system.

[0062] In one or more embodiments, one or more of the solder balls 414 and / or various other components (not shown), such as one or more of the solder balls 414 disposed between the printed circuit board 402 and the package substrate 404, are operable to implement various functions of the system, such as implementing a Peripheral Component Interconnect Express (PCIe), providing electrical current, and acting as a computing component (e.g., display) connector, to name a few.

[0063] It should be understood that many variations are possible based on the disclosure herein, and although features and elements are described above in particular combinations, each feature or element can be used alone without the other features and elements, or in various combinations with or without the other features and elements.

[0064] The various functional units illustrated in the figures and / or described herein (including, where appropriate, memory 110, controller 108, and core 106) may be implemented in any of a variety of different ways, such as hardware circuits, software or firmware running on a programmable processor, or any combination of two or more of hardware, software, and firmware. The provided methods may be performed in any of a variety of devices, such as a general-purpose computer, a processor, or a processor core. Suitable processors include, by way of example only, a general-purpose processor, a special-purpose processor, a conventional processor, a digital signal processor (DSP), a graphics processing unit (GPU), a parallel-accelerated processor, multiple microprocessors, one or more microprocessors associated with a DSP core, a controller, a microcontroller, an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) circuit, any other type of integrated circuit (IC), and / or a state machine.

[0065] In one or more embodiments, the methods and procedures provided herein are implemented in a computer program, software, or firmware embodied in a non-transitory computer-readable storage medium for execution by a general-purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random-access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs).

Claims

1. 1. A system comprising: a processor; a first thermal sensor disposed in a first portion of the processor; a second thermal sensor disposed in a second portion of the processor; a system manager; The system manager: obtaining a first temperature measurement from the first thermal sensor and a second temperature measurement from the second thermal sensor; predicting a temperature of a hot spot on the processor based on the first temperature measurement and the second temperature measurement; adjusting one or more settings of the processor based on the predicted temperature of the hot spot; configured to: system.

2. the predicted temperature of the hot spot is greater than the first temperature measurement and the second temperature measurement; The system of claim 1.

3. the hot spot is located in a portion of the processor different from a location where the first thermal sensor and the second thermal sensor are located; The system of claim 1.

4. The system manager: determining a temperature delta between the first temperature measurement and the second temperature measurement; determining a slope of the temperature delta; predicting the temperature of the hot spot based on the slope of the temperature delta; and predicting the temperature of the hot spot by The system of claim 1.

5. the first thermal sensor and the second thermal sensor are disposed on a first portion and a second portion of a core of the processor; The system of claim 1.

6. the system manager is configured to adjust one or more settings of the core to keep a temperature reading of the first thermal sensor within a threshold value of a temperature reading of the second thermal sensor. The system of claim 5.

7. the first thermal sensor is located on a first core of the processor, and the second thermal sensor is located on a second core of the processor; The system of claim 1.

8. the system manager is configured to adjust one or more settings of at least one of the first core or the second core to keep a temperature reading of the first thermal sensor within a threshold temperature reading of the second thermal sensor. The system of claim 7.

9. the system is a system-on-chip; The system of claim 1.

10. 1. A method comprising: obtaining temperature measurements of the component from two or more sensors in the component; predicting a temperature of a hot spot of the component based on temperature measurements obtained from the two or more sensors of the component; and adjusting operation of the component based on the predicted temperature of the hot spot. method.

11. the hot spots are located on different parts of the component on which the two or more sensors are disposed; The method of claim 10.

12. the predicted temperature of the hot spot is higher than the acquired temperature measurement; The method of claim 10.

13. the component comprises a processor; The method of claim 10.

14. the component comprises a memory; The method of claim 10.

15. The predicting step comprises: determining a temperature delta between temperature measurements obtained from the two or more sensors of the component; determining a gradient of a temperature delta between the two or more sensors of the component; and predicting a temperature of a hot spot of the component based on a gradient of a temperature delta between the two or more sensors of the component. The method of claim 10.

Images