Arithmetic device and arithmetic method

Abstract

To provide a technique for suppressing increase in delay and power consumption by reducing the number of optical-electrical conversions in an arithmetic unit having an optical circuit.SOLUTION: The arithmetic unit includes a first optical circuit for receiving an electric signal converted from an optical signal and performing a nonlinear operation, and a second optical circuit for receiving an optical signal output from the first optical circuit and performing a linear operation.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a technology for implementing a loop architecture type optical circuit by combining it with an electrical circuit. [Background technology]

[0002] Conventionally, when implementing cryptographic operations in hardware using electrical circuits, some of the operations that make up the cryptographic algorithm are implemented using combinational circuits, and a loop architecture type implementation is used in which these operations are repeatedly performed. This type of implementation has made it possible to achieve small size and high speed.

[0003] In particular, block ciphers, which are a type of symmetric key ciphers, perform calculations by repeating round functions, and therefore, calculations for one round are implemented as a combinational circuit (Non-Patent Document 1).

[0004] When implementing this loop architecture using optical circuits, there are currently no optical registers capable of meeting the capacity of the registers used in cryptographic operations, so it is necessary to use electrical registers to store the intermediate values ​​of the optical cryptographic operations. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] Security of Cryptographic Hardware, Kazuo Sakiyama, Ken Sugawara, and Yang Li, Corona Publishing, 2019, 18 pages [Non-patent document 2] A. Bogdanov, LR Knudsen, G. Leander, C. Paar, A. Poschmann, MJB Robshaw, Y. Seurin, C. Vikkelsoe, PRESENT: An Ultra-Lightweight Block Cipher, Cryptographic Hardware and Embedded Systems - CHES 2007, pp 450-466, 2017. Summary of the Invention [Problem to be solved by the invention]

[0006] Regarding block ciphers, for example, in the lightweight cipher PRESENT, one block is defined as an operation consisting of "exclusive OR of key and data, nonlinear function (sBoxLayer), and linear function (pLayer)" (Non-Patent Document 2).

[0007] However, when the configuration for performing the above calculations is implemented using optical circuits, the number of optical-electrical conversions (or electrical-optical conversions) increases, which poses a problem of increased delay and power consumption.

[0008] The present invention has been made in consideration of the above points, and aims to provide a technology for reducing the number of optical-electrical conversions and suppressing increases in delay and power consumption in a computing device having an optical circuit. [Means for solving the problem]

[0009] According to the disclosed technology, a first optical circuit that performs nonlinear calculations using an electrical signal converted from an optical signal as an input; a second optical circuit that performs linear operations using the optical signal output from the first optical circuit as an input; A computing device is provided, comprising: [Effects of the Invention]

[0010] The disclosed technology provides a technology for reducing the number of optical-electrical conversions and suppressing increases in delay and power consumption in a computing device having optical circuits. This becomes possible. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram for explaining a problem. [Figure 2] FIG. 2 is a configuration diagram of an encryption circuit according to the first embodiment. [Figure 3] FIG. 2 is a configuration diagram of an optical encryption circuit according to the first embodiment. [Figure 4] FIG. 2 is a diagram illustrating the configuration of a 4-bit S-box according to the first embodiment. [Figure 5] FIG. 10 is a diagram illustrating an example of one round of calculation in the first embodiment. [Figure 6] FIG. 10 is a configuration diagram of a decoding circuit according to a second embodiment. [Figure 7] FIG. 10 is a configuration diagram of an optical decoding circuit according to a second embodiment. [Figure 8] FIG. 10 is a diagram illustrating an example of one round of calculation in the second embodiment. [Figure 9] FIG. 10 is a configuration diagram of an optical encryption circuit according to a third embodiment. [Figure 10] FIG. 11 is a diagram illustrating an example of one round of calculation in the third embodiment. [Figure 11] FIG. 10 is a configuration diagram of an optical decoding circuit according to a fourth embodiment. [Figure 12] FIG. 13 is a diagram illustrating an example of one round of calculation in the fourth embodiment. [Figure 13] FIG. 10 is a configuration diagram of an encryption circuit according to a fifth embodiment. [Figure 14] FIG. 10 is a diagram illustrating the configuration of an electric circuit in a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, an embodiment of the present invention (the present embodiment) will be described with reference to the drawings. The embodiment described below is merely an example, and the embodiment to which the present invention is applied is not limited to the following embodiment.

[0013] In the following, the conventional technology and its problems will be described in more detail with reference to the drawings, and then the technology according to this embodiment will be described.

[0014] (Regarding conventional technology and its issues) As mentioned above, with regard to block ciphers, for example, in the lightweight cipher PRESENT, one block is defined as an operation consisting of "exclusive OR of key and data, nonlinear function (sBoxLayer), and linear function (pLayer)" (Non-Patent Document 2).

[0015] In this case, when performing the above calculations using an optical circuit, if a 4-bit S-box (part of the sBoxLayer) is executed in one-hot encoding format and other calculations are performed using bit operations, the calculation processing configuration will be as shown in Figure 1. Figure 1 shows the functional configuration of the data calculation unit that performs the PRESENT calculation. Note that the data calculation unit may also be called a "data calculation device" or "calculation device." The data calculation unit shown in Figure 1 includes an optical-electrical conversion unit 1, a selector 2, a data register 3, an electrical-optical conversion unit 4, an exclusive OR calculation unit 5, an optical-electrical conversion unit 6, a 4-bit S-box 7, and a pLayer 8.

[0016] Here, PRESENT has a block length of 64 bits, but for simplicity, it is expressed in 4 bits in the data calculation unit shown in Fig. 1. In the configuration shown in Fig. 1, the optical-electrical conversion unit 1 (a processing unit that performs the process of converting optical signals into electrical signals) is a functional unit required to store the intermediate value, which is the calculation result of one round, in the data register 3 (a functional unit composed of an electrical circuit).

[0017] Furthermore, when a Mach-Zehnder modulator (MZM) is used to convert from bit representation to one-hot encoding representation, the input to the MZM is only an electrical signal, so an optical-electrical converter 6 is required. Furthermore, the exclusive-OR calculation unit 5 performs the exclusive-OR calculation of the key and data optically, so an electrical-optical converter 4 is required in the preceding stage.

[0018] Generally, it is thought that the process of converting an optical signal into an electrical signal results in large delays and power consumption. Therefore, the processing by the data calculation unit shown in Figure 1, which is assumed from the prior art (Non-Patent Document 2), involves two optical-electrical conversions and one electrical-optical conversion in one round of calculation, which poses the problem of increased delays and power consumption. Block ciphers such as PRESENT repeatedly perform one round of calculation (31 rounds in the example of PRESENT), which poses the problem of the number of optical-electrical conversions (or electrical-optical conversions) increasing with the number of iterations.

[0019] (Outline of the embodiment) In order to solve the above problems, in this embodiment, the data operation unit that performs block cipher operations is implemented in the order of nonlinear operation and linear operation of the cipher, thereby reducing the amount of optical-electrical conversion processing when realizing a loop architecture implementation using optical circuits.

[0020] More specifically, the optical-electrical conversion process is performed only once per round when storing data in the data register. In this embodiment, the encryption circuit and the decryption circuit have the same circuit configuration, so that only nonlinear operations are performed in the final round, and the output result is used as the operation result.

[0021] The technology according to this embodiment can be applied to general-purpose operations such as deep learning operations implemented in a loop architecture, regardless of encryption / decryption operations. In addition, the technology according to this embodiment can eliminate the optical-electrical conversion unit by using an optical memory instead of an electric data register, and the input to the nonlinear function can be an optical signal.

[0022] Hereinafter, a more specific configuration of the data calculation unit (calculation device) will be described using Examples 1 to 5.

[0023] Example 1 FIG. 2 shows an example of the configuration of an encryption circuit as a data calculation unit in Example 1, in which a block cipher (specifically, PRESENT) is implemented by combining an optical circuit and a register using an electrical circuit. In this encryption circuit, an optical-electrical conversion unit 1, a selector 2, a data register 3, a 4-bit S-box 7 (part of sBoxLayer), a pLayer 8, and an exclusive-OR calculation unit 5 are arranged as shown in FIG. 2. With this configuration, calculations are performed in the order of sBoxLayer, pLayer, and exclusive-OR with the key, so that only one optical-electrical conversion is required. In other words, the electrical-optical conversion unit 4 and the optical-electrical conversion unit 6 shown in FIG. 1 are unnecessary. The 4-bit S-box 7, pLayer 8, and exclusive-OR calculation unit 5 may be referred to as the first optical circuit, the second optical circuit, and the third optical circuit, respectively.

[0024] FIG. 3 shows an example of a circuit configuration (called an optical encryption circuit) when one round of "optical calculation by the 4-bit S-box 7, optical calculation by the pLayer 8, and exclusive OR calculation of the key and data by the exclusive OR calculation unit 5 shown in FIG. 2" is implemented by an optical circuit. The example configuration in FIG. 3 uses an implementation configuration that modifies the PRESENT encryption algorithm. In this embodiment, encoding is performed by intensity modulation. Specifically, when the optical intensity is higher than a certain threshold, it is encoded as bit 1, and when the optical intensity is 0 or lower than the certain threshold, it is encoded as bit 0.

[0025] Fig. 4 shows the configuration of only the 4-bit S-box 7 (S-box circuit) shown in Fig. 3. As shown in Fig. 4, the 4-bit S-box 7 includes a decode circuit 71, a wiring conversion unit 72 that depends on the S-box, and an encode circuit 73.

[0026] As shown in Figure 4, in the 4-bit S-box 7, by implementing the decoding circuit 71 with MZM, 16 combinations (=2 4 ) optical path. The MZM has the function of a switch that switches the direction of the output light by turning the voltage of the input electrical signal on and off.

[0027] Based on the 4-bit electrical signal input (x0, x1, x2, x3), the optical path is switched by the MZM, and only one path out of 16 has a strong optical intensity. After that, the wiring conversion unit 72 performs wiring conversion based on the 4-bit S-box conversion table of PRRSENT.

[0028] The final stage, the encoding circuit 73, is implemented using one stage of Y-branching elements and three stages of Y-merging elements. As shown in Figure 4, the encoding circuit 73 converts the 16 optical wiring patterns back into a 4-bit value representation (actually, an 8-bit representation, since the complement is also included).

[0029] Here, the Y-branching element is an element that splits the light intensity into two parts, ideally 50% each, and the Y-combining element is an element that combines light. Here, in the encoding circuit 73, due to the nature of one-hot encoding, one of the two inputs to the Y-combining is always in a state where there is no light (corresponding to bit 0).

[0030] The optical encryption circuit configuration example shown in Figure 3 uses a wiring conversion for the 4-bit pLayer8, which is different from the pLayer of PRESENT. The wiring connection for this 4-bit pLayer8 can be arbitrarily wired. In addition, since the output of the encoding circuit 73 of the 4-bit S-box 7 has a dual rail logic structure using complements, the output of the encoding circuit 73 (input of pLayer8) consists of eight optical wirings.

[0031] In the final stage of the configuration shown in Fig. 3, the exclusive-OR operation unit 5 performs an exclusive-OR operation on the key and data. In the configuration shown in Fig. 3, the exclusive-OR operation unit 5 has four MZMs. In the processing by the exclusive-OR operation unit 5, the optical path of each MZM is switched based on the value of the round key (1 bit), and the operation result of one round is output.

[0032] In the configuration shown in Figure 3, the round key is a 4-bit key value, but the 4-bit key value may be, for example, the upper or lower 4-bit value of a 64-bit round key obtained by the PRESENT key generation algorithm.

[0033] As shown in Figure 2, based on the output result of the first round, the optical-electrical conversion unit 1 performs optical-electrical conversion (receiving light intensity), stores the data in the data register 3, and uses the data as the 4-bit output for the next round.

[0034] As described above, in this embodiment, the encryption circuit is configured to be equivalent to the decryption circuit. Therefore, in the encryption circuit of Example 1 shown in Fig. 2, the output of the 31st round (i.e., ciphertext) is the output result of the 4-bit S-box 7. Note that if the encryption circuit is not configured to be equivalent to the decryption circuit, the output result of which function is used as the ciphertext is not limited to this example.

[0035] Figure 5 shows an example of one round of operation in the encryption circuit. In the example in Figure 5, the input to the 4-bit S-box 7 is 0x7 ((x0, x1, x2, x3) = (0111)), and the round key is 0x9 ((k 0,i ,k 1,i ,k 2,i ,k 3,i )=(1001)).

[0036] At this time, light passes through the path shown by the thick line. Finally, the output light is converted into a bit value by optical-electrical conversion unit 1, resulting in the calculation result of one round, 0x2 (0010). In this way, it is possible to achieve loop architecture implementation with one optical-electrical conversion process for a 4-bit value.

[0037] Example 2 Next, an example of the configuration of a decoding circuit will be described as Example 2. As a data calculation unit in Example 2, Fig. 6 shows an example of the configuration of a PRESENT decoding circuit that combines optical and electrical circuits. Also, Fig. 7 shows an example of the configuration of one round of an optical decoding circuit. In the decoding circuit of Example 2, an optical-electrical conversion unit 1, a selector 2, a data register 3, a 4-bit Inv S-box 9, an Inv pLayer 10, and an exclusive OR calculation unit 5 are arranged as shown in Fig. 6. Note that the 4-bit Inv S-box 9, the Inv pLayer 10, and the exclusive OR calculation unit 5 may also be called the first optical circuit, the second optical circuit, and the third optical circuit, respectively.

[0038] The decryption circuit shown in Figure 6 is basically equivalent to the encryption circuit shown in Figure 2, but differs from the encryption circuit shown in Figure 2 in that a transformation based on the inverse function of the S-box (Inv S-box) is performed, and the value of the round key (4 bits) is the value obtained by performing the inverse function of the P function (Inv player).

[0039] In the second embodiment, the 4-bit inverse function of PRESENT is used as the 4-bit Inv S-box9. Furthermore, the round key used in the 30th round of the encryption circuit is used as the round key in the first round of the decryption circuit. The same applies thereafter. For example, the round key used in the 29th round of the encryption circuit is used in the second round of the decryption circuit. The reason for using the value obtained by performing the inverse transformation of the P function as the round key value (4 bits) here is to make the decryption circuit have the same circuit configuration as the encryption circuit. As with the encryption circuit, the decryption circuit also calculates only the inverse function of the S-box in the 31st round, and outputs the result (plaintext).

[0040] 8 shows an example of one round of calculations in the decryption circuit in the second embodiment. In the example of FIG. 8, the input to the 4-bit Inv S-box 9 is 0xb((x0, x1, x2, x3)=(1011)), and the value obtained by performing the inverse function of the P function of the round key is 0x5((k' 0,i ,k' 1,i ,k' 2,i ,k' 3,i) = (0101)). At this time, light passes through the path shown by the thick line. Finally, the output light is converted into a bit value by optical-electrical conversion unit 1, and the calculation result of one round, 0x9 (1001), is obtained. This round calculation is repeated 30 times, and in the final round (31st round), the output of the inverse function of the S-box (4bit Inv S-box9) is used as the calculation output, thereby obtaining the decryption result.

[0041] As described above, it is possible to realize a cryptographic loop architecture implementation in the decryption circuit by performing a single optical-electrical conversion with a configuration equivalent to that of the encryption circuit.

[0042] Example 3 In the third and fourth embodiments, embodiments for reducing the number of wires will be described. First, the third embodiment will be described. The overall configuration of the encryption circuit in the third embodiment is basically the same as the configuration shown in FIG.

[0043] Fig. 9 shows an example of a circuit configuration in which the number of wires in the optical encryption circuit shown in Fig. 3 is reduced. As shown in Fig. 9, in the third embodiment, the number of wires and the number of elements (Y-branch and Y-join) in the 4-bit S-box 7 are reduced compared to the first embodiment, and the exclusive-OR operation unit 5 that performs the exclusive-OR operation on the key and data is realized by a Y-join element. The key value in the third embodiment is an optical signal.

[0044] In the configuration of the third embodiment, a phase shifter is provided immediately before the Y junction in the exclusive OR operation of the key and data. j,i The phase shifter value must be set to a fixed value so that the phase is opposite to that of the optical signal (i=0,...,29,j=0,1,2,3). As mentioned above, the key value in this case is an optical signal.

[0045] In addition, when light waves pass through an MZM in the cross direction, the phase generally shifts by π / 2 (+π / 2 or -π / 2). Therefore, in order to make the phase equivalent on the path for each bit, in the four-stage MZM of the 4-bit S-box7, the MZM must be implemented so that the phase of the output result after four stages is equivalent on all 16 paths.

[0046] As a method for this, for example, a phase shifter set to -π / 2 (when the phase shifts by π / 2 when light passes through the cross) can be installed in the upper arm of each MZM output (a total of 15 MZMs). Alternatively, a phase shifter can be installed to adjust the phase difference that occurs only in the MZMs (8 units) after the fourth stage.

[0047] By implementing it as described above, for example, when a data bit is light with an intensity corresponding to "1" and the key value is "1", two lights with a phase difference of π are combined by Y-combining, which results in them canceling each other out and resulting in a result equivalent to a bit "0". Therefore, it is possible to perform a pseudo-exclusive OR operation.

[0048] In the configuration shown in Fig. 9, a 4-bit input signal (electrical) is converted into 16 values, and then converted back into a 4-bit value by an encoding circuit that uses multiple stages of Y branching and Y merging. However, unlike the configuration shown in Fig. 3, Example 3 does not use complements and is implemented using four optical wirings (corresponding to 4-bit calculations).

[0049] 10 shows an example of the calculation in FIG. 9. In the calculation example shown in FIG. 10, the input to the 4-bit S-box 7 is 0x7((x0, x1, x2, x3)=(0111)), and the round key is 0x9((k 0,i ,k 1,i ,k 2,i ,k 3,i ) = (1001)). At this time, the light passes through the path shown by the thick line. Finally, the output light is converted into a bit value by optical-electrical conversion, and the calculation result of one round, 0x2 (0010), is obtained. By calculating this round multiple times, the encryption result can be obtained in the same way as in Example 1 (Figure 5).

[0050] Example 4 Next, a description will be given of Example 4. The overall configuration of the decoding circuit in Example 4 is basically the same as the configuration shown in FIG.

[0051] Fig. 11 shows an example of a circuit configuration in which the number of wires in the optical decryption circuit shown in Fig. 7 is reduced. As in the third embodiment in which the number of wires in the optical encryption circuit is reduced, the fourth embodiment also reduces the number of wires and elements (Y-branch and Y-join) in the 4-bit Inv S-box 9, and implements the exclusive-OR operation unit 5 that performs the exclusive-OR operation on the key and data using a Y-join element. The one-round implementation shown in Fig. 11 is repeated 30 times, and the output of the 4-bit Inv S-box 9 in the final round (31st round) is taken as the decryption result.

[0052] Fig. 12 shows an example of the operation of the optical decoding circuit in Fig. 11. In the example of operation in Fig. 12, the input to the 4-bit Inv S-box 9 is 0xb((x0, x1, x2, x3) = (1011)), and the result of operating the inverse function of the P function on the round key is 0x5((k' 0,i ,k' 1,i ,k' 2,i ,k' 3,i ) = (0101)). At this time, light passes through the path shown by the thick line. In the exclusive OR operation of the key and data by Y merging, when both have optical intensity, the phases are opposite and the light waves cancel each other out, resulting in a state where there is no light (corresponding to bit 0) (second most significant bit).

[0053] Finally, the output light is converted into a bit value by optical-electrical conversion, resulting in the first round's calculation result, 0x9 (1001). This round is calculated 30 times, and in the 31st round, the decoded result is obtained by using the output of the inverse function of 4bit Inv S-box9 as the calculation result.

[0054] Example 5 In the optical encryption circuit configuration shown in Fig. 3 in Example 1 and the optical decryption circuit configuration shown in Fig. 7 in Example 2, an MZM was used to perform calculations when converting a 4-bit electrical signal into 16 different optical wiring patterns. The calculation method is not limited to the method using an MZM, and Example 5 uses an implementation method in which calculations for conversion into 16 different optical wiring patterns are performed by an electrical circuit and the results are added to the output to the laser. Note that in Example 5 as well, the overall configuration of the encryption circuit / decryption circuit is the same as the configurations shown in Figs. 2 / 6.

[0055] Fig. 13 shows an example of the configuration of the encryption circuit in Example 5. As shown in Fig. 13, instead of the MZM, an electric circuit 20 that converts 4 bits to 16 wirings and lasers 30 (16 lasers) are provided. In this configuration, the lasers 30 may be directly modulated and implemented as a laser device outside the optical circuit, or may be implemented as an on-chip laser within the optical circuit.

[0056] 14 shows an example of the configuration of an electric circuit 20 that converts a 4-bit electric signal into 16 different wirings. The configuration shown in FIG. 14 is generally called a decoder (reference: "Takeshi Asakawa, Design of Logic Circuits, Corona Publishing, pp. 16-17, 2007 (ISBN978-4-339-00788-6)"), and converts 16 wirings (y0, ..., y3) according to the value of a 4-bit electric signal (x0, ..., x3). 15 ), only one of the 16 possible values ​​will be "1". Only one laser corresponding to that value will emit light, and this will become the input to the Y branch in the configuration of Figure 13.

[0057] The configuration shown in FIG. 13 can also be applied to the decoding circuit of FIG. 7 and the circuits in FIGS. 9 and 11 in which wiring has been reduced.

[0058] (Effects of the Technology According to the Embodiments) According to the technology of this embodiment, when an encryption circuit or a decryption circuit is realized using optical circuits and a loop architecture is implemented, the number of optical-electrical conversions (or electrical-optical conversions) can be reduced. This makes it possible to suppress increases in delay and power consumption. The technology of this embodiment can be generally applied to systems that realize loop architecture implementation using optical circuits.

[0059] (Summary of the technology according to the embodiment) As described above, in the technology according to the present embodiment, when performing calculations using an optical circuit, the input of the optical circuit is an electrical signal and the output is an optical signal, thereby reducing the number of optical-electrical conversions, suppressing delays and power consumption, and improving calculation performance.

[0060] More specifically, when applying optical circuits to cryptographic operations, implementing the optical circuits in the order of nonlinear operations and then linear operations can reduce the amount of optical-electrical conversion processing when implementing a loop architecture with optical circuits. Also, to ensure that the encryption and decryption circuits have the same circuit configuration, only nonlinear operations are performed in the final round, and the output is used as the calculation result.

[0061] The following additional notes are provided regarding the above-described embodiments.

[0062] <Additional Notes> (Additional note 1) a first optical circuit that performs a nonlinear operation using an electrical signal converted from an optical signal as an input; a second optical circuit that performs linear operations using the optical signal output from the first optical circuit as an input; A computing device comprising: (Additional note 2) a third optical circuit that receives the optical signal output from the second optical circuit and a key value and performs an exclusive OR operation on the optical signal and the key value; Item 1. The arithmetic device according to item 1, further comprising: (Additional note 3) an optical-electrical converter that converts the optical signal output from the third optical circuit into the electrical signal used as input to the first optical circuit; 3. The arithmetic device according to claim 2, further comprising: (Additional note 4) A computing method in a computing device including a first optical circuit and a second optical circuit, a step in which the first optical circuit performs a nonlinear operation using an electrical signal converted from an optical signal as an input; a step in which the second optical circuit performs a linear operation using the optical signal output from the first optical circuit as an input; A calculation method comprising:

[0063] Although the present embodiment has been described above, the present invention is not limited to such a specific embodiment, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims. [Explanation of symbols]

[0064] 1 Optical-electrical conversion section 2. Selectors 3 Data Register 4 Electrical-optical conversion section 5 Exclusive OR operation section 6 Optical-electrical conversion section 7 4bit S-box 8 pLayer 9 4bit Inv S-box 10 Inv pLayer 71 Decoding circuit 72 Wiring conversion section 73 Encoding Circuit

Claims

1. a first optical circuit that performs a nonlinear operation using an electrical signal converted from an optical signal as an input; a second optical circuit that performs linear calculations using the optical signal output from the first optical circuit as an input; A computing device comprising:

2. a third optical circuit that receives the optical signal output from the second optical circuit and a key value as input and performs an exclusive OR operation on the optical signal and the key value; The computing device of claim 1 further comprising:

3. an optical-electrical converter that converts the optical signal output from the third optical circuit into the electrical signal used as input to the first optical circuit; The computing device of claim 2 further comprising:

4. A computing method in a computing device including a first optical circuit and a second optical circuit, a step in which the first optical circuit performs a nonlinear operation using an electrical signal converted from an optical signal as an input; a step in which the second optical circuit performs a linear operation using the optical signal output from the first optical circuit as an input; A calculation method comprising:

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