Electronic device

Abstract

To provide an electronic apparatus capable of suppressing occurrence of a short circuit between a second electrode and a first electrode on the outermost periphery.SOLUTION: An electronic apparatus includes a substrate, a plurality of optical diodes each having a first electrode, a first carrier transport layer, an active layer, a second carrier transport layer, and a second electrode and provided in a detection region of the substrate, a third electrode to which a reference potential is supplied, a conductive wiring, and a connection terminal that connects the conductive wiring and the second electrode. The second electrode is provided across the plurality of optical diodes, and the second electrode has a second electrode side wall portion covering a side surface of an optical diode layer at an endmost portion of the plurality of optical diodes. The third electrode is disposed between the first electrode provided in the endmost optical diode and the second electrode side wall portion. The second electrode is electrically connected to the conductive wiring. The conductive wire is routed to a peripheral region outside the third electrode in planar view, and extends in parallel with the third electrode along one direction in a plane parallel with the substrate. The connection terminal is in the same layer as the third electrode.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present disclosure relates to electronic devices. [Background technology]

[0002] Optical sensors capable of detecting fingerprint patterns and vein patterns are known (see, for example, Patent Document 1). Such optical sensors have multiple photodiodes that use an organic semiconductor material as an active layer. As described in Patent Document 2, the photodiodes are disposed between a lower electrode and an upper electrode, and for example, the lower electrode, electron transport layer, active layer, hole transport layer, and upper electrode are stacked in this order. The electron transport layer or hole transport layer is also called a buffer layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-32005 [Patent Document 2] International Publication No. 2020 / 188959 Summary of the Invention [Problem to be solved by the invention]

[0004] The upper electrode is connected to wiring in a frame region around the detection region. The upper electrode is laminated on the side surfaces of the active layer and the buffer layer in the frame region, and leakage current may flow between the upper electrode and the outermost lower electrode.

[0005] An object of the present disclosure is to provide an electronic device that can prevent a short circuit from occurring between a second electrode and an outermost first electrode. [Means for solving the problem]

[0006] An electronic device according to one embodiment of the present disclosure includes a substrate, a plurality of optical diodes each having a first electrode, a first carrier transport layer, an active layer, a second carrier transport layer, and a second electrode, and disposed in a detection region of the substrate, a third electrode to which a reference potential is supplied, conductive wiring, and a connection terminal connecting the conductive wiring to the second electrode, wherein the second electrode is disposed across the plurality of optical diodes, the second electrode has a second electrode sidewall portion covering a side surface of the optical diode at the outermost position among the plurality of optical diodes, the third electrode is disposed between the first electrode and the second electrode sidewall portion disposed on the optical diode at the outermost position, the second electrode is electrically connected to the conductive wiring, the conductive wiring is routed to a peripheral region outside the third electrode in a planar view, and extends parallel to the third electrode along one direction in a plane parallel to the substrate, and the connection terminal is in the same layer as the third electrode. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic diagram showing a detection device according to a first embodiment. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of the detection device according to the first embodiment. [Figure 3] FIG. 3 is a circuit diagram showing the detection device. [Figure 4] FIG. 4 is a circuit diagram showing a plurality of detection elements. [Figure 5] FIG. 5 is a plan view showing the detection device according to the first embodiment. [Figure 6] FIG. 6 is a plan view schematically showing the detection device according to the first embodiment. [Figure 7] FIG. 7 is a plan view schematically showing the first electrode and the transistor of the detection device according to the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII' in FIG. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX' in FIG. [Figure 10] FIG. 10 is a plan view showing a detection device according to the second embodiment. [Figure 11] FIG. 11 is a plan view showing a detection device according to the third embodiment.

[0008] Modes (embodiments) for carrying out the present disclosure will be described in detail with reference to the drawings. The present disclosure is not limited to the contents described in the following embodiments. Furthermore, the components described below include those that can be easily imagined by a person skilled in the art and those that are substantially identical. Furthermore, the components described below can be combined as appropriate. Note that the disclosure is merely an example, and any appropriate modifications that a person skilled in the art can easily conceive while maintaining the gist of the present disclosure are naturally included within the scope of the present disclosure. Furthermore, for clarity of explanation, the drawings may schematically depict the width, thickness, shape, etc. of each part compared to the actual embodiment. However, these are merely examples and are not intended to limit the interpretation of the present disclosure. Furthermore, in this disclosure and each figure, elements similar to those described above with reference to the previous figures may be designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0009] In the present embodiment and claims, when expressing an aspect in which another structure is placed on top of another structure, the term "on top" is used, unless otherwise specified, to include both a case in which another structure is placed directly on top of a certain structure so as to be in contact with the certain structure, and a case in which another structure is placed above a certain structure via yet another structure.

[0010] (First embodiment) Fig. 1 is a schematic diagram showing a detection device according to a first embodiment. As shown in Fig. 1, the detection device 1 includes a substrate 21, a sensor unit 10, a gate line driving circuit 15, a signal line selection circuit 16, a detection circuit 48, a control circuit 122, a power supply circuit 123, a first light source substrate 51, a second light source substrate 52, a first light source 53, and a second light source 54. The first light source substrate 51 is provided with a plurality of first light sources 53. The second light source substrate 52 is provided with a plurality of second light sources 54.

[0011] A control board 121 is electrically connected to the substrate 21 via a flexible printed circuit board 71. The flexible printed circuit board 71 is, for example, a flexible printed circuit board or a rigid board. The flexible printed circuit board 71 is provided with a detection circuit 48. The control board 121 is provided with a control circuit 122 and a power supply circuit 123. The control circuit 122 is, for example, an FPGA (Field Programmable Gate Array). The control circuit 122 supplies control signals to the sensor unit 10, the gate line driving circuit 15, and the signal line selection circuit 16 to control the detection operation of the sensor unit 10. The control circuit 122 also supplies control signals to the first light source 53 and the second light source 54 to control the lighting or non-lighting of the first light source 53 and the second light source 54. The power supply circuit 123 supplies voltage signals such as a sensor power supply signal VDDSNS (see FIG. 4) to the sensor unit 10, the gate line driving circuit 15, and the signal line selection circuit 16. The power supply circuit 123 also supplies a power supply voltage to the first light source 53 and the second light source 54.

[0012] The substrate 21 has a detection area AA and a peripheral area GA. The detection area AA is an area where a plurality of photodiodes PD (see FIG. 4) of the sensor unit 10 are provided. The peripheral area GA is an area between the periphery of the detection area AA and the outer edge of the substrate 21, where a plurality of photodiodes PD are not provided.

[0013] The gate line driving circuit 15 and the signal line selection circuit 16 are provided in the peripheral area GA. Specifically, the gate line driving circuit 15 is provided in a region of the peripheral area GA extending along the second direction Dy. The signal line selection circuit 16 is provided in a region of the peripheral area GA extending along the first direction Dx, and is provided between the sensor unit 10 and the detection circuit 48.

[0014] In the following description, the first direction Dx is a direction in a plane parallel to the substrate 21. The second direction Dy is a direction in a plane parallel to the substrate 21, and is a direction perpendicular to the first direction Dx. The second direction Dy may intersect with the first direction Dx without being perpendicular thereto. Furthermore, "plan view" refers to the positional relationship when viewed from a direction perpendicular to the substrate 21.

[0015] The plurality of first light sources 53 are provided on the first light source substrate 51 and arranged along the second direction Dy. The plurality of second light sources 54 are provided on the second light source substrate 52 and arranged along the second direction Dy. The first light source substrate 51 and the second light source substrate 52 are electrically connected to the control circuit 122 and the power supply circuit 123 via terminal portions 124 and 125 provided on the control board 121, respectively.

[0016] The plurality of first light sources 53 and the plurality of second light sources 54 may be, for example, inorganic light emitting diodes (LEDs) or organic light emitting diodes (OLEDs). The plurality of first light sources 53 and the plurality of second light sources 54 emit first light and second light of different wavelengths, respectively.

[0017] The first light emitted from the first light source 53 is mainly reflected by the surface of the object to be detected, such as a finger, and enters the sensor unit 10. As a result, the sensor unit 10 can detect a fingerprint by detecting the uneven shape of the surface of the finger or the like. The second light emitted from the second light source 54 is mainly reflected by the inside of the finger or the like or passes through the finger or the like and enters the sensor unit 10. As a result, the sensor unit 10 can detect information about the living body inside the finger or the like. The information about the living body includes, for example, the pulse wave, pulse rate, blood vessel image, etc. of the finger or palm. In other words, the detection device 1 may be configured as a fingerprint detection device that detects fingerprints, or a vein detection device that detects blood vessel patterns such as veins.

[0018] The first light may have a wavelength of 500 nm or more and 600 nm or less, for example, approximately 550 nm, and the second light may have a wavelength of 780 nm or more and 950 nm or less, for example, approximately 850 nm. In this case, the first light is blue or green visible light, and the second light is infrared light. Sensor unit 10 can detect a fingerprint based on the first light emitted from first light source 53. The second light emitted from second light source 54 is reflected from the inside of a detection object such as a finger or transmitted through or absorbed by the finger or the like, and then enters sensor unit 10. This allows sensor unit 10 to detect a pulse wave or a blood vessel image (blood vessel pattern) as information about the inside of a biological body such as a finger.

[0019] Alternatively, the first light may have a wavelength of 600 nm or more and 700 nm or less, for example, about 660 nm, and the second light may have a wavelength of 780 nm or more and 900 nm or less, for example, about 850 nm. In this case, based on the first light emitted from the first light source 53 and the second light emitted from the second light source 54, the sensor unit 10 can detect information about the living body, such as pulse wave, pulse rate, and blood vessel image, as well as blood oxygen saturation. In this way, the detection device 1 has the first light source 53 and multiple second light sources 54, and therefore can detect various pieces of information about the living body by performing detection based on the first light and detection based on the second light.

[0020] The arrangement of the first light source 53 and the second light source 54 shown in FIG. 1 is merely an example and can be changed as appropriate. The detection device 1 is provided with multiple types of light sources (first light source 53 and second light source 54). However, this is not limited to this, and the light source may be of one type. For example, multiple first light sources 53 and multiple second light sources 54 may be arranged on each of the first light source substrate 51 and the second light source substrate 52. Furthermore, the number of light source substrates on which the first light source 53 and the second light source 54 are arranged may be one or three or more. Alternatively, it is sufficient that at least one or more light sources are arranged.

[0021] Fig. 2 is a block diagram showing an example of the configuration of the detection device according to the first embodiment. As shown in Fig. 2, the detection device 1 further includes a detection control unit 11 and a detection unit 40. Some or all of the functions of the detection control unit 11 are included in a control circuit 122. In addition, some or all of the functions of the detection unit 40 other than the detection circuit 48 are included in the control circuit 122.

[0022] The sensor unit 10 has a plurality of photodiodes PD. The photodiodes PD of the sensor unit 10 output electrical signals corresponding to the incident light as detection signals Vdet to the signal line selection circuit 16. The sensor unit 10 also performs detection in accordance with the gate drive signals Vgcl supplied from the gate line drive circuit 15.

[0023] The detection control unit 11 is a circuit that supplies control signals to the gate line driving circuit 15, the signal line selection circuit 16, and the detection unit 40, respectively, and controls their operations. The detection control unit 11 supplies various control signals, such as a start signal STV, a clock signal CK, and a reset signal RST1, to the gate line driving circuit 15. The detection control unit 11 also supplies various control signals, such as a selection signal ASW, to the signal line selection circuit 16. The detection control unit 11 also supplies various control signals to the first light source 53 and the second light source 54, and controls the lighting and non-lighting of each.

[0024] The gate line driving circuit 15 is a circuit that drives multiple gate lines GCL (see FIG. 3) based on various control signals. The gate line driving circuit 15 selects the multiple gate lines GCL sequentially or simultaneously and supplies a gate driving signal Vgcl to the selected gate lines GCL. In this way, the gate line driving circuit 15 selects multiple photodiodes PD connected to the gate lines GCL.

[0025] The signal line selection circuit 16 is a switch circuit that sequentially or simultaneously selects a plurality of signal lines SGL (see FIG. 3). The signal line selection circuit 16 is, for example, a multiplexer. The signal line selection circuit 16 connects the selected signal line SGL to the detection circuit 48 based on a selection signal ASW supplied from the detection control unit 11. As a result, the signal line selection circuit 16 outputs a detection signal Vdet of the photodiode PD to the detection unit 40.

[0026] The detection unit 40 includes a detection circuit 48, a signal processing circuit 44, a coordinate extraction circuit 45, a memory circuit 46, a detection timing control circuit 47, an image processing circuit 49, and an output processing unit 50. Based on a control signal supplied from the detection control unit 11, the detection timing control circuit 47 controls the detection circuit 48, the signal processing circuit 44, the coordinate extraction circuit 45, and the image processing circuit 49 so that they operate in synchronization.

[0027] The detection circuit 48 is, for example, an analog front end (AFE) circuit. The detection circuit 48 is a signal processing circuit having at least the functions of a detection signal amplifier circuit 42 and an A / D conversion circuit 43. The detection signal amplifier circuit 42 amplifies the detection signal Vdet. The A / D conversion circuit 43 converts the analog signal output from the detection signal amplifier circuit 42 into a digital signal.

[0028] The signal processing circuit 44 is a logic circuit that detects a predetermined physical quantity input to the sensor unit 10 based on the output signal of the detection circuit 48. When a finger comes into contact with or close to the detection surface, the signal processing circuit 44 can detect unevenness on the surface of the finger or palm based on the signal from the detection circuit 48. The signal processing circuit 44 can also detect information about the living body based on the signal from the detection circuit 48. The information about the living body includes, for example, an image of the blood vessels of the finger or palm, a pulse wave, a pulse rate, and a blood oxygen concentration.

[0029] The signal processing circuit 44 may also acquire detection signals Vdet (biological information) simultaneously detected by a plurality of photodiodes PD and average these signals. In this case, the detection unit 40 can suppress measurement errors caused by noise and relative positional deviation between the object to be detected, such as a finger, and the sensor unit 10, thereby enabling stable detection.

[0030] The memory circuit 46 temporarily stores the signals calculated by the signal processing circuit 44. The memory circuit 46 may be, for example, a RAM (Random Access Memory), a register circuit, or the like.

[0031] The coordinate extraction circuit 45 is a logic circuit that calculates the detected coordinates of the unevenness of the surface of a finger or the like when the signal processing circuit 44 detects contact or proximity of a finger. The coordinate extraction circuit 45 is also a logic circuit that calculates the detected coordinates of the blood vessels of the finger or palm. The image processing circuit 49 combines the detection signals Vdet output from each photodiode PD of the sensor unit 10 to generate two-dimensional information indicating the shape of the unevenness of the surface of the finger or the like and two-dimensional information indicating the shape of the blood vessels of the finger or palm. The coordinate extraction circuit 45 may output the detection signal Vdet as the sensor output voltage Vo without calculating the detection coordinates. The coordinate extraction circuit 45 and the image processing circuit 49 may not be included in the detection unit 40.

[0032] The output processing unit 50 functions as a processing unit that performs processing based on outputs from the multiple photodiodes PD. The output processing unit 50 may include the detected coordinates determined by the coordinate extraction circuit 45, the two-dimensional information generated by the image processing circuit 49, etc. in the sensor output voltage Vo. Furthermore, the function of the output processing unit 50 may be integrated into another configuration (for example, the image processing circuit 49, etc.).

[0033] Next, an example of the circuit configuration of the detection device 1 will be described. Fig. 3 is a circuit diagram showing the detection device. As shown in Fig. 3, the sensor unit 10 has a plurality of detection elements PAA arranged in a matrix. Each of the plurality of detection elements PAA is provided with a photodiode PD.

[0034] The gate line GCL extends in a first direction Dx and is connected to a plurality of detection elements PAA arranged in the first direction Dx. Furthermore, a plurality of gate lines GCL(1), GCL(2), ..., GCL(8) are arranged in a second direction Dy and are each connected to a gate line driving circuit 15. In the following description, when there is no need to distinguish between the plurality of gate lines GCL(1), GCL(2), ..., GCL(8), they will simply be referred to as gate lines GCL. Furthermore, for ease of understanding, eight gate lines GCL are shown in FIG. 3, but this is merely an example, and M gate lines GCL (M is 8 or more, for example, M=256) may be arranged.

[0035] The signal line SGL extends in the second direction Dy and is connected to the photodiodes PD of the plurality of detection elements PAA arranged in the second direction Dy. The plurality of signal lines SGL(1), SGL(2), ..., SGL(12) are arranged in the first direction Dx and are each connected to the signal line selection circuit 16 and the reset circuit 17. In the following description, when it is not necessary to distinguish between the plurality of signal lines SGL(1), SGL(2), ..., SGL(12), they will simply be referred to as signal lines SGL.

[0036] For ease of understanding, 12 signal lines SGL are shown, but this is merely an example, and N signal lines SGL (N is 12 or more, for example, N=252) may be arranged. The resolution of the sensor is, for example, 508 dpi (dots per inch), and the number of cells is 252×256. In FIG. 3, the sensor unit 10 is provided between the signal line selection circuit 16 and the reset circuit 17. However, this is not limiting, and the signal line selection circuit 16 and the reset circuit 17 may be connected to ends of the signal lines SGL in the same direction.

[0037] The gate line driving circuit 15 receives various control signals, such as a start signal STV, a clock signal CK, and a reset signal RST1, from the control circuit 122 (see FIG. 1). Based on the various control signals, the gate line driving circuit 15 sequentially selects multiple gate lines GCL(1), GCL(2), ..., GCL(8) in a time-division manner. The gate line driving circuit 15 supplies a gate driving signal Vgcl to the selected gate line GCL. As a result, the gate driving signal Vgcl is supplied to multiple first switching elements Tr connected to the gate line GCL, and multiple detection elements PAA arranged in the first direction Dx are selected as detection targets.

[0038] The signal line selection circuit 16 has a plurality of selection signal lines Lsel, a plurality of output signal lines Lout, and a third switching element TrS. The plurality of third switching elements TrS are provided corresponding to the plurality of signal lines SGL, respectively. The six signal lines SGL(1), SGL(2), ..., SGL(6) are connected to a common output signal line Lout1. The six signal lines SGL(7), SGL(8), ..., SGL(12) are connected to a common output signal line Lout2. The output signal lines Lout1 and Lout2 are each connected to a detection circuit 48.

[0039] Here, the signal lines SGL(1), SGL(2), ..., SGL(6) are defined as a first signal line block, and the signal lines SGL(7), SGL(8), ..., SGL(12) are defined as a second signal line block. The multiple selection signal lines Lsel are connected to the gates of the third switching elements TrS included in one signal line block. Furthermore, one selection signal line Lsel is connected to the gates of the third switching elements TrS of multiple signal line blocks.

[0040] The control circuit 122 (see FIG. 1) sequentially supplies the selection signal ASW to the selection signal line Lsel. As a result, the signal line selection circuit 16 sequentially selects the signal lines SGL in one signal line block in a time-division manner through the operation of the third switching element TrS. The signal line selection circuit 16 also selects one signal line SGL from each of the multiple signal line blocks. With this configuration, the detection device 1 can reduce the number of ICs (Integrated Circuits) including the detection circuit 48 or the number of IC terminals. The signal line selection circuit 16 may also bundle multiple signal lines SGL and connect them to the detection circuit 48.

[0041] 3, the reset circuit 17 includes a reference signal line Lvr, a reset signal line Lrst, and a fourth switching element TrR. The fourth switching element TrR is provided corresponding to the plurality of signal lines SGL. The reference signal line Lvr is connected to one of the sources or drains of the plurality of fourth switching elements TrR. The reset signal line Lrst is connected to the gates of the plurality of fourth switching elements TrR.

[0042] The control circuit 122 supplies a reset signal RST2 to the reset signal line Lrst. This turns on the multiple fourth switching elements TrR, and the multiple signal lines SGL are electrically connected to the reference signal line Lvr. The power supply circuit 123 supplies a reference signal COM to the reference signal line Lvr. This causes the reference signal COM to be supplied to the capacitive elements Ca (see FIG. 4) included in the multiple detection elements PAA.

[0043] Fig. 4 is a circuit diagram showing a plurality of detection elements. Fig. 4 also shows the circuit configuration of a detection circuit 48. As shown in Fig. 4, the detection element PAA includes a photodiode PD, a capacitance element Ca, and a first switching element Tr. The capacitance element Ca is a capacitance (sensor capacitance) formed in the photodiode PD, and is equivalently connected in parallel with the photodiode PD.

[0044] 4 shows two gate lines GCL(m) and GCL(m+1) aligned in the second direction Dy among the multiple gate lines GCL. Also, two signal lines SGL(n) and SGL(n+1) aligned in the first direction Dx among the multiple signal lines SGL. The detection element PAA is an area surrounded by the gate lines GCL and the signal lines SGL.

[0045] The first switching element Tr is provided corresponding to the photodiode PD. The first switching element Tr is configured by a thin film transistor, and in this example, is configured by an n-channel MOS (Metal Oxide Semiconductor) TFT (Thin Film Transistor).

[0046] The gates of the first switching elements Tr belonging to the plurality of detection elements PAA arranged in the first direction Dx are connected to the gate line GCL, the sources of the first switching elements Tr belonging to the plurality of detection elements PAA arranged in the second direction Dy are connected to the signal line SGL, and the drains of the first switching elements Tr are connected to the cathodes of the photodiodes PD and the capacitance elements Ca.

[0047] A sensor power supply signal VDDSNS is supplied to the anode of the photodiode PD from the power supply circuit 123. In addition, a reference signal COM, which becomes the initial potential of the signal line SGL and the capacitance element Ca, is supplied from the power supply circuit 123 to the signal line SGL and the capacitance element Ca.

[0048] When light is irradiated onto the detection element PAA, a current corresponding to the amount of light flows through the photodiode PD, causing charge to accumulate in the capacitance element Ca. When the first switching element Tr is turned on, a current corresponding to the charge accumulated in the capacitance element Ca flows through the signal line SGL. The signal line SGL is connected to the detection circuit 48 via the third switching element TrS of the signal line selection circuit 16. This allows the detection device 1 to detect a signal corresponding to the amount of light irradiated onto the photodiode PD for each detection element PAA or for each block unit PAG.

[0049] During the readout period, the switch SSW of the detection circuit 48 is turned on and connected to the signal line SGL. The detection signal amplifier circuit 42 of the detection circuit 48 converts fluctuations in the current supplied from the signal line SGL into fluctuations in voltage and amplifies the voltage. A reference potential (Vref) having a fixed potential is input to the non-inverting input terminal (+) of the detection signal amplifier circuit 42, and the signal line SGL is connected to the inverting input terminal (-). In this embodiment, a signal identical to the reference signal COM is input as the reference potential (Vref) voltage. The signal processing circuit 44 (see FIG. 2) calculates the difference between the detection signal Vdet when light is irradiated and the detection signal Vdet when light is not irradiated as the sensor output voltage Vo. The detection signal amplifier circuit 42 also has a capacitance element Cb and a reset switch RSW. During the reset period, the reset switch RSW is turned on and the charge of the capacitance element Cb is reset.

[0050] Next, the configuration of the photodiode PD will be described. Fig. 5 is a plan view showing the detection device according to the first embodiment. Fig. 6 is a plan view schematically showing the detection device according to the first embodiment. Fig. 7 is a plan view schematically showing the first electrode and transistor of the detection device according to the first embodiment. In Fig. 6, the insulating film 95 is shown with diagonal lines to make the drawing easier to see. Fig. 7 is a plan view schematically showing a part of the detection device of Fig. 6 excluding the insulating film.

[0051] As shown in FIG. 5, a control board 121 is electrically connected to the substrate 21 via a flexible printed circuit board 71. The flexible printed circuit board 71 is provided with a detection circuit 48. The control board 121 is provided with a control circuit 122 and a power supply circuit 123. The control circuit 122 is, for example, an FPGA (Field Programmable Gate Array). The control circuit 122 supplies control signals to the sensor unit 10, the gate line driving circuit 15, and the signal line selection circuit 16 to control the detection operation of the sensor unit 10. The power supply circuit 123 supplies voltage signals such as a sensor power supply signal VDDSNS (see FIG. 4) to the sensor unit 10, the gate line driving circuit 15, and the signal line selection circuit 16.

[0052] The substrate 21 has a detection area AA and a peripheral area GA. The detection area AA is an area that includes an area that overlaps with the multiple first electrodes 23 of the sensor unit 10. The peripheral area GA is an area outside the detection area AA that does not overlap with the first electrodes 23. In other words, the peripheral area GA is an area between the periphery of the detection area AA and the edge of the substrate 21. The gate line driving circuit 15 and the signal line selection circuit 16 are provided in the peripheral area GA.

[0053] The multiple first electrodes 23 are detection electrodes of the photodiode PD, and each outputs an electrical signal in response to light irradiated thereon. The multiple first electrodes 23 of the sensor unit 10 are arranged in a matrix in the detection area AA. The multiple first electrodes 23 output an electrical signal in response to light irradiated thereon as a detection signal Vdet to the signal line selection circuit 16. The detection device 1 detects information about a living body based on the detection signals Vdet from the multiple first electrodes 23. In other words, the photodiode PD functions as a biological sensor. The multiple first electrodes 23 perform detection in response to a gate drive signal Vgcl supplied from the gate line drive circuit 15.

[0054] The gate line driving circuit 15 and the signal line selection circuit 16 are provided in the peripheral area GA. Specifically, the gate line driving circuit 15 is provided in a region of the peripheral area GA extending along the second direction Dy. The signal line selection circuit 16 is provided in a region of the peripheral area GA extending along the first direction Dx, and is provided between the sensor unit 10 and the detection circuit 48.

[0055] The second electrode 24 covers the detection area AA and has an area larger than the detection area AA. Conductive wiring 56 is arranged in the peripheral area GA, and the conductive wiring 56 and the second electrode 24 are electrically connected by a connection terminal 55. The conductive wiring 56 is connected to the power supply circuit 123 shown in FIG. 1, and a sensor power supply signal VDDSNS is supplied to the conductive wiring 56.

[0056] 5, 6, and 7, the photodiode PD, the first electrode 23, and the first switching element Tr are provided in an area surrounded by the gate line GCL and the signal line SGL. The first electrode 23 is a lower electrode (cathode electrode) of the photodiode PD, and a plurality of the photodiodes PD and a plurality of the first electrodes 23 are arranged in a matrix above the substrate 21.

[0057] 6, the insulating film 95 is provided between adjacent first electrodes 23 and covers the outer periphery of the first electrode 23. More specifically, the insulating film 95 includes first portions 95a extending in the first direction Dx and second portions 95b extending in the second direction Dy. The insulating film 95 is provided in a lattice pattern, with the multiple first portions 95a and multiple second portions 95b intersecting each other.

[0058] The first portion 95a is provided to overlap the gate line GCL and is provided across the first electrodes 23 adjacent to each other in the second direction Dy with the gate line GCL sandwiched therebetween. The second portion 95b is provided to overlap the signal line SGL and is provided across the first electrodes 23 adjacent to each other in the first direction Dx with the signal line SGL sandwiched therebetween. In other words, the multiple first electrodes 23 are partitioned by the insulating film 95. The multiple first electrodes 23 are connected to the lower buffer layer 32 (see FIG. 8) of the photodiode PD through openings OP formed in the insulating film 95. The lower buffer layer 32 is an electron transport layer.

[0059] As shown in FIG. 7, the first switching element Tr has a semiconductor layer 61, a source electrode 62, a drain electrode 63, and a gate electrode 64. The semiconductor layer 61 extends along the gate line GCL and intersects with the gate electrode 64 in a plan view. The gate electrode 64 is connected to the gate line GCL and extends in a direction perpendicular to the gate line GCL. One end of the semiconductor layer 61 is connected to the source electrode 62 via a second contact hole CH2. The first electrode 23 is electrically connected to the source electrode 62 of the first switching element Tr via a first contact hole CH1. This electrically connects the first switching element Tr to the photodiode PD. The other end of the semiconductor layer 61 is connected to the drain electrode 63 via a third contact hole CH3. The drain electrode 63 is connected to the signal line SGL.

[0060] 6, the second organic insulating film 96 is provided to cover the first contact hole CH1. Detailed configurations of the second organic insulating film 96 and the photodiode PD will be described with reference to FIG. 8. Note that the configuration and arrangement of the first switching element Tr shown in FIGS. 6 and 7 are merely examples and can be changed as appropriate.

[0061] Fig. 8 is a cross-sectional view taken along line VIII-VIII' in Fig. 6. As shown in Fig. 8, the detection device 1 includes a substrate 21, a first switching element Tr, a first organic insulating film 94, a first electrode 23, an insulating film 95, a second organic insulating film 96, an organic photodiode layer PDL, a second electrode 24, sealing films 97a, 97b, and 97c, and a resin mask 98.

[0062] The substrate 21 is an insulating base material, and is made of, for example, glass or a resin material. The substrate 21 is not limited to a flat plate shape and may have a curved surface. In this case, the substrate 21 may be a film-like resin.

[0063] In this embodiment, the direction perpendicular to the surface of the substrate 21 from the substrate 21 to the organic photodiode layer PDL is referred to as the "upper side" or simply "upper." Also, the direction from the organic photodiode layer PDL to the substrate 21 is referred to as the "lower side" or simply "lower."

[0064] The light-shielding film 65 is provided on the substrate 21. The light-shielding film 65 is provided between the semiconductor layer 61 and the substrate 21. The light-shielding film 65 can prevent light from entering the channel region of the semiconductor layer 61 from the substrate 21 side.

[0065] The undercoat film 91 is provided on the substrate 21, covering the light-shielding film 65. The undercoat film 91 is formed of an inorganic insulating film such as a silicon nitride film or a silicon oxide film. The configuration of the undercoat film 91 is not limited to a single-layer film, and may be a laminated film in which a plurality of inorganic insulating films are stacked. Furthermore, an undercoat film may also be provided between the substrate 21 and the light-shielding film 65.

[0066] A plurality of first switching elements Tr (transistors) are provided on a substrate 21. A semiconductor layer 61 is provided on an undercoat film 91. The semiconductor layer 61 is made of, for example, polysilicon. However, the semiconductor layer 61 is not limited to this and may be made of a microcrystalline oxide semiconductor, an amorphous oxide semiconductor, low-temperature polysilicon, or the like. Although only n-type TFTs are shown as the first switching elements Tr, p-type TFTs may also be formed at the same time.

[0067] The gate insulating film 92 is provided on the undercoat film 91 to cover the semiconductor layer 61. The gate insulating film 92 is an inorganic insulating film such as a silicon oxide film. The gate electrode 64 is provided on the gate insulating film 92. In the example shown in FIG. 7, the first switching element Tr has a top-gate structure. However, without being limited to this, the first switching element Tr may have a bottom-gate structure or a dual-gate structure in which the gate electrodes 64 are provided on both the upper and lower sides of the semiconductor layer 61.

[0068] The interlayer insulating film 93 is provided on the gate insulating film 92, covering the gate electrode 64. The interlayer insulating film 93 has, for example, a stacked structure of a silicon nitride film and a silicon oxide film. The source electrode 62 and the drain electrode 63 are provided on the interlayer insulating film 93. The source electrode 62 is connected to the source region of the semiconductor layer 61 via a second contact hole CH2 provided in the gate insulating film 92 and the interlayer insulating film 93. The drain electrode 63 is connected to the drain region of the semiconductor layer 61 via a third contact hole CH3 provided in the gate insulating film 92 and the interlayer insulating film 93.

[0069] The first organic insulating film 94 covers the source electrode 62 and the drain electrode 63 of the first switching element Tr and is provided on the interlayer insulating film 93. The first organic insulating film 94 is an organic planarizing film, and is superior in coverage of wiring steps and surface flatness compared to inorganic insulating materials formed by CVD or the like.

[0070] The organic photodiode layer PDL is provided on the first organic insulating film 94. The first electrode 23 and the insulating film 95 are provided in a direction perpendicular to the surface of the substrate 21, between the substrate 21 and the first organic insulating film 94, and between the organic photodiode layer PDL and the substrate 21.

[0071] More specifically, the first electrode 23 is provided on the first organic insulating film 94 and covers the bottom and inner side surfaces of a first contact hole CH1 formed in the first organic insulating film 94. The first electrode 23 is connected to the source electrode 62 of the first switching element Tr at the bottom surface of the first contact hole CH1. The first electrode 23 is a cathode electrode of the organic photodiode layer PDL and is formed of a light-transmitting conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The multiple first electrodes 23 are arranged spaced apart from each other for each detection element PAA (photodiode PD). The organic photodiode layer PDL has a larger area than the first electrode 23 in a plan view and covers the upper surface and outer edge portion 23e of the first electrode 23.

[0072] The insulating film 95 is provided between adjacent first electrodes 23, and is provided to cover the outer edge portion 23e of the first electrode 23. In this embodiment, the insulating film 95 is an inorganic insulating film, and is made of a material such as a silicon nitride film or an aluminum oxide film. The insulating film 95 has at least one opening OP (see FIG. 6) in a region overlapping the upper surface of the first electrode 23. The organic photodiode layer PDL is electrically connected to the first electrode 23 through the opening OP.

[0073] The insulating film 95 is provided between the first organic insulating film 94 and the organic photodiode layer PDL in the region between the adjacent first electrodes 23. As a result, the insulating film 95 insulates the adjacent first electrodes 23. In other words, the insulating film 95 can suppress leakage current between the adjacent photodiodes PD. The insulating film 95 also functions as a barrier film that suppresses penetration of moisture from the first organic insulating film 94 into the organic photodiode layer PDL in the region between the adjacent first electrodes 23.

[0074] The second organic insulating film 96 is provided to cover the inside of the first contact hole CH1. The first electrode 23 and the second organic insulating film 96 are stacked on the inner side surface and bottom surface of the first contact hole CH1. The first organic insulating film 94, the first electrode 23, and the second organic insulating film 96 are stacked in this order on the inner side surface of the first contact hole CH1. On the bottom surface of the first contact hole CH1, the first electrode 23 and the second organic insulating film 96 are stacked in this order on top of the source electrode 62. The second organic insulating film 96 is provided to cover the corner portion 23t of the first electrode 23 at a position overlapping the opening edge of the first contact hole CH1.

[0075] The organic photodiode layer PDL is provided to cover the plurality of first electrodes 23, the insulating film 95, and the second organic insulating film 96. More specifically, the organic photodiode layer PDL includes an active layer 31, a lower buffer layer 32 (first carrier transport layer), and an upper buffer layer 33 (second carrier transport layer). The lower buffer layer 32 (first carrier transport layer) is provided between the active layer 31 and the first electrode 23. The upper buffer layer 33 (second carrier transport layer) is provided between the active layer 31 and the second electrode 24. The upper buffer layer 33 is a hole transport layer.

[0076] The lower buffer layer 32 is formed by coating a material such as zinc acetate, ethoxylated polyethyleneimine (PEIE), polyethyleneimine (PEI), etc. The lower buffer layer 32 is a single layer, and its thickness is, for example, about 30 nm or less.

[0077] The active layer 31 is made of a mixture of a p-type organic semiconductor and an n-type organic semiconductor. An example of a p-type organic semiconductor is PMDPP3T (poly((2,5-bis(2-hexyldecyl)-2,3,5,6-tetrahydro-3,6-dioxopyrrolo(3,4-c)pyrrole-1,4-diyl)-alt-(3',3"-dimethyl-2,2':5',2"-terthiophene)-5,5"-diyl)). An example of an n-type organic semiconductor is PC61BM ([6,6]-phenyl C61-butyric acid methyl ester). The thickness of the active layer 31 is, for example, about 100 nm to 500 nm, preferably about 350 nm.

[0078] The upper buffer layer 33 is, for example, a metal oxide layer such as tungsten oxide (WO3) or molybdenum oxide (MoOx). The upper buffer layer 33 is formed of a vapor deposition film or a sputtering film, and its thickness is, for example, about 30 nm or less.

[0079] The lower buffer layer 32, the active layer 31, and the upper buffer layer 33, which form the organic photodiode layer PDL, are provided to cover the plurality of first electrodes 23, the insulating film 95, and the second organic insulating film 96. The lower buffer layer 32 is connected to the first electrodes 23 in a region overlapping with the opening OP of the insulating film 95. The lower buffer layer 32 also includes an overlapping portion 32s provided on the insulating film 95, and an overlapping portion 32t provided on the second organic insulating film 96 in a region overlapping with the first contact hole CH1.

[0080] In the detection device 1, in a region overlapping with the first electrode 23, a first organic insulating film 94, the first electrode 23, the lower buffer layer 32, the active layer 31, the upper buffer layer 33, and the second electrode 24 are stacked in this order in a direction perpendicular to the substrate 21. Furthermore, in a region overlapping with the first contact hole CH1, the first electrode 23, the second organic insulating film 96, the lower buffer layer 32 (overlapping portion 32t), the active layer 31, the upper buffer layer 33, and the second electrode 24 are stacked in this order. Furthermore, in a region between adjacent first electrodes 23, the first organic insulating film 94, the insulating film 95, the lower buffer layer 32 (overlapping portion 32s), the active layer 31, the upper buffer layer 33, and the second electrode 24 are stacked in this order.

[0081] As described above, the insulating film 95 is provided between adjacent first electrodes 23 and covers the outer edge portions 23e of the first electrodes 23. This causes the thickness of the lower buffer layer 32 to be thin at the position overlapping the outer edge portions 23e of the first electrodes 23. Even if a step occurs in the film between the overlapping portion 32s and the lower buffer layer 32 above the first electrode 23, the insulating film 95 can suppress the occurrence of a short circuit between the active layer 31 and the first electrode 23. Note that, for ease of understanding, FIG. 8 shows a case where the overlapping portion 32s and the lower buffer layer 32 above the first electrode 23 are formed separately, but the overlapping portion 32s and the lower buffer layer 32 above the first electrode 23 may be formed continuously and integrally.

[0082] Furthermore, the second organic insulating film 96 is provided to cover the inside of the first contact hole CH1 and covers the corner portion 23t of the first electrode 23 formed at the opening edge of the first contact hole CH1. As a result, the region overlapping with the first contact hole CH1 is planarized, and the overlapping portion 32t of the lower buffer layer 32 is formed continuously with the lower buffer layer 32 above the first electrode 23. The second organic insulating film 96 also covers most of the region of the first electrode 23 inside the first contact hole CH1. Therefore, even if a portion of the lower buffer layer 32 is formed thin in the region overlapping with the first contact hole CH1 or if a step occurs in the lower buffer layer 32, the second organic insulating film 96 can suppress the occurrence of a short circuit between the active layer 31 and the first electrode 23.

[0083] Furthermore, since the region overlapping with the first contact hole CH1 is planarized by the second organic insulating film 96, variations in film thickness of the active layer 31, the lower buffer layer 32, and the upper buffer layer 33 that form the organic photodiode layer PDL are suppressed across the region overlapping with the first contact hole CH1 and the region not overlapping with the first contact hole CH1. That is, compared to a configuration in which the second organic insulating film 96 is not provided, discontinuities and thinning of the active layer 31, the lower buffer layer 32, and the upper buffer layer 33 in the region overlapping with the first contact hole CH1 are suppressed. This enables the detection device 1 to suppress leakage current between the anode and cathode of the photodiode PD.

[0084] The second electrode 24 is an upper electrode provided on the organic photodiode layer PDL. More specifically, the second electrode 24 is provided on the upper buffer layer 33 of the organic photodiode layer PDL. The second electrode 24 is an anode electrode of the photodiode PD, and is formed continuously across the plurality of detection elements PAA (photodiodes PD). The second electrode 24 is made of, for example, a metal material such as silver (Ag), and functions as a reflective electrode. However, the second electrode 24 may be made of a light-transmitting conductive material similar to the first electrode 23.

[0085] The sealing films 97a, 97b, and 97c are provided on the second electrode 24. For example, an inorganic insulating film such as a silicon nitride film or an aluminum oxide film is used for the sealing films 97a and 97c. For example, a resin film such as an acrylic film is used for the sealing film 97b. The sealing films 97a, 97b, and 97c are not limited to laminated films in which an inorganic insulating film and an organic insulating film are laminated, and may be single layers. Furthermore, a resin mask 98 is provided to cover the sealing film 97c. The organic photodiode layer PDL is well sealed by the sealing films 97a, 97b, and 97c and the resin mask 98, and can prevent moisture from entering from the upper surface side.

[0086] The thickness of the first electrode 23 is, for example, about 50 nm. The thickness of the second electrode 24 is, for example, about 100 nm or less. That is, the thickness of each of the lower buffer layer 32 and the upper buffer layer 33 is thinner than the active layer 31 and thinner than the thickness of the first electrode 23 and the second electrode 24. In other words, the thickness of each of the first electrode 23 and the second electrode 24 is thinner than the active layer 31 and thicker than the thickness of the lower buffer layer 32 and the upper buffer layer 33.

[0087] The materials and manufacturing methods of the lower buffer layer 32, the active layer 31, and the upper buffer layer 33 are merely examples, and other materials and manufacturing methods may be used. For example, the lower buffer layer 32 may be a vapor-deposited or sputtered film using a material such as zinc oxide (ZnO) or titanium oxide (TiO2). The upper buffer layer 33 may be a vapor-deposited or sputtered film using a material such as nickel oxide (NiO). Alternatively, the upper buffer layer 33 may be formed by coating a nanoparticle ink such as vanadium oxide (VO5) or tungsten oxide (WO3), or a material such as PEDOT:PSS.

[0088] 6 and 8 are merely schematic views and may be modified as appropriate. For example, the upper surface of the second organic insulating film 96 is not limited to a curved surface, and a portion of the upper surface may be flat. The planar shape of the second organic insulating film 96 is not limited to a quadrangle, and may be a circle, a polygon, or another shape depending on the planar shape of the first contact hole CH1. Furthermore, the shape of the opening OP formed in the insulating film 95 is not limited to a quadrangle, and may be modified as appropriate depending on the shape of the first electrode 23.

[0089] FIG. 9 is a cross-sectional view taken along line IX-IX′ in FIG. 5 . The second electrode 24 is connected to the conductive wiring 56 in the peripheral region GA around the detection region AA. The organic photodiode layer PDL has a non-formed region in the peripheral region GA, and the side surface 33e of the upper buffer layer 33, the side surface 31e of the active layer 31, and the side surface 32e of the lower buffer layer 32 are exposed at the edge. The side surface 33e of the upper buffer layer 33, the side surface 31e of the active layer 31, and the side surface 32e of the lower buffer layer 32 are the side surface PDL e of the organic photodiode layer PDL e. The second electrode 24, which covers the side surface PDL e of the organic photodiode layer PDL e, is electrically connected to the side surface 33e of the upper buffer layer 33, the side surface 31e of the active layer 31, and the side surface 32e of the lower buffer layer 32. Therefore, the second electrode 24 is stacked on the exposed side surface PDL e of the organic photodiode layer PDL in the peripheral region GA, and leakage current may flow between the second electrode 24 and the outermost first electrode 23. In the first embodiment, in order to suppress leakage current to this first electrode 23, a third electrode 25 is formed between the second electrode 24 on the side surface PDLe of the organic photodiode layer PDL and the outermost first electrode 23.

[0090] In the peripheral region GA, conductive wiring 56 is routed, and a connection terminal 55 is formed. The conductive wiring 56 is formed on an undercoat film 91. The connection terminal 55 has a conductive base portion 57 electrically connected to the conductive wiring 56, and a terminal electrode 23a electrically connected to the base portion 57 via a contact hole CHA. A second organic insulating film 96 is provided to cover the inside of the contact hole CHA. The terminal electrode 23a is electrically connected to a second electrode 24.

[0091] The third electrode 25 is electrically connected to the reference potential wiring 26 via a contact hole CHC. The reference potential wiring 26 is routed along the outermost periphery of the first electrode 23.

[0092] The same potential as the reference signal COM is supplied to the reference potential wiring 26. Therefore, the third electrode 25 has the same potential as the reference signal, which is the reset potential supplied from the reset circuit 17 to the signal line SGL. As a result, the potential difference between the third electrode 25 and the first electrode 23 becomes small, and leakage current from the third electrode 25 to the first electrode 23 becomes less likely to occur.

[0093] If leakage current from the second electrode 24 to the third electrode 25 becomes a problem during periods when light detection is not performed, the same potential as that of the second electrode 24 may be supplied to the reference potential wiring 26. As a result, the potential difference between the third electrode 25 and the second electrode 24 becomes smaller, and leakage current from the second electrode 24 to the third electrode 25 becomes less likely to occur.

[0094] The second organic insulating film 96 is provided to cover the inside of the contact hole CHC. As shown in Fig. 5, the third electrode 25 is routed along the outermost periphery of the first electrode 23, surrounding the first electrode 23 in a rectangular shape. In this manner, the third electrode 25 surrounds the entire outermost periphery of the first electrode 23. The second electrode 24 is electrically connected to a conductive wiring 56 routed in the peripheral region GA outside the third electrode 25.

[0095] As described above, the detection device 1 of the first embodiment includes a plurality of photodiodes PD provided on the substrate 21, a plurality of first electrodes 23, second electrodes 24, third electrodes 25, and an organic photodiode layer PDL. The plurality of first electrodes 23 are provided corresponding to the plurality of photodiodes PD, respectively. The second electrode 24 is provided across the plurality of photodiodes PD. The organic photodiode layer PDL includes a lower buffer layer 32 (first carrier transport layer), an active layer 31, and an upper buffer layer 33 (second carrier transport layer), and is provided across the plurality of photodiodes PD.

[0096] In the detection area AA where the first electrode 23 is arranged, the multiple photodiodes PD are stacked in the following order: the first electrode 23, a lower buffer layer 32 (first carrier transport layer), an active layer 31 and an upper buffer layer 33 (second carrier transport layer), and a second electrode 24. A reference potential is supplied to the third electrode 25. The third electrode 25 is arranged between the second electrode 24 provided outside the detection area AA to cover the side surface PDLe of the organic photodiode layer PDL, and the first electrode 23 arranged on the outermost periphery.

[0097] This allows a leakage current to flow between the second electrode 24 and the third electrode 25, and suppresses a leakage current between the second electrode 24 on the side surface PDLe of the organic photodiode layer PDL and the outermost first electrode 23.

[0098] (Second embodiment) 10 is a plan view showing a detection device according to the second embodiment. In the following description, the same components as those described in the above-mentioned embodiments are denoted by the same reference numerals, and redundant description will be omitted.

[0099] 10, in the detection device 1A according to the second embodiment, conductive wiring 56 is arranged in a U-shape in the peripheral area GA, and the conductive wiring 56 and the second electrode 24 are electrically connected by a connection terminal 55. The conductive wiring 56 is connected to the power supply circuit 123 shown in FIG. 1, and a sensor power supply signal VDDSNS is supplied to the conductive wiring 56. The third electrode 25 is routed along the outermost periphery of the first electrode 23, and surrounds the first electrode 23 in a U-shape.

[0100] This allows a leakage current to flow between the second electrode 24 and the third electrode 25, and suppresses a leakage current between the second electrode 24 on the side surface PDLe of the organic photodiode layer PDL and the outermost first electrode 23.

[0101] As described above, in the detection device 1A of the second embodiment, the third electrode 25 is arranged on all sides surrounding the outermost periphery of the first electrode 23 except for one side. In the region where the third electrode 25 is not arranged, the second electrode 24 is arranged more inward than the side surface PDL e of the organic photodiode layer PDL e. In other words, in the region where the third electrode 25 is not arranged, the second electrode 24 is not stacked on the side surface PDL e of the organic photodiode layer PDL e. This suppresses leakage current in the region where the third electrode 25 is not arranged.

[0102] (Third embodiment) 11 is a plan view showing a detection device according to the third embodiment. In the following description, the same components as those described in the above embodiments are denoted by the same reference numerals, and redundant description will be omitted.

[0103] 11, in the detection device 1B according to the third embodiment, conductive wiring 56 is linearly arranged in a part of the peripheral area GA, and the conductive wiring 56 and the second electrode 24 are electrically connected by a connection terminal 55. The conductive wiring 56 is connected to the power supply circuit 123 shown in FIG. 1, and a sensor power supply signal VDDSNS is supplied to the conductive wiring 56. The third electrode 25 is routed along the outermost periphery of the first electrode 23 and is linearly arranged.

[0104] This allows a leakage current to flow between the second electrode 24 and the third electrode 25, and suppresses a leakage current between the second electrode 24 on the side surface PDLe of the organic photodiode layer PDL and the outermost first electrode 23.

[0105] As described above, in the detection device 1B of the third embodiment, the third electrode 25 is arranged on only one of the sides surrounding the outermost periphery of the first electrode 23. In the regions of the multiple sides where the third electrode 25 is not arranged, the second electrode 24 is arranged inside the side surface PDL e of the organic photodiode layer PDL e. In other words, in the region where the third electrode 25 is not arranged, the second electrode 24 is not stacked on the side surface PDL e of the organic photodiode layer PDL e. This suppresses leakage current in the regions of the multiple sides where the third electrode 25 is not arranged.

[0106] Although preferred embodiments of the present disclosure have been described above, the present disclosure is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible within the scope of the present disclosure. Appropriate modifications made within the scope of the present disclosure naturally fall within the technical scope of the present disclosure. At least one of various omissions, substitutions, and modifications of components can be made within the scope of the gist of each of the above-described embodiments and modifications. [Explanation of symbols]

[0107] 1, 1A, 1B Detector 10 Sensor section 21 PCB 23 1st electrode 23a terminal electrode 24 2nd electrode 25 3rd electrode 26 Reference potential wiring 31 Active layer 31e side 32 Lower buffer layer 32e side 33 Upper buffer layer 33e side 57 Base AA detection area GA peripheral area PD photodiode PDL Organic Photodiode Layer PDLe side RST1 Reset signal RST2 Reset signal RSW Reset switch SGL signal line Tr First switching element

Claims

1. A substrate; a plurality of optical diodes disposed in a detection region of the substrate, each optical diode having a first electrode, a first carrier transport layer, an active layer, a second carrier transport layer, and a second electrode; a third electrode to which a reference potential is applied; A conductive wiring; a connection terminal that connects the conductive wiring and the second electrode, the second electrode is provided across the plurality of optical diodes, the second electrode has a second electrode sidewall portion covering a side surface of the optical diode at the outermost position among the plurality of optical diodes, and the third electrode is disposed between the first electrode provided on the optical diode at the outermost position and the second electrode sidewall portion; the second electrode is electrically connected to the conductive wiring; the conductive wiring is routed to a peripheral region outside the third electrode in a plan view, and extends parallel to the third electrode along one direction in a plane parallel to the substrate; the connection terminal is in the same layer as the third electrode; electronic equipment.

2. the third electrode surrounds the entire outermost periphery of the first electrode; The electronic device according to claim 1 .

3. the third electrode is disposed on all sides surrounding the outermost periphery of the first electrode except for one side; The electronic device according to claim 1 .

4. In a region where the third electrode is not disposed, the second electrode sidewall portion is not formed, and the second electrode is disposed inside a side surface of the outermost optical diode. The electronic device according to claim 3 .

5. the third electrode is disposed on only one of the sides surrounding the outermost periphery of the first electrode; The electronic device according to claim 1 .

6. The electronic device according to claim 1 , wherein the second electrode sidewall portion is electrically connected to the first carrier transport layer, the active layer, and the second carrier transport layer.

7. the second electrode sidewall portion is not formed in a region of a plurality of sides surrounding the outermost periphery of the first electrode where the third electrode is not arranged, and the second electrode is arranged more inward than a side surface of the optical diode at the outermost end. The electronic device according to claim 5 .

8. A plurality of signal lines; a first switching element provided for each of the optical diodes, for selecting the optical diode and outputting a detection signal to the signal line; the reference potential supplied to the third electrode is the same as a reset potential that keeps the potential of the signal line constant; The electronic device according to claim 1 .

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