Real-time control of temperature in a plasma chamber

Abstract

To provide a system, an apparatus, a method and a computer program for real-time control of temperature in a plasma chamber.SOLUTION: One method includes sensing, in real time, a voltage of a rail coupled to a voltage source. The voltage source supplies a voltage to a plurality of heater elements of the plasma chamber. The sensed voltage is used to adjust one or more duty cycles of a corresponding one or more of the heater elements. The adjusted one or more duty cycles facilitate achieving and maintaining a temperature value within the plasma chamber over time.SELECTED DRAWING: Figure 4A

Description

[Technical Field]

[0001] The present disclosure relates to systems and methods for real-time control of temperature in a plasma chamber. [Background technology]

[0002] The background art discussion provided herein is intended to generally provide a context for the present disclosure. To the extent described in this background art section, neither the works of the inventors named herein, nor aspects of the discussion that may not otherwise be considered prior art at the time of submission, are admitted, expressly or impliedly, as prior art to the present disclosure.

[0003] The plasma tool includes a radio frequency (RF) generator and a plasma chamber. The RF generator is coupled to the plasma chamber. The RF generator generates an RF signal and supplies the RF signal to the plasma chamber.

[0004] A substrate is processed within the plasma chamber using a plasma generated when an RF signal is supplied to the plasma chamber in addition to one or more gases. To achieve uniformity in processing the substrate, it is important that the temperature within the plasma chamber is substantially uniform. Summary of the Invention [Problem to be solved by the invention]

[0005] It is within this context that the embodiments described in this disclosure arise. [Means for solving the problem]

[0006]

[0006] Embodiments of the present disclosure provide systems, apparatus, methods, and computer programs for real-time control of temperature in a plasma chamber. It should be appreciated that the embodiments can be implemented in numerous ways, for example, as a process, an apparatus, a system, an instrument, or a method on a computer-readable medium. Several embodiments are described below.

[0007] A conductive or dielectric etch tool includes a matrix of heaters, such as heater elements, adjusted to operate at different duty cycles to achieve a desired temperature uniformity or a particular temperature pattern comprising a range of temperature values ​​during wafer processing within a plasma chamber. The total amount of energy applied to the heater is linear with respect to the on-time of the duty cycle when the amount of voltage supplied to the heater by the power supply is substantially constant. The duty cycle is the fraction of a clock cycle that supplies the amount of voltage to the heater. Thus, the temperature of the heater has a known relationship to the duty cycle at which the heater is operated.

[0008] In some cases, open-loop control is used to control a matrix of heaters, where the setpoint, such as the duty cycle, of the matrix of heaters is calibrated to various profiles under the assumption that the voltage generated by the power supply and delivered via the power rails is constant, such as at a nominal value. To achieve this assumption, the power supply should closely adhere to strict specifications for how much voltage it should deliver to the matrix of heaters, e.g., limiting the voltage it should deliver to a specified level with little or no variation or deviation.

[0009] However, the voltage supplied by a power supply using open-loop control may be inaccurate or fluctuate, resulting in a voltage that differs from or deviates from the intended nominal voltage value. Furthermore, the voltage supplied by the power supply may drift from its nominal value due to changes in the temperature surrounding the power supply. The voltage supplied by the power supply may also ripple due to dynamic load variations. During dynamic load variations, different heaters in a matrix consume different amounts of power from the power supply, causing the voltage supplied by the power supply to deviate from its nominal value, resulting in ripples. Therefore, open-loop control is impaired, adversely affecting the uniform heating of a chuck, such as an electrostatic chuck (ESC). Furthermore, there may be chamber-to-chamber or intra-chamber variations in temperature. These chamber-to-chamber and intra-chamber variations result in non-uniformity when processing one or more substrates.

[0010] To achieve uniformity in supplying voltage to the various heaters, the power supply is regulated by a regulator. For example, the power supply may include a regulator or be coupled to a regulator to regulate the amount of voltage the power supply supplies. Regulators used to regulate the voltage supplied by the power supply are expensive. Furthermore, when using a regulator, it is difficult to ensure that the power supply supplies voltage to the heaters in the matrix within strict accuracy specifications. Therefore, a nominal value is not always supplied. Furthermore, when the heaters in the matrix consume different amounts of power from the power supply, ripple occurs in the voltage. Even when a regulator is used, there is no or minimal compensation for power supply inaccuracies or ripple or drift, so the ripple or drift of the power supply is reflected in the amount of temperature to be achieved inside the plasma chamber.

[0011] In some embodiments, a real-time automatic compensation method is described to remove the effects of many of the power supply inaccuracies or fluctuations. A power supply used with the real-time automatic compensation method can have relaxed specifications and is cost-effective to manufacture. The real-time automatic compensation method employs voltage sensors to monitor the voltage at the power supply rails in real time. A digital signal processor (DSP) on the printed circuit board assembly also polls the voltage sensors in real time. The DSP can receive a set point from another device, such as a user interface system (UIS), via a communication medium. The set point is pre-calibrated at the factory where the chuck is fabricated, assuming that the power supply has a constant value, such as a nominal value. The DSP performs a function Adjusted duty cycle = (V-nominal / V-sense) 2 × Initial duty cycle The duty cycle is adjusted in real time based on multiple voltage readings measured in real time by a voltage sensor according to where V-nominal is the nominal value, V-sense is the voltage sensed by the voltage sensor on the power rail, and initial duty cycle is the duty cycle of the heaters in the matrix when the voltage is at the nominal value. The DSP controls multiple heater switching devices to switch the heaters to operate at the adjusted duty cycle.

[0012] In some embodiments, a method for achieving a target temperature within a plasma chamber of a wafer processing system is described. The wafer processing system includes a plurality of heater elements disposed within the plasma chamber and a voltage source that supplies voltage to the plurality of heater elements via a rail. The method includes maintaining mapping information between the target temperature and a plurality of duty cycles corresponding to the plurality of heater elements. The mapping information includes a nominal voltage associated with the voltage source. The method further includes measuring a parameter value at the rail and generating one or more adjusted duty cycles for corresponding heater elements of the plurality of heater elements based on at least one of the plurality of duty cycles, the nominal voltage, and the measured parameter value.

[0013] In various embodiments, a system for achieving a target temperature within a plasma chamber of a wafer processing system is described. The system includes a memory device configured to maintain mapping information between the target temperature and a plurality of duty cycles corresponding to a plurality of heater elements. The mapping information includes a nominal voltage associated with a voltage source. The system further includes a sensor configured to measure a parameter value at a rail. The system also includes a processor. The processor is configured to generate one or more adjusted duty cycles for corresponding heater elements of the plurality of heater elements based on at least one of the plurality of duty cycles, the nominal voltage, and the measured parameter value.

[0014] Some advantages of the systems and methods described herein for controlling the temperature in a plasma chamber in real time include the use of inexpensive power supplies that are unregulated or regulated with loose regulation specifications to control a matrix of heaters. Furthermore, by applying a regulated duty cycle, the temperature inside the plasma chamber is minimally affected by ripple and drift in the power supply. In some embodiments, when a regulated duty cycle is applied, ripple and drift have no effect on the temperature inside the plasma chamber. Additionally, the temperature inside the plasma chamber is controlled to be uniform over time, achieving etch uniformity in processes such as etching wafers inside the plasma chamber. Furthermore, better chamber-to-chamber and intra-chamber repeatability of substrate processing is achieved due to real-time compensation for variations in the amount of voltage supplied by the power supply.

[0015] Other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0016] The embodiments may be best understood by referring to the following description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0017] [Figure 1A] FIG. 1 is a diagram of an embodiment of a system illustrating real-time control of temperature by controlling multiple heater elements in real time.

[0018] [Figure 1B] 1 is a system embodiment illustrating real-time control of temperature by controlling a heater element in real time.

[0019] [Figure 2] FIG. 1 illustrates an embodiment of a voltage sensor.

[0020] [Figure 3]1 shows several tables of an embodiment illustrating the correspondence between the temperature inside the plasma chamber, the nominal voltage generated by the voltage source, the duty cycle of the heater element, and the adjusted duty cycle of the heater element.

[0021] [Figure 4A] 10 is a graph of an embodiment illustrating adjusting the duty cycle or adjusted duty cycle in real time.

[0022] [Figure 4B] 10 is a graph of an embodiment illustrating adjusting the duty cycle or adjusted duty cycle in real time.

[0023] [Figure 5] 1 is a diagram of an embodiment of a plasma system illustrating the use of heater elements within the plasma system.

[0024] [Figure 6] FIG. 1 is a diagram of an embodiment of a system illustrating the use of a heater element within a showerhead of a plasma chamber.

[0025] [Figure 7] FIG. 1 is a diagram of an embodiment of a system illustrating the use of a heater element within an inductively coupled plasma (ICP) chamber.

[0026] [Figure 8] 6 is a diagram of an embodiment of a system illustrating chamber-to-chamber matching to achieve the same temperature values ​​within the plasma chamber as are achieved within the plasma chamber of FIG. 5. DETAILED DESCRIPTION OF THE INVENTION

[0027] The following embodiments describe systems and methods for real-time control of temperature in a plasma chamber. It will be apparent that the embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail in order to not unnecessarily obscure the embodiments.

[0028] FIG. 1A is a diagram of an embodiment of a system 100 illustrating real-time temperature control by controlling multiple heater elements HE1, HE2, HE3, and HE4 in real time. System 100 is an example of a wafer processing system. System 100 includes a voltage source Vs, an electrode assembly 101, a multiplexer 106, a non-volatile memory 116, and a user interface system (UIS) 112. As used herein, the multiplexer is fabricated as a printed circuit board assembly (PCBA). For example, the terms multiplexer and PCBA are used interchangeably herein. Examples of non-volatile memory, as used herein, include flash memory and ferroelectric random access memory (RAM). Examples of voltage source Vs include a power supply. For illustrative purposes, voltage source Vs provides a certain amount of voltage. Examples of electrode assembly 101 include a substrate support, a chuck, a showerhead, and an upper electrode assembly. The upper electrode assembly includes an upper electrode and other components, such as a dielectric surrounding the upper electrode and an upper electrode extension surrounding the dielectric. Examples of user interface system 112 include a host computer, a desktop computer, a laptop computer, a smartphone, and a server.

[0029] The electrode assembly 101 includes a plurality of switches Sx1, Sx2, Sy1, and Sy2. In addition, the electrode assembly 101 includes a plurality of buses x1, x2, y1, and y2, which include heater elements HE1-HE4. An example of a heater element, as used herein, is a resistor. An example of a bus, as used herein, is a conductor such as a wire. An example of a switch, as used herein, is a relay. As another example, a switch, as used herein, includes one or more transistors coupled to each other.

[0030] The voltage source Vs is coupled to ground potential in several ways: via rail 102, bus y1, switch Sy1, heater element HE1, bus x1, and switch Sx1; via rail 102, bus y2, switch Sy2, heater element HE2, bus x1, and switch Sx1; via rail 102, bus y1, switch Sy1, heater element HE3, bus x2, and switch Sx2; via rail 102, bus y2, switch Sy2, heater element HE4, bus x2, and switch Sx2.

[0031] In some embodiments, the voltage source Vs is loosely adjusted. To illustrate, the voltage source Vs is designed to generate a voltage value Vnominal1 to provide a range of voltage quantities. The voltage value Vnominal1 is an example of mapping information. The range of voltage quantities may be outside of the range of specified voltage quantities. In one example, the specified range follows a specification that can be written onto another voltage source that is tightly adjusted to operate within the specified range.

[0032] In various embodiments, the voltage source Vs is not regulated. As one example, there is no need to include a parameter regulator within the voltage source Vs or to couple a parameter regulator to the voltage source Vs to regulate the amount of voltage that the voltage source Vs provides so that it is within a specified range. To further illustrate, the voltage source Vs excludes a parameter regulator. A parameter regulator, when used in conjunction with or within the voltage source Vs, regulates the amount of voltage that the voltage source Vs provides so that it is within a specified range.

[0033] The multiplexer 106 includes a switch circuit 108, a processor 104, and a sensor 114. The processor 104 is coupled to the switch circuit 108 and the sensor 114. The sensor 114 is coupled to a point on the rail 102 that is coupled to a voltage source Vs. The rail 102 is coupled between a bus y1 and the voltage source Vs and between a bus y2 and the voltage source Vs. The rail 102 is coupled to buses y1 and y2. The switch circuit 108 is coupled to a switch Sy1 via a line Ly1, to a switch Sy2 via a line Ly2, to a switch Sx1 via a line Lx1, and to a switch Sx2 via a line Lx2. An example of a line, as used herein, is a conductor such as a wire.

[0034] As used herein, a processor is an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA), or a programmable logic device (PLD), or a central processing unit (CPU), or a microprocessor, or a digital signal processor, or a microcontroller. Examples of memory elements, as used herein, include random access memory (RAM) and read-only memory (ROM). For illustrative purposes, memory elements include flash memory, hard disks, or storage devices. A memory element is an example of a computer-readable medium. An example of switch circuit 108 includes a circuit including multiple switches (not shown), such as tri-state buffers or tri-state transistors. An example of sensor 114 includes a voltage sensor that senses the voltage provided by voltage source Vs at a point on rail 102. The sensed voltage is therefore related to the voltage provided by voltage source Vs. Another example of the sensor 114 includes a combination of a current sensor and a resistor coupled to the current sensor. The current sensor senses the current generated from the voltage supplied by the voltage source Vs to the rail 102. The resistor coupled to the current sensor senses the voltage at a point on the rail 102 by measuring the voltage across the resistor generated from the current. Voltage is an example of a parameter.

[0035] The user interface system 112 includes a processor 110, a memory device 118, and a display device 120. Examples of the display device 120 include a liquid crystal display, a light-emitting diode display, and a plasma display. The non-volatile memory 116 is coupled to the processor 110 via a transmission cable. The processor 110 is coupled to the memory device 118 and the display device 120 via one or more buses. Additionally, the processor 110 is coupled to the processor 104 of the multiplexer 106 via a transmission cable 122. Examples of a transmission cable, as used herein, include a parallel transmission cable that facilitates parallel transmission of data between the processors 104 and 110, a serial transmission cable that facilitates serial transmission of data, and a universal serial bus (USB) cable.

[0036] The non-volatile memory 116 includes one or more mappings, such as one-to-one relationships, correspondences, links, or unique relationships, between temperature values ​​to be achieved within the plasma chamber, duty cycles for the operation of the heater elements HE1-HE4, and nominal values ​​for the voltages generated by the voltage source Vs. An example of a mapping is provided in FIG. 3. As used herein, a mapping is sometimes referred to herein as mapping information. As illustrated in mapping 306, to achieve a temperature value Temp1 within the plasma chamber including the heater elements HE1-HE4, the voltage source Vs should be operated to generate a nominal voltage amount Vnominal1, the heater element HE1 should be operated at a duty cycle DC1, the heater element HE2 should be operated at a duty cycle DC2, the heater element HE3 should be operated at a duty cycle DC3, and the heater element HE4 should be operated at a duty cycle DC4. As another example, to achieve a temperature value Temp2 within a plasma chamber including heater elements HE1-HE4, as illustrated in mapping 308, voltage source Vs should be operated to generate a nominal voltage amount Vnominal1, heater element HE1 should be operated at a duty cycle DC11, heater element HE2 should be operated at a duty cycle DC21, heater element HE3 should be operated at a duty cycle DC31, and heater element HE4 should be operated at a duty cycle DC41. In various embodiments, the terms map and mapping are used interchangeably herein. Each temperature Temp1 and Temp2 is an example of a target temperature.

[0037] It should be noted that in some embodiments, one or more of the duty cycles DC11-DC41 at which heater elements HE1-HE4 are operated to achieve temperature Temp2 in the two preceding examples above are changed to a corresponding one or more of the duty cycles DC1-DC4 at which heater elements HE1-HE4 are operated to achieve temperature Temp1. For example, to achieve temperature Temp2, instead of DC11, heater element HE1 is operated at duty cycle DC1, and instead of DC21, heater element HE2 is operated at duty cycle DC2.

[0038] It is further noted that the non-volatile memory 116 is pre-loaded with a mapping specific to the corresponding electrode assembly 101 upon delivery of the electrode assembly 101 to a user. For example, the mapping stored in the non-volatile memory 116 may be specific to the electrode assembly 101 having heater elements HE1-HE4 and may be different for another electrode assembly having a different set of heater elements. As another example, the duty cycles DC1-DC4 are pre-calibrated at the factory that fabricates the electrode assembly 101, assuming that the voltage source Vs generates and supplies a voltage at a constant value, such as a nominal value Vnominal1. Information regarding the off and on periods of the duty cycles DC1-DC4 is calculated and stored in the non-volatile memory 116 at the factory prior to delivery to a user.

[0039] It should be noted that in some embodiments, the terms storing and maintaining are used interchangeably herein, for example, the mapping information is maintained within the memory element by being stored in the memory element.

[0040] The processor 110 receives one or more mapping information, such as mappings 306 and 308, from the non-volatile memory 116, e.g., accesses the mapping information, and identifies, from the one or more mapping information, duty cycles DC1-DC4 at which to operate the heater elements HE1-HE4 to achieve a temperature value Temp1. The voltage source Vs can generate a nominal voltage value Vnominal1 to achieve the temperature value Temp1. The temperature value Temp1 is to be achieved as part of a recipe for processing a substrate inside the plasma chamber. As used herein, examples of a substrate include a semiconductor wafer, which may be a test wafer or a wafer to be processed. For example, the substrate may include multiple stacked layers overlaid on a substrate layer, such as silicon. The recipe includes other values, such as the operating frequency of a radio frequency (RF) generator, the operating power level of the RF generator, the gap between the upper and lower electrodes inside the plasma chamber, the amount of pressure inside the plasma chamber, and the chemistry of the process gases supplied inside the plasma chamber. The processor 110 accesses the recipe stored in the memory device 118 and controls the RF generator and the plasma chamber according to the recipe to execute the recipe.

[0041] During substrate processing within the plasma chamber, voltage source Vs generates a nominal voltage value Vnominal1 to supply to one or more of heater elements HE1-HE4 via rail 102. Furthermore, during substrate processing, processor 110 identifies from the recipe that a temperature value Temp1 should be achieved within the plasma chamber. As the substrate is being processed, processor 110 sends one or more duty cycle control signals to processor 104 to control heater elements HE1-HE4 to achieve respective duty cycles DC1-DC4 of heater elements HE1-HE4. The one or more duty cycle control signals include frequencies for opening and closing switches Sx1, Sx2, Sy1, and Sy2 to achieve duty cycles DC1-DC4. Upon receiving the one or more duty cycle control signals, processor 104 generates a number of duty cycle selection signals and sends the duty cycle selection signals to switch circuit 108 to instruct or control switch circuit 108.

[0042] In response to receiving the duty cycle selection signal, the switch circuit 108 manages the opening and closing of the switches Sy1, Sy2, Sx1, and Sx2 to accordingly achieve the desired duty cycles DC1-DC4. For example, when a first switch of the switch circuit 108 is closed and the remaining three switches of the switch circuit 108 are opened, a first duty cycle selection signal of the duty cycle selection signal is transmitted to the switch Sy1 via the first switch of the switch circuit 108 and the line Ly1 to close the switch Sy1. Also, when a second switch of the switch circuit 108 is closed and the remaining three switches of the switch circuit 108 are opened, a second duty cycle selection signal of the duty cycle selection signal is transmitted to the switch Sy2 via the second switch of the switch circuit 108 and the line Ly2 to close the switch Sy2. Furthermore, when the third switch of the switch circuit 108 is closed and the remaining three switches of the switch circuit 108 are opened, a third duty cycle selection signal of the duty cycle selection signals is transmitted to the switch Sx1 via the third switch of the switch circuit 108 and the line Lx1, thereby closing the switch Sx1. When the fourth switch of the switch circuit 108 is closed and the remaining three switches of the switch circuit 108 are opened, a fourth duty cycle selection signal of the duty cycle selection signals is transmitted to the switch Sx2 via the fourth switch of the switch circuit 108 and the line Lx2, thereby closing the switch Sx2.

[0043] All switches in the switch circuit 108 remain open until a duty cycle selection signal is received. For example, during a period when a first duty cycle selection signal is not received from the processor 104, the first switch in the switch circuit 108 remains open. During a period when the first switch in the switch circuit 108 remains open, the switch Sy1 also remains open. As another example, during a period when a second duty cycle selection signal is not received from the processor 104, the second switch in the switch circuit 108 remains open. During a period when the second switch in the switch circuit 108 remains open, the switch Sy2 also remains open. As yet another example, during a period when a third duty cycle selection signal is not received from the processor 104, the third switch in the switch circuit 108 remains open. During a period when the third switch in the switch circuit 108 remains open, the switch Sx1 also remains open. As yet another example, during a period when a fourth duty cycle selection signal is not received from the processor 104, the fourth switch in the switch circuit 108 remains open. During the period that the fourth switch of the switch circuit 108 remains open, the switch Sx2 also remains open.

[0044] The first and third duty cycle select signals are received to transmit a nominal voltage generated by voltage source Vs through rail 102, bus y1, switch Sy1, heater element HE1, bus x1, and switch Sx1 to ground potential during the period when switches Sy1 and Sx1 are closed to achieve an on-period of duty cycle DC1. By way of example, the on-period of a duty cycle is the duration of a clock cycle as a percentage of the clock cycle during which the on-period occurs. In this example, the on-period of a duty cycle defines the duty cycle as a percentage of the clock cycle.

[0045] Similarly, during the period when switch Sy1 or Sx1 is open, the nominal voltage generated by voltage source Vs is not transmitted to ground via rail 102, bus y1, switch Sy1, heater element HE1, bus x1, and switch Sx1, thereby achieving an off-period associated with duty cycle DC1. By way of example, an off-period associated with a duty cycle is the period of a clock cycle as a percentage of the clock cycle during which the off-period occurs. Continuing with this example, the off-period of a clock cycle's duty cycle continuously follows the duty cycle of the clock cycle. In this example, the duty cycle of the clock cycle precedes the off-period of the clock cycle, and the duty cycle is the on-period of the clock cycle. For illustrative purposes, the off-period of a duty cycle defines the remaining portion of the clock cycle during which no on-period occurs. In some embodiments, the terms “off-period associated with a duty cycle” and “off-period of a duty cycle” are used interchangeably herein.

[0046] Further, second and third duty cycle selection signals are received to transmit the nominal voltage generated by voltage source Vs to ground potential via rail 102, bus y2, switch Sy2, heater element HE2, bus x1, and switch Sx1 while switches Sy2 and Sx1 are closed, thereby achieving an on period of duty cycle DC2. Similarly, during a period when switch Sy2 or Sx1 is open, the nominal voltage generated by voltage source Vs is not transmitted to ground potential via rail 102, bus y2, switch Sy2, heater element HE2, bus x1, and switch Sx1, thereby achieving an off period of duty cycle DC2.

[0047] The first and fourth duty cycle selection signals are also received to transmit the nominal voltage generated by voltage source Vs to ground potential via rail 102, bus y1, switch Sy1, heater element HE3, bus x2, and switch Sx2 during a period when switches Sy1 and Sx2 are closed, thereby achieving an on period of duty cycle DC3. Similarly, during a period when switch Sy1 or Sx2 is open, the nominal voltage generated by voltage source Vs is not transmitted to ground potential via rail 102, bus y1, switch Sy1, heater element HE3, bus x2, and switch Sx2, thereby achieving an off period of duty cycle DC3.

[0048] Furthermore, second and fourth duty cycle selection signals are received to transmit the nominal voltage generated by voltage source Vs to ground potential via rail 102, bus y2, switch Sy2, heater element HE4, bus x2, and switch Sx2 during a period when switches Sy2 and Sx2 are closed, thereby achieving an on period of duty cycle DC4. Similarly, during a period when switch Sy2 or Sx2 is open, the nominal voltage generated by voltage source Vs is not transmitted to ground potential via rail 102, bus y2, switch Sy2, heater element HE4, bus x2, and switch Sx2, thereby achieving an off period of duty cycle DC4.

[0049] During a period when voltage source Vs is generating a nominal voltage amount Vnominal1 to achieve a temperature value Temp1 and heater elements HE1-HE4 are operating at corresponding duty cycles DC1-DC4, sensor 114 measures voltage Vsense1 present on rail 102. Sensor 114 then provides information about voltage Vsense1 to processor 104. For example, processor 104 polls sensor 114 to obtain information about voltage Vsense1 obtained from sensor 114. Processor 104 periodically or continuously polls sensor 114 in real time to obtain information about a plurality of measured voltages. To illustrate, processor 104 polls, e.g., sends a polling signal, sensor 114 every few microseconds or every few milliseconds. It should be noted that one microsecond or more is an example of several microseconds, and one millisecond or more is an example of several milliseconds. It should be noted that in some embodiments, the terms periodically and on a periodic basis are used interchangeably herein.

[0050] In response to receiving a polling signal from processor 104, sensor 114 provides information regarding voltage Vsense1 to processor 104. Processor 104 then transmits information regarding voltage Vsense1 to processor 110.

[0051] Upon receiving information regarding the voltage Vsense1, the processor 110 calculates adjusted duty cycles (ADC) for the heater elements HE1-HE4 from the duty cycles DC1-DC4, the nominal voltage Vnominal1 generated by the voltage source Vs, and the voltage Vsense1, if any. For example, the processor 110 calculates the adjusted duty cycle ADC1 for the heater element HE1 to be the product of the duty cycle DC1 and the square of the ratio of the voltage value Vnominal1 to the voltage Vsense1. To illustrate, the adjusted duty cycle ADC1 may be calculated as (Vnominal1 / Vsense1). 2×DC1. As another example, processor 110 calculates an adjusted duty cycle ADC2 for heater element HE2 to be the product of duty cycle DC2 and the square of the ratio of voltage value Vnominal1 to voltage Vsense1. To illustrate, adjusted duty cycle ADC2 is equal to (Vnominal1 / Vsense1). 2 ×DC2. As yet another example, processor 110 calculates an adjusted duty cycle ADC3 for heater element HE3 to be the product of duty cycle DC3 and the square of the ratio of voltage value Vnominal1 to voltage Vsense1. To illustrate, adjusted duty cycle ADC3 is equal to (Vnominal1 / Vsense1). 2 ×DC3. As yet another example, processor 110 calculates an adjusted duty cycle ADC4 for heater element HE4 to be the product of duty cycle DC4 and the square of the ratio of voltage value Vnominal1 to voltage Vsense1. To illustrate, adjusted duty cycle ADC4 is equal to (Vnominal1 / Vsense1). 2 ×DC4.

[0052] After calculating the adjusted duty cycles ADC1-ADC4, processor 110 transmits one or more adjusted duty cycles to processor 104 to control heater element HE1 to achieve adjusted duty cycle ADC1, heater element HE2 to achieve adjusted duty cycle ADC2, heater element HE3 to achieve adjusted duty cycle ADC3, and heater element HE4 to achieve adjusted duty cycle ADC4. For example, processor 110 generates and transmits one or more adjusted duty cycle control signals to processor 104 within a few microseconds, such as one microsecond or more, after transmitting the one or more duty cycle control signals. As another example, processor 110 generates and transmits one or more adjusted duty cycle control signals to processor 104 within a few milliseconds, such as one millisecond or more, after transmitting the one or more duty cycle control signals. Duty cycles DC1-DC4 are adjusted in real time by adjusting one or more of duty cycles DC1-DC4 every few milliseconds or microseconds. Furthermore, the duty cycles DC1-DC4 are adjusted in real time by adjusting one or more of the duty cycles DC1-DC4 while a substrate is being processed inside the plasma chamber. Upon receiving the one or more duty cycle control signals from the processor 110, the processor 104 generates and transmits a plurality of adjusted duty cycle selection signals and transmits the adjusted duty cycle selection signals to the switch circuit 108 to instruct the switch circuit 108. The one or more adjusted duty cycle control signals include frequencies for opening and closing the switches Sx1, Sx2, Sy1, and Sy2 to achieve the duty cycles ADC1-ADC4.

[0053] In response to receiving the adjusted duty cycle selection signals, the switch circuit 108 closes some of its switches and keeps the remaining switches open to achieve the adjusted duty cycles ADC1-ADC4. For example, when a first switch of the switch circuit 108 is closed, a first adjusted duty cycle selection signal of the adjusted duty cycle selection signals is transmitted to the first switch of the switch circuit 108 and the line Ly1 to the switch Sy1, thereby closing the switch Sy1. When a second switch of the switch circuit 108 is closed, a second adjusted duty cycle selection signal of the adjusted duty cycle selection signals is transmitted to the second switch of the switch circuit 108 and the line Ly2 to the switch Sy2, thereby closing the switch Sy2. When a third switch of the switch circuit 108 is closed, a third adjusted duty cycle selection signal of the adjusted duty cycle selection signals is transmitted to the third switch of the switch circuit 108 and the line Lx1 to the switch Sx1, thereby closing the switch Sx1. When the fourth switch of the switch circuit 108 is closed, a fourth adjusted duty cycle selection signal of the adjusted duty cycle selection signals is transmitted to the fourth switch of the switch circuit 108 and the line Lx2 to the switch Sx2, thereby closing the switch Sx2.

[0054] The switch of the switch circuit 108 remains open until it receives an adjusted duty cycle selection signal. For example, during a period when the first adjusted duty cycle selection signal is not received from the processor 104, the first switch of the switch circuit 108 remains open. During a period when the first switch of the switch circuit 108 remains open, the switch Sy1 also remains open. As another example, during a period when the second adjusted duty cycle selection signal is not received from the processor 104, the second switch of the switch circuit 108 remains open. During a period when the second switch of the switch circuit 108 remains open, the switch Sy2 also remains open. As yet another example, during a period when the third adjusted duty cycle signal is not received from the processor 104, the third switch of the switch circuit 108 remains open. During a period when the third switch of the switch circuit 108 remains open, the switch Sx1 also remains open. As yet another example, the fourth switch of the switch circuit 108 remains open during a period of time when the fourth adjusted duty cycle selection signal is not received from the processor 104. During the period in which the fourth switch of the switch circuit 108 remains open, the switch Sx2 remains open.

[0055] ADC1 receives the first and third adjusted duty cycle select signals and transmits a nominal voltage generated by voltage source Vs to ground potential via rail 102, bus y1, switch Sy1, heater element HE1, bus x1, and switch Sx1 during the period when switches Sy1 and Sx1 are closed to achieve an on-period of adjusted duty cycle ADC1. As an example, the on-period of the adjusted duty cycle is the duration of a clock cycle as a percentage of the clock cycle in which the on-period occurs. For illustrative purposes, the on-period of the adjusted duty cycle defines the adjusted duty cycle as a percentage of the clock cycle.

[0056] Similarly, during the period when switches Sy1 and Sx1 are open, the nominal voltage generated by voltage source Vs is not transmitted to ground potential via rail 102, bus y1, switch Sy1, heater element HE1, bus x1, and switch Sx1 to achieve the off-period associated with adjusted duty cycle ADC1. As an example, the off-period associated with the adjusted duty cycle is the period of the clock cycle as a percentage of the clock cycle during which the off-period occurs. Continuing with this example, the off-period of the adjusted duty cycle of the clock cycle continuously follows the adjusted duty cycle of the clock cycle. In this example, the adjusted duty cycle of the clock cycle precedes the off-period of the clock cycle, and the adjusted duty cycle is the on-period of the clock cycle. For illustrative purposes, the off-period of the adjusted duty cycle defines the remaining portion of the clock cycle during which the on-period of the adjusted duty cycle does not occur. In some embodiments, the terms “off-period associated with the adjusted duty cycle” and “off-period of the adjusted duty cycle” are used interchangeably herein.

[0057] Furthermore, the second and third adjusted duty cycle select signals are received to transmit the nominal voltage generated by the voltage source Vs to ground potential via the rail 102, bus y2, switch Sy2, heater element HE2, bus x1, and switch Sx1 during the period when switches Sy2 and Sx1 are closed, thereby achieving an on period of the adjusted duty cycle ADC2. Similarly, the nominal voltage generated by the voltage source Vs is not transmitted to ground potential via the rail 102, bus y2, switch Sy2, heater element HE2, bus x1, and switch Sx1 during the period when switch Sy2 or Sx1 is open, thereby achieving an off period of the adjusted duty cycle ADC2.

[0058] Also, the first and fourth adjusted duty cycle selection signals are received to transmit the nominal voltage generated by the voltage source Vs to ground potential via the rail 102, bus y1, switch Sy1, heater element HE3, bus x2, and switch Sx2 during the period when switches Sy1 and Sx2 are closed, thereby achieving an on period of the adjusted duty cycle ADC3. Similarly, during the period when switch Sy1 or Sx2 is open, the nominal voltage generated by the voltage source Vs is not transmitted to ground potential via the rail 102, bus y1, switch Sy1, heater element HE3, bus x2, and switch Sx2, thereby achieving an off period of the adjusted duty cycle ADC3.

[0059] Further, the second and fourth adjusted duty cycle selection signals are received to transmit the nominal voltage generated by the voltage source Vs to ground potential via rail 102, bus y2, switch Sy2, heater element HE4, bus x2, and switch Sx2 during the period when switches Sy2 and Sx2 are closed, thereby achieving the on period of the adjusted duty cycle ADC4. Similarly, the nominal voltage generated by the voltage source Vs is not transmitted to ground potential via rail 102, bus y2, switch Sy2, heater element HE4, bus x2, and switch Sx2 during the period when switch Sy2 or Sx2 is open, thereby achieving the off period of the adjusted duty cycle ADC4. The duty cycles DC1-DC4 are modified, e.g., increased or decreased, to the corresponding adjusted duty cycles ADC1-ADC4 to achieve the temperature value Temp1 of the recipe for processing the substrate. The probability of achieving the temperature value Temp1 using one or more of the adjusted duty cycles ADC1-ADC4 is substantially higher compared to the probability of achieving the temperature value Temp1 using duty cycles DC1-DC4.

[0060] In this manner, after receiving an initial voltage value Vsense1, the processor 110 continues to receive additional measurements, such as Vsense, of the voltage measured by the sensor 114 on the rail 102 and applies the additional measurements to modify, e.g., increase or decrease, the adjusted duty cycles ADC1-ADC4 of the corresponding heater elements HE1-HE4 to achieve a temperature Temp1 within the plasma chamber for processing a substrate. The duty cycles ADC1-ADC4 are adjusted in real time by adjusting one or more of the adjusted duty cycles ADC1-ADC4 every few milliseconds or microseconds. Furthermore, the duty cycles ADC1-ADC4 are adjusted in real time by adjusting one or more of the duty cycles ADC1-ADC4 while a substrate is being processed within the plasma chamber.

[0061] In some embodiments, real-time adjustments to one or more of the duty cycles DC1-DC4 or real-time adjustments to one or more of the adjusted duty cycles ADC1-ADC4 can be performed without processing any substrates. Such adjustments may be performed to retune or recalibrate the plasma chamber. For example, the plasma chamber may be cleaned by adjusting one or more of the duty cycles DC1-DC4 and applying a corresponding one or more of the adjusted duty cycles ADC1-ADC4 in real time, or by adjusting one or more adjusted duty cycles ADC1-ADC4 in real time. In this example, the plasma chamber excludes substrates.

[0062] In some embodiments, the electrode assembly 101 includes any number of heater elements, any number of switches, and any number of buses. For example, the electrode assembly 101 includes 144 heater elements. As another example, the electrode assembly 101 includes 100 heater elements.

[0063] In various embodiments, instead of ground potential, a reference potential, such as a positive or negative potential amount, is used, the positive or negative potential amount being less than the potential of the voltage source Vs.

[0064] In some embodiments, the voltage source Vs includes a parameter regulator.

[0065] In some embodiments, instead of the switch of switch circuit 108 closing upon receiving a duty cycle select signal or an adjusted duty cycle select signal from processor 104, the switch of switch circuit 108 opens upon receiving a plurality of duty cycle deselect signals or adjusted duty cycle deselect signals from processor 104. The switch of switch circuit 108 remains closed during periods when no duty cycle deselect signals are received from processor 104. Similarly, the switch of switch circuit 108 remains closed during periods when no adjusted duty cycle deselect signals are received from processor 104.

[0066] Additionally, in some embodiments, one or more of the operations described herein as being performed by processor 110 to calculate adjusted duty cycles ADC1-ADC4 and control or instruct switch circuit 108 to implement adjusted duty cycles ADC1-ADC4 are performed by processor 104. For example, instead of processor 110 calculating adjusted duty cycles ADC1-ADC4 from corresponding duty cycles DC1-DC4, processor 104 of multiplexer 106 calculates adjusted duty cycles ADC1-ADC4 in the same manner as processor 110 calculates adjusted duty cycles ADC1-ADC4, without generating any duty cycle control signals or adjusted duty cycle control signals. Rather, processor 104 generates duty cycle selection signals or adjusted duty cycle selection signals to control or instruct switch circuit 108 to vary duty cycles DC1-DC4 or to vary adjusted duty cycles ADC1-ADC4. Also, in these embodiments, processor 104 receives mappings, such as mapping 306 and / or mapping 308, from processor 110 for storage in and access to a memory device coupled to processor 104.

[0067] In some embodiments, instead of a single sensor 114, multiple sensors, such as sensor 114, are used to sense voltage at rail 102 in real time. The voltage values ​​sensed by the multiple sensors are provided to a processor, such as processor 104 or 110, which calculates multiple adjusted duty cycles from the duty cycle of one of heater elements HE1-HE4 based on multiple voltage values ​​measured at rail 102. Processor 104 or 110 generates a statistically adjusted duty cycle, such as an average or median, from the multiple calculated adjusted duty cycles and implements the statistically adjusted duty cycle for one of heater elements HE1-HE4. For example, the statistically adjusted duty cycle is applied to one of heater elements HE1-HE4. Similarly, additional statistically adjusted duty cycles for the remaining heater elements HE1-HE4 are created or calculated and applied to one or more of the remaining heater elements.

[0068] In various embodiments, the sensor 114 is located outside the multiplexer 106 and is positioned between the multiplexer 106 and the rail 102. The sensor 114 is coupled to the processor 104 at one end of the sensor 114 and to a point on the rail 102 at another end of the sensor 114.

[0069] 1B is an embodiment of a system 150 illustrating real-time control of temperature by controlling multiple heater elements HE1, HE2, HE3, and HE4 in real time. System 150 is another example of a wafer processing system. System 150 is structurally similar to system 100 of FIG. 1A, except that in system 150, sensor 114 is located within user interface system 112 instead of within multiplexer 106. Additionally, in system 150, processor 110 is coupled to sensor 114 to receive a voltage value, Vsense1, from sensor 114.

[0070] The sensor 114 provides the voltage value Vsense1 to the processor 110 on behalf of the processor 104. For example, the processor 110 polls the sensor 114 to obtain the voltage quantity Vsense1. The processor 110 may periodically or continuously poll the sensor 114 in real time to obtain multiple measured voltage quantities, such as Vsense. To illustrate, the processor 110 may poll the sensor 114 every few microseconds or every few milliseconds, e.g., send a polling signal to the sensor 114. In response to receiving the polling signal from the processor 110, the sensor 114 provides the voltage quantity Vsense1 to the processor 110. Upon receiving the voltage value Vsense1 from the sensor 114, the processor 110 calculates adjusted duty cycles ADC1-ADC4 to achieve a temperature value Temp1 within the plasma chamber. The remaining operation of the system 150, similar to the operation of the system 100 of FIG. 1A, achieves the temperature Temp1 within the plasma chamber.

[0071] In some embodiments, processor 104 or processor 110 of sensor 114 need not poll at all. For example, sensor 114 periodically or continuously measures the amount of voltage sensed at rail 102 in real time and transmits the amount of voltage sensed at rail 102 to processor 110 or processor 104, without processor 104 or processor 110 requesting it. To illustrate, sensor 114 transmits the amount of voltage sensed at rail 102 to processor 104 or processor 110 every few microseconds or every few milliseconds.

[0072] In some embodiments, instead of being coupled to processor 110, non-volatile memory 116 is coupled to processor 104. A mapping is provided from non-volatile memory 116 to processor 104 for calculating one or more of the adjusted duty cycles ADC1-ADC4.

[0073] In various embodiments, the sensor 114 is located outside the user interface system 112 and is positioned between the user interface system 112 and the rail 102. The sensor 114 is coupled to the processor 110 at one end of the sensor 114 and to a point on the rail 102 at another end of the sensor 114.

[0074] 2 is a diagram of an embodiment of a voltage sensor 204, which is an example of the sensor 114 of FIGS. 1A and 1B. The voltage sensor 204 is integrated within an integrated circuit chip 202. The voltage sensor 204 is connected to the rail 102 via the 204 to a voltage source Vs to sense the voltage provided by the voltage source Vs at a point on the rail 102. The voltage sensor 204 includes a resistor Rx, another resistor Ry, and an analog-to-digital converter (ADC). The resistor Ry is coupled to ground potential. The analog-to-digital converter ADC is coupled to a point 206 between the resistors Rx and Ry, providing a resistive divider. The resistor Rx drops the voltage provided by the voltage source Vs to a measurable quantity. The analog-to-digital converter ADC converts the voltage quantity at point 206 from analog to digital form and transmits the voltage quantity in digital form to the processor 104 of the multiplexer 106 or to the processor 110 of the user interface system 112. The voltage quantity at point 206 is an example of a voltage quantity, such as Vsense or Vsense1 or Vsense2 (FIG. 3), sensed by the sensor 114.

[0075] 3 shows an embodiment of tables 302 and 304 illustrating correspondences between temperatures within the plasma chamber, nominal voltages generated by voltage source Vs, corresponding duty cycles of heater elements HE1-HE4, and adjusted duty cycles of corresponding heater elements HE1-HE4. Table 302 is stored within memory element 118 of user interface system 112. Similarly, table 304 is stored within memory element 118.

[0076] Table 302 includes a mapping 306. A processor, such as processor 110 or processor 104, described herein, calculates adjusted duty cycles ADC1-ADC4 from mapping 306 and the voltage quantity Vsense1 provided by voltage source Vs and measured by sensor 114. Further, a processor, described herein, stores the adjusted duty cycles ADC1-ADC4 in table 302.

[0077] 1A or 1B senses a voltage value Vsense2 during periods when heater elements HE1-HE4 operate at corresponding duty cycles DC11-DC41. For example, sensor 114 senses a voltage value Vsense2 at rail 102 when heater element HE1 operates at duty cycle DC11, heater element HE2 operates at duty cycle DC21, heater element HE3 operates at duty cycle DC31, and heater element HE4 operates at duty cycle DC41. Processor 110 or 104 calculates a plurality of adjusted duty cycles ADC11, ADC21, ADC31, and ADC41 from the voltage value Vnominal1, the measured value Vsense2, and the corresponding duty cycles DC11-DC41 in the same manner as it calculates adjusted duty cycles ADC1-ADC4 from the corresponding duty cycles DC1-DC4, the voltage value Vnominal1, and the measured voltage value Vsense1. Processor 110 stores the adjusted duty cycles ADC11-ADC41 in memory element 118 of FIG. 1A of user interface system 112, or processor 110 stores the adjusted duty cycles ADC11-ADC41 in memory element 118 of FIG. 104 is the processor 104The processor 110 or 104 stores the adjusted duty cycles ADC11-ADC41 in a memory device (not shown) coupled to the switch circuit 108. In the same manner as the processor 110 or 104 controls or directs the switch circuit 108 to operate the heater elements HE1-HE4 at the corresponding adjusted duty cycles ADC11-ADC41 to achieve the temperature value Temp1, the processor 110 or 104 controls or directs the switch circuit 108 to operate the heater elements HE1-HE4 at the corresponding adjusted duty cycles ADC11-ADC41 to achieve the temperature value Temp2 within the plasma chamber.

[0078] In some embodiments, the processor 104 of the multiplexer 106 is coupled to a memory device (not shown), and the tables 302 and 304 are stored within the memory device (not shown).

[0079] FIG. 4A is an embodiment of a graph 402 illustrating adjusting duty cycles DC1-DC4 or adjusted duty cycles ADC1-ADC4 in real time. Graph 402 plots the duty cycle of a heater element, such as heater element HE1 or HE2 or HE3 or HE4, versus time t in milliseconds. Graph 402 includes plot 404. As illustrated in graph 402, the heater element operates at a 60% duty cycle for a 1 millisecond period from time 0 milliseconds to time 1 millisecond. The 60% duty cycle is an example of any of duty cycles DC1-DC4. The 60% duty cycle is then adjusted to achieve an adjusted 50% duty cycle. The adjusted 50% duty cycle is an example of any of duty cycles ADC1-ADC4. The adjusted 50% duty cycle is maintained for a 1 millisecond period from time 1 millisecond to time 2 milliseconds.

[0080] The adjusted duty cycle of 50% is then further adjusted to achieve another adjusted duty cycle of 70%. Another adjusted duty cycle of 70% is maintained for a period of 1 millisecond between a time of 2 milliseconds and a time of 3 milliseconds. Thereafter, another adjusted duty cycle of 70% is then adjusted to achieve an additional adjusted duty cycle of 40%. An additional adjusted duty cycle of 40% is maintained for a period of 1 millisecond between a time of 3 milliseconds and a time of 4 milliseconds. Thus, the duty cycle of the heater element is adjusted every millisecond, or the adjusted duty cycle is adjusted every millisecond.

[0081] Note that milliseconds are used as examples herein, and in some embodiments, the duty cycle of the heater element, or the adjusted duty cycle of the heater element, is adjusted every few milliseconds, such as every 2 milliseconds or every 3 milliseconds.

[0082] In various embodiments, the duty cycle is adjusted to an adjusted duty cycle within a range of a different time period than the time period for adjusting the adjusted duty cycle. For example, the duty cycle DC1 is adjusted to an adjusted duty cycle ADC1 within a range of 1 millisecond, and the adjusted duty cycle ADC1 is adjusted to another adjusted duty cycle within a range of 2 milliseconds. As another example, the adjusted duty cycle ADC1 is adjusted to another adjusted duty cycle within a range of 1 millisecond, and the other adjusted duty cycle is adjusted to an additional adjusted duty cycle within a range of 1.5 milliseconds.

[0083] The duty cycle or adjusted duty cycle is adjusted in real time by adjusting the duty cycle or adjusted duty cycle within a range of 1 millisecond or more.

[0084] While a large amount of fluctuation in the duty cycle or adjusted duty cycle is illustrated in Figure 4A, note that in some embodiments, the duty cycle or adjusted duty cycle changes by 5% to 10% every millisecond or every few milliseconds. For a large amount of fluctuation to occur, the voltage measurement provided by voltage source Vs and sensed by sensor 114 in Figures 1A and 1B will fluctuate significantly.

[0085] 4B is an embodiment of a graph 406 illustrating adjusting duty cycles DC1-DC4 or adjusted duty cycles ADC1-ADC4 in real time. Graph 406 plots the duty cycle of a heater element, such as heater element HE1 or HE2 or HE3 or HE4, versus time t in microseconds. Graph 406 includes plot 408. 406 As illustrated in the example, the heater element operates at a 40% duty cycle for a 1 microsecond period from a time of 0 microseconds to a time of 1 microsecond. The 40% duty cycle is an example of any of duty cycles DC1 through DC4. The 40% duty cycle is then adjusted to achieve an adjusted 60% duty cycle. The adjusted 60% duty cycle is an example of any of duty cycles ADC1 through ADC4. The adjusted 60% duty cycle is maintained for a 1 microsecond period from a time of 1 microsecond to a time of 2 microseconds.

[0086] The adjusted duty cycle of 60% is then adjusted to achieve another adjusted duty cycle of 50%. The other adjusted duty cycle of 50% is maintained for a period of 1 microsecond between a time of 2 microseconds and a time of 3 microseconds. Thereafter, another duty cycle of 50% is then adjusted to achieve an additional adjusted duty cycle of 70%. The additional adjusted duty cycle of 70% is maintained for a period of 1 microsecond between a time of 3 microseconds and a time of 4 microseconds. Thus, the duty cycle of the heater element is adjusted every microsecond, or the adjusted duty cycle is adjusted every microsecond.

[0087] Note that microseconds are used as an example herein, and in some embodiments, the duty cycle of the heater element or the adjusted duty cycle of the heater element is adjusted every few microseconds, such as every 2 microseconds or every 3 microseconds.

[0088] In various embodiments, the duty cycle is adjusted to an adjusted duty cycle within a range of a different period than the period for adjusting the adjusted duty cycle. For example, the duty cycle DC1 is adjusted to an adjusted duty cycle ADC1 within a range of 1 microsecond, and the adjusted duty cycle ADC1 is adjusted to another adjusted duty cycle within a range of 2 microseconds. As another example, the adjusted duty cycle ADC1 is adjusted to another adjusted duty cycle within a range of 1 microsecond, and the other adjusted duty cycle is adjusted to an additional adjusted duty cycle within a range of 1.5 microseconds.

[0089] The duty cycle or adjusted duty cycle is adjusted in real time by adjusting the duty cycle or adjusted duty cycle within a range of 1 microsecond or greater.

[0090] While large fluctuations in the duty cycle or adjusted duty cycle are illustrated in FIG. 4B, note that in some embodiments the duty cycle or adjusted duty cycle changes by 5%-10% every microsecond or every few microseconds.

[0091] 5 is a diagram of an embodiment of a plasma system 500 illustrating the use of heater elements HE1-HE4 within the plasma system 500. The plasma system 500 is an example of a wafer processing system. The plasma system 500 includes a radio frequency generator (RFG) 510, an impedance matching circuit (IMC) 516, a plasma chamber 502, a user interface system 112, and a multiplexer. 106 An impedance matching circuit, as used herein, often refers to an impedance matching network or impedance matching.

[0092] An input of the impedance matching circuit 516 is coupled to the RF generator 510 via an RF cable 512, and an output of the impedance matching circuit 516 is coupled to the lower electrode 508 of the plasma chamber 502 via an RF transmission line 518. An example of the RF generator 510 is a generator having an operating frequency in kilohertz (kHz). For illustrative purposes, the RF generator 510 operates at a frequency of 200 kHz or 400 kHz. Another example of an RF generator is a generator having an operating frequency in megahertz (MHz). For illustrative purposes, the RF generator 510 operates at a frequency of 2 MHz, 13.56 MHz, 27 MHz, or 60 MHz.

[0093] As described herein, an impedance matching circuit is a network of one or more components, such as one or more resistors, one or more capacitors, one or more inductors, or a combination thereof, that matches the impedance of a load coupled to the output of the impedance matching circuit to the impedance of a source coupled to one or more inputs of the impedance matching circuit. Two or more of the components are coupled in parallel or series with each other. Examples of loads coupled to the output of the impedance matching circuit 516 include the plasma chamber 502 and the RF transmission line 518. Additionally, examples of sources coupled to the input of the impedance matching circuit 516 include the RF cable 512 and the RF generator 510.

[0094] Plasma Chamber 502 The substrate support 504 includes an upper electrode 506 and a substrate support 504, such as a chuck. The substrate support 504 is an example of the electrode assembly 101 of FIG. 1A or 1B. The substrate support 504 includes a lower electrode 508 and a heater system including heater elements HE1-HE4. 520 A substrate support 504 on which a substrate S, such as a semiconductor wafer, is placed includes a lower electrode 508 and a heater system. 520 5. An example of a chuck includes an electromagnetic chuck or a magnetic chuck. The substrate support 504 faces the upper electrode 506. The upper electrode 506 is coupled to a ground potential. The lower electrode 508 and the upper electrode 506 are each made of a metal such as aluminum or an aluminum alloy. The lower electrode 508 is positioned above a heater system 520.

[0095] The user interface system 112 is coupled to the RF generator 510 via a transmission cable. The processor 110 of the user interface system 112 provides one or more power levels and / or one or more frequency levels to the RF generator 510. The one or more power levels and one or more frequency levels are part of a recipe stored in the memory element 118 of the user interface system 112. The RF generator 510 generates an RF signal having one or more power levels and / or one or more frequency levels and provides the RF signal to an impedance matching circuit 516 via the RF cable 512. The impedance matching circuit 516 matches the impedance of a load coupled to the output of the impedance matching circuit 516 with the impedance of a source coupled to the input of the impedance matching circuit 516 to generate a modified RF signal from the RF signal received via the RF cable 512. The impedance matching circuit 516 provides the modified RF signal to the lower electrode 508 of the plasma chamber 502 via an RF transmission line 518.

[0096] In addition to supplying the modified RF signal, when one or more process gases are supplied to the plasma chamber 502, a plasma is ignited and maintained within the plasma chamber 502 to process the substrate S. An example of the one or more process gases includes an oxygen-containing gas, such as O. Other examples of the one or more process gases include a fluorine-containing gas, such as tetrafluoromethane (CF), sulfur hexafluoride (SF), hexafluoroethane (CF), etc. Examples of processing the substrate S include depositing one or more materials on the substrate S, etching the substrate S, sputtering the substrate S, and cleaning the substrate S.

[0097] During processing of the substrate S, the processor 110 and / or multiplexer of the user interface system 112 106The processor 104 applies the method described above with reference to FIG. 1A or FIG. 1B to adjust one or more of the duty cycles DC1-DC4 to a corresponding one or more adjusted duty cycles ADC1-ADC4 to achieve a temperature value Temp1 inside the plasma chamber 502.

[0098] Additionally, the processor 110 and / or multiplexer of the user interface system 112 106 The processor 104 applies the above-described method to adjust one or more of the duty cycles DC11-DC41 to a corresponding one or more adjusted duty cycles ADC11-ADC41 to achieve a temperature value Temp2 inside the plasma chamber 502.

[0099] In some embodiments, instead of being embedded within the substrate support 504, the heater system is located within the upper electrode assembly, including the upper electrode 506. 520 is embedded, and the bottom electrode 508 is coupled to ground potential.

[0100] In some embodiments, instead of being embedded within the substrate support 504, the heater system is located within the upper electrode assembly, including the upper electrode 506. 520 and the bottom electrode 508 is coupled to one or more RF generators.

[0101] In various embodiments, instead of being coupled to ground potential, the upper electrode 506 is coupled to one or more RF generators.

[0102] FIG. 6 is a diagram of an embodiment of a system 600 illustrating the use of the heater system 520 within a showerhead 616 of a plasma chamber 602. The system 600 is another example of a wafer processing system. The system 600 includes a voltage source Vs, rail 102, a multiplexer 106, a user interface system 112, a radio frequency generator 606, and an impedance matching circuit 608, as well as a plasma chamber 602. The user interface system 112 is coupled to the RF generator 606 via a transmission cable. The RF generator 606 is further coupled to an input of the impedance matching circuit 608 via an RF cable 610, and the output of the impedance matching circuit 608 is coupled to an upper electrode 620 within the showerhead 616 via an RF transmission line 612. The plasma chamber 602 includes a substrate support 604 facing the showerhead 616 to form a gap between the showerhead 616 and the substrate support 604. The showerhead 616 is an example of the electrode assembly 101 of FIG. 1A or 1B. A lower electrode 614 is embedded within the substrate support 604. Additionally, a heater system 520 is embedded within the showerhead 616. The heater system 520 is positioned above the upper electrode 620. The lower electrode 614 is coupled to ground potential. A substrate S is placed on top of the substrate support 604 for processing.

[0103] The user interface system 112 controls the RF generator 606 based on a recipe. Upon receiving one or more power levels and / or one or more frequency levels of the recipe, the RF generator 606 generates an RF signal and provides the RF signal to the impedance matching circuit 608 via an RF cable 610. The impedance matching circuit 608 modifies the RF signal received from the RF generator 606 to match the impedance of a load coupled to the output of the impedance matching circuit 608 with the impedance of a source coupled to the input of the impedance matching circuit 608, and outputs the modified RF signal. Examples of loads coupled to the output of the impedance matching circuit 608 include the plasma chamber 602 and an RF transmission line 612, and examples of sources coupled to the input of the impedance matching circuit 608 include the RF generator 606 and the RF cable 610.

[0104] The showerhead 616 includes a plurality of holes used to transport one or more process gases or one or more liquid metals into the gap between the showerhead 616 and the substrate support 604. In addition to providing a modified RF signal from the impedance match circuit 608 to the upper electrode 620, supplying one or more process gases or one or more liquid metals into the gap between the showerhead 616 and the substrate support 604 ignites and sustains a plasma within the plasma chamber 602 to process the substrate S. For example, the showerhead 616 is used to perform plasma enhanced atomic layer deposition (PEALD) or plasma enhanced chemical vapor deposition (PECVD) on the substrate S. A voltage source Vs is coupled to the heater system 520 via the rail 102 in the manner described above with reference to FIGS. 1A and 1B . The method described above with reference to FIGS. 1A or 1B is applied to the system 600.

[0105] In some embodiments, instead of coupling the lower electrode 614 to ground potential, the upper electrode 620 is coupled to ground potential and the lower electrode 614 is coupled to the RF generator 606 via the RF transmission line 612, the impedance matching circuit 608, and the RF cable 610.

[0106] In various embodiments, the upper electrode 620 is coupled to the RF generator 606 and the lower electrode 614 is coupled to another RF generator (not shown) through an impedance matching circuit (not shown).

[0107] Figure 7 shows an inductively coupled plasma (ICP) chamber. 702 7 is a diagram of an embodiment of a system 700 illustrating the use of the heater system 520 therein. The system 700 is an example of a wafer processing system. The system 700 includes a user interface system 112, a multiplexer 106, an RF generator 706, an impedance matching circuit 720, an RF coil 712, and a plasma chamber 702. The plasma chamber 702 includes a dielectric window 718. The RF coil 712 is positioned above the dielectric window 718.

[0108] The user interface system 112 couples to the RF generator 706 via a transmission cable, and the RF generator 706 is coupled to the input of an impedance matching circuit 720 via an RF cable 708. Further, the output of the impedance matching circuit is coupled to an RF coil 712 via an RF transmission line 710. The user interface system 112 provides one or more power levels and / or one or more frequency levels to the RF generator 706. offer The RF generator 706 generates an RF signal having one or more power levels and / or one or more frequency levels and transmits the RF signal via an RF cable 708 to the input of the impedance matching circuit 720.

[0109] The plasma chamber 702 includes a substrate support 704 having a lower electrode 716 embedded therein. The substrate support 704 is an example of the electrode assembly 101 of FIG. 1A or 1B. The lower electrode 716 is coupled to ground potential. A heater system 520 is embedded within the substrate support 704 and positioned below the lower electrode 716. For processing, a substrate S is superimposed on top of the substrate support 704.

[0110] The impedance matching circuit 720 matches the impedance of a load coupled to the output of the impedance matching circuit 720 to the impedance of a source coupled to the input of the impedance matching circuit 720, and outputs a modified RF signal at the output of the impedance matching circuit. Examples of loads coupled to the output of the impedance matching circuit include an RF transmission line 710 and an RF coil 712. Examples of sources coupled to the input of the impedance matching circuit 720 include an RF generator 706 and an RF cable 708. The RF coil 712 receives the modified RF signal from the output of the impedance matching circuit 720 via the RF transmission line 710. When one or more process gases are supplied to the plasma chamber 702 and RF power of the modified RF signal provided to the RF coil 712 is inductively coupled to the plasma chamber 702, a plasma is ignited and maintained within the plasma chamber 702 to process the substrate S.

[0111] The voltage source Vs is coupled to the heater system 520 via rail 102. The user interface system 112 and the multiplexer 106 perform the processing described above with reference to FIG. 1A or with reference to FIG. 1B to control the heater elements HE1-HE4 to adjust one or more of the duty cycles DC1-DC4 to generate and apply a corresponding one or more adjusted duty cycles ADC1-ADC4.

[0112] In some embodiments, instead of the RF coil 712, multiple RF coils 712 are positioned above the dielectric window 718. In various embodiments, instead of or in addition to the RF coil 712, one or more RF coils are positioned proximate to the sidewall SW of the plasma chamber 702. In some embodiments, a Faraday shield is positioned below and proximate to the dielectric window 718 to clean the dielectric window 718 of material that deposits thereon.

[0113] In various embodiments, instead of coupling the bottom electrode 716 to ground potential, it is coupled to a separate RF generator (not shown) through an impedance matching circuit.

[0114] 8 is a diagram of an embodiment of a system 800 illustrating chamber-to-chamber matching to achieve the same temperature value Temp1 within a plasma chamber 802 as the temperature achieved within plasma chamber 502 of FIG. 5. System 800 is another example of a wafer processing system. System 800 includes a user interface system 112, a multiplexer 818, an RF generator 810, an impedance matching circuit 814, and a plasma chamber 802. System 800 further includes a voltage source Vs and rail 806.

[0115] A transmission cable couples the user interface system 112 to an RF generator 810. An RF cable 812 couples the RF generator 810 to the input of an impedance matching circuit 814. An RF transmission line 816 couples the output of the impedance matching circuit 814 to a lower electrode 808 of the plasma chamber 802. The plasma chamber 802 is coupled to an upper electrode 808 that is coupled to ground potential. 807 The lower electrode 808 is embedded within a substrate support 804, such as a chuck, and the substrate support 804 is connected to the upper electrode 8071A or 1B. A substrate S is placed on top of the substrate support 804. Furthermore, a heater system 820 is embedded within the substrate support 804 and positioned below the bottom electrode 808. The heater system 820 includes a plurality of heater elements HE5, HE6, HE7, and HE8. The heater elements HE5-HE8 are coupled to a voltage source Vs via rail 806 in the same manner as the heater elements HE1-HE4 of FIG. 1A or 1B are coupled to a voltage source Vs via rail 102 of FIG. 1A or 1B.

[0116] upper electrode 807 The multiplexer 818 is made of a metal such as aluminum or an aluminum alloy. Furthermore, the bottom electrode 808 is made of a metal such as aluminum or an aluminum alloy. The multiplexer 818 has the same structure as the multiplexer 106 of FIG. 1A or FIG. 1B. For example, the multiplexer 818 may be a 811 , switch circuit 813 , and a sensor 815. 811 has the same structure as the processor 104 of FIG. 1A or FIG. 1B, and the switch circuit 813 1A or 1B, and the sensor 815 has the same structure as the sensor 114 in FIG. 1A or 1B. 811 1A or 1B. The sensor 815 is further coupled to the heater element 820, which is further coupled to the voltage source Vs via rail 806. The switch circuit 108 is also coupled to the heater elements HE1-HE4 of FIG. 1A or 1B. 813 are coupled to heater elements HE5 to HE8 of heater system 820.

[0117] The system 800 includes a non-volatile memory 817, such as a flash memory device, coupled to the processor 110. The non-volatile memory 817 stores a plurality of duty cycles DC5, DC6, DC7 at which corresponding ones of the heater elements HE5-HE8 should be operated during processing of the substrate S within the plasma chamber 802, and a mapping between DC8 and a temperature value Temp1. For example, to achieve a temperature value Temp1 within the plasma chamber 802, the heater element HE5 should be operated at a duty cycle DC5, the heater element HE6 should be operated at a duty cycle DC6, the heater element HE7 should be operated at a duty cycle DC7, and the heater element HE8 should be operated at a duty cycle DC8. The processor 811 The mapping accessed by the processor includes a correspondence, such as a one-to-one relationship, between the temperature value Temp1 and the duty cycles DC5-DC8 to achieve the temperature value Temp1. Additionally, the mapping includes a voltage value Vnominal1 that the voltage source Vs should generate during processing of the substrate S. 811 receives, eg, accesses, a mapping between a plurality of duty cycles DC5-DC8 that operate corresponding ones of the heater elements HE5-HE8 to achieve the temperature value Temp1.

[0118] During processing of the substrate S, the processor 110 controls the heater elements HE5-HE8 to operate at corresponding duty cycles DC5-DC8 in the same manner as it controls the heater elements HE1-HE4 to operate at corresponding duty cycles DC1-DC4. 8118 to control the heater elements HE5-HE8 to operate at corresponding duty cycles DC5-DC8. When the heater elements HE5-HE8 are operated at their corresponding duty cycles DC5-DC8 to achieve a temperature value Temp1 within the plasma chamber 802, the sensor 815 senses a voltage value VsenseM on the rail 806. The heater elements HE5-HE8 are operated in the same manner as the heater elements HE1-HE4 are operated by controlling switches (not shown) of the heater system 820 that are coupled to the corresponding heater elements HE5-HE8. The sensor 815 controls the processor 811 provides the voltage value VsenseM to the processor 811 processor 110 and 811 The voltage value VsenseM is transmitted to the processor 110 via a transmission cable coupled to the

[0119] The processor 110 converts one or more of the adjusted duty cycles ADC1-ADC4 into one or more corresponding duty cycles DC1-DC4. DC4 The processor 110 calculates one or more adjusted duty cycles ADC5, ADC6, ADC7, and ADC8 from the corresponding one or more duty cycles DC5-DC8 in the same manner as it calculates the duty cycle ADC5 from the corresponding one or more voltage values ​​Vnominal1 and VsenseM. For example, the processor 110 calculates the adjusted duty cycle ADC5 as equal to the product of the duty cycle DC5 and the square of the ratio of the voltage value Vnominal1 to the voltage value VsenseM. As another example, the processor 110 calculates the adjusted duty cycle ADC6 as equal to the product of the duty cycle DC6 and the square of the ratio of the voltage value Vnominal1 to the voltage value VsenseM. As yet another example, the processor 110 calculates the adjusted duty cycle ADC7 as equal to the product of the duty cycle DC7 and the square of the ratio of the voltage value Vnominal1 to the voltage value VsenseM. As yet another example, the processor 110 calculates the adjusted duty cycle ADC8 as the product of the duty cycle DC8 and the square of the ratio of the voltage value Vnominal1 to the voltage value VsenseM.

[0120] When processing a substrate S inside the plasma chamber 802, the processor 110 controls the duty cycles DC1 to DC2. DC4 For example, upon calculating the adjusted duty cycles ADC5-ADC8, the processor 110 may adjust one or more of the duty cycles DC5-DC8 in the same manner as adjusting one or more of the heater elements ADC5-ADC8. HE5 to achieve the adjusted duty cycle ADC5, to control the heater element HE6 to achieve the adjusted duty cycle ADC6, to control the heater element HE7 to achieve the adjusted duty cycle ADC7, and to control the heater element HE8 to achieve the adjusted duty cycle ADC8. 811 For example, the processor 110 may transmit 811 and generating an adjusted duty cycle control signal within a few microseconds, such as one microsecond or more, after transmitting the duty cycle control signal to the processor. 811 In another example, the processor 110 may 811 and generating an adjusted duty cycle control signal within a few milliseconds, such as one millisecond or more, after transmitting the duty cycle control signal to the processor. 811 The duty cycles DC5-DC8 are adjusted in real time by adjusting one or more of the duty cycles DC5-DC8 every few milliseconds or microseconds.

[0121] The adjusted duty cycle control signal is 813 The frequency for opening and closing the switches ADC5 to ADC8 to achieve the duty cycles ADC5 to ADC8 is included. Upon receiving the adjusted duty cycle control signal, the processor 811 generates and transmits a plurality of adjusted duty cycle selection signals; 813 In response to receiving the adjusted duty cycle selection signal, the switch circuit 813closes some of its switches and opens the rest of its switches to achieve the adjusted duty cycle ADC5 to ADC8.

[0122] Receive two corresponding adjusted duty cycle selection signals to switch the 813 During the period when corresponding two of the switches are closed, a nominal voltage value Vnominal1 generated by voltage source Vs is transmitted to rail 806, the corresponding y-bus of heater system 820, the corresponding switch of heater system 820 coupled to the corresponding y-bus of heater system 820, the corresponding heater element coupled to the corresponding y-bus, the corresponding x-bus of heater system 820 coupled to the corresponding heater element, and the corresponding switch of heater system 820 coupled to the corresponding x-bus of heater system 820 to ground potential to achieve the on-period of the adjusted duty cycle, such as ADC5, ADC6, ADC7, or ADC8. For the remainder of the clock cycle, the nominal voltage value Vnominal1 generated by voltage source Vs is transmitted to rail 806, the corresponding y-bus of heater system 820, the corresponding switch of heater system 820 coupled to the corresponding y-bus of heater system 820, the corresponding heater element coupled to the corresponding y-bus, the corresponding x-bus I of heater system 820 coupled to the corresponding heater element, and the corresponding switch of heater system 820 coupled to the corresponding x-bus of heater system 820, without transmitting to ground potential, thereby achieving the off period of the adjusted duty cycle of ADC5, ADC6, ADC7, and ADC8, etc.

[0123] One or more of the duty cycles DC5-DC8 of the corresponding one or more heater elements HE5-HE8 are adjusted to corresponding one or more duty cycles ADC5-ADC8 to achieve a temperature value Temp1 within plasma chamber 802. The temperature value Temp1 is the same as the temperature value Temp1 to be achieved within plasma chamber 502 of FIG. 5 to achieve chamber-to-chamber matching in processing substrate S. For example, when the same recipe is applied to substrate S in both plasma chambers 502 and 802 in addition to applying the same temperature value Temp1, substrate S is processed, e.g., etched or cleaned, in a substantially similar manner in both plasma chambers 502 and 802. For example, substantially the same etch rate and the same deposition rate are achieved in both plasma chambers 502 and 802. To illustrate, the etch rate for etching substrate S within plasma chamber 502 is within a predetermined value range of the etch rate for etching substrate S within plasma chamber 802. As another example, the deposition rate at which material is deposited on substrate S within plasma chamber 502 is within a preset range of values ​​at which material is deposited on substrate S within plasma chamber 802 .

[0124] 1 and 5, it should be noted that one and the same voltage source Vs is not used in both systems 500 and 800. For example, the voltage source Vs used in system 500 is a separate voltage source from the voltage source Vs used in system 800. Both voltage sources Vs used in systems 500 and 800 are designed and specified to generate the same amount of nominal voltage Vnominal1.

[0125] In some embodiments, non-volatile memory 817 is received by a user of heater system 820 when the user receives heater system 820. For example, the mapping stored in non-volatile memory 817 is specific to heater elements HE5-HE8 and may be different for different sets of heater elements. As another example, duty cycles DC5-DC8 are pre-calibrated at the factory that fabricates substrate support 804, assuming that voltage source Vs has a constant value, such as a nominal value Vnominal1.

[0126] The embodiments described herein may be practiced with various computer system configurations including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. Furthermore, embodiments may be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a network.

[0127] In some embodiments, a controller, as described herein, is part of a system, which may be part of the examples described above. Such systems include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (such as wafer pedals, gas flow systems, etc.). These systems are integrated with electronics for controlling their operation before, during, and after processing of semiconductor wafers or substrates. The electronics are referred to as "controllers," which may control various components or subdivisions of one or more systems. Depending on the processing requirements and / or type of system, the controller is programmed to control any of the processes disclosed herein, including process gas delivery, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer into and out of tools and other transfer tools, and / or load locks coupled to or interfaced with the system.

[0128] Broadly speaking, in various embodiments, a controller is defined as an electronic device having various integrated circuits, logic circuits, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. Integrated circuits include chips in the form of firmware that store program instructions, or chips defined as digital signal processors (DSPs), ASICs, PLDs, and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions are instructions communicated to the controller in the form of various individual settings (or program files) that define parameters, factors, variables, etc., to perform specific operations on or for a semiconductor wafer or system. Program instructions, in some embodiments, are part of a recipe defined by a process engineer to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon oxides, surfaces, circuits, and / or die of a wafer.

[0129] The controller, in some embodiments, is part of or coupled to a computer that is integrated with, coupled to, or otherwise networked to the system, or a combination thereof. For example, the controller may be all or part of a host computer system in a semiconductor fab that resides in the "cloud" or enables remote access of wafer processing. The computer enables remote access to the system to monitor the current progress of fabrication operations, examine the history of past fabrication operations, examine trends or performance indicators from multiple fabrication operations, and modify parameters of a current process, set up processing steps following the current process, or initiate a new process.

[0130] In some examples, a remote computer (e.g., a server) provides process recipes to the system over a network, including a local network or the Internet. The remote computer includes a user interface that allows for input or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, a controller receives instructions in the form of data that specify parameters, factors, and / or variables for each processing step to be performed during one or more operations. It should be understood that the parameters, factors, and / or variables are specific to the type of process to be performed and the type of tool the controller is configured to interface with or control. Thus, as described above, a controller may be distributed, such as by including one or more separate controllers networked together, operating toward a common purpose, such as the processing and control described herein. An example of a distributed controller for such purposes includes one or more integrated circuits on the chamber in communication with one or more remotely located integrated circuits (e.g., at the platform level or as part of a remote computer) that combine to control processing on the chamber.

[0131] Without limitation, in various embodiments, example systems to which the present methods may be applied include plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing systems associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0132] It is further noted that in some embodiments, the above-described operations apply to several types of plasma chambers, such as plasma chambers including inductively coupled plasma (ICP) reactors, transformer-coupled plasma chambers, conductor tools, dielectric tools, plasma chambers including electron cyclotron resonance (ECR) reactors, etc. For example, one or more RF generators are coupled to an inductor inside an ICP reactor. Examples of inductor shapes include a solenoid, a dome-shaped coil, a flat-shaped coil, etc.

[0133] As noted above, depending on the processing step or steps to be performed by the tool, the host computer communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, nearby tools, adjacent tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to carry containers of wafers to and from tool locations and / or load ports within the semiconductor fabrication factory.

[0134] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These operations are operations that physically manipulate physical quantities. Any of the operations described herein that form part of the embodiments are useful machine operations.

[0135] Some of the embodiments also relate to hardware units or devices for performing these operations. The device is specially constructed for a special-purpose computer. When defined as a special-purpose computer, the computer may perform other processes, program execution, or routines that are not part of the special purpose computer, while still being able to operate for the special purpose computer.

[0136] In some embodiments, the operations may be processed by a computer selectively activated or configured by one or more computer programs stored in a computer memory, cache, or obtained over a computer network. When data is obtained over a computer network, the data may be processed by other computers on the computer network, for example, by a cloud of computing resources.

[0137] One or more embodiments can also be fabricated as computer-readable code on a non-transitory computer-readable medium. The non-transitory computer-readable medium is any data storage hardware unit, such as a memory device, that stores data that is subsequently read by a computer system. Examples of non-transitory computer-readable media include hard drives, network-attached storage (NAS), ROM, RAM, compact disc-ROMs (CD-ROMs), CD-recordables (CD-Rs), CD-rewritables (CD-RWs), magnetic tapes, and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer-readable medium includes tangible computer-readable media distributed across network-coupled computer systems so as to store and execute the computer-readable code in a distributed manner.

[0138] Although the method operations above are described in a particular order, it should be understood that various embodiments may perform other housekeeping operations between operations, or adjust the method operations to occur at slightly different times, or distribute the method operations over a system that allows them to occur at various intervals, or perform the method operations in an order different from that described above.

[0139] It is further noted that in an embodiment, one or more features from any of the above-described embodiments may be combined with one or more features from any other embodiment without departing from the scope described in the various embodiments described in this disclosure.

[0140] Although the foregoing embodiments have been described in some detail for clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments should not be limited to the details set forth herein. The present invention can be realized, for example, in the following manner. Application example 1: 1. A method for achieving a target temperature within a plasma chamber of a wafer processing system, the wafer processing system including a plurality of heater elements disposed within the plasma chamber, and a voltage source configured to supply voltage to the plurality of heater elements via a rail, the method comprising: maintaining mapping information, including a nominal voltage associated with the voltage source, between the target temperature and a plurality of duty cycles corresponding to the plurality of heater elements; measuring a parameter value at the rail; generating one or more adjusted duty cycles for corresponding heater elements of the plurality of heater elements based on at least one of the plurality of duty cycles, the nominal voltage, and the measured parameter value; A method for providing the above. Application example 2: The method of Application Example 1, applying the one or more adjusted duty cycles to the corresponding heater elements of the plurality of heater elements to achieve the target temperature. A method further comprising: Application example 3: The method of application example 1, wherein the parameter value is related to the voltage at the rail. Application example 4: In the method of application example 1, measuring the parameter value comprises: measuring said parameter values ​​on a periodic basis. And offer more. The method wherein the one or more adjusted duty cycles are created according to the periodic criteria. Application example 5: The method of application example 4, wherein the periodic reference is every microsecond or every millisecond. Application example 6: A method according to Application Example 1, wherein each of the one or more adjusted duty cycles is calculated as the product of a corresponding duty cycle among the plurality of duty cycles and the square of the ratio of the nominal voltage to the measured parameter value. Application example 7: The method of Application Example 1, wherein the method is used across multiple plasma chambers to achieve the target temperature and facilitate chamber-to-chamber matching. Application example 8: The method of Application Example 1, measuring one or more additional parameter values ​​at corresponding locations along said rail; Furthermore, creating the one or more adjusted duty cycles generating the one or more adjusted duty cycles based on at least one of the plurality of duty cycles, the nominal voltage, the measured parameter value, and the measured one or more additional parameter values; A method further comprising: Application example 9: The method of Application Example 8, generating one or more statistically adjusted duty cycles for the corresponding heater elements of the plurality of heater elements based on the one or more adjusted duty cycles; A method further comprising: Application example 10: The method of Application Example 9, applying the one or more statistically adjusted duty cycles to the corresponding heater elements of the plurality of heater elements; A method further comprising: Application example 11: The method of application example 1, wherein the method is performed in real time during substrate processing. Application example 12: The method of application example 1, wherein the method is carried out without processing the substrate. Application example 13: The method of application example 12, wherein the method is performed to readjust the plasma chamber. Application 14: 1. A system for achieving a target temperature within a plasma chamber of a wafer processing system, the wafer processing system including a plurality of heater elements disposed within the plasma chamber, and a voltage source configured to supply voltage to the plurality of heater elements via a rail, the system comprising: a memory device configured to maintain mapping information between the target temperature and a plurality of duty cycles corresponding to the plurality of heater elements, the memory device including a nominal voltage associated with the voltage source; a sensor configured to measure a parameter value at the rail; 1. A processor, comprising: generating one or more adjusted duty cycles for corresponding heater elements of the plurality of heater elements based on at least one of the plurality of duty cycles, the nominal voltage, and the measured parameter value; and a processor configured as A system comprising: Application example 15: The system of Application Example 14, a switch circuit controllable by the processor and configured to control the plurality of heater elements; The system further comprises: Application 16: 16. The system of Application Example 15, wherein the processor is configured to instruct the switch circuit to apply the one or more adjusted duty cycles to the corresponding heater elements of the plurality of heater elements to achieve the target temperature. Application 17: The system of application example 14, wherein the system is coupled to a substrate support within the plasma chamber. Application 18: 15. The system of application example 14, wherein the measured parameter value is related to the voltage at the rail. Application 19: A system according to Application Example 14, wherein the processor is configured to poll the sensor on a periodic basis to receive the measured parameter values ​​and to create the one or more adjusted duty cycles according to the periodic basis. Example 20: The system of application example 19, wherein the periodic reference is every microsecond or every millisecond. Example 21: A system according to Application Example 14, wherein each of the one or more adjusted duty cycles is calculated as the product of a corresponding duty cycle among the plurality of duty cycles and the square of the ratio of the nominal voltage to the measured parameter value. Application example 22: A system according to Application Example 14, wherein the sensor is configured to measure one or more additional parameter values ​​at corresponding locations along the rail, and the processor is configured to generate the one or more adjusted duty cycles based on at least one of the plurality of duty cycles, the nominal voltage, the measured parameter values, and the measured one or more additional parameter values. Application 23: The system of Application Example 22, wherein the processor is configured to generate one or more statistically adjusted duty cycles for the corresponding heater elements among the plurality of heater elements based on the one or more adjusted duty cycles. Application 24: 24. The system of claim 23, wherein the processor is configured to apply the one or more statistically adjusted duty cycles to the corresponding heater elements of the plurality of heater elements. Example 25: 15. The system of claim 14, wherein the processor is configured to generate the one or more adjusted duty cycles in real time during substrate processing. Application 26: The system of Application Example 14, wherein the processor is configured to create the one or more adjusted duty cycles and recondition the plasma chamber without processing a substrate.

Claims

1. 1. A method for achieving a target temperature within a plasma chamber of a wafer processing system, the wafer processing system including a plurality of heater elements disposed within the plasma chamber, and a voltage source configured to supply voltage to the plurality of heater elements via a rail, the method comprising: maintaining mapping information, including a nominal voltage associated with the voltage source, between the target temperature and a plurality of duty cycles corresponding to the plurality of heater elements; measuring a parameter value at the rail; generating one or more adjusted duty cycles for corresponding heater elements of the plurality of heater elements based on at least one of the plurality of duty cycles, the nominal voltage, and the measured parameter values; A method for providing

2. 10. The method of claim 1, applying the one or more adjusted duty cycles to the corresponding heater elements of the plurality of heater elements to achieve the target temperature. A method further comprising:

3. 2. The method of claim 1, wherein the parameter value is related to the voltage at the rail.

4. 2. The method of claim 1, wherein measuring the parameter values ​​comprises: measuring said parameter values ​​on a periodic basis. And offer more. The method wherein the one or more adjusted duty cycles are created according to the periodic criteria.

5. 5. The method of claim 4, wherein the periodic basis is every microsecond or every millisecond.

6. 2. The method of claim 1, wherein each of the one or more adjusted duty cycles is calculated as the product of a corresponding duty cycle of the plurality of duty cycles and the square of the ratio of the nominal voltage to the measured parameter value.

7. 10. The method of claim 1, wherein the method is used across multiple plasma chambers to achieve the target temperature and facilitate chamber-to-chamber matching.

8. 10. The method of claim 1, measuring one or more additional parameter values ​​at corresponding locations along said rail; Furthermore, Creating the one or more adjusted duty cycles comprises: generating the one or more adjusted duty cycles based on at least one of the plurality of duty cycles, the nominal voltage, the measured parameter value, and the measured one or more additional parameter values; A method further comprising:

9. 9. The method of claim 8, generating one or more statistically adjusted duty cycles for the corresponding heater elements of the plurality of heater elements based on the one or more adjusted duty cycles; A method further comprising:

10. 10. The method of claim 9, applying the one or more statistically adjusted duty cycles to the corresponding heater elements of the plurality of heater elements; A method further comprising:

11. 10. The method of claim 1, wherein the method is performed in real time during substrate processing.

12. 10. The method of claim 1, wherein the method is performed without processing the substrate.

13. 13. The method of claim 12, performed to recondition the plasma chamber.

14. 1. A system for achieving a target temperature within a plasma chamber of a wafer processing system, the wafer processing system including a plurality of heater elements disposed within the plasma chamber, and a voltage source configured to supply voltage to the plurality of heater elements via a rail, the system comprising: a memory device configured to maintain mapping information between the target temperature and a plurality of duty cycles corresponding to the plurality of heater elements, the memory device including a nominal voltage associated with the voltage source; a sensor configured to measure a parameter value at the rail; 1. A processor, comprising: generating one or more adjusted duty cycles for corresponding heater elements of the plurality of heater elements based on at least one of the plurality of duty cycles, the nominal voltage, and the measured parameter value; and a processor configured as A system comprising:

15. 15. The system of claim 14, a switch circuit controllable by the processor and configured to control the plurality of heater elements; The system further comprises:

16. 16. The system of claim 15, wherein the processor is configured to instruct the switch circuit to apply the one or more adjusted duty cycles to the corresponding heater elements of the plurality of heater elements to achieve the target temperature.

17. 15. The system of claim 14, wherein the system is coupled to a substrate support within the plasma chamber.

18. 15. The system of claim 14, wherein the measured parameter value is related to the voltage at the rail.

19. 15. The system of claim 14, wherein the processor is configured to poll the sensor on a periodic basis to receive the measured parameter values ​​and to create the one or more adjusted duty cycles according to the periodic basis.

20. 20. The system of claim 19, wherein the periodic basis is every microsecond or every millisecond.

21. 15. The system of claim 14, wherein each adjusted duty cycle of the one or more adjusted duty cycles is calculated as the product of a corresponding duty cycle of the plurality of duty cycles and the square of the ratio of the nominal voltage to the measured parameter value.

22. 15. The system of claim 14, wherein the sensors are configured to measure one or more additional parameter values ​​at corresponding locations along the rail, and the processor is configured to generate the one or more adjusted duty cycles based on at least one of the plurality of duty cycles, the nominal voltage, the measured parameter values, and the measured one or more additional parameter values.

23. 23. The system of claim 22, wherein the processor is configured to generate one or more statistically adjusted duty cycles for the corresponding heater elements of the plurality of heater elements based on the one or more adjusted duty cycles.

24. 24. The system of claim 23, wherein the processor is configured to apply the one or more statistically adjusted duty cycles to the corresponding heater elements of the plurality of heater elements.

25. 15. The system of claim 14, wherein the processor is configured to generate the one or more adjusted duty cycles in real time during substrate processing.

26. 15. The system of claim 14, wherein the processor is configured to create the one or more adjusted duty cycles to recondition the plasma chamber without processing a substrate.

Images