Selective deposition using graphene as an inhibitor

Abstract

To provide a method of selective deposition on a dielectric layer.SOLUTION: The graphene is selectively deposited on the metal layer 802 relative to the dielectric layer 804 of the semiconductor substrate. The dielectric material 808 is selectively deposited on the dielectric layer 804 relative to the metal layer 802 of the semiconductor substrate. The graphene is a high quality graphene film 806 that acts as an inhibitor during deposition of the dielectric material. In some implementations, the dielectric material may be a metal oxide. In some implementations, the dielectric material may be a low-k dielectric material. The graphene remains throughout the semiconductor integration process. In some implementations, the graphene may be subsequently modified to allow deposition of the graphene onto a surface, or the graphene may be subsequently removed.SELECTED DRAWING: Figure 8D

Description

[Background technology]

[0001] [Incorporated by reference] A PCT application is being filed concurrently herewith as part of this application, and each application identified in that concurrently filed PCT application to which this application claims benefit or priority is incorporated herein by reference in its entirety for all purposes.

[0002] Graphene is an allotrope of carbon in which atoms are arranged in a regular hexagonal pattern in a single atomic sheet. Graphene has attracted interest in many fields and industries due to its high electrical conductivity, high thermal conductivity, excellent mechanical strength and toughness, optical transparency, and high electron mobility, among other favorable properties. Graphene has attracted increasing interest in the semiconductor industry.

[0003] The Background Art provided herein is intended to present the contents of the present disclosure generally. Work by the currently named inventors within the scope of this Background Art, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure. Summary of the Invention

[0004] Provided herein is a method of selective deposition onto a dielectric layer. The method includes providing a semiconductor substrate, the semiconductor substrate having a metal layer formed on the dielectric layer, the metal layer having an exposed metal surface. The method further includes selectively depositing graphene onto the exposed metal surface and selectively depositing a dielectric material onto the dielectric layer.

[0005] In some embodiments, the surface of the graphene is free or substantially free of hydrogen-terminated and hydroxyl-terminated sites. In some embodiments, the graphene inhibits the deposition of a dielectric material onto the graphene when the dielectric material is selectively deposited onto the dielectric layer. In some embodiments, the dielectric material comprises a metal oxide. In some embodiments, the metal oxide comprises aluminum oxide, hafnium oxide, zirconium oxide, yttrium oxide, zinc oxide, titanium oxide, or a combination thereof. In some embodiments, the thickness of the metal oxide is from about 5 Å to about 60 Å. In some embodiments, the dielectric material comprises a low-k dielectric material. In some embodiments, the method further comprises depositing a metal oxide on the low-k dielectric material and the graphene, wherein the metal oxide has an etch selectivity different from the low-k dielectric material, and the thickness of the low-k dielectric material is at least twice the thickness of the metal oxide. In some embodiments, the metal layer comprises copper, cobalt, ruthenium, nickel, molybdenum, or a combination thereof. In some embodiments, graphene is exposed to an indirect plasma to modify the surface of the graphene, and a metal oxide is deposited on the modified surface of the graphene and the dielectric material by a thermal-based deposition technique. In some embodiments, depositing the metal oxide comprises depositing aluminum oxide by atomic layer deposition (ALD). In some embodiments, the method further comprises removing the graphene and depositing a metal oxide on the exposed metal surface and the dielectric material. In some embodiments, the method further comprises exposing graphene to an indirect plasma to modify the surface of the graphene, and depositing a hermetic barrier on the modified surface of the graphene and the dielectric material by an indirect plasma deposition technique. In some embodiments, depositing the hermetic barrier comprises depositing nitrogen-doped silicon carbide, oxygen-doped silicon carbide, or silicon nitride using remote hydrogen plasma chemical vapor deposition (CVD). In some embodiments, the indirect plasma comprises hydrogen radicals mixed with radicals of oxygen, ammonia, nitrogen, or a combination thereof.In some embodiments, the method further includes removing the graphene and depositing a hermetic barrier on the exposed metal surface and the dielectric material. In some embodiments, selectively depositing graphene on the exposed metal surface includes flowing one or more hydrocarbon precursors into a reaction chamber toward the semiconductor substrate, generating hydrogen radicals from a hydrogen source gas with a remote plasma source, and directing the hydrogen radicals into the reaction chamber toward the semiconductor substrate, where the hydrogen radicals react with the one or more hydrocarbon precursors and deposit graphene on the exposed metal surface.

[0006] Also provided herein is a substrate processing apparatus comprising: a reaction chamber; a substrate support within the reaction chamber configured to support a substrate, the substrate comprising a metal layer formed on a dielectric layer, the metal layer having an exposed metal surface; a remote plasma source upstream of the reaction chamber, the exposed metal surface facing toward the remote plasma source; one or more gas outlets within the reaction chamber downstream from the remote plasma source; and a controller configured to perform operations to selectively deposit graphene on the exposed metal surface of the substrate and to selectively deposit a dielectric material on the dielectric layer of the substrate.

[0007] Also provided herein is a semiconductor device comprising: a first dielectric layer, a first metal layer formed on the first dielectric layer, a selective graphene film formed on an upper surface of the first metal layer selectively relative to the first dielectric layer, and a selective dielectric layer formed on an upper surface of the first dielectric layer selectively relative to the first metal layer.

[0008] In some embodiments, the selective dielectric layer comprises a metal oxide, the first dielectric layer comprises a low-k dielectric material, and the first metal layer comprises copper, cobalt, ruthenium, nickel, molybdenum, or a combination thereof. In some embodiments, the semiconductor device further comprises an etch stop layer over the selective dielectric layer and the selective graphene film, the etch stop layer comprising a metal oxide. In some embodiments, the semiconductor device further comprises a second dielectric layer over the etch stop layer, a second metal layer formed in the second dielectric layer, and a via formed in the second dielectric layer, the via being between the selective graphene film and the second metal layer, the via providing an electrical interconnection between the first metal layer and the second metal layer. In some embodiments, the etch selectivity of the etch stop layer is different from that of the second dielectric layer, and the etch selectivity of the selective dielectric layer is different from that of the etch stop layer. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a cross-sectional schematic diagram of an exemplary substrate having a metal surface with graphene deposited thereon, according to some embodiments.

[0010] [Figure 2] FIG. 2 is a schematic diagram of an exemplary plasma processing apparatus having a remote plasma source, according to some embodiments.

[0011] [Figure 3] FIG. 3 is a graph illustrating Raman spectra of example single-layer and multi-layer graphene, according to some embodiments.

[0012] [Figure 4] FIG. 4 is a flow diagram of an exemplary method for depositing graphene on a metal surface of a substrate, according to some embodiments.

[0013] [Figure 5A]FIG. 5A is a cross-sectional schematic diagram of an exemplary dual damascene fabrication process with a "partially landed" via. [Figure 5B] FIG. 5B is a cross-sectional schematic diagram of an exemplary dual damascene fabrication process with a "partially landed" via. [Figure 5C] FIG. 5C is a cross-sectional schematic diagram of an exemplary dual damascene fabrication process with a "partially landed" via. [Figure 5D] FIG. 5D is a cross-sectional schematic diagram of an exemplary dual damascene fabrication process with a "partially landed" via.

[0014] [Figure 5E] FIG. 5E is a cross-sectional schematic diagram of an exemplary semiconductor device having a "partially landed" via that results in a tooth-shaped hole.

[0015] [Figure 6A] FIG. 6A is a cross-sectional schematic of the process of selective deposition using self-assembled monolayers (SAMs) as inhibitors. [Figure 6B] FIG. 6B is a cross-sectional schematic of the process of selective deposition using a self-assembled monolayer (SAM) as an inhibitor.

[0016] [Figure 7] FIG. 7 is a flow diagram of an exemplary method for selective deposition using graphene, according to some embodiments.

[0017] [Figure 8A] FIG. 8A is a cross-sectional schematic diagram of a selective deposition process using graphene as an inhibitor, according to some embodiments. [Figure 8B] FIG. 8B is a cross-sectional schematic diagram of a selective deposition process using graphene as an inhibitor, according to some embodiments. [Figure 8C] FIG. 8C is a cross-sectional schematic diagram of a selective deposition process using graphene as an inhibitor, according to some embodiments. [Figure 8D] FIG. 8D is a cross-sectional schematic diagram of a selective deposition process using graphene as an inhibitor, according to some embodiments. [Figure 8E] FIG. 8E is a cross-sectional schematic diagram of a selective deposition process using graphene as an inhibitor, according to some embodiments.

[0018] [Figure 9] FIG. 9 is a cross-sectional schematic diagram of an exemplary semiconductor device having selective graphene films and selective dielectric layers in a dual damascene structure according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0019] In this disclosure, the terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially fabricated integrated circuit" are used interchangeably. Those skilled in the art will understand that the term "partially fabricated integrated circuit" can refer to a silicon wafer at any of the many stages of integrated circuit fabrication. Wafers or substrates used in the semiconductor device industry typically have diameters of 200 mm, 300 mm, or 450 mm. The following detailed description assumes that the present disclosure is practiced on a wafer. However, the disclosure is not so limited. Workpieces can be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that can utilize the present disclosure include various articles such as printed circuit boards.

[0020] Graphene deposition There is growing interest in synthesizing large-area graphene films for semiconductor applications. However, there are many challenges associated with producing graphene in sufficient quantities and under conditions suitable for semiconductor integration. Due to the difficulty of growing graphene with minimal defects, many fabrication methods suffer from low surface coverage. Therefore, scalability for producing large-area graphene films, especially those on semiconductor wafers, presents particular challenges. Furthermore, graphene films are typically grown by thermal chemical vapor deposition (CVD). Thermal CVD methods are generally preferred for synthesizing large-area, high-quality graphene. However, thermal CVD of graphene is often performed at high temperatures, which are not necessarily compatible with semiconductor applications. At such high temperatures, various materials, such as semiconductors and metals, on semiconductor wafers can be physically damaged.

[0021] Thermal CVD is a common method for depositing graphene. The thermal CVD process involves at least two steps: activation of a gaseous precursor and a chemical reaction that forms a stable, solid film on a suitable substrate. In thermal CVD, activation of the gaseous precursor can be achieved by pyrolysis. At high temperatures, hydrocarbon precursors pyrolyze and adsorb onto the substrate surface. The hydrocarbon radicals are chemically reactive and can interact with the substrate surface. The substrate surface can be a metal surface that acts as a catalyst for graphene nucleation and growth. Without being limited to any theory, the catalytic metal surface can dehydrogenate the hydrocarbon radicals so that carbon atoms can bond with other carbon atoms, thereby promoting graphene nucleation and growth. Various transition metals, such as copper, have been recognized as catalysts for graphene nucleation and growth.

[0022] The activation of hydrocarbon species and graphene growth can depend on factors such as the temperature and metal surface on which graphene is grown. Additionally, graphene growth can depend on the carbon solubility on the metal surface. When a metal has high carbon solubility, carbon dissolves more readily in the metal and tends to precipitate on the metal surface. This generally results in less uniform graphene layers and more microstructural defects due to multiple nucleation sites and unpredictable amounts of segregated carbon on the metal surface. Nickel substrates, for example, have high carbon solubility and typically result in low-quality graphene or multiple layers of disordered carbon. When a metal has low carbon solubility, carbon dissolves less in the metal, resulting in extensive surface migration of carbon adatoms on the metal surface and minimal diffusion into the bulk metal. This generally results in more uniform graphene layers and fewer microstructural defects due to more controlled growth. Copper substrates, for example, have low carbon solubility and result in epitaxial growth of high-quality graphene. High-quality graphene can be grown as single-, double-, or few-layer graphene films.

[0023] Plasma-enhanced chemical vapor deposition (PECVD) is another method for depositing graphene. While thermal CVD activates hydrocarbon precursors by pyrolysis, in PECVD, energized electrons generated by plasma cause ionization, excitation, and dissociation of the hydrocarbon precursors. The plasma can be formed in situ or remotely. Typically, a hydrocarbon precursor (e.g., methane) is activated in the plasma, and a substrate is exposed to the plasma. The plasma can be generated using a radio frequency (RF) plasma source, a microwave (MW) plasma source, a surface wave (SW) plasma source, or a remote plasma source. As an example, molecular hydrogen and methane gas can be introduced into a reaction chamber and an RF plasma can be directly ignited to promote graphene growth on the substrate. In PECVD, graphene growth in some PECVD methods can be performed at lower temperatures compared to thermal CVD methods. Furthermore, graphene growth in some PECVD methods can be achieved on nonmetallic substrates, such as dielectric materials. In other words, plasma-based methods can deposit graphene in the absence of a metal catalyst. Plasma-based methods can deposit graphene at lower temperatures and without the assistance of a metal catalyst.

[0024] FIG. 1A illustrates a cross-sectional schematic diagram of an exemplary substrate having a metal surface on which graphene is deposited, according to some embodiments. The substrate 100 can be any wafer, semiconductor wafer, partially fabricated integrated circuit, printed circuit board, display screen, or other suitable workpiece. In some embodiments, the substrate 100 is a semiconductor substrate, such as a silicon (Si) substrate. The substrate 100 can include a metal surface 101. As described below, the metal surface 101 can also be referred to as a temperature-sensitive underlayer. In some embodiments, the metal surface 101 can include any suitable metal, such as a transition metal. For example, the metal surface 101 can include copper (Cu), ruthenium (Ru), nickel (Ni), molybdenum (Mo), cobalt (Co), or a combination thereof. A graphene film 102 can be deposited on the metal surface 101.

[0025] In some embodiments, deposition of the graphene film 102 on the metal surface 101 of the substrate 100 may be achieved by remote hydrogen plasma CVD. In other embodiments, deposition of the graphene film 102 on the metal surface 101 of the substrate 100 may be achieved using any suitable deposition technique, such as thermal CVD or PECVD. Remote hydrogen plasma CVD methods can deposit the graphene film 102 at low temperatures compatible with semiconductor processing, such as back-end of line (BEOL) semiconductor processing. In some embodiments, the graphene film 102 may be deposited at temperatures below about 500°C, below about 450°C, below about 400°C, below about 350°C, below about 300°C, or between about 200°C and about 400°C.

[0026] When depositing graphene film 102 using remote hydrogen plasma CVD, a hydrocarbon precursor is flowed onto the metal surface 101 of the substrate 100, and hydrogen radicals are generated in a remote plasma source upstream of the hydrocarbon precursor flow. The hydrogen radicals interact with the hydrocarbon precursor to activate the hydrocarbon precursor downstream from the remote plasma source, and the activated hydrocarbon precursor interacts with the metal surface 101 to deposit graphene film 102. In some embodiments, the hydrocarbon precursor comprises an alkene or alkyne group.

[0027] In some embodiments of the present disclosure, the substrate 100 can include a temperature-sensitive underlayer 101. The temperature-sensitive underlayer 101 can have a temperature-sensitive limit. If the temperature-sensitive limit of the temperature-sensitive underlayer 101 is exceeded, the temperature-sensitive underlayer 101 will melt or, in some cases, be physically damaged. The temperature-sensitive limit can be about 400°C to about 700°C for many materials of the temperature-sensitive underlayer 101. Some thermal CVD methods and some conventional plasma-based CVD methods may exceed the temperature-sensitive limit of the temperature-sensitive underlayer 101. Examples of the temperature-sensitive underlayer 101 can include transition metals such as copper, cobalt, and ruthenium. In some embodiments, a graphene film 102 is deposited on the temperature-sensitive underlayer 101. In some embodiments, the graphene film 102 is deposited at a temperature low enough to avoid melting or, in some cases, physically damaging the temperature-sensitive underlayer 101. The substrate 100 can be a semiconductor wafer or semiconductor workpiece. Thus, the graphene film 102 may be deposited as a large area graphene film on the substrate 100 at a full wafer level.

[0028] In some embodiments, the graphene film 102 is deposited using remote hydrogen plasma CVD. As used herein, the term "remote" in literature generally refers to the distance between the substrate and the plasma. As used herein, "remote plasma" refers to plasma in which plasma generation occurs at a location remote from the substrate. Here, remote hydrogen plasma may contain hydrogen radicals but not carbon radicals. Instead, carbon radicals are generated downstream from the remote plasma source. This means that in some embodiments of "remote plasma," precursor gases are not introduced into the plasma generation region. Hydrocarbon precursors are independently flowed into the reaction chamber and activated by hydrogen radicals generated from the remote plasma source. Furthermore, carbon radicals are generated from hydrocarbon precursors containing alkene or alkyne groups. In fact, hydrocarbon precursors that are alkanes (e.g., methane) are not deposited in embodiments involving remote hydrogen plasma CVD. Using the remote hydrogen plasma CVD method, graphene deposits selectively on metal surfaces. Graphene does not deposit on dielectric or other non-metallic surfaces. The remote hydrogen plasma CVD method is an exemplary method capable of depositing high-quality graphene films at low temperatures suitable for semiconductor applications. For example, high-quality graphene films can function as a barrier layer in damascene or dual damascene structures. Furthermore, high-quality graphene can function as a capping layer on metal surfaces, thereby reducing resistance by reducing surface scattering. However, it will be appreciated that high-quality graphene films can be used in numerous industrial applications.

[0029] One aspect of the present disclosure is an apparatus configured to accomplish the graphene deposition methods described herein. Suitable apparatus includes hardware for accomplishing process operations and a system controller having instructions for controlling the process operations in accordance with the present disclosure. In some embodiments, an apparatus for performing the aforementioned process operations can include a remote plasma source. A remote plasma source provides milder reaction conditions compared to a direct plasma.

[0030] FIG. 2 shows a schematic diagram of an exemplary plasma processing apparatus having a remote plasma source, according to some embodiments. The plasma processing apparatus 200 includes a remote plasma source 202 separated from a reaction chamber 204. The remote plasma source 202 is fluidly coupled to the reaction chamber 204 via a showerhead 206, which may also be referred to as a multi-port gas distributor. Radical species are generated in the remote plasma source 202 and supplied to the reaction chamber 204. One or more hydrocarbon precursors are supplied to the reaction chamber 204 downstream from the remote plasma source 202 and downstream from the showerhead 206. The one or more hydrocarbon precursors react with the radical species in a chemical vapor deposition zone 208 of the reaction chamber 204 to deposit a graphene film on the front surface of a substrate 212. The chemical vapor deposition zone 208 includes an environment adjacent to the front surface of the substrate 212, where the front surface of the substrate 212 faces the remote plasma source 202.

[0031] Substrate 212 is supported on a substrate support or pedestal 214. Pedestal 214 can move within reaction chamber 204 to position substrate 212 within chemical vapor deposition zone 208. In the embodiment shown in Figure 2, pedestal 214 is shown elevating substrate 210 within chemical vapor deposition zone 208. Pedestal 214 can also, in some embodiments, regulate the temperature of substrate 212, which can provide some selective control over thermally activated surface reactions on substrate 212.

[0032] FIG. 2 shows a coil 218 disposed around a remote plasma source 202, which includes an outer wall (e.g., a quartz dome). The coil 218 is electrically coupled to a plasma generator controller 222, which can be used to form and maintain a plasma in a plasma region 224 via inductively coupled plasma generation. In some embodiments, the plasma generator controller 222 can include a power supply for supplying power to the coil 218, which can range from approximately 1 to 6 kilowatts (kW) during plasma generation. In some embodiments, electrodes or antennas for parallel plate or capacitively coupled plasma generation can be used to generate a continuous supply of radicals via plasma excitation rather than inductively coupled plasma generation. Regardless of the mechanism used to ignite and maintain the plasma in the plasma region 224, radical species can be continuously generated during film deposition using plasma excitation. In some embodiments, hydrogen radicals are generated under near-steady-state conditions during steady-state film deposition, although transients may occur at the beginning and end of film deposition.

[0033] A supply of hydrogen radicals can be continuously generated within the plasma region 224 while hydrogen gas or other source gas is being supplied to the remote plasma source 202. Excited hydrogen radicals can be generated within the remote plasma source 202. Without re-excitation or re-supply of energy or recombination with other radicals, the excited hydrogen radicals will lose energy or relax. Thus, the excited hydrogen radicals can relax and form hydrogen radicals that are substantially in a lower energy state or ground state. Hydrogen radicals that are substantially in a lower energy state or ground state.

[0034] Hydrogen gas (H) or other source gases can be diluted with one or more additional gases. These one or more additional gases can be supplied to the remote plasma source 202. In some implementations, the hydrogen gas or other source gas is mixed with one or more additional gases to form a gas mixture, where the one or more additional gases can include a carrier gas. Non-limiting examples of additional gases can include helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), and nitrogen (N). The one or more additional gases can support or stabilize steady-state plasma conditions within the remote plasma source 202 or assist in transient plasma ignition or extinction processes. In some implementations, diluting hydrogen gas or other source gases with, for example, helium can allow for higher total pressures without concomitant plasma collapse. Stated another way, a dilution gas mixture of hydrogen gas and helium can allow for higher total gas pressures without increasing the plasma power to the remote plasma source 202. In certain embodiments, the hydrogen gas is provided in a carrier, such as helium. As an example, hydrogen gas may be provided in a helium carrier at a concentration of about 1-25% hydrogen or about 1-10% hydrogen.

[0035] As shown in FIG. 2 , a source gas supply 226 is fluidly coupled to the remote plasma source 202 to supply hydrogen gas or a source gas. Additionally, an additional gas supply 228 is fluidly coupled to the remote plasma source 202 to supply one or more additional gases. The one or more additional gases may also include a co-reactant gas. While the embodiment of FIG. 2 illustrates the gas mixture of the source gas and one or more additional gases being introduced through separate gas outlets, it will be understood that the gas mixture may be introduced directly into the remote plasma source 202. That is, a premixed dilution gas mixture may be supplied to the remote plasma source 202 through a single gas outlet.

[0036] Gases, such as excited hydrogen and helium radicals and relaxed gases / radicals, flow from the remote plasma source 202 through the showerhead 206 and into the reaction chamber 204. The gases in the showerhead 206 and the reaction chamber 204 generally do not undergo continuous plasma excitation therein. In some embodiments, the showerhead 206 includes an ion filter and / or a photon filter. Filtering ions and / or photons can reduce substrate damage, unwanted re-excitation of molecules, and / or selective decay or decomposition of hydrocarbon precursors in the reaction chamber 204. The showerhead 206 has multiple gas ports 234 to diffuse the gas flow into the reaction chamber 204. In some embodiments, the multiple gas ports 234 can be spaced apart from one another. In some embodiments, the multiple gas ports 234 can be arranged as an array of regularly spaced channels or through-holes extending through a plate separating the remote plasma source 202 and the reaction chamber 204. The multiple gas ports 234 can smoothly distribute and diffuse the existing radicals from the remote plasma source 202 into the reaction chamber 204 .

[0037] Typical remote plasma sources are far from the reaction vessel. As a result, radical quenching and recombination, for example, via wall collision events, can substantially reduce the number of activated species. In contrast, in some embodiments, the dimensions of the gas ports 234 are configured to account for the mean free path or gas flow residence time under typical processing conditions, which can support the free passage of radicals into the reaction chamber 204. In some embodiments, the openings for the gas ports 234 can occupy about 5% to about 20% of the exposed surface area of ​​the showerhead 206. In some embodiments, the gas ports 234 can each have an axial length-to-diameter ratio of about 3:1 to 10:1, or about 6:1 to about 8:1. Such aspect ratios can provide sufficient time for a majority of the excited-state radical species to relax to ground-state radical species while reducing the wall collision frequency for radical species passing through the gas ports 234. In some embodiments, the dimensions of the plurality of gas ports 234 can be configured so that the residence time of gas passing through the showerhead 206 is longer than the typical energy relaxation time of the excited state radical species. The excited state radical species for the hydrogen source gas are represented by H * and the ground state radical species for the hydrogen source gas may be represented by ●H in FIG.

[0038] In some embodiments, excited-state radical species exiting the plurality of gas ports 234 can flow into a relaxation zone 238 contained within the reaction chamber 204. The relaxation zone 238 is positioned upstream of the chemical vapor deposition zone 208 and downstream of the showerhead 206. Substantially all, or at least 90%, of the excited-state radical species exiting the showerhead 206 transition to relaxed-state radical species in the relaxation zone 238. Stated another way, almost all of the excited-state radical species (e.g., excited hydrogen radicals) entering the relaxation zone 238 are de-excited or transition to relaxed-state radical species (e.g., ground-state hydrogen radicals) before exiting the relaxation zone 238. In some embodiments, the process conditions or geometry of the relaxation zone 238 can be configured to provide a residence time for the radical species flowing through the relaxation zone 238, e.g., a time determined by the mean free path and average molecular velocity, resulting in the relaxed-state radical species flowing out of the relaxation zone 238.

[0039] One or more hydrocarbon precursors can be introduced into the chemical vapor deposition zone 208 by delivering radical species from the showerhead 206 to the relaxation zone 238. The one or more hydrocarbon precursors can be introduced through a gas distributor or gas outlet 242, which can be fluidly coupled to the precursor source 240. The relaxation zone 238 can be contained within the space between the showerhead 206 and the gas outlet 242. The gas outlet 242 can include spaced-apart openings such that a flow of one or more hydrocarbon precursors can be introduced in a direction parallel to the gas mixture flowing from the relaxation zone 238. The gas outlet 242 can be located downstream from the showerhead 206 and the relaxation zone 238. The gas outlet 242 can be located upstream from the chemical vapor deposition zone 208 and the substrate 212. The chemical vapor deposition zone 208 is located within the reaction chamber 204 between the gas outlet 242 and the substrate 212.

[0040] Substantially all of the flow of the one or more hydrocarbon precursors can be prevented from mixing with excited state radical species adjacent to the showerhead 206. The relaxed or ground state radical species mix with the one or more hydrocarbon precursors in a region adjacent to the substrate 212. The chemical vapor deposition zone 208 includes a region adjacent to the substrate 212 where the relaxed or ground state radical species mix with the one or more hydrocarbon precursors. The relaxed or ground state radical species mix with the one or more hydrocarbon precursors in the gas phase during CVD formation of graphene.

[0041] In some embodiments, a co-reactant may be introduced through the showerhead 206 and flowed into the reaction chamber 204 along with the radical species generated in the remote plasma source 202. This may include radicals and / or ions of a co-reactant gas provided to the remote plasma source 202. The co-reactant may be supplied from an additional gas supply 228. In some embodiments, the co-reactant may include a nitrogen-containing agent, such as nitrogen gas (N). For example, during pretreatment of the metal surface of the substrate 212, nitrogen radicals and / or ions may be generated and flowed along with the hydrogen radical species.

[0042] The gas outlet 242 can be separated from the showerhead 206 by a distance sufficient to prevent back-diffusion or backflow of one or more hydrocarbon precursors. This allows sufficient time for hydrogen radical species to transition from an excited state to a relaxed state (e.g., a ground state). In some embodiments, the gas outlet 242 can be separated from the plurality of gas ports 234 by a distance of about 0.5 inches to about 5 inches, or about 1.5 inches to about 4.5 inches, or about 1.5 inches to about 3 inches.

[0043] Process gases can be removed from the reaction chamber 204 via an outlet 248 fluidly coupled to a pump (not shown). Thus, excess hydrocarbon precursor, co-reactant, radical species, as well as diluents and displacement or purge gases can be removed from the reaction chamber 204. In some embodiments, a system controller 250 is in operative communication with the plasma processing apparatus 200. In some embodiments, the system controller 250 includes a processor system 252 (e.g., a microprocessor) configured to execute instructions stored in a data system 254 (e.g., a memory). In some embodiments, the system controller 250 can communicate with the plasma generator controller 222 to control plasma parameters and / or conditions. In some embodiments, the system controller 250 can communicate with the pedestal 214 to control the height and temperature of the pedestal. In some embodiments, the system controller 250 can control other processing conditions such as RF power settings, frequency settings, duty cycle, pulse time, pressure in the reaction chamber 204, pressure in the remote plasma source 202, gas flow rates from the source gas supply 226 and additional gas supply 228, gas flow rates from the precursor source 240 and other sources, the temperature of the pedestal 214, and the temperature of the reaction chamber 204, among others.

[0044] The controller 250 may contain instructions for controlling process conditions for operation of the plasma processing apparatus 200. The controller 250 typically includes one or more memory devices and one or more processors. The processor may include a CPU or computer, analog and / or digital input / output connections, a stepper motor controller board, etc. Instructions for performing appropriate control operations are executed on the processor. These instructions may be stored in a memory device associated with the controller 250 or provided over a network.

[0045] In certain embodiments, the controller 250 controls all or most of the activities of the plasma processing apparatus 200 described herein. For example, the controller 250 can control all or most of the activities of the plasma processing apparatus 200 associated with graphene deposition and, optionally, other operations in a fabrication flow involving graphene. The controller 250 can execute system control software including a set of instructions for controlling timing, gas composition, gas flow rates, chamber pressure, chamber temperature, RF power levels, substrate position, and / or other parameters. In some embodiments, other computer programs, scripts, or routines stored on a memory device associated with the controller 250 can be used. Parameters such as RF power levels, gas flow rates to the plasma region 224, gas flow rates to the chemical vapor deposition zone 208, and timing of plasma ignition can be adjusted and maintained by the controller 250 to provide relatively mild reaction conditions in the environment adjacent to the substrate 212. Additionally, adjusting the substrate position can further reduce the presence of high-energy radical species in the environment adjacent to the substrate 212. In a multi-station reactor, the controller 250 can contain different or identical instructions for different equipment stations, thus allowing the equipment stations to operate independently or synchronously.

[0046] In some embodiments, the controller 250 may include instructions for performing operations such as flowing one or more hydrocarbon precursors into the reaction chamber 204 through the gas outlet 242, providing a source gas into the remote plasma source 202, generating one or more radical species of the source gas in the remote plasma source 202 upstream of the one or more hydrocarbon precursors, and introducing the one or more radical species from the remote plasma source 202 into the reaction chamber 204 and reacting them with the one or more hydrocarbon precursors to deposit graphene on the metal surface of the substrate 212. The one or more radical species in the reaction chamber 204 in the environment adjacent to the substrate 212 may be ground-state hydrogen radicals. In some embodiments, the controller 250 may include instructions for treating the metal surface of the substrate 212 before depositing graphene. In some embodiments, the controller 250 may include instructions for maintaining the temperature of the substrate 212 at or below about 400°C, or between about 200°C and about 400°C. In some embodiments, each of the one or more hydrocarbon precursors includes an alkene group or an alkyne group.

[0047] In some embodiments, the apparatus 200 may include a user interface associated with the controller 250. The user interface may include a display screen, a graphical software display of the apparatus 200 and / or process conditions, and a user input device such as a pointing device, a keyboard, a touch screen, a microphone, etc.

[0048] Computer program code for controlling the above operations can be written in any conventional computer-readable programming language (e.g., assembly language, C, C++, Pascal, Fortran, etc.) The compiled object code or script is executed by a processor to perform the tasks identified in the program.

[0049] Signals for monitoring the process may be provided by analog and / or digital input connections of the system controller, and signals for controlling the process are output at analog and digital output connections of the processing system.

[0050] Generally, the methods described herein can be performed on systems including semiconductor processing equipment, such as one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (e.g., wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling system operation before, during, and after processing of a semiconductor wafer or substrate. Generally, the electronics are referred to as a "controller" and may control various components or subcomponents of one or more systems. The controller may be programmed to control any of the processes disclosed herein depending on the processing requirements and / or type of system. Such processes include process gas delivery, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and motion settings, wafer transfer to and from the tool, and wafer transfer to and from other transfer tools and / or load locks connected or interfaced with the particular system.

[0051] Broadly, a controller may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. Integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application-specific integrated circuits (ASICs), and / or one or more microprocessors, i.e., microcontrollers, that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. The operational parameters, in some embodiments, may be part of a recipe defined by a process engineer to implement one or more processing steps in the fabrication of one or more layers, materials (e.g., silicon carbide), surfaces, circuits, and / or wafer dies.

[0052] In some embodiments, the controller may be part of, coupled to, or a combination of a computer integrated with, coupled to, or otherwise networked to the system. For example, the controller may be in the “cloud” or all or part of a fab host computer system. This allows for remote access to wafer processing. The computer may provide remote access to the system to monitor the current progress of a fabrication operation, review the history of past fabrication operations, review trends or performance criteria from multiple fabrication operations, modify parameters of a current process, set processing steps following a current process, or initiate a new process. In some examples, a remote computer (e.g., a server) can provide process recipes to the system over a network. Such a network may include a local network or the Internet. The remote computer may include a user interface that allows entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data. Such data may identify parameters for each processing step performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Thus, as discussed above, the controller may be distributed, for example, by having one or more individual controllers networked together and working together toward a common purpose (such as the processes and controls described herein). An example of a distributed controller for such purposes would include one or more integrated circuits on the chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer) and coupled to control the process in the chamber.

[0053] In addition to the graphene deposition described herein, exemplary systems may include a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a tracking chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0054] As noted above, depending on the process step or steps being performed by the tool, the controller may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to and from tool locations and / or load ports in a semiconductor fabrication factory.

[0055] Raman spectroscopy can be used to characterize graphene. Raman spectroscopy can also be suitable for determining the number of graphene layers as well as the amount of disorder in graphene. By identifying specific features of graphene in the Raman spectrum, graphene can be distinguished from disordered or amorphous carbon layers.

[0056] 3 shows a graph illustrating Raman spectra of example single-layer and multi-layer graphene, according to some embodiments. Graphene has a peak at about 1580 cm -1 G peak at about 2680 cm -1Graphene can be characterized in the Raman spectrum by the presence of a 2D peak at approximately 1380 cm, which is generally equal to or greater than the G peak in intensity. If the intensity of the 2D peak is significantly less than the G peak, the deposited film cannot be characterized as graphene. The presence of a 2D peak and a G peak is generally a strong indicator of the presence of graphene. However, disordered or amorphous carbon can be characterized by a 2D peak at approximately 1380 cm. -1 Disorder can be characterized in Raman spectra by the presence of a D peak at the nucleus. As disorder increases, the Raman intensity of the D peak typically increases. The higher the D peak, the greater the number of defects in the as-deposited graphene. Such defects may include, but are not limited to, vacancies that signal the absence of graphene, or grain boundaries between different graphene crystals that potentially disrupt the planar structure of graphene.

[0057] Raman spectroscopy can also be used to determine the number of graphene layers. In some embodiments, the ratio of the intensity of the 2D peak to the intensity of the G peak (I 2D / I G ) can correspond to the number of graphene layers. Specifically, I 2D / I G When the ratio of I is greater than 2, the deposited graphene film corresponds to monolayer graphene. 2D / I G When the ratio of is slightly larger than 1 or slightly smaller than 1 as shown in FIG. 3, the deposited graphene film may correspond to bilayer graphene or few-layer graphene, respectively.

[0058] Raman spectroscopy can also be used to determine the size and type of crystallites within the graphene structure. In some embodiments, the ratio of the intensity of the G peak to the intensity of the D peak (I G / I D ) can correspond to the grain size. As the ratio increases, this also indicates an increase in the grain size. In addition, as the ratio decreases, this also indicates an increase in the number of defects that can potentially disrupt the planar structure of graphene.

[0059] In some embodiments, the graphene film deposited on a metal surface has a thickness of about 10 nm or less, about 5 nm or less, about 3 nm or less, or about 1 nm or less. The thickness of the graphene film can depend on the metal surface on which it is deposited. For example, when deposited on copper, the graphene film can be monolayer or several monolayers thick, and its thickness can be less than about 1 nm. The graphene film can be monolayer graphene, bilayer graphene, or several layers of graphene. This can occur when the graphene film is deposited on a metal such as copper. In another example, when deposited on other metals such as cobalt, the graphene film can be several nanometers thick (e.g., about 2-3 nm).

[0060] 4 shows a flow diagram of an exemplary method for depositing graphene on a metal surface of a substrate, according to some embodiments. The operations of process 400 may be performed in a different order and / or with different, fewer, or additional operations. The operations of process 400 may be performed using the plasma processing apparatus shown in FIG. 2. In some embodiments, the operations of process 400 may be performed, at least in part, according to software stored on one or more non-transitory computer-readable media.

[0061] In block 410 of process 400, the metal surface of the substrate can be optionally treated before graphene deposition. Graphene deposition can depend on the smoothness and purity of the metal surface on which the graphene is grown. Surface treatment techniques can be applied to the metal surface to polish the substrate and remove impurities. Substrate polishing can be performed by light etching in some embodiments. Impurity removal can be performed by chemical treatment, for example, to remove metal oxides. Impurity removal can additionally or alternatively involve removal of residue or contaminants from a chemical mechanical planarization (CMP) process. In some embodiments, metal surface treatment can be performed before diffusion barrier deposition, etch stop deposition, or hermetic barrier deposition.

[0062] In some embodiments, treating the metal surface of the substrate can include exposing the metal surface to a plasma of a reducing gas species. Treating the metal surface can include at least removing impurities and / or reducing metal oxides by exposure to the plasma. In some embodiments, the plasma can include ions and radicals of the reducing gas species. The reducing gas species can include, for example, hydrogen gas (H), ammonia (NH), or a combination thereof. Thus, the metal surface can be treated with H plasma, NH plasma, or H / NH plasma. The plasma can be a direct (in-situ) plasma or a remote plasma. In some embodiments, exposing the metal surface to a plasma of a reducing gas species includes exposing the metal surface to a remote hydrogen plasma.

[0063] In some embodiments, treating the metal surface further comprises exposing the metal surface to cyano-based radical species. In some other embodiments, treating the metal surface comprises exposing the metal surface to cyano-based radical species instead of exposing the metal surface to reducing gas species. The cyano-based radical species can perform a light etch to smooth the metal surface prior to graphene growth. Exposing the metal surface to cyano-based radical species can occur before or after exposing the metal surface to a plasma of reducing gas species. This can be referred to as a multi-step pretreatment process. The multi-step pretreatment process, or at least some steps of the multi-step pretreatment process, can be performed in the same or a different apparatus as the plasma processing equipment used to deposit graphene. Exposing the metal surface to cyano-based radical species can occur simultaneously with exposing the metal surface to a plasma of reducing gas species. This can be referred to as a single-step pretreatment process. The single-step pretreatment process can be performed in the same or a different apparatus as the plasma processing equipment used to deposit graphene.

[0064] In the multi-step pretreatment process, cyano-based radical species can be generated by igniting a plasma, which can be an in-situ plasma or a remote plasma. The cyano-based radical species can be generated from a gas mixture containing at least a carbon-containing source gas and a nitrogen-containing source gas, or from a gas mixture containing a precursor having a carbon-nitrogen (CN) bond. Thus, treating the metal surface can further include generating a plasma containing cyano-based radical species from at least a carbon-containing source gas and a nitrogen-containing source gas, or from a precursor having a carbon-nitrogen bond. For example, a gas mixture of a hydrocarbon precursor, nitrogen gas, and hydrogen gas can be supplied to a plasma generator, and a plasma of the gas mixture can be ignited to form the cyano-based radical species.

[0065] In a single-stage pretreatment process, cyano-based radical species can be generated by activating a downstream carbon-containing precursor. The activation of the downstream carbon-containing precursor is performed simultaneously with surface pretreatment with a plasma of a reducing gas species. In such cases, a remote plasma source is positioned upstream of the downstream carbon-containing precursor, and the plasma of the reducing gas species is generated by the remote plasma source. In some embodiments, the downstream carbon-containing precursor can be a hydrocarbon precursor. Thus, the downstream carbon-containing precursor can be chemically the same as or different from the hydrocarbon precursor used to deposit graphene. In such cases, the plasma of the reducing gas species is a plasma of a reducing gas species and a nitrogen-containing agent. For example, the reducing gas species can include hydrogen gas. The nitrogen-containing agent can include nitrogen gas. Thus, the plasma of the reducing gas species and the nitrogen-containing agent can be a remote H2 and N2 plasma. The concentration of the reducing gas species can be higher than the concentration of the nitrogen-containing agent in the plasma. Without being limited to any theory, it is believed that ions / radicals of the nitrogen-containing agent interact with the downstream carbon-containing precursor to form cyano-based radical species. Cyano-based radical species can perform light etching to smooth metal surfaces, and reducing gas species plasma can reduce metal oxides on metal surfaces to metal. In some other embodiments, the downstream carbon-containing precursor can be a precursor gas containing one or more C-N bonds. Such precursors can be activated by a reducing gas species plasma, which is a remote plasma generated upstream from a remote plasma source. In some cases, the reducing gas species plasma is a remote hydrogen plasma. Without being limited to any theory, it is believed that hydrogen ions / radicals interact with the downstream carbon-containing precursor containing one or more C-N bonds to form cyano-based radical species.

[0066] While the processing operations in block 410 may be described with respect to multi-step and single-step pretreatment processes, it will be understood that the pretreatment of the metal surface is not limited to such techniques. The metal surface of the substrate can be pretreated prior to graphene deposition using any suitable surface treatment technique known in the art.

[0067] At block 420 of process 400, a substrate is provided in the reaction chamber, the substrate including a metal surface. In some implementations, the substrate may already be provided in the reaction chamber during processing at block 410. The substrate may be a semiconductor substrate used in semiconductor applications. The metal surface may include any suitable metal, such as a transition metal. For example, the metal surface may include copper, ruthenium, nickel, molybdenum, cobalt, or a combination thereof. The metal surface may function as a catalyst to promote graphene nucleation and growth. Graphene deposition may be selective to certain metals on the metal surface. In other words, graphene deposition may not occur on dielectric or other non-metallic surfaces.

[0068] The reaction chamber may include a substrate support or pedestal for supporting the substrate. The remote plasma source may be fluidly coupled to the reaction chamber via a showerhead. The metal surface of the substrate may face toward the remote plasma source. Precursor gas lines may be separately fluidly coupled to the reaction chamber via one or more gas outlets. The one or more gas outlets may be located downstream from the remote plasma source. The one or more gas outlets may deliver hydrocarbon precursors into the reaction chamber, and the remote plasma source may generate hydrogen radicals for delivery into the reaction chamber.

[0069] In block 430 of process 400, one or more hydrocarbon precursors are flowed into the reaction chamber toward the substrate. Each of the one or more hydrocarbon precursors includes an alkene or alkyne group. This means that the hydrocarbon precursor includes one or more unsaturated carbon bonds, such as one or more carbon-carbon double bonds and / or carbon-carbon triple bonds. Examples of hydrocarbon precursors having an alkene or alkyne group include, but are not limited to, toluene, benzene, ethylene, propylene, butene, pentadiene (e.g., 1,4-pentadiene), hexene, acetylene, propyne, butyne, or pentyne. In some embodiments, each of the one or more hydrocarbon precursors can include a carbon chain having at least two carbon atoms, at least three carbon atoms, at least four carbon atoms, at least five carbon atoms, at least six carbon atoms, or at least seven carbon atoms.

[0070] The one or more hydrocarbon precursors can be flowed into the reaction chamber through one or more gas outlets fluidly coupled to the reaction chamber. The one or more gas outlets are positioned downstream from the remote plasma source. The plasma of the one or more hydrocarbon precursors is not generated in the reaction chamber or the remote plasma source. Rather, the one or more hydrocarbon precursors are flowed into the reaction chamber independently of the plasma generated in the remote plasma source.

[0071] One or more hydrocarbon precursors are flowed toward the substrate and adsorb onto the metal surface, or are at least positioned in an environment adjacent to the metal surface of the substrate. In some embodiments, the one or more hydrocarbon precursors are flowed into the reaction chamber simultaneously with plasma generation and plasma exposure, as described in blocks 440 and 450. In some embodiments, the one or more hydrocarbon precursors are flowed into the reaction chamber before plasma generation and plasma exposure, as described in blocks 440 and 450.

[0072] In some embodiments, one or more hydrocarbon precursors are delivered into an environment adjacent to the metal surface of the substrate along with other species, particularly a carrier gas. Upstream of the deposition reaction surface, the one or more hydrocarbon precursors can be mixed with an inert carrier gas. Exemplary inert carrier gases include, but are not limited to, argon (Ar) and helium (He). In some embodiments, the one or more hydrocarbon precursors are delivered as a mixture of multiple hydrocarbon precursors. The multiple hydrocarbon precursors can be present in equimolar or relatively similar proportions appropriate for forming the main backbone or matrix of the resulting graphene. In other embodiments, the relative amounts of the multiple hydrocarbon precursors are substantially different from equimolar.

[0073] In block 440 of process 400, hydrogen radicals are generated from a hydrogen source gas in a remote plasma source positioned upstream of one or more hydrocarbon precursors. Specifically, the hydrogen radicals are generated in a remote plasma source upstream from one or more gas outlets for introducing the one or more hydrocarbon precursors into the reaction chamber. The remote plasma source can be any suitable plasma source for plasma generation, such as an inductively coupled plasma source or a capacitively coupled plasma source. In some implementations, the hydrogen source gas is hydrogen gas (H). In some implementations, the hydrogen gas is flowed into the remote plasma source along with one or more additional gases, such as helium (He). In certain embodiments, the hydrogen source gas is provided in a carrier gas, such as helium. By way of example, the hydrogen gas can be provided in a helium carrier at a concentration of about 1-25% hydrogen or 1-10% hydrogen. Thus, in some cases, a H / He plasma is generated in the remote plasma source.

[0074] In block 450 of process 400, hydrogen radicals are introduced into a reaction chamber toward the substrate, where they react with one or more hydrocarbon precursors to deposit graphene on the metal surface of the substrate. The hydrogen radicals are delivered into the reaction chamber under process conditions such that excited radicals transition to relaxed radicals without recombining. The pressure, the proportion of a carrier gas such as helium, the geometry of the showerhead gas ports, the distance between the showerhead and one or more gas outlets, and other process conditions are configured so that hydrogen atoms encounter the substrate as low-energy (e.g., ground-state) radicals without recombining. In some embodiments, all or substantially all of the hydrogen radicals in the environment adjacent to the substrate are ground-state hydrogen radicals. In this manner, the substrate is exposed to a remote hydrogen plasma that minimizes damage to surface growth.

[0075] When generated, the hydrogen radicals may be in an excited energy state. For example, hydrogen in an excited energy state may have an energy of at least 10.2 eV (first excited state). The excited hydrogen radicals may cause surface growth damage during graphene growth. In some embodiments, when the excited hydrogen radicals lose their energy or relax, they may become substantially lower energy state or ground state hydrogen radicals. In some embodiments, process conditions may be provided such that the excited hydrogen radicals lose energy or relax to form substantially lower energy state or ground state hydrogen radicals. For example, the remote plasma source or associated components may be designed such that the residence time of hydrogen radicals diffusing from the remote plasma source to the substrate is longer than the energy relaxation time of the excited hydrogen radicals. The energy relaxation time for excited hydrogen atom radicals is approximately 1×10 -3Other process conditions that are controlled to cause the excited hydrogen radicals to lose energy and relax to form ground state hydrogen radicals include, but are not limited to, pressure, gas flow rate, size and geometry of the relaxation zone, size and geometry of the gas ports in the showerhead, and the relative concentrations of the hydrogen source gas to the inert carrier gas.

[0076] The environment adjacent to the metal surface of the substrate may include one or more hydrocarbon precursors. In addition, the environment adjacent to the metal surface of the substrate may include hydrogen radicals in a low-energy state (e.g., ground state). The environment adjacent to the metal surface of the substrate includes the metal surface as well as the space immediately above the exposed surface of the substrate. Indeed, activation of hydrocarbon precursors by low-energy hydrogen radicals may occur on the metal surface of the substrate or at a distance from the metal surface. In some embodiments, the distance from the metal surface of the substrate may be up to about 100 millimeters above the metal surface of the substrate. Typically, the reaction conditions in the environment adjacent to the metal surface of the substrate are generally uniform across the metal surface of the substrate, although some variation may be tolerated.

[0077] In some embodiments, all, substantially all, or a significant proportion of the hydrogen atom radicals may be in the ground state, e.g., at least about 90% or 95% of the hydrogen atom radicals adjacent to the metal surface of the substrate are in the ground state. As used herein, hydrogen radicals may also be referred to as "hydrogen radicals" and "hydrogen atom radicals." A state in which a significant proportion of the hydrogen atom radicals are in the ground state can be achieved by various techniques. Some apparatuses, such as those described in FIG. 2, are designed to achieve this state. Process conditions for achieving hydrogen atom radicals in the ground state may not have a significant amount of ions, electrons, or radical species in higher energy states, such as states above the ground state. The presence of a significant amount of ions or high-energy radicals may cause surface growth damage on the substrate, resulting in poor-quality graphene or disordered carbon growth. In some embodiments, the concentration of ions in the environment adjacent to the metal surface of the substrate is greater than about 10 7 / cm 3 Ground-state hydrogen atom radicals can provide sufficient energy to activate one or more hydrocarbon precursors while providing mild conditions in the environment adjacent to the metal surface to limit damage to the surface growth.

[0078] One or more hydrocarbon precursors are flowed into the reaction chamber downstream from the hydrogen radicals, which are generated in a remote plasma source located upstream from one or more gas outlets for introducing the one or more hydrocarbon precursors. By the time the hydrogen radicals reach the one or more hydrocarbon precursors, the hydrogen radicals have mixed or interacted with the one or more hydrocarbon precursors and are in a low energy or ground state.

[0079] Without being limited to any theory, one of the more kinetically favorable reaction mechanisms in the deposition reaction involves hydrogen abstraction, resulting in activated hydrocarbon precursors. Without being limited to any theory, hydrogen radicals in a low-energy or ground state can interact with alkyne or alkene groups within hydrocarbon molecules, resulting in the formation of activated alkanes (e.g., methane). In some cases, hydrocarbon precursors decompose into shorter-chain hydrocarbon molecules or radicals. Activated alkanes contain at least one carbon radical as an active site, which can react with each other to form carbon-carbon bonds within graphene. Bonding and crosslinking at the active sites can form the main backbone or matrix of the resulting graphene film. Metal surfaces can act as catalysts to promote the reaction between activated hydrocarbon precursors.

[0080] The hydrocarbon precursors do not function as passive spectators but contribute significantly to the composition of graphene. In some embodiments, substantially all or a significant proportion of the atoms in graphene are provided by one or more hydrocarbon precursors, with small amounts of hydrogen or other elements from the remote hydrogen plasma providing less than about 5 atomic percent or less than about 2 atomic percent of the film mass. In such cases, the low-energy hydrogen atom radicals used to drive the deposition reaction do not substantially contribute to the mass of the deposited graphene.

[0081] The temperature of the environment adjacent to the metal surface of the substrate can be any suitable temperature that promotes the deposition reaction. In some embodiments, the temperature of the environment adjacent to the metal surface of the substrate can be largely controlled by the temperature of the pedestal on which the substrate is supported during graphene deposition. In some embodiments, the operating temperature can be about 500°C or less, about 450°C or less, about 400°C or less, about 350°C or less, about 300°C or less, about 200°C to about 400°C, about 250°C to about 400°C, or about 200°C to about 300°C. Such temperatures can be suitable for semiconductor applications. In some embodiments, the temperature can depend on the metal of the metal surface on which graphene is deposited. For example, copper can withstand temperatures of 400°C or less, and ruthenium can withstand temperatures of 450°C or less.

[0082] The pressure in the environment adjacent to the metal surface of the substrate can be any suitable pressure to promote graphene growth in the reaction chamber. In some embodiments, the pressure can be about 10 Torr or less, or about 5 Torr or less. For example, the pressure can be about 1 Torr to about 2 Torr.

[0083] Graphene can be selectively deposited on metal surfaces from the reaction of hydrogen radicals with one or more hydrocarbon precursors provided downstream from a remote plasma source. The relatively mild reaction conditions provided by the hydrogen radicals in a low-energy state (e.g., ground state) activate the one or more hydrocarbon precursors to form carbon radicals. Thus, the carbon radicals are formed outside the remote plasma source where the plasma is generated. Controlling the amount of carbon radicals in the environment adjacent to the metal surface of the substrate can limit the number of nucleation sites for graphene growth. Without being limited to any theory, an excessive number of nucleation sites may correspond to an excessive number of defects during graphene growth.

[0084] Graphene can be selectively deposited on transition metals such as copper, ruthenium, nickel, molybdenum, cobalt, or combinations thereof. In some embodiments, the metal surface comprises copper. In some embodiments, the graphene on the metal surface is relatively thin, being on the order of a few monolayers thick. In some embodiments, the thickness of the graphene is about 10 nm or less, about 5 nm or less, about 3 nm or less, or about 1 nm or less. The thickness of the graphene can depend on the metal surface on which it is deposited. For example, the thickness of the graphene can be less than about 1 nm when deposited on copper. The graphene can be monolayer graphene, bilayer graphene, or few-layer graphene. The Raman spectrum of graphene can be characterized by a D peak of negligible intensity and a 2D peak that is equal to or greater than the G peak. It will be appreciated that the intensity of the D peak is significantly less than the 2D peak and the G peak.

[0085] In some embodiments, the process 400 may further include annealing the graphene on the metal surface of the substrate. The graphene annealing may be performed at an elevated temperature to remove defects from the graphene crystal structure. More specifically, the graphene annealing may be performed at an elevated temperature higher than the graphene deposition temperature. This ensures the formation of high-quality graphene. In some embodiments, the elevated temperature may be about 200°C or higher, about 250°C or higher, about 300°C or higher, or about 400°C or higher. For example, if the graphene is deposited at a temperature less than about 250°C, the annealing may be performed at an elevated temperature greater than about 250°C.

[0086] Annealing of graphene can be performed at a temperature range between the graphene deposition temperature and the semiconductor processing temperature limit. The semiconductor processing temperature limit can be the temperature limit at which materials (e.g., metals) in the substrate melt or are potentially physically damaged. For example, the temperature limit for copper is approximately 400°C, and the temperature limit for ruthenium is approximately 450°C. The elevated temperature for annealing can depend on the metals in the semiconductor substrate and the temperature limits compatible with back-end semiconductor processing. Thus, annealing can be performed at a temperature higher than the graphene deposition temperature but not exceeding the semiconductor processing temperature limit. In some embodiments, the temperature range for annealing graphene is 200°C to 450°C, 200°C to 400°C, 250°C to 400°C, or 300°C to 350°C.

[0087] Annealing graphene can significantly improve graphene quality by reducing defects, resulting in a decrease in the D peak, an increase in the ratio between the 2D peak and the G peak, and / or an increase in the ratio between the G peak and the D peak. As previously mentioned, a decrease in the D peak indicates the removal of defects in the graphene's crystalline structure. An increase in the ratio between the 2D peak and the G peak indicates the presence of single-layer, bilayer, or few-layer graphene, as opposed to disordered or amorphous carbon. The higher the ratio, the higher the crystallinity of the film. For example, annealing graphene can increase the ratio between the 2D peak and the G peak from approximately 1:1 to approximately 2:1. Furthermore, an increase in the ratio between the G peak and the D peak indicates an increase in grain size. Annealing can remove adsorbates or defects that disrupt the planar structure of graphene while simultaneously increasing grain size, thereby improving film quality. In some embodiments, annealing of the graphene is carried out in air or an inert gas atmosphere, the inert gas atmosphere comprising an inert gas such as argon (Ar), helium (He), nitrogen (N), or a combination thereof. In some embodiments, annealing can be carried out for a period of about 30 minutes or less, about 20 minutes or less, about 10 minutes or less, or about 5 minutes or less.

[0088] Graphene films are not typically subjected to annealing because they are typically deposited at high temperatures, e.g., above about 400°C. However, when graphene is deposited at low temperatures, e.g., about 200°C to about 300°C, annealing can be a critical step to improve the quality of the graphene film without exceeding the temperature-sensitive limits of semiconductor processing. In other words, annealing is performed within back-end thermal budget constraints. Therefore, annealing can be a critical step in integrating graphene into semiconductor processing applications. In some embodiments, annealing occurs after graphene deposition, but may occur before and / or after deposition of an etch stopper, diffusion barrier, or hermetic barrier.

[0089] Graphene can reduce the effective resistivity of metal lines and limit electromigration. Low-temperature deposition of graphene allows it to be integrated into process flows for manufacturing semiconductor devices, such as back-end of line (BEOL) semiconductor processing. BEOL semiconductor processing can involve providing electrical interconnects with one or more conductive vias between metallization layers. During BEOL semiconductor processing, graphene can be deposited on the metallization layers or metal lines.

[0090] Graphene as an inhibitor Conductive structures typically include line features that traverse distances across a chip and via features that connect lines at different levels. Damascene or dual damascene processes can be used to connect lines at different levels. To improve the performance of semiconductor devices, feature sizes are becoming smaller and smaller. As a result, interconnect features and vias are also shrinking. This presents many challenges during fabrication and in maintaining device performance and reliability.

[0091] Typically, standard deposition and lithography techniques are utilized when connecting lines at different levels. For example, conventional photolithography techniques use patterning and etching processes to define conductive structure features. In these processes, a photoresist material is deposited on a substrate and then exposed to light filtered by a reticle. The reticle is typically a glass plate patterned with feature geometries that block light from propagating through the reticle. After passing through the reticle, the light contacts the surface of the photoresist material, changing its chemical composition, allowing a developer to remove portions of the photoresist material. To remove portions of the photoresist material, a developer is applied to the photoresist material. The patterned photoresist material is used as a mask to etch the underlying layer.

[0092] As feature sizes decrease, scaling conventional lithography processes to accommodate smaller feature sizes can become difficult. This is due, at least in part, to alignment or overlay errors between features within a conductive structure. Such alignment or overlay errors are sometimes referred to as edge placement errors. Edge placement errors inevitably occur during the lithography process when the mask is not perfectly aligned with the underlying structure. For example, during the exposure step using a reticle in the photolithography process, misalignment of several nanometers can occur when patterning the mask for vias and trenches. As a result, vias intended to connect top metal lines with bottom metal lines can be misaligned. While edge placement errors can be minimized by reworking the lithography process, some degree of overlay error is unavoidable.

[0093] 5A-5D show cross-sectional schematic views of an exemplary dual damascene fabrication process with a "partially landed" via. As shown in FIG. 5A, a substrate 500 includes a first dielectric layer 510 having first metal layers 520A and 520B formed thereon, where each of the first metal layer 520A and adjacent first metal layer 520B can extend partially or completely through the first dielectric layer 510. The substrate 500 can be a semiconductor wafer built on a semiconductor wafer or a portion of a semiconductor wafer. The first dielectric layer 510, sometimes referred to as an interlayer dielectric, includes a dielectric material such as a low-k dielectric material. In some implementations, the first dielectric layer 510 includes fluorine-doped or carbon-doped silicon oxide or an organic-containing low-k dielectric material such as organosilicate glass (OSG). Each of the first metal layer 520A and the adjacent first metal layer 520B may comprise any suitable metal, such as copper (Cu). Each of the first metal layer 520A and the adjacent first metal layer 520B may be lined with at least a first barrier layer 522 to limit diffusion of the metal into the first dielectric layer 510. Examples of barrier layers may include, but are not limited to, titanium (Ti), tantalum (Ta), tantalum nitride (TaN), and titanium nitride (TiN). While FIG. 5A shows a single layer for the first barrier layer 522, it will be understood that the first barrier layer 522 may include multiple layers, such as diffusion barrier layers and liner layers.

[0094] In Figure 5B, a second dielectric layer 540 is formed on the first dielectric layer 510. Optionally, an etch stop layer 530 is positioned between the second dielectric layer 540 and the first dielectric layer 510. Although Figure 5B shows a single layer for the etch stop layer 530, it will be understood that the etch stop layer 530 may include multiple layers, such as diffusion barrier layers and / or liner layers.

[0095] 5C, etching is performed to form a recess 550 through the second dielectric layer 540. The recess 550 can be formed through the second dielectric layer 540 using standard lithography techniques. The recess 550 may also be referred to as an opening, trench, contact hole, or etched feature. The recess 550 may expose the top surface of the first metal layer 520A. However, due to the above-mentioned overlay and alignment errors, the recess 550 may partially expose the top surface of the first dielectric layer 510 in addition to the top surface of the first metal layer 520A.

[0096] In FIG. 5D , the recess 550 is lined with a second barrier layer 562 and subsequently filled with metal to form a via 560 and a second metal layer 570. While FIG. 5D shows a single layer for the second barrier layer 562, it will be understood that the second barrier layer 562 may include multiple layers, such as diffusion barrier layers and liner layers. The second metal layer 570 and the via 560 are formed through the second dielectric layer 540. The second metal layer 570 and the first metal layer 520A are electrically connected, forming a conductive path through the via 560. In FIG. 5D , for example, the via 560 is shown as being misaligned with the first metal layer 520A. This type of misalignment can become more significant as feature sizes shrink.

[0097] Due to the above-mentioned overlay and alignment errors, the via 560 partially “lands” on the top surface of the first metal layer 520A, thereby bringing the via 560 closer to the adjacent first metal layer 520B. This reduces the distance 580 between the conductive features, which means that the insulating space between the via 560 and the adjacent first metal layer 520B is reduced. When the via 560 partially lands on the top surface of the first dielectric layer 510, it is sometimes referred to as an “unlanded” via. This means that the via 560 provides a landing portion on the first metal layer 520A and an unlanded portion outside the first metal layer 520A.

[0098] As the distance 580 decreases, the short-circuit margin becomes insufficient, potentially leading to reduced time-dependent dielectric breakdown (TDDB) or even complete shorts. TDDB is a failure mode in which an insulating layer (such as the first dielectric layer 510) no longer functions as an adequate electrical insulator in typical electric fields. TDDB depends on the electric field between metal features, as areas exposed to higher electric fields are more susceptible to TDDB failure. Higher voltages can lead to higher electric fields. TDDB also depends on the spacing between metal features, as the spacing can be reduced to the point where the dielectric layer cannot withstand the electric field, thereby creating unintended conductance between the metal features. If the dielectric layer cannot support the operating electric field, the end result is a short or reduced reliability. Non-landing vias can cause significant reliability issues due to TDDB degradation.

[0099] FIG. 5E shows a cross-sectional schematic diagram of an exemplary semiconductor device having an “unlanded” via that results in a tooth-shaped hole. In addition to the degradation of TDDB as a result of the unlanded via, overetching can occur when forming the recess 550 in FIG. 5C. When etching proceeds through the second dielectric layer 540, misalignment can expose not only the first metal layer 520A to the etch but also the first dielectric layer 510. The first metal layer 520A and the first dielectric layer 510 can etch at different rates. This allows etching to continue well below the local interconnect, forming a narrow channel at least partially through the first dielectric layer 510. When a narrow channel forms at least partially through the first dielectric layer 510, a tooth-shaped hole can result. The tooth-shaped hole is sometimes referred to as a “fang” or “tiger tooth” defect. The tooth-shaped hole may be lined with a barrier layer and filled with metal. This deposition in the tooth pits can cause metal shorts, which can result in significant RC delay, greater TDDB degradation, and possible device failure.

[0100] To address TDDB degradation and potential tooth-shaped hole formation in the dielectric layer, a spacer layer can be deposited on the dielectric layer to increase the distance between conductive features. For example, a spacer layer (not shown) can be deposited on the first dielectric layer 510 and between the first dielectric layer 510 and the second dielectric layer 540 in FIGS. 5A-5E to increase the separation distance 580 between the via 560 and the adjacent first metal layer 520B. Increasing the thickness of the spacer layer increases the separation distance 580, mitigating the effects of TDDB degradation. In some implementations, the spacer layer can function as an etch stop layer to prevent etching through the underlying dielectric layer. In some implementations, an etch stop layer can be deposited on the spacer layer to prevent etching through the underlying dielectric layer.

[0101] The placement of a spacer layer can aid in perfectly aligned via patterning. A perfectly aligned via patterning scheme not only aligns the via with the top metal layer, but also aligns the top metal layer with the bottom metal layer in the conductive structure. In other words, a perfectly aligned via is x The bottom metal layer and M x+1 This results in a via that is perfectly aligned with the upper metal layer on the level. Perfectly aligned vias refer to alignment in both the x and y directions. x Bottom metal layer on level or M x+1 A perfectly aligned via does not "unland" any portion of the via to any of the upper metal layers on the level. x ) and there is no overlapping contact on the top surface of the first dielectric layer 510. A spacer layer may be selectively deposited on the top surface of the first dielectric layer 510 relative to the first metal layer 520A to prevent such overlapping contact. The presence of the spacer layer creates a step-like topography, which allows for the M xThe bottom metal layer on the level is recessed below the top surface of the spacer layer. Perfectly aligned vias can address issues related to TDDB degradation and tooth-shaped hole formation caused by non-landing vias.

[0102] Formation of the spacer layer on the top surface of the dielectric layer may rely on selective deposition of the spacer layer on the top surface of the dielectric layer. In this way, the spacer layer can be formed on the top surface of the dielectric layer. x The insulating material is deposited only on the top surface of the dielectric layer, without depositing on the top surface of the underlying metal layer on the level. This prevents the deposition of insulating material on the exposed metal surfaces, thereby making more surface area available for electrical interconnections. By applying an inhibitor to the exposed metal surfaces, selective deposition of spacer layers or other insulating layers may be possible.

[0103] Figures 6A-6B show cross-sectional schematics of the selective deposition process using self-assembled monolayers (SAMs) as inhibitors. SAMs are molecular assemblies that include a head group, a spacer group, and an end group. The head group can be selected to bind to the surface or sidewall of a particular material, the end group can be functionalized for various purposes, and the spacer group can affect the thickness and density of the SAM. Exemplary head groups include, but are not limited to, thiols, silanes, and phosphates. SAMs can be deposited by chemisorption onto the surface of a particular material in the liquid or vapor phase.

[0104] In FIG. 6A , substrate 600 includes a metal layer 602 and a dielectric layer 604 adjacent to metal layer 602. SAM film 606 is deposited on the top surface of metal layer 602 in either liquid or vapor phase. The precursors utilized to form SAM film 606 can be selected to chemically react with the top surface of metal layer 602 but not with the top surface of dielectric layer 604. As a result, the top surface of dielectric layer 604 remains an exposed surface for subsequent deposition of one or more materials. The entire or substantially entire top surface of metal layer 602 is covered by SAM film 606. The terminal groups of SAM film 606 can have chemical properties that prevent or in some cases limit deposition on SAM film 606.

[0105] 6B, metal oxide 608 is selectively deposited on dielectric layer 604. In some embodiments, metal oxide 608 is selectively deposited on dielectric layer 604 using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or any other suitable deposition technique. In some embodiments, metal oxide 608 comprises aluminum oxide (AlO), hafnium oxide (HfO), zirconium oxide (ZrO), yttrium oxide (YO), zinc oxide (ZnO), or titanium oxide (TiO). SAM film 606 inhibits deposition of metal oxide 608 on metal layer 602. Thus, SAM film 606 functions as a wet or dry molecular inhibitor that inhibits deposition on SAM film 606, thereby selectively allowing deposition on dielectric layer 604 but inhibiting deposition on metal layer 602. In some embodiments, the SAM film 606 may optionally be removed by a suitable method, such as oxygen plasma, ozone plasma, and / or acidic solution.

[0106] Using SAM films as inhibitors can facilitate the selective deposition of one or more materials onto a dielectric layer instead of a metal layer. However, using SAM films can reduce selectivity and increase processing costs and complexity. Because SAM films are typically long-chain hydrocarbons, achieving a consistent dosage for chemisorption onto the inhibited surface presents challenges. In addition, SAM films generally require surface pretreatment of the inhibited surface prior to deposition. Because many SAM films are thermally unstable at high temperatures, deposition or other semiconductor integration steps performed at high temperatures can degrade the SAM film and reduce selectivity. Furthermore, SAM films are typically not integrated into semiconductor devices and must be removed after selectively depositing one or more materials onto a dielectric layer.

[0107] The present disclosure provides a method for selectively depositing graphene on a metal layer of a substrate, where the graphene facilitates selective deposition of a dielectric material on a dielectric layer of the substrate relative to the metal layer of the substrate. The graphene is a high-quality graphene film that acts as an inhibitor to prevent or limit deposition of the dielectric material on the surface of the graphene and metal layer when the dielectric material is deposited on the substrate. In some embodiments, the dielectric material is a metal oxide, such as aluminum oxide, deposited by ALD. In some embodiments, the dielectric material is a spacer layer, such as silicon nitride, silicon carbide, or silicon carbonitride. In some embodiments, the dielectric layer is a low-k dielectric material, such as silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride. In some embodiments, the surface of the graphene film may be subsequently modified after deposition of the dielectric material. Surface modification allows for the deposition of materials such as an etch stop layer and / or a hermetic barrier on the graphene film.

[0108] Graphene can be selectively deposited on metal surfaces relative to dielectric surfaces. Graphene acts as an inhibitor, promoting selective deposition of materials on dielectric surfaces while inhibiting deposition on metal surfaces. Graphene films are generally stable at high temperatures. Graphene films deposited on metal surfaces can reduce the effective resistivity of metal lines due to reduced electron scattering, allowing for the incorporation of graphene films into semiconductor integration. In some embodiments, graphene films do not necessarily require subsequent removal in semiconductor manufacturing applications. However, in some other embodiments, graphene can be removed after selective deposition of dielectric materials, allowing subsequent deposition operations to occur elsewhere.

[0109] FIG. 7 shows a flow diagram of an exemplary method of selective deposition using graphene, according to some embodiments. The operations of process 700 may be performed in a different order and / or with different, fewer, or additional operations. The operations of process 700 are described with reference to the exemplary process of selective deposition of FIGS. 8A-8E in which graphene is used as an inhibitor. One or more operations of process 700 may be performed using the plasma processing apparatus shown in FIG. 2. In some embodiments, the operations of process 700 may be performed, at least in part, according to software stored on one or more non-transitory computer-readable media.

[0110] At block 710 of process 700, a semiconductor substrate is provided, the semiconductor substrate including a metal layer formed on a dielectric layer. The metal layer has an exposed metal surface. The semiconductor substrate may be a silicon wafer, such as a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer, and may include a wafer having one or more layers of material, such as a dielectric material, a conductive material, or a semiconducting material, deposited thereon. The dielectric layer may be a low-k dielectric material, such as silicon oxide or doped silicon carbide. The low-k dielectric material may have a dielectric constant of about 4.0 or less. In some embodiments, the dielectric layer may be an ultra-low-k dielectric material, such as fluorine-doped or carbon-doped silicon oxide. The ultra-low-k dielectric material may have a dielectric constant of about 2.5 or less. In some embodiments, the metal layer may be a metallization layer in a metallization scheme, and the metal layer may include any suitable conductive material, such as copper, ruthenium, aluminum, nickel, cobalt, tungsten, molybdenum, or a combination thereof. In some embodiments, the metal layer may be treated prior to depositing graphene thereon, and this treatment may function to at least polish the metal layer or remove impurities. For example, the exposed metal surface of the metal layer may be exposed to a reducing agent to reduce metal oxides.

[0111] FIG. 8A shows a cross-sectional schematic diagram of an exemplary semiconductor substrate 800 including a dielectric layer 804 adjacent to a metal layer 802. In some implementations, the metal layer 802 can be formed in the dielectric layer 804, which can be an interlayer dielectric for a damascene or dual damascene structure. A recess can be etched through the dielectric layer 804, which can be patterned and formed using an appropriate lithography process. The recess can be filled with a conductive material to form the metal layer 802. In some implementations, the metal layer 802 comprises copper, ruthenium, aluminum, nickel, cobalt, tungsten, molybdenum, or a combination thereof. A diffusion barrier layer and / or liner layer can be lined between the metal layer 802 and the dielectric layer 804. The diffusion barrier layer can limit diffusion of metal atoms into the dielectric layer 804. The metal layer 802 and the dielectric layer 804 each have an exposed top surface.

[0112] 7 , in block 720 of process 700, graphene is selectively deposited on exposed metal surfaces. Graphene is selectively deposited on exposed metal surfaces relative to other surfaces, including dielectric surfaces. In some embodiments, graphene is selectively deposited on exposed metal surfaces using a remote hydrogen plasma CVD process, a thermal CVD process, a PECVD process, or other suitable deposition process. For example, graphene is selectively deposited on exposed metal surfaces using a remote hydrogen plasma CVD process as described above.

[0113] In some embodiments, the graphene deposited on the exposed metal surface is high-quality graphene. High-quality graphene functions as an effective inhibitor because it has a limited number of sites on which films can nucleate. In the absence of defect sites, such as hydrogen- or hydroxyl-terminated sites, various precursors cannot nucleate on the surface of graphene. For example, ALD or CVD of metal oxides may not nucleate on high-quality graphene if the precursors to such metal oxides cannot adsorb to high-quality graphene. High-quality graphene may be characterized by being free or substantially free of hydrogen- and hydroxyl-terminated sites. High-quality graphene may be characterized by a 2D peak significantly larger than the G peak in the Raman spectrum and a negligible D peak in the Raman spectrum. In some embodiments, the 2D peak is at least two times larger than the G peak in the Raman spectrum.

[0114] Graphene can be deposited under conditions in which the semiconductor substrate is maintained at a deposition temperature below a semiconductor processing temperature limit during the selective deposition of graphene. In some embodiments, the semiconductor processing temperature limit can correspond to the temperature-sensitive limit of a material or component within the semiconductor substrate. For example, the temperature-sensitive limit can be about 400°C for copper and about 450°C for ruthenium. In some embodiments, the semiconductor processing temperature limit is about 400°C. Thus, the deposition temperature can be less than about 400°C, less than about 350°C, less than about 300°C, between about 200°C and about 400°C, or between about 200°C and about 300°C. Higher temperatures can degrade the quality of the graphene. Graphene can be deposited and processed under conditions that cause graphene nucleation delay. Not only does deposition temperature affect graphene properties, but deposition time, precursor flow rates, and other parameters can also affect graphene properties. Generally speaking, shorter deposition times and higher precursor flow rates can provide improved nucleation delay for graphene. In some embodiments, graphene with delayed nucleation may be provided by annealing. For example, annealing graphene at high temperatures of about 300° C. to about 450° C. (e.g., about 400° C.) for a period of 20 seconds to 3 minutes (e.g., 1 minute) can remove functional groups and make graphene nucleation very difficult.

[0115] In some embodiments, graphene can be selectively deposited on exposed metal surfaces without being deposited on a dielectric layer. Selectively depositing graphene on exposed metal surfaces can include flowing one or more hydrocarbon precursors into a reaction chamber toward a semiconductor substrate, generating hydrogen radicals from a hydrogen source gas with a remote plasma source, and introducing the hydrogen radicals into the reaction chamber toward the semiconductor substrate, where the hydrogen radicals react with the one or more hydrocarbon precursors and deposit graphene on the exposed metal surfaces. The one or more hydrocarbon precursors are provided downstream from the hydrogen radicals. In some embodiments, the one or more hydrocarbon precursors include an alkene group or an alkyne group.

[0116] FIG. 8B shows a cross-sectional schematic diagram of the semiconductor substrate 800 of FIG. 8A in which a graphene film 806 is selectively deposited on the metal layer 802. The graphene film 806 is formed on the metal layer 802 without being formed, placed, or positioned on the dielectric layer 804. The graphene film 806 can comprise high-quality graphene, and the graphene film 806 can be a single-layer graphene film, a bilayer graphene film, or a few-layer graphene film. The graphene film 806 may be free of defect sites at which a deposited precursor of a dielectric material may nucleate. The conductive properties of the graphene film 806 can reduce the effective resistivity of the metal layer 802 when electrically connected to a via (not shown) due to reduced electron scattering. In some embodiments, the graphene film 806 can be deposited using a remote hydrogen plasma CVD process as described above. In some embodiments, the graphene film 806 can be deposited at a low deposition temperature of about 200° C. to about 300° C. In some embodiments, graphene film 806 has a thickness of about 3 Å to about 20 Å, or about 5 Å to about 10 Å.

[0117] Returning to FIG. 7 , in block 730 of process 700, a dielectric material is selectively deposited on the dielectric layer. The dielectric material is selectively deposited on the dielectric layer relative to other materials, including on top of the graphene. The graphene inhibits the deposition of the dielectric material on the graphene when the dielectric material is selectively deposited on the dielectric layer. As a result, the graphene blocks the deposition of the dielectric material on the metal layer. When the graphene is removed, this allows perfectly aligned vias to land on the exposed metal surface. The dielectric material can have a different composition than the dielectric layer.

[0118] In some embodiments, the dielectric material can be selectively deposited using any suitable deposition technique, such as PVD, ALD, CVD, PECVD, or remote plasma CVD. For example, the dielectric material can be selectively deposited using ALD. After selectively depositing the dielectric material on the dielectric layer, the graphene is left intact so that the top surface of the graphene remains exposed. The dielectric material can be deposited using a deposition technique that does not damage the graphene. As used herein, "does not damage" refers to a process that does not etch the graphene and that substantially maintains the crystallinity of the graphene. With respect to the Raman spectrum characterizing graphene, this means that the ratio of the 2D peak to the G peak increases or does not decrease by at least more than about 10%, the intensity of the G peak does not increase by more than about 10%, and the intensity of the D peak does not increase by more than about 10%.

[0119] In some embodiments, the dielectric material comprises a metal oxide. The metal oxide can have an etch contrast with the dielectric layer, meaning that the metal oxide provides a different etch selectivity than the dielectric layer. In some embodiments, the metal oxide can function as an etch stop layer, which has an etch contrast with the surrounding material. The metal oxide is not easily etched and therefore acts as a spacer that remains intact. In some embodiments, the metal oxide comprises aluminum oxide, hafnium oxide, zirconium oxide, yttrium oxide, zinc oxide, titanium oxide, or a combination thereof. For example, the metal oxide may comprise aluminum oxide. In some embodiments, the aluminum oxide is deposited on the dielectric layer using a thermal-based deposition technique, such as ALD. Thermal-based deposition techniques can avoid damage to the graphene from exposing it to harmful plasmas. In some embodiments, the thickness of the metal oxide is about 5 Å to about 60 Å.

[0120] In some implementations, the dielectric material comprises a low-k dielectric material. Exemplary low-k dielectric materials include doped or undoped silicon oxide (SiO), doped or undoped silicon carbide (SiC), doped or undoped silicon nitride (SiN), or doped or undoped silicon carbonitride (SiC). x N y ) In some embodiments, the low-k dielectric material comprises silicon oxynitride, silicon oxycarbide, or silicon oxycarbonitride, and the low-k dielectric material can be deposited using a non-direct plasma deposition technique, such as a remote plasma CVD technique. When the low-k dielectric material is deposited using a remote plasma CVD technique, the low-k dielectric material can be selectively deposited in the same reaction chamber or tool as the graphene. In this way, the semiconductor substrate is not exposed to a vacuum break during the deposition operations in blocks 720 and 730.

[0121] In one example of a remote plasma CVD technique for depositing low-k dielectric materials, a silicon-containing precursor is flowed to a semiconductor substrate, and radicals are generated from a source gas in a remote plasma source. The radicals are introduced into a reaction chamber, flow toward the semiconductor substrate, and react with the silicon-containing precursor in the reaction chamber. In some embodiments, the source gas includes a hydrogen source gas (H), and the radicals include hydrogen radicals. The radicals are provided under process conditions such that the radicals are substantially in a low-energy or ground state when reacting with the silicon-containing precursor in an environment adjacent to the semiconductor substrate. The radicals are generated in a remote plasma source upstream from the silicon-containing precursor. The silicon-containing precursor contains silicon-hydrogen and / or silicon-silicon bonds, as well as silicon-carbon, silicon-nitrogen, and / or silicon-oxygen bonds. In some embodiments, the silicon-containing precursor does not contain carbon-oxygen or carbon-nitrogen bonds. By generating the radicals in a remote plasma source upstream from the silicon-containing precursor, the semiconductor substrate is not directly exposed to the plasma. This avoids exposing graphene to harmful plasma. When the silicon-containing precursor reacts with hydrogen radicals in an environment adjacent to the semiconductor substrate, the silicon-containing material is deposited as a dielectric material on the dielectric layer.

[0122] The dielectric material can function as a spacer layer that increases the distance between the contact via and the adjacent metal layer / line. In other words, the spacer layer provides additional topography that increases the spacing between the contact via and the adjacent metal layer / line, mitigating TDDB degradation and improving device performance. Selective dielectric deposition onto the dielectric layer eliminates or reduces problems associated with unlanded vias and supports perfectly aligned via patterning schemes.

[0123] FIG. 8C illustrates a cross-sectional schematic diagram of the semiconductor substrate 800 of FIG. 8B in which a first dielectric material 808 is selectively deposited on the dielectric layer 804. The first dielectric material 808 is deposited on the dielectric layer 804 without being formed, resting, or positioned on top of the graphene film 806. The graphene film 806 inhibits deposition of the first dielectric material 808 on the metal layer 802. In some embodiments, the first dielectric material 808 can be deposited without damaging the graphene film 806. In some embodiments, the first dielectric material 808 can include a metal oxide, such as aluminum oxide, which can be deposited using a thermal-based deposition technique, such as ALD. In some embodiments, the metal oxide can have a thickness of about 5 Å to about 60 Å. The first dielectric material 808 can function as an etch stop layer. In some implementations, the first dielectric material 808 can include a low-k dielectric material such as silicon oxycarbide, silicon oxynitride, or silicon oxycarbonitride, which can be deposited by a non-direct plasma deposition technique such as remote hydrogen plasma CVD. In some implementations, the low-k dielectric material can have a thickness of about 1 nm to about 10 nm. The first dielectric material 808 can function as a spacer layer in a perfectly aligned patterning scheme.

[0124] Returning to Figure 7, in block 740a of process 700, graphene can be treated with non-direct plasma or treatment conditions for a period of time sufficient to modify the surface of the graphene. After selective deposition of a dielectric material, where the graphene acts as an inhibitor, the surface of the graphene can be modified to facilitate subsequent deposition onto the graphene. In other words, high-quality graphene can be converted to low-quality graphene, and materials can be deposited onto the surface of the graphene. This treatment functionalizes the surface of the graphene so that nucleation can occur on the graphene.

[0125] In some embodiments, the treatment includes exposing the graphene to an indirect plasma. Exposing the graphene to a direct or in-situ plasma can etch the graphene or disrupt the graphene crystal structure to form disordered or amorphous carbon. Exposing the graphene to an indirect or remote plasma can functionalize the surface of the graphene without etching it. In some embodiments, the indirect plasma can be a remote hydrogen plasma (e.g., H plasma) containing hydrogen radicals. In some embodiments, the indirect plasma can be a remote plasma (e.g., H / O plasma) containing hydrogen radicals mixed with radicals of oxygen, ammonia, nitrogen, or a combination thereof. The semiconductor substrate can be maintained at a low treatment temperature during exposure to the indirect plasma. In some embodiments, the treatment temperature can be from about 20°C to about 400°C, or from about 20°C to about 200°C. After exposure to the indirect plasma at a low treatment temperature, the surface of the graphene can have defect sites, such as hydrogen- or hydroxyl-terminated sites, which can facilitate the nucleation and growth of subsequent material deposition on the graphene. In some embodiments, the processing at block 740a and the selective dielectric deposition at block 730 may be performed in the same reaction chamber or tool such that no vacuum break is introduced between the operations at blocks 730 and 740a.

[0126] In some embodiments, the treatment includes exposing the graphene to treatment conditions for a sufficient period of time. The treatment conditions can include exposing the graphene to one or more gases for an extended period of time. The one or more gases can include one or both of hydrogen and oxygen. For example, the graphene can be exposed to atmospheric conditions with an air break. Without being limited to any theory, the air break may allow oxygen and / or water molecules to functionalize the surface of the graphene. In some embodiments, the treatment conditions can include exposure to atmospheric pressure (760 Torr) or below, exposure to air, and exposure to about room temperature (15°C to about 25°C). A period of at least about 2 minutes, at least about 5 minutes, at least about 10 minutes, or at least about 15 minutes is sufficient to adequately functionalize the surface of the graphene. In some embodiments, the treatment conditions include one or more deposition operations. The surface of the graphene can be at least partially functionalized after selectively depositing a dielectric material on the dielectric layer. Additionally, the surface of the graphene can be further functionalized after performing an additional deposition operation on the semiconductor substrate. Over an extended period of time, or after sufficient deposition operations, sufficient defect sites of hydrogen-terminated and / or hydroxyl-terminated sites may be formed on the surface of the graphene to facilitate the nucleation and growth of subsequent material deposition on the graphene.

[0127] In some embodiments, the processing conditions can result in the deposition of an ultrathin layer on the graphene, which facilitates subsequent material deposition on the graphene. For example, such an ultrathin layer can include aluminum oxide itself deposited by CVD. Alternatively, the ultrathin layer can include silicon carbonitride, silicon oxycarbide, or silicon nitride.

[0128] After surface modification of the graphene, the graphene is a low-quality graphene film, which can be characterized by a higher D peak in the Raman spectrum. In some embodiments, the D peak in the Raman spectrum can increase by more than 20%. The surface modification facilitates subsequent processing steps performed on the graphene for semiconductor integration. Such subsequent processing steps in the process flow can involve depositing one or both of an etch stopper and a hermetic barrier. This can be referred to as encapsulating the graphene, and the film properties of the graphene can be maintained over long periods of time. In some embodiments, an additional dielectric layer (e.g., an ultra-low k dielectric) can be deposited on the etch stopper and / or hermetic barrier, and conductive vias can be formed in the additional dielectric layer to provide electrical contact to the graphene with a perfectly aligned via patterning scheme.

[0129] Alternatively, in block 740b of process 700, the graphene can be removed. In some embodiments, the graphene can be removed by direct or indirect plasma exposure. Graphene may be selectively deposited as an inhibitor to promote selective deposition of a dielectric material onto the dielectric layer. After selective deposition of a dielectric material onto the dielectric layer, the graphene can be removed. The graphene is no longer present and acts as an inhibitor. Removal of the graphene may be desirable for perfectly aligned vias to contact the metal layer.

[0130] After graphene removal, deposition may occur anywhere on the semiconductor substrate. In some embodiments, a metal oxide is deposited on the exposed metal surfaces and dielectric material after graphene removal. In some embodiments, a hermetic barrier is deposited on the exposed metal surfaces and dielectric material after graphene removal. The metal oxide or hermetic barrier may be deposited using any suitable deposition technique, including plasma-based deposition techniques.

[0131] FIG. 8D shows a cross-sectional schematic diagram of the semiconductor substrate 800 of FIG. 8C , where the graphene film 806 is exposed to processing conditions 810, resulting in surface modification of the graphene film 806. The modified surface of the graphene film 806 may be characterized by more defect sites for nucleation, and the defect sites may include hydrogen-terminated and / or hydroxyl-terminated defect sites. In some embodiments, the processing conditions 810 may include exposure to a remote plasma, such as a remote hydrogen plasma. The remote plasma may additionally or alternatively include oxygen, nitrogen, ammonia, or a combination thereof. In some embodiments, the processing conditions 810 include exposure to one or more deposition operations. After sufficient deposition operations, the surface of the graphene film 806 may eventually be functionalized, allowing nucleation to occur on the graphene film 806. In some embodiments, the processing conditions 810 include exposing the graphene film 806 to a delay sufficient to cause the quality of the graphene film 806 to deteriorate over time. Such processing conditions 810 may include, for example, exposing the graphene film 806 to air breaks for an extended period of time. Although not shown in FIG. 8D , the graphene film 806 may alternatively be removed rather than modified. Removing the graphene film 806 may facilitate subsequent deposition elsewhere on the semiconductor substrate 800 without the graphene film 806 acting as an inhibitor.

[0132] Returning to FIG. 7, process 700 can further include depositing a metal oxide by a thermal-based deposition technique. The thickness of the metal oxide can be about 5 Å to about 50 Å. Alternatively, process 700 can further include depositing a hermetic barrier by a non-direct plasma deposition technique. The thickness of the hermetic barrier can be about 5 Å to about 100 Å. The metal oxide or hermetic barrier can be deposited on the modified surface of the graphene and on the dielectric layer on which the graphene remains intact. If the graphene has been removed, the metal oxide or hermetic barrier can be deposited on the exposed metal surface and on the dielectric layer.

[0133] In some embodiments, the metal oxide is deposited by thermal ALD or thermal CVD. Metal oxide deposition can be performed at temperatures below semiconductor processing temperature limits. In some cases, metal oxide deposition can improve the crystalline properties of the underlying graphene. The metal oxide may include aluminum oxide, hafnium oxide, zirconium oxide, yttrium oxide, zinc oxide, titanium oxide, or a combination thereof. For example, the metal oxide includes aluminum oxide. Aluminum oxide deposition can be performed by thermal ALD by introducing a dose of an aluminum-containing precursor, such as trimethylaluminum (TMA), and exposing the semiconductor substrate to an oxidizing agent, such as methanol. The metal oxide can function as an etch stop. Additionally or alternatively, the metal oxide can function as a protective layer for graphene against potentially damaging plasmas. In some embodiments, when the dielectric material selectively deposited on the dielectric layer is a low-k dielectric material, the metal oxide is deposited on the low-k dielectric material and graphene, or on the low-k dielectric material and metal layer. The metal oxide has a different etch selectivity than the low-k dielectric material, and the thickness of the low-k dielectric material is at least twice the thickness of the metal oxide.

[0134] In some embodiments, a hermetic barrier can be deposited following deposition of a metal oxide on graphene. The hermetic barrier can be deposited by any suitable deposition technique, including non-direct and direct plasma deposition techniques. The metal oxide on the graphene can protect the graphene from harmful plasma exposure. Thus, the hermetic barrier can be deposited using PECVD or PEALD, and the plasma can be generated in situ or remotely.

[0135] In some embodiments, a hermetic barrier such as nitrogen-doped silicon carbide, oxygen-doped silicon carbide, or silicon nitride is deposited. If the hermetic barrier is deposited on the graphene, the deposition can be performed by a non-direct plasma deposition technique. The non-direct plasma deposition technique can be a remote plasma CVD technique. If the hermetic barrier layer is deposited after removing the graphene, the deposition can be performed using any suitable deposition technique. The hermetic barrier can function as an etch stopper and a hermetic barrier. In some embodiments, the hermetic barrier can provide protection to the graphene by sealing it from water, oxygen, and other chemicals in the ambient environment that can adversely affect the graphene's film properties.

[0136] In remote plasma CVD techniques, a silicon-containing precursor is flowed to a semiconductor substrate in a reaction chamber, and radicals are generated from a source gas in a remote plasma source. The radicals are then introduced into the reaction chamber and flowed to the semiconductor substrate, reacting with the silicon-containing precursor in the reaction chamber and forming a hermetic barrier. In some embodiments, the source gas comprises hydrogen gas (H), and the radicals comprise hydrogen radicals. The radicals are provided under process conditions such that the radicals are substantially in a low-energy or ground state when reacting with the silicon-containing precursor in an environment adjacent to the semiconductor substrate. The radicals are generated in a remote plasma source upstream from the silicon-containing precursor. The silicon-containing precursor contains silicon-hydrogen and / or silicon-silicon bonds, as well as silicon-carbon, silicon-nitrogen, and / or silicon-oxygen bonds. In some embodiments, the silicon-containing precursor does not contain carbon-oxygen or carbon-nitrogen bonds. By generating radicals in a remote plasma source upstream from the silicon-containing precursor, the semiconductor substrate is not directly exposed to the plasma.

[0137] FIG. 8E shows a cross-sectional schematic diagram of the semiconductor substrate 800 of FIG. 8D in which a second dielectric material 812 is deposited on the graphene film 806 and the first dielectric material 808. The graphene film 806 can be conditioned according to process conditions 810 of FIG. 8D to facilitate deposition. In some implementations, the second dielectric material 812 comprises a metal oxide such as aluminum oxide, hafnium oxide, zirconium oxide, yttrium oxide, zinc oxide, titanium oxide, or a combination thereof. The metal oxide can be deposited by a thermal-based deposition technique such as thermal ALD. The metal oxide can function as an etch stop layer. In some implementations, the second dielectric material 812 comprises a hermetic barrier such as silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride. The hermetic barrier can be deposited by a non-direct plasma deposition technique such as remote hydrogen plasma CVD. The hermetic barrier can function to encapsulate and protect the graphene film 806. In embodiments in which the graphene film 806 is removed, it will be appreciated that the second dielectric material 812 may be deposited using any suitable deposition technique. The second dielectric material 812 may be deposited over the metal layer 802 and the first dielectric material 808.

[0138] 9 shows a cross-sectional schematic diagram of an exemplary semiconductor device having a graphene film and selective dielectric layers in a dual damascene structure according to some embodiments. The semiconductor device 900 includes a first dielectric layer 910 and a first metal layer 920A formed on the first dielectric layer 910. The semiconductor device 900 can further include an adjacent first metal layer 920B formed on the first dielectric layer 910, the first metal layer 920A being adjacent to the adjacent first metal layer 920B without contacting the adjacent first metal layer 920B. Each of the first metal layer 920A and the adjacent first metal layer 920B is lined with a first barrier layer 922. The first barrier layer 922 can provide a diffusion barrier layer and / or a liner layer at the interface between the first metal layer 920A and the first dielectric layer 910, as well as between the adjacent first metal layer 920B and the first dielectric layer 910.

[0139] In some implementations, first metal layer 920A and adjacent first metal layer 920B each comprise copper, cobalt, ruthenium, nickel, molybdenum, or a combination thereof. For example, first metal layer 920A and adjacent first metal layer 920B each comprise copper. In some implementations, first dielectric layer 910 comprises any suitable dielectric material, such as silicon oxide or doped silicon carbide.

[0140] The semiconductor device 900 further includes a selective graphene film 932 formed on the top surface of the first metal layer 920A. The selective graphene film 932 is selectively deposited on the first metal layer 920A relative to the first dielectric layer 910. In some implementations, the selective graphene film 932 is also formed on the top surface of the adjacent first metal layer 920B. The selective graphene film 932 can have a thickness of about 3 Å to about 20 Å, or about 5 Å to about 10 Å. The selective graphene film 932 is deposited on the upper surface of the first metal layer 920A by flowing one or more hydrocarbon precursors toward the semiconductor device 900, generating hydrogen radicals from a hydrogen source gas using a remote plasma source, and directing the hydrogen radicals toward the semiconductor device 900. The hydrogen radicals are introduced upstream from the one or more hydrocarbon precursors, and the hydrogen radicals react with the one or more hydrocarbon precursors in an environment adjacent to at least the first metal layer 920A to deposit the selective graphene film 932. The one or more hydrocarbon precursors may each contain an alkene group or an alkyne group. In some cases, the hydrogen source gas may be provided in a helium carrier with a concentration of about 1-25% hydrogen or about 1-10% hydrogen. The selective graphene film 932 is deposited at a low deposition temperature, which may be about 200°C to about 400°C, about 250°C to about 400°C, or about 200°C to about 300°C.

[0141] The semiconductor device 900 further includes a selective dielectric layer 925 formed on the top surface of the first dielectric layer 910. The selective dielectric layer 925 is selectively deposited on the first dielectric layer 910 relative to the first metal layer 920A and the adjacent first metal layer 920B. The selective dielectric layer 925 can have a thickness of about 1 nm to about 10 nm. In some implementations, the selective dielectric layer 925 comprises a low-k dielectric material such as silicon oxynitride, silicon oxycarbide, or silicon oxycarbonitride. In some implementations, the selective dielectric layer 925 is deposited on the first dielectric layer 910 using a non-direct plasma deposition technique, such as remote hydrogen plasma CVD.

[0142] In some embodiments, the semiconductor device 900 further includes an etch stop layer 930 on the selective dielectric layer 925 and the selective graphene film 932, where the etch stop layer 930 comprises a metal oxide. Examples of metal oxides include aluminum oxide, hafnium oxide, zirconium oxide, yttrium oxide, zinc oxide, titanium oxide, or combinations thereof. In some embodiments, the etch stop layer 930 comprises aluminum oxide. The etch stop layer 930 can have a thickness of about 5 Å to about 30 Å. In some embodiments, the etch stop layer 930 is deposited on the selective dielectric layer 925 and the selective graphene film 932 using a thermal deposition technique, such as thermal ALD or thermal CVD.

[0143] The semiconductor device 900 may further include a second dielectric layer 940 on the etch stop layer 930. The second dielectric layer 940 may include any suitable dielectric material, such as silicon oxide or doped silicon carbide. The etch stop layer 930 may have a different etch selectivity than the second dielectric layer 940. For example, the etch stop layer 930 may have an etch resistance that is 10 times or more greater than the etch resistance of the second dielectric layer 940 when one or more recesses are formed in the second dielectric layer 940. In this manner, etching through the second dielectric layer 940 does not result in etching of the selective graphene film 932. The selective dielectric layer 925 may have a different etch selectivity than the etch stop layer 930.

[0144] A recess or opening is formed through the second dielectric layer 940 and filled with a conductive material to form a via 960 and a second metal layer 970 over the via 960. The second metal layer 970 is positioned over the first metal layer 920A, and the via 960 is positioned between the selective graphene film 932 and the second metal layer 970. The via 960 provides an electrical interconnection between the first metal layer 920A and the second metal layer 970. The via 960 and the second metal layer 970 may be lined with a second barrier layer 962. The second barrier layer 962 may provide a diffusion barrier layer and / or a liner layer at the interface between the via 960 and the second dielectric layer 940, as well as between the adjacent second metal layer 970 and the second dielectric layer 940. In some implementations, via 960 and second metal layer 970 each comprise copper, cobalt, ruthenium, nickel, molybdenum, or a combination thereof. For example, via 960 and second metal layer 970 each comprise copper.

[0145] As shown in FIG. 9 , the selective graphene film 932 is positioned at the interface between the via 960 and the first metal layer 920A. The selective graphene film 932 acts as an inhibitor so that the selective dielectric layer 925 is deposited on the first dielectric layer 910 relative to the first metal layer 920A and the adjacent first metal layer 920B. The selective graphene film 932 is not removed after the selective dielectric layer 925 is deposited. The selective graphene film 932 lowers the electrical resistance in the via 960 due to reduced electron scattering. The selective dielectric layer 925 ensures that the via 960 is a perfectly aligned via, and the selective dielectric layer 925 provides additional spacing between the via 960 and the adjacent first metal layer 920B.

[0146] conclusion In the foregoing description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with specific embodiments, it will be understood that they are not intended to limit the disclosed embodiments.

[0147] Although the foregoing embodiments have been described in some detail for clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Therefore, the present embodiments should be considered as illustrative rather than restrictive, and the embodiments should not be limited to the details set forth herein.

Claims

1. 1. A method for selective deposition onto a dielectric layer, comprising: providing a semiconductor substrate, the semiconductor substrate comprising a metal layer formed on a dielectric layer, the metal layer having an exposed metal surface; Selectively depositing graphene on the exposed metal surfaces; Selectively depositing a dielectric material on the dielectric layer; A method comprising:

2. 10. The method of claim 1, wherein the surface of the graphene is free or substantially free of hydrogen-terminated and hydroxyl-terminated sites.

3. 10. The method of claim 1, The method, wherein the graphene inhibits deposition of the dielectric material on the graphene when the dielectric material is selectively deposited on the dielectric layer.

4. 10. The method of claim 1, The method, wherein the dielectric material comprises a metal oxide.

5. 5. The method of claim 4, The method, wherein the metal oxide comprises aluminum oxide, hafnium oxide, zirconium oxide, yttrium oxide, zinc oxide, titanium oxide, or a combination thereof.

6. 10. The method of claim 1, The method, wherein the dielectric material comprises a low-k dielectric material.

7. 7. The method of claim 6, depositing a metal oxide on the low-k dielectric material and the graphene, wherein the metal oxide has a different etch selectivity than the low-k dielectric material, and the thickness of the low-k dielectric material is at least twice the thickness of the metal oxide. The method further comprises:

8. The method according to any one of claims 1 to 7, The method, wherein the metal layer comprises copper, cobalt, ruthenium, nickel, molybdenum, or a combination thereof.

9. The method according to any one of claims 1 to 7, modifying a surface of the graphene by indirectly exposing the graphene to plasma; depositing a metal oxide on the modified surface of the graphene and the dielectric material by a thermal-based deposition technique; The method further comprises:

10. The method according to any one of claims 1 to 7, removing the graphene; depositing a metal oxide on the exposed metal surfaces and the dielectric material; The method further comprises:

11. The method according to any one of claims 1 to 7, modifying a surface of the graphene by indirectly exposing the graphene to plasma; depositing a hermetic barrier on the modified surface of the graphene and the dielectric material by a non-direct plasma deposition technique; The method further comprises:

12. 12. The method of claim 11, The method wherein the indirect plasma comprises hydrogen radicals mixed with radicals of oxygen, ammonia, nitrogen, or combinations thereof.

13. The method according to any one of claims 1 to 7, removing the graphene; depositing a hermetic barrier over the exposed metal surfaces and the dielectric material; The method further comprises:

14. The method according to any one of claims 1 to 7, Selectively depositing the graphene on the exposed metal surfaces includes: flowing one or more hydrocarbon precursors into a reaction chamber toward the semiconductor substrate; generating hydrogen radicals from a hydrogen source gas in a remote plasma source; introducing the hydrogen radicals into the reaction chamber toward the semiconductor substrate, wherein the hydrogen radicals react with the one or more hydrocarbon precursors to deposit the graphene on the exposed metal surface; A method comprising:

15. a reaction chamber; a substrate support within the reaction chamber and configured to support a substrate, the substrate comprising a metal layer formed on a dielectric layer, the metal layer having an exposed metal surface; a remote plasma source upstream of the reaction chamber, the exposed metal surface facing toward the remote plasma source; one or more gas outlets within the reaction chamber downstream from the remote plasma source; a controller, selectively depositing graphene on the exposed metal surface of the substrate; Selectively depositing a dielectric material onto the dielectric layer of the substrate. a controller configured with instructions for performing an operation; A substrate processing apparatus comprising:

16. a first dielectric layer; a first metal layer formed on the first dielectric layer; a selective graphene film formed on the top surface of the first metal layer selectively with respect to the first dielectric layer; a selective dielectric layer formed on the upper surface of the first dielectric layer selectively with respect to the first metal layer; A semiconductor device comprising:

17. 17. The semiconductor device of claim 16, 1. A semiconductor device, wherein the selective dielectric layer comprises a metal oxide, the first dielectric layer comprises a low-k dielectric material, and the first metal layer comprises copper, cobalt, ruthenium, nickel, molybdenum, or a combination thereof.

18. 17. The semiconductor device of claim 16, an etch stop layer over the selective dielectric layer and the selective graphene film, the etch stop layer comprising a metal oxide; The semiconductor device further comprises:

19. 20. The semiconductor device of claim 18, a second dielectric layer over the etch stop layer; a second metal layer formed on the second dielectric layer; a via formed in the second dielectric layer, the via being between the selective graphene film and the second metal layer, the via providing an electrical interconnection between the first metal layer and the second metal layer; The semiconductor device further comprises:

20. 20. The semiconductor device of claim 19, A semiconductor device, wherein the etch selectivity of the etch stop layer is different from the second dielectric layer, and the etch selectivity of the selective dielectric layer is different from the etch stop layer.

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