Semiconductor device

Abstract

To provide a semiconductor device of a new structure which can hold storage contents even in a situation where power is not supplied and has no limitation on the number of times of writing, and to provide a method of manufacturing the same.SOLUTION: The semiconductor device includes a nonvolatile memory cell including a writing transistor 162 which uses an oxide semiconductor and has a small leakage current (off-state current) between a source and a drain in an off state, a reading transistor 160 which uses a semiconductor material different from that of the writing transistor, and a capacitor 164. Data is written to and rewritten in the memory cell in such a manner that a potential is supplied to a node FG where one of a source electrode and a drain electrode of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected to each other by turning on the writing transistor, and then a predetermined amount of charge is held in the node by turning off the writing transistor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The disclosed invention relates to a semiconductor device using a semiconductor element and a manufacturing method thereof. do. [Background technology]

[0002] Memory devices that use semiconductor elements are volatile, meaning that the stored contents are lost when the power supply is cut off. and non-volatile memory, which retains its contents even when the power supply is cut off. .

[0003] A typical example of a volatile memory device is a DRAM (Dynamic Random Access Memory). DRAM is a memory element that can be selected from transistors. By storing charge in the capacitor, information is stored.

[0004] According to the above principle, in DRAM, when information is read, the charge in the capacitor is lost. Every time information is read, a write operation is required again. In a transistor, leakage current (off-state current) between the source and drain in the off state causes transistor Even when the transistor is not selected, charge flows in and out, so data (information) ) retention period is short. Therefore, rewrite operation (refresh operation) is performed at a predetermined cycle. It is difficult to reduce power consumption sufficiently. Therefore, for long-term memory retention, magnetic or optical materials are used. A separate storage device is required.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM uses circuits such as flip-flops to store the memory contents. In order to retain data, no refresh operation is required, which is an advantage over DRAM. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. In addition, there is a problem that the memory contents are lost when the power supply is cut off. In this regard, it is no different from DRAM.

[0006] A typical example of a nonvolatile memory device is flash memory. A floating gate is provided between the gate electrode of the transistor and the channel forming region, Since memory is stored by holding an electric charge in the floating gate, the data retention period is extremely long. The advantage is that it lasts for a very long time (semi-permanent) and does not require the refresh operations required for volatile storage devices. The point is as follows (see, for example, Patent Document 1).

[0007] However, the gate insulating layer that constitutes the memory element is damaged by the tunnel current that occurs during writing. This causes a problem in that the memory element will stop functioning after a certain number of writes. To mitigate the effect of this problem, for example, the number of writes to each memory element is made uniform. However, to achieve this, complex peripheral circuits are required. However, even if such a method is adopted, the fundamental problem of lifespan will not be resolved. Therefore, flash memory is not suitable for applications where information needs to be rewritten frequently.

[0008] Also, to hold charge on the floating gate or to remove that charge. This requires a high voltage and a circuit for it. , or removal operation takes a relatively long time, and it is not easy to speed up writing and erasing. There is also the problem that: [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 57-105889 Summary of the Invention [Problem to be solved by the invention]

[0010] In view of the above-mentioned problems, one embodiment of the disclosed invention provides a method for storing stored contents even when power is not supplied. To provide a semiconductor device having a new structure that can retain data and has no limit on the number of times it can be written. This is one of the purposes of the organization. [Means for solving the problem]

[0011] The invention disclosed in this specification and the like provides a writing transistor using an oxide semiconductor, A readout transistor and a capacitance element are made of semiconductor materials different from those of the write transistor. The present invention provides a semiconductor device having a nonvolatile memory cell including: Writing and rewriting are performed by turning on the write transistor. One of the source electrode or the drain electrode of the transistor, one of the electrodes of the capacitor, and A potential is supplied to a node electrically connected to the gate electrode of the output transistor, and then By turning off the write transistor, a predetermined amount of charge is held in the node. This is done by making

[0012] One embodiment of the disclosed invention is a semiconductor device including a first transistor, a second transistor, a capacitor, and a first transistor and a second transistor; The first transistor includes a different semiconductor material, and the second transistor includes an oxide semiconductor. One of the source electrode and the drain electrode of the second transistor and the electrode of the capacitor element A first potential is applied to a node electrically connected to the gate electrode of the first transistor. a first write mode in which a predetermined amount of first charge is held in the node by supplying a first charge to the node; By supplying a second potential to the node holding a charge of 1, a predetermined amount of second charge is stored in the node. and a second write mode in which the first write signal is held.

[0013] Another embodiment of the disclosed invention is a semiconductor device including a first transistor, a second transistor, and a capacitor. a nonvolatile memory cell including a first transistor and a second transistor; The first transistor is made of a different semiconductor material than the first transistor, and the second transistor is made of an oxide semiconductor. and a second transistor is turned on to one of the source electrode or the drain electrode of the capacitor element, one of the electrodes of the first transistor, a first potential is supplied to a node electrically connected to the gate electrode of the second transistor; A first write operation that causes a node to hold a predetermined amount of first charge by turning off the transistor. The first charge is maintained by turning on the second transistor. After supplying the second potential to the node, the second transistor is turned off. a second write mode for causing the node to hold a predetermined amount of second charge. is.

[0014] In the semiconductor device, the off-state current of the second transistor is It is preferable that the OFF current is lower than the OFF current of the capacitor.

[0015] In the semiconductor device, the switching speed of the first transistor is faster than that of the second transistor. It is preferable that the switching speed is faster than the switching speed of the transistor.

[0016] In the semiconductor device, the second transistor has an energy gap of 3 eV. Preferably, it comprises larger materials.

[0017] In the above, a writing transistor using an oxide semiconductor with low off-state current However, the disclosed invention is not limited thereto. Materials that can realize these characteristics, such as wide-gap materials (Eg >3 eV) may also be applied.

[0018] In this specification, a nonvolatile memory cell is a memory cell that remains operational even when power is not supplied. Over a certain period (at least 1 × 10 4 seconds or more, preferably 1 x 10 6 (more than 2 seconds) A memory cell that can be read or written.

[0019] In this specification, the terms "above" and "below" refer to the positional relationship of a component "directly above" or "below." For example, the term "gate electrode on a gate insulating layer" does not necessarily mean "directly below." " excludes those that include other components between the gate insulating layer and the gate electrode. Furthermore, the terms "upper" and "lower" are merely used for the convenience of explanation and are not to be specifically mentioned. Except in certain cases, this also includes cases where the top and bottom are reversed.

[0020] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes" and "wirings." This also includes cases where the "line" is formed as a single unit.

[0021] Also, the functions of "source" and "drain" may differ depending on whether transistors with different polarities are used or not. However, they may be swapped when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" can be used interchangeably. It shall be possible.

[0022] In this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects.

[0023] For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitors, and other various functions. This includes elements such as [Effects of the Invention]

[0024] Since a transistor using an oxide semiconductor has an extremely low off-state current, By applying this to memory cells, it is possible to retain stored information for an extremely long period of time. In other words, the refresh operation becomes unnecessary or the frequency of the refresh operation is reduced. Since it is possible to extremely reduce the power consumption of a semiconductor device including memory cells, It is possible to reduce power consumption sufficiently. In addition, even if there is no power supply, it is possible to It is possible to maintain the stored contents even after the power is turned off.

[0025] Furthermore, the memory cell used in the semiconductor device according to the disclosed invention has high write-in performance. It does not require voltage and does not have the problem of element degradation. For example, unlike conventional non-volatile memory, There is no need to inject or extract electrons from the floating gate. The problem of deterioration of the gate insulating layer does not occur at all. The cells are not limited in the number of times they can be rewritten, which is a problem with conventional non-volatile memory, and are therefore reliable. Furthermore, the on / off state of the transistor determines the writing and reading of information. Since the data is written to the memory, high-speed operation can be easily realized. Another advantage is that no work is required.

[0026] Furthermore, transistors using materials other than oxide semiconductors can operate at sufficiently high speeds. Therefore, by using this in combination with a transistor using an oxide semiconductor, This makes it possible to ensure sufficient high speed of the operation of the device (for example, the operation of reading information). In addition, transistors using materials other than oxide semiconductors are being developed for various applications requiring high-speed operation. Circuits (logic circuits, driver circuits, etc.) can be suitably realized.

[0027] In this way, transistors using semiconductor materials other than oxide semiconductors and transistors using oxide semiconductors By integrating the semiconductor device with the transistor, a semiconductor device with unprecedented features can be realized. It can be realized. [Brief explanation of the drawings]

[0028] [Figure 1] Circuit diagram of semiconductor device [Figure 2] Circuit diagram of semiconductor device [Figure 3] Circuit diagram of semiconductor device [Figure 4] Cross-sectional and plan views of a semiconductor device [Figure 5] Cross-sectional views relating to a manufacturing process of a semiconductor device [Figure 6] Cross-sectional views relating to a manufacturing process of a semiconductor device [Figure 7] Cross-sectional and plan views of a semiconductor device [Figure 8] Cross-sectional views relating to a manufacturing process of a semiconductor device [Figure 9] Cross-sectional views relating to a manufacturing process of a semiconductor device [Figure 10] Cross-sectional and plan views of a semiconductor device [Figure 11] Cross-sectional views relating to a manufacturing process of a semiconductor device [Figure 12] FIG. 1 is a diagram illustrating an electronic device using a semiconductor device. [Figure 13] Figure showing the results of the memory window width survey [Figure 14] Characteristics of a transistor using an oxide semiconductor [Figure 15] Circuit diagram for evaluating the characteristics of a transistor using an oxide semiconductor [Figure 16] Timing chart for evaluating the characteristics of a transistor using an oxide semiconductor [Figure 17] Characteristics of a transistor using an oxide semiconductor [Figure 18] Characteristics of a transistor using an oxide semiconductor DETAILED DESCRIPTION OF THE INVENTION

[0029] An example of an embodiment of the present invention will be described below with reference to the drawings. and the present invention is not limited to the above description, and may be modified in various forms and without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention is not to be construed as being limited to the description of the embodiment shown in the accompanying drawings.

[0030] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as those in the actual embodiment for ease of understanding. Therefore, the disclosed invention may not necessarily represent the actual position, size, range, etc. The position, size, range, etc. are not necessarily limited to those disclosed in the drawings, etc.

[0031] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. It should be noted that the numbers are added to avoid confusion and are not intended to limit the number.

[0032] (Embodiment 1) In this embodiment, a circuit configuration and operation of a semiconductor device according to one embodiment of the disclosed invention will be described. The following description will be given with reference to FIG. 1. Note that the circuit diagram shows a transistor using an oxide semiconductor. To indicate that it is a transistor, the symbol OS may also be added.

[0033] The semiconductor device illustrated in FIG. 1A-1 includes a transistor 160, a transistor 162, and a capacitor. 1A-1, the transistor 162 has a nonvolatile memory cell including a capacitor 164. One of the source electrode or the drain electrode of the transistor 162 and one of the electrodes of the capacitor 164 , is electrically connected to the gate electrode of the transistor 160. The 1st Line (also called the source line) and the source electrode of the transistor 160 are electrically , and the second line (also called the bit line) and the transistor 160 The drain electrode is electrically connected to the third wiring (3rd Line: a first signal line) and the other of the source electrode and the drain electrode of the transistor 162. are electrically connected to the fourth wiring (also called the 4th Line: second signal line) and the The fifth wiring (5 The other electrode of the capacitor 164 is electrically connected to the word line (also called a word line). It is being done.

[0034] Here, a transistor including an oxide semiconductor is used as the transistor 162. A transistor using a nitride semiconductor has a leakage current between the source and drain in the off state (on Therefore, when the transistor 162 is turned off, By setting the transistor 162 in this state, one of the source electrode and the drain electrode of the transistor 162 and the capacitor One of the electrodes of the element 164 and the gate electrode of the transistor 160 are electrically connected. Therefore, the potential of the node FG can be maintained for an extremely long period of time. In addition, by including the capacitor 164, the charge given to the node FG can be easily held. This also makes it easier to read out the stored information.

[0035] In addition, the transistor 160 has no limit on its off-state current, and the operating speed of the memory cell can be increased. Therefore, it has a faster switching speed (e.g., a higher field-effect mobility) than transistor 162. In other words, the transistor 160 is made of an oxide semiconductor. The transistors using semiconductor materials other than silicon are applied. Therefore, the off-state current of the transistor 160 is higher than the off-state current of the transistor 162. The semiconductor material used for the transistor 160 may be, for example, silicon, gel, or the like. For example, silicon germanium, silicon carbide, or gallium arsenide may be used. It is preferable to use a single crystal semiconductor. 160 is capable of reading out stored information at high speed.

[0036] The semiconductor device illustrated in FIG. 1A-1 utilizes the feature that the potential of the node FG can be maintained. This makes it possible to set the write mode and the read mode.

[0037] In a write mode in which information is stored in a memory cell, first, the potential of the fourth wiring is set to The transistor 162 is turned on by applying a potential that turns the transistor 162 on. As a result, the potential of the third wiring is supplied to the node FG, and a predetermined amount of charge is stored in the node FG. Here, charges that give two different potential levels (hereinafter referred to as Low) are stored. Either a low level charge or a high level charge is given. After that, the potential of the fourth wiring is set to a potential that turns off the transistor 162. The resistor 162 is turned off. As a result, the node FG is in a floating state, and the node F As described above, a predetermined amount of charge is held at node FG. By storing and holding electric charges, information can be stored in the memory cell (write (Read mode).

[0038] Since the off-state current of the transistor 162 is extremely small, the charge supplied to the node FG is retained for a long time. Therefore, no refresh operation is required or the data is retained for a certain period of time. It is possible to reduce the frequency of cleaning operations extremely, and power consumption can be reduced significantly. In addition, even if there is no power supply, the memory contents can be retained for a long period of time. It is possible.

[0039] In a read mode, the information stored in the memory cell is read. When an appropriate potential (read potential) is applied to the fifth wire while a potential (constant potential) is applied, Depending on the amount of charge stored at node FG, transistor 160 assumes different states. Generally, when the transistor 160 is an n-channel type, a high-level charge is applied to the node FG. The apparent threshold voltage V of transistor 160 when held th_H is the node FG The apparent threshold voltage V of the transistor 160 when a low-level charge is held in t h_L Here, the apparent threshold voltage is the voltage at which the transistor 160 is This refers to the potential of the fifth wiring required to turn on the fifth wiring. The potential of the wiring is V th_H and V th_L By setting the potential V0 between the node FG For example, in write mode, the high level charge is given, the potential of the fifth wire is V0 (>V th_H ) then, If a low level charge is applied, the fifth resistor 160 is in the "ON state." The potential of the wiring is V0( <V th_L ), transistor 160 is in the "off state" Therefore, the potential of the fifth wiring is controlled to turn on the transistor 160. By reading out the ON or OFF state (reading out the potential of the second wiring), the stored information can be read. (read mode).

[0040] When memory cells are arranged in an array, only the information in the desired memory cell can be read. If the information in the memory cell is not read, the state of node FG is The potential at which transistor 160 is in the "off state" regardless of V th_H Alternatively, a smaller potential may be applied to the fifth wiring. The potential at which transistor 160 is in the "on" state, i.e., V th_L Larger potential is given to the fifth wire.

[0041] In addition, when rewriting information stored in a memory cell, the above-mentioned write mode By supplying a new potential to the node FG, which has held a predetermined amount of charge by G holds the charge related to the new information. Specifically, the potential of the fourth wiring is The transistor 162 is turned on by applying a potential to the transistor 162. The potential of the third wiring (potential related to new information) is supplied to the node FG. After that, the potential of the fourth wiring is turned off by the transistor 162. By setting the potential at the node FG to a value that is in the low state and turning off the transistor 162, In other words, the node FG is in a write mode. A predetermined amount of charge is held by the write mode (first write mode). By performing the same operation (second write mode), the information stored in the memory cell is overwritten. It is possible to write.

[0042] In this way, the semiconductor device according to the disclosed invention can directly write information again. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need to extract charge from the floating gate using a high voltage, and the erase operation In other words, the semiconductor device can operate at high speed. It will be realized.

[0043] The source electrode or drain electrode of the transistor 162 is connected to the gate of the transistor 160. By electrically connecting the gate electrode to the flow cell, the flow cell can be used as a nonvolatile memory element. The floating gate of a floating gate transistor functions in the same way as a floating gate of a floating gate transistor. When the transistor 162 is in the off state, the node FG is buried in the insulator (so-called floating state). As can be seen, charge is held at node FG. The off-state current of 162 is less than 1 / 100,000 of that of transistors made of silicon semiconductors, etc. Therefore, the loss of charge stored in the node FG due to leakage of the transistor 162 is prevented. That is, the transistor 162 including an oxide semiconductor can It is possible to realize a nonvolatile memory device that can retain information even without a power supply.

[0044] For example, the off-state current of the transistor 162 at room temperature is 10 zA (1 zeptoampere). is 1 x 10 -21 A) or less, and the capacitance value of the capacitance element 164 is about 10 fF. is at least 10 4 It is possible to hold data for more than 10 seconds. It goes without saying that this will vary depending on the resistor characteristics and capacitance value.

[0045] In addition, in conventional floating gate transistors, the gate Since charges move through the gate insulating film (tunnel insulating film), However, in the semiconductor device shown in this embodiment, The switching operation of the transistor 162 simply changes the charge between the third wiring and the node FG. Since only migration occurs, the degradation of the gate insulating film, which has been a problem in the past, is eliminated. This means that there is no theoretical limit to the number of times it can be written, and it has extremely high rewrite durability. In addition, in the conventional floating gate type transistor, The high voltage required for writing and erasing is also no longer necessary.

[0046] The semiconductor device shown in FIG. 1(A-1) includes elements such as transistors that constitute the semiconductor device. It can be thought of as including resistance and capacitance as shown in Figure 1(A-2). That is, in FIG. 1(A-2), the transistor 160 and the capacitor 164 are respectively It is considered to be composed of resistance and capacitance. R1 and C1 are The resistance value R1 is the resistance value and capacitance value of the capacitance element 164. R2 and C2 correspond to the resistance of the insulating layer. The resistance and capacitance of the transistor 160 are shown in FIG. The capacitance C2 corresponds to the resistance value of the gate insulating layer, and the capacitance C2 is the so-called gate capacitance (the capacitance between the gate electrode and The capacitance formed between the source electrode and / or drain electrode, and the capacitance formed between the gate electrode and the channel This corresponds to the capacitance formed between the gate electrode and the channel forming region.

[0047] The resistance between the source and drain electrodes when the transistor 162 is in the off state (actual If the gate leakage of transistor 162 is sufficiently small, then In the condition, if R1 and R2 satisfy R1 is equal to or greater than ROS, and R2 is equal to or greater than ROS, In this case, the charge retention period (which can also be called the information retention period) is mainly determined by the transistor. The value is determined by the off-current of the capacitor 162.

[0048] On the other hand, if this condition is not satisfied, the off-state current of the transistor 162 is not sufficiently small. In addition, it becomes difficult to secure a sufficient retention period. The leakage current (for example, the leakage current generated between the source electrode and the gate electrode) is large. For this reason, the semiconductor device disclosed in this embodiment has the above-mentioned characteristics. It is desirable that the above conditions be met.

[0049] On the other hand, it is desirable that C1 and C2 satisfy the relationship that C1 is equal to or greater than C2. By doing so, when the potential of the node FG is controlled by the fifth wiring (for example, when reading ) and therefore, fluctuations in the potential of the fifth wiring can be kept low.

[0050] By satisfying the above-mentioned relationship, it is possible to realize a more suitable semiconductor device. R1 and R2 are controlled by the gate insulating layer of transistor 160 and transistor 162. The same applies to C1 and C2. Therefore, the material and thickness of the gate insulating layer It is desirable to appropriately set the above so as to satisfy the above relationship.

[0051] In the semiconductor device shown in this embodiment, the node FG is connected to a flow It functions in the same way as the floating gate of a floating gate type transistor. The node FG in this form has a characteristic that is essentially different from the floating gate of a flash memory or the like. In flash memory, the voltage applied to the control gate is high, To prevent the potential from affecting the floating gate of an adjacent cell, This makes it necessary to maintain a certain distance between the cell and the substrate. This hinders the high integration of semiconductor devices. This is one of the factors that cause tunnel current to be generated by applying a high electric field. This is due to the fundamental principle of flash memory.

[0052] In addition, due to the above-mentioned principle of flash memory, the insulating film deteriorates and the number of times it can be rewritten is limited. Another problem arises: the limit (about 10,000 times).

[0053] The semiconductor device according to the disclosed invention is a semiconductor device including a transistor including an oxide semiconductor. This operates in this way, and does not use the principle of charge injection by tunnel current as described above. Unlike flash memory, there is no need to apply a high electric field to inject charges. Therefore, there is no need to consider the influence of the high electric field caused by the control gate on the adjacent cells. Therefore, the interval between cells can be narrowed, facilitating high integration.

[0054] In addition, since the principle of charge injection by tunnel current is not used, there is no cause for deterioration of the memory cell. This means that it has higher durability and reliability than flash memory. become.

[0055] In addition, the fact that a high electric field is not required and large peripheral circuits (such as a boost circuit) are not required is also an advantage of flash memory. This is an advantage over Schmemoria.

[0056] The relative dielectric constant εr1 of the insulating layer constituting the capacitance element 164 and the dielectric constant εr2 of the insulating layer constituting the transistor 160 are When the relative dielectric constant εr2 of the insulating layer constituting the capacitance element 164 is made different from the relative dielectric constant εr2 of the insulating layer constituting the capacitance element 164, and the area S2 of the insulating layer that constitutes the gate capacitance of the transistor 160. , 2·S2 satisfies S1 or more (preferably S2 is S1 or more), and C1 satisfies C2 or more. That is, the area of ​​the insulating layer that constitutes the capacitance element 164 can be reduced. It is easy to realize C1 to be equal to or larger than C2 while minimizing the capacitance. The insulating layer constituting the element 164 is made of a high dielectric constant (high-k) material such as hafnium oxide. A film made of a material, or a film made of a high-dielectric constant (high-k) material such as hafnium oxide and an acid A laminated structure with a film made of a nitride semiconductor is adopted to set εr1 to 10 or more, preferably 15 or more. In the insulating layer that constitutes the gate capacitance, silicon oxide is used, and εr2=3 to 4. It is possible.

[0057] By using such a configuration in combination, the semiconductor device according to the disclosed invention can be further improved. Integration is possible.

[0058] The above explanation is for n-type transistors (n-channel transistors) in which electrons are the majority carriers. This is about using a large number of hole-capacitors instead of n-type transistors. The p-type transistor (p-channel transistor) can be used as a carrier when Needless to say.

[0059] As described above, the semiconductor device according to one embodiment of the disclosed invention has a source and a drain in an off state. A write transistor with low leakage current (off-state current) between the write transistors, A nonvolatile memory device including a read transistor and a capacitor element using a semiconductor material different from that of the memory device. It has memory cells.

[0060] The off-state current of the write transistor is 100 zA ( 1×10 -19 A) or less, preferably 10zA (1 x 10 -20 A) The following are more preferable: For example, 1zA (1 x 10 -21 A) It is desirable that the value is less than or equal to the value of the normal silicon semiconductor. Although it is difficult to obtain a low off-state current as described above, it is possible to This can be achieved in the processed transistor. A transistor including an oxide semiconductor is preferably used as the transistor.

[0061] Furthermore, transistors using oxide semiconductors have a small subthreshold swing (S value). Therefore, even if the mobility is relatively low, the switching speed can be increased sufficiently. Therefore, by using this transistor as a writing transistor, The rise of the applied write pulse can be made extremely steep. Since the current is small, it is possible to reduce the amount of charge held at node FG. By using a transistor including an oxide semiconductor as a writing transistor, This allows information to be rewritten quickly.

[0062] There is no limit to the off-state current of the readout transistor, but the readout speed is To increase the readout speed, it is preferable to use transistors that operate at high speed. It is possible to use transistors with a switching speed of less than 1 nanosecond as the transistors for preferable.

[0063] Data is written to the memory cell by turning on the write transistor. One of the source electrode or the drain electrode of the writing transistor and the electrode of the capacitor element A potential is supplied to a node electrically connected to one of the gate electrodes of the read transistor. Then, by turning off the write transistor, a predetermined amount of This is done by holding the charge. Here, the off-state current of the writing transistor is extremely small. Therefore, the charge supplied to the node is maintained for a long time. If the value is essentially 0, the refresh operation required in conventional DRAM is not required, or Therefore, the frequency of refresh operations should be extremely low (for example, once a month or once a year). This makes it possible to sufficiently reduce the power consumption of the semiconductor device.

[0064] In addition, information can be directly rewritten by writing information to the memory cell again. This makes it possible to eliminate the erase operation required in flash memories and the like. This makes it possible to suppress a decrease in the operation speed due to the erase operation. In addition, the conventional floating gate transistors can be used for writing and erasing data at high speed. Since it does not require the high voltage required for the previous method, the power consumption of the semiconductor device is further reduced. The voltage applied to the memory cell according to this embodiment (the voltage of the memory cell) can be reduced. The maximum value of the difference between the maximum and minimum potentials simultaneously applied to each terminal is two levels (1 When writing information (bits), the voltage in one memory cell should be 5V or less, preferably 3V The following is the result.

[0065] A memory cell arranged in a semiconductor device according to the disclosed invention includes a write transistor and It is sufficient to include at least a read transistor and a capacitance element. Therefore, the area per memory cell can be reduced to, for example, It is significantly smaller than SRAM, which requires six transistors per memory cell. This allows memory cells to be arranged at high density in a semiconductor device. .

[0066] In addition, in conventional floating gate transistors, the gate insulating film (transistor) Since charges move through the gate insulating film (tunnel insulating film), deterioration of the gate insulating film (tunnel insulating film) occurs. However, in the memory cell according to one embodiment of the present invention, By switching the transistor, a certain amount of charge is held at the node, and information is stored. This eliminates the problem of gate insulating film deterioration, which has been a problem in the past. This is because there is no theoretical limit to the number of times it can be written, and it has extremely high rewrite durability. For example, a memory cell according to one embodiment of the present invention has a capacity of 1×10 9 times( Even after more than 1 billion write cycles, no degradation in the current-voltage characteristics is observed.

[0067] Furthermore, a transistor using an oxide semiconductor as a writing transistor in a memory cell When using oxide semiconductors, the energy gap is large, 3.0 to 3.5 eV, and the thermal For example, the memory cell can function even in a high-temperature environment of 150°C. No degradation in the current-voltage characteristics of the filter is observed.

[0068] As a result of extensive research, the present inventors have found that a transistor using an oxide semiconductor can be Even under high temperatures, the characteristics do not deteriorate, and the off-state current is extremely small at 100 zA or less at room temperature. One embodiment of the present invention provides the following: The transistor with such excellent characteristics is applied as a write transistor for memory cells. The present invention provides a semiconductor device having unprecedented features.

[0069] Note that the configurations, methods, and the like described in this embodiment may be applied to configurations, methods, and the like described in other embodiments. They can be used in any suitable combination.

[0070] (Embodiment 2) In this embodiment mode, an application example of the semiconductor device shown in the previous embodiment will be described with reference to FIGS. 2 and 3. This will be used to explain.

[0071] 2(A) and 2(B) are diagrams illustrating the semiconductor device shown in FIG. 1(A-1) (hereinafter referred to as memory cell 1) 90.) is a circuit diagram of a semiconductor device formed using a plurality of. 1 is a circuit diagram of a so-called NAND type semiconductor device in which memory cells 190 are connected in series. 2B shows a so-called NOR type semiconductor device in which memory cells 190 are connected in parallel. FIG. 1 is a circuit diagram of the device.

[0072] The semiconductor device shown in FIG. 2A includes a source line SL, a bit line BL, a first signal line S1, and a plurality of The memory cell array 190 includes a second signal line S2, a plurality of word lines WL, and a plurality of memory cells 190. ) has one source line SL and one bit line BL. Without being limited thereto, a configuration having a plurality of source lines SL and bit lines BL may also be used.

[0073] In each memory cell 190, the gate electrode of transistor 160 and the gate electrode of transistor 162 One of the source electrode and the drain electrode of the capacitor 164 is electrically connected to one of the electrodes of the capacitor 164. Also, the first signal line S1 and the source electrode or the drain electrode of the transistor 162 are connected. The other of the gate electrodes is electrically connected to the second signal line S2 and the gate of the transistor 162. The electrode of the capacitor 164 is electrically connected to the word line WL. The other is electrically connected.

[0074] The source electrode of the transistor 160 in the memory cell 190 is connected to the adjacent memory cell The drain electrode of the transistor 160 in the memory cell 190 is electrically connected to the drain electrode of the transistor 160 in the memory cell 190. The drain electrode of the transistor 160 is connected to the transistor of the adjacent memory cell 190. 160. However, the plurality of memory cells connected in series are electrically connected to the source electrode of the memory cell 160. The drain of the transistor 160 of the memory cell 190 provided at one end of the The electrode is electrically connected to a bit line. That is, the source electrode of the transistor 160 of the memory cell 190 provided at the other end is , and are electrically connected to the source line.

[0075] The semiconductor device shown in FIG. 2A performs writing and reading operations for each row. The write operation is performed as follows: Transistor 1 is connected to the second signal line S2 of the row to be written. 62 is applied with a potential to be turned on, and the transistor 162 of the row to be written is turned on. As a result, the gate electrodes of the transistors 160 in the specified row are connected to the first signal line S1. A potential is applied to the gate electrode, and a predetermined charge is applied to the gate electrode. Data can be written to the memory cells.

[0076] The read operation is performed as follows: First, the word lines WL other than the row from which the read is to be performed are connected. Therefore, the transistor 160 is turned on regardless of the charge on the gate electrode of the transistor 160. A potential is applied so that the transistors 160 in the rows other than the row to be read out are turned on. Then, the gate electrode of the transistor 160 is connected to the word line WL of the row to be read. The charge applied to the transistor 160 selects the on or off state. Then, a constant potential is applied to the source line SL, and a potential is applied to the bit line BL. The read circuit (not shown) connected to the source line SL is set to an operating state. The transistors 160 between the bit lines BL are in the on state except for the row to be read. The conductance between the source line SL and the bit line BL is 60. That is, the gate of the transistor 160 of the row to be read is determined by the The potential of the bit line BL read by the read circuit varies depending on the charge on the bit electrode. In this way, data can be read from the memory cells of a specified row.

[0077] The semiconductor device shown in FIG. 2B includes a source line SL, a bit line BL, a first signal line S1, a second signal line S2, a The memory cell array 100 includes a plurality of signal lines S2 and word lines WL, and a plurality of memory cells 190. The gate electrode of each transistor 160 and the source or drain electrode of each transistor 162 One of the electrodes of the capacitor 164 is electrically connected to one of the electrodes of the capacitor 164. The source line SL and the source electrode of the transistor 160 are electrically connected, and the bit line BL and The first signal line S 1 and the other of the source electrode or the drain electrode of the transistor 162 are electrically connected. The second signal line S2 and the gate electrode of the transistor 162 are electrically connected. The word line WL and the other electrode of the capacitor 164 are electrically connected to each other.

[0078] The semiconductor device shown in FIG. 2B performs writing and reading operations for each row. The write operation is performed in the same manner as in the semiconductor device shown in FIG. The read operation is performed as follows: First, a transistor 1 is connected to a word line WL other than the row where the read operation is performed. A potential is applied so that the transistor 160 is turned off regardless of the charge on the gate electrode of the transistor 60. Then, the transistors 160 other than the row to be read are turned off. The charge carried by the gate electrode of the transistor 160 is applied to the word line WL of the row in which the transistor 160 is to be applied. A potential (read potential) that selects the on or off state of the transistor 160 is applied. Then, a constant potential is applied to the source line SL, and the read The circuit (not shown) is set to an operating state. Here, the conduction between the source line SL and the bit line BL is The capacitance is determined by the state of the transistor 160 of the row being read. , the charge on the gate electrode of the transistor 160 in the row to be read out is The potential of the bit line BL read by the circuit is different. Data can be read from the memory cells.

[0079] Next, an example of a read circuit that can be used in the semiconductor device shown in FIG. 2 will be described with reference to FIG. This will be explained using:

[0080] FIG. 3A shows a schematic diagram of a readout circuit. The readout circuit is composed of a transistor and a sensor. It has a amplifier circuit.

[0081] When reading, terminal A is connected to the bit line to which the memory cell to be read is connected. In addition, a bias potential Vbias is applied to the gate electrode of the transistor, and the potential at terminal A is The position is controlled.

[0082] The memory cell 190 exhibits different resistance values ​​depending on the data stored therein. When the transistor 160 of the selected memory cell 190 is in an on state, it is in a low resistance state. When the transistor 160 of the selected memory cell 190 is in an off state, it is in a high resistance state. .

[0083] When the memory cell 190 is in a high resistance state, the potential at terminal A becomes higher than the reference potential Vref, The sense amplifier outputs a potential (data "1") corresponding to the potential of terminal A. When cell 190 is in a low resistance state, the potential at terminal A becomes lower than the reference potential Vref, and the sense The amplifier circuit outputs a potential corresponding to the potential of terminal A (data "0").

[0084] In this way, by using the read circuit, data can be read from the memory cell 190. The readout circuit of this embodiment is an example. Other known circuits may also be used. The read circuit may also include a precharge circuit. Instead, a reference bit line may be connected.

[0085] Fig. 3(B) shows a differential sense amplifier which is an example of a sense amplifier circuit. The differential sense amplifier has an input terminal Vin(+), an input terminal Vin(-), and an output terminal Vout, and amplifies the difference between Vin(+) and Vin(-). If Vin(+) > Vin(-), Vout is generally a High output, and if Vin(+) < Vin(-), Vout is generally a Low output. When the differential sense amplifier is used in a read circuit, one of Vin(+) and Vin(-) is connected to terminal A, and a reference potential Vref is applied to the other of Vin(+) and Vin(-).

[0086] Fig. 3(C) shows a latch-type sense amplifier which is an example of a sense amplifier circuit. The latch-type sense amplifier has an input / output terminal V1, an input / output terminal V2, an input terminal for a control signal Sp, and an input terminal for a control signal Sn. First, the signal Sp is set to High and the signal Sn is set to Low to cut off the power supply potential (Vdd). Then, potentials for comparison are applied to V1 and V2. After that, when the signal Sp is set to Low and the signal Sn is set to High to supply the power supply potential (Vdd), if the potentials for comparison V1in and V2in are in the relationship V1in > V2in, the output of V1 is High and the output of V2 is Low, and if they are in the relationship V1in < V2in, the output of V1 is Low and the output of V2 is High. By utilizing such a relationship, the difference between V1in and V2in can be amplified. When the latch-type sense amplifier is used in a read circuit, one of V1 and V2 is connected to terminal A and the output terminal via a switch, and a reference potential Vref is applied to the other of V1 and V2.

[0087] The configurations, methods, etc. shown in the present embodiment can be appropriately combined with the configurations, They can be used in combination.

[0088] (Embodiment 3) In this embodiment, a structure of a semiconductor device according to one embodiment of the disclosed invention and a manufacturing method thereof will be described. This will be described with reference to FIGS.

[0089] <Cross-sectional and planar configurations of semiconductor device> FIG. 7 shows an example of the configuration of a semiconductor device. FIG. 7(A) shows a cross section of the semiconductor device, and FIG. 7B) shows a plan view of the semiconductor device. Here, FIG. 7A shows the A of FIG. 7B. 7(A) and 7(B) correspond to the cross sections taken along lines 1-A2 and B1-B2. The semiconductor device includes a transistor 160 using a semiconductor material other than an oxide semiconductor in a lower portion. The transistor 162 includes an oxide semiconductor in the upper portion. The transistor 160 using a semiconductor material other than silicon dioxide has a higher field efficiency than an oxide semiconductor material. High-speed operation is possible by using materials with high electron mobility. The transistor 162 using the material can retain charge for a long time due to its characteristics.

[0090] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can also be used. The technical essence of the present invention is to use an oxide semiconductor as the transistor 162 to store data. The specific configuration of the semiconductor device does not need to be limited to that shown here. .

[0091] The transistor 160 in FIG. 7 is formed on a substrate 100 that includes a semiconductor material (e.g., silicon). 00 and the channel forming region 116 provided in between. The impurity region 114 and the high concentration impurity region 120 (collectively referred to as the impurity region) a gate insulating layer 108a provided on the channel forming region 116; A gate electrode 110a provided on the insulating layer 108a is electrically connected to the impurity region. Source or drain electrode 130a and source or drain electrode 130b It has.

[0092] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110a. Also, when viewed from the direction perpendicular to the surface of the substrate 100, the sidewall insulating layer 118 is not overlapped. The lower region has a high-concentration impurity region 120, and a metal compound in contact with the high-concentration impurity region 120. The substrate 100 also has an element region 124 surrounding the transistor 160. An isolation insulating layer 106 is provided, and an interlayer insulating layer 12 is provided to cover the transistor 160. 6 and an interlayer insulating layer 128. A source electrode or drain electrode 130a, The source electrode or drain electrode 130b is formed between the interlayer insulating layer 126 and the interlayer insulating layer 1 The metal compound region 124 is electrically connected to the metal compound region 124 through the opening formed in the metal compound region 28. The source or drain electrode 130a and the source or drain electrode 13 0b is connected to the high concentration impurity region 120 and the impurity region 114 via the metal compound region 124. The electrode 130c is electrically connected to the interlayer insulating layer 126 and the interlayer insulating layer The gate electrode 110a is electrically connected to the gate electrode 110a through an opening formed in the gate electrode 128. , the sidewall insulating layer 118 is not formed due to the integration of the transistor 160, etc. There are cases like this.

[0093] The transistor 162 in FIG. 7 has a source electrode or A drain electrode 142a and a source or drain electrode 142b are connected to each other. and the source or drain electrode 142b. The oxide semiconductor layer 144 is connected to the source or drain electrode 142a. a gate insulating layer 146 covering the gate electrode or drain electrode 142b and the oxide semiconductor layer 144; A gate electrode 141 is provided on the gate insulating layer 146 so as to overlap with the oxide semiconductor layer 144. 48a and

[0094] Here, impurities such as hydrogen are sufficiently removed from the oxide semiconductor layer 144. It is desirable that the water be highly purified by supplying sufficient oxygen. Specifically, for example, the hydrogen concentration in the oxide semiconductor layer 144 is 5×10 19 atoms / c m 3 Below 5×10 18 atoms / cm 3 Less than or equal to 5×10 1 7 atoms / cm 3 Note that the hydrogen concentration in the oxide semiconductor layer 144 is as follows: Secondary Ion Mass Spectrometry (SIMS) The hydrogen concentration was sufficiently reduced to obtain a highly pure Defect levels in the energy gap due to oxygen deficiency are formed by the supply of sufficient oxygen. In the oxide semiconductor layer 144 in which the carrier concentration is reduced, the carrier concentration is 1×10 12 / cm 3 Less than, hope Preferably 1 x 10 11 / cm 3 Less than 1.45 × 10 10 / cm 3 less than For example, the off-current at room temperature (here, the value per unit channel width (1 μm)) is 100zA / μm (1zA (zeptoampere) is 1×10 -21 A) The following are desirable: In this way, the i-type (intrinsic) or substantially i-type By using the oxide semiconductor, a transistor 162 with excellent off-state current characteristics can be obtained. It is possible.

[0095] Note that in the transistor 162 in FIG. 7, the oxide semiconductor layer 144 is not processed into an island shape. This can prevent contamination of the oxide semiconductor layer 144 due to etching during processing.

[0096] The capacitor 164 includes a source electrode or a drain electrode 142a, an oxide semiconductor layer 144, a gate electrode 142b, and a gate insulating film 142c. The gate insulating layer 146 and the electrode 148b are the source or drain electrodes. The drain electrode 142a functions as one electrode of the capacitance element 164, and the electrode 148b functions as the capacitance element 164. This will function as the other electrode of the capacitor 164.

[0097] In the capacitor 164 of FIG. 7, the oxide semiconductor layer 144 and the gate insulating layer 146 are stacked. By doing so, the insulation between the source electrode or drain electrode 142a and the electrode 148b is reduced. This ensures sufficient safety.

[0098] Note that in the transistor 162 and the capacitor 164, the source electrode or the drain electrode The ends of the electrode 142a and the source or drain electrode 142b are tapered. Here, the taper angle is preferably set to, for example, 30° or more and 60° or less. The taper angle is the angle at which a layer having a tapered shape (for example, a source electrode or a drain electrode) 42a) from a direction perpendicular to its cross section (a plane perpendicular to the surface of the substrate). The inclination angle between the side and bottom surfaces of the source electrode or drain electrode 142a, The end of the electrode 142b is tapered, so that the oxide semiconductor layer This is because the covering property of 144 can be improved and step disconnection can be prevented.

[0099] In addition, an interlayer insulating layer 150 is provided on the transistor 162 and the capacitor element 164. An interlayer insulating layer 152 is provided on the interlayer insulating layer 150 .

[0100] <Method for manufacturing semiconductor device> Next, an example of a method for manufacturing the semiconductor device will be described. The method for fabricating the transistor 160 will be explained with reference to FIG. A method for manufacturing the capacitor 162 will be described with reference to FIG.

[0101] <Method for manufacturing the lower transistor>

[0102] First, a substrate 100 containing a semiconductor material is prepared (see FIG. 8(A)). The plate 100 may be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be used. Here, the substrate 100 containing a semiconductor material is a single crystal silicon substrate. An example will be shown below. Generally, an "SOI substrate" is a substrate in which silicon semiconductor is formed on an insulating surface. It refers to a substrate having a structure in which a conductor layer is provided, but in this specification, it refers to a substrate having a silicon layer on an insulating surface. The term "substrate" is used as a concept that also includes a substrate having a semiconductor layer made of a material other than The semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The plate has a structure in which a semiconductor layer is provided on an insulating substrate such as a glass substrate via an insulating layer. shall be included.

[0103] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. (See FIG. 8(A)). The protective layer 102 may be made of, for example, silicon oxide or silicon nitride. An insulating layer made of silicon oxynitride or the like can be used. In order to control the threshold voltage of the transistor, an impurity that gives n-type conductivity is added. An element or an impurity element that imparts p-type conductivity may be added to the substrate 100. In the case of capacitors, impurities that give n-type conductivity include, for example, phosphorus (P) and arsenic (As ) can be used. As impurities that impart p-type conductivity, for example, Boron (B), aluminum (Al), gallium (Ga), etc. can be used.

[0104] Next, etching is performed using the protective layer 102 as a mask, and the This removes a portion of the substrate 100 from the exposed area. A semiconductor region 104 separated from the region is formed (see FIG. 8(B)). Although dry etching is preferably used for this purpose, wet etching may also be used. The etching gas and etching solution should be selected appropriately depending on the material to be etched. can.

[0105] Next, an insulating layer is formed so as to cover the semiconductor region 104, and the region overlapping the semiconductor region 104 is The insulating layer is selectively removed to form an element isolation insulating layer 106 (see FIG. 8(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, etc. There are several methods for removing the insulating layer, such as polishing processes like CMP and etching processes. Either of them may be used. After the semiconductor region 104 is formed or after the element isolation insulating layer After forming 106, the protective layer 102 is removed.

[0106] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. do.

[0107] The insulating layer will later become the gate insulating layer and is obtained using a CVD method, sputtering method, etc. Silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide tantalum oxide, yttrium oxide, hafnium silicate (HfSixOy(x>0 , y>0), nitrogen-doped hafnium silicate (HfSixOy(x>0, y> 0), nitrogen-doped hafnium aluminate (HfAlxOy(x>0, y>0) ) and the like. The surface of the semiconductor region 104 is oxidized and nitrided by the chemical treatment, thereby forming the insulating layer. The high density plasma treatment may be performed using, for example, a rare gas such as He, Ar, Kr, or Xe, It can be carried out using a mixed gas of oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, etc. The thickness of the insulating layer is, for example, 1 nm or more and 100 nm or less, preferably 10 nm or more and 50 nm or less. It can be made to be nm or less.

[0108] The layer containing the conductive material is made of a metal material such as aluminum, copper, titanium, tantalum, or tungsten. Also, a conductive material such as polycrystalline silicon can be used to form the conductive layer. The method for forming the layer is not particularly limited, and may be a vapor deposition method, a CVD method, a sputtering method, or the like. Various film forming methods such as talc coating and spin coating can be used. In this embodiment, an example in which a layer containing a conductive material is formed using a metal material is shown. Let's say.

[0109] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108. a) A gate electrode 110a is formed (see FIG. 8(C)).

[0110] Next, an insulating layer 112 is formed to cover the gate electrode 110a (see FIG. 8(C)). Phosphorus (P) or arsenic (As) is added to the semiconductor region 104 to form an impurity region with a shallow junction depth. In this case, a region 114 is formed (see FIG. 8(C)). To achieve this, phosphorus (P) or arsenic (As) is added. In this case, impurity elements such as boron (B) and aluminum (Al) may be added. By forming the region 114, a channel-shaped region is formed below the gate insulating layer 108a of the semiconductor region 104. A compound region 116 is formed (see FIG. 8(C)). Here, the concentration of the added impurity is set appropriately. However, when semiconductor elements are highly miniaturized, the concentration can be increased. In this case, the impurity region 114 is formed after the insulating layer 112 is formed. However, the process of forming the insulating layer 112 after forming the impurity region 114 is adopted. It's fine to do that.

[0111] Next, a sidewall insulating layer 118 is formed (see FIG. 8(D)). The layer 118 is formed by forming an insulating layer to cover the insulating layer 112 and then removing the insulating layer and the insulating layer 118. By subjecting 12 to highly anisotropic etching, it can be formed in a self-aligned manner. At this time, the insulating layer 112 is partially etched to form a layer on the top surface of the gate electrode 110a. It is preferable that the top surfaces of the impurity regions 114 are exposed. In some cases, it is not formed for the purpose of achieving high integration.

[0112] Next, a layer is formed so as to cover the gate electrode 110a, the impurity region 114, the sidewall insulating layer 118, etc. Then, an insulating layer is formed in a region in contact with the impurity region 114 by ion implantation of phosphorus (P) or arsenic (Ar). By adding arsenic (As) or the like, a high concentration impurity region 120 is formed (see FIG. 8(E)). Thereafter, the insulating layer is removed, and the gate electrode 110a, the sidewall insulating layer 118, and the high-concentration impurity A metal layer 122 is formed so as to cover the pure region 120 and the like (see FIG. 8(E)). 122 is formed using various film formation methods such as vacuum deposition, sputtering, and spin coating. The metal layer 122 can be formed by reacting with the semiconductor material that constitutes the semiconductor region 104. It is desirable to form the insulating layer using a metal material that becomes a low-resistance metal compound by this process. Examples of such metal materials include titanium, tantalum, tungsten, nickel, and copper. Examples include baltic and platinum.

[0113] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. A metal compound region 124 is formed in contact with the high concentration impurity region 120 (see FIG. 8(F)). When polycrystalline silicon or the like is used as the gate electrode 110a, the gate electrode 11 A metal compound region is also formed in the portion of Oa that comes into contact with the metal layer 122.

[0114] The heat treatment may be, for example, a heat treatment by irradiation with a flash lamp. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds In order to improve the controllability of the heat treatment, it is desirable to use a method that can realize heat treatment in a very short time. The metal compound region 124 is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed by the metal compound, and is a region with sufficiently enhanced conductivity. By doing so, the electrical resistance can be sufficiently reduced and the device characteristics can be improved. After compound region 124 is formed, metal layer 122 is removed.

[0115] Next, an interlayer insulating layer 126 and an interlayer insulating layer 127 are formed to cover the respective components formed by the above-described steps. The interlayer insulating layer 126 and the interlayer insulating layer 128 are formed by oxidation. Silicon, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, titanium oxide The insulating layer can be formed using a material containing an inorganic insulating material such as aluminum. It is also possible to form the insulating layer using an organic insulating material such as acrylic. However, one embodiment of the disclosed invention is not limited to this. The interlayer insulating layer 128 may be a single layer or may have a laminated structure of three or more layers. After the formation of the layer, the surface can be flattened by CMP or etching. desirable.

[0116] Thereafter, an opening is formed in the interlayer insulating layer so as to reach the metal compound region 124. The source or drain electrode 130a and the source or drain electrode 130b are The source or drain electrode 130a and the source or drain electrode 130b are formed (see FIG. 8(H)). The drain electrode 130b is formed by, for example, using a PVD method or a CVD method in the region including the opening. After forming the conductive layer, a part of the conductive layer is removed by a method such as etching or CMP. can be formed by removing

[0117] More specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then CV After forming a thin titanium nitride film by the D method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method is The oxide film (natural oxide film, etc.) on the surface is reduced, and the lower electrode (here, the metal compound region 1 24) and the titanium nitride film formed thereafter. It has a barrier function that suppresses the diffusion of conductive materials. After forming the barrier film, a copper film may be formed by plating.

[0118] In addition, a part of the conductive layer is removed to form the source electrode or drain electrode 130a and the source electrode Alternatively, when forming the drain electrode 130b, the surface thereof is processed to be flat. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When a tungsten film is formed to fill the opening, the inclusions are removed by the subsequent CMP. It removes the necessary tungsten film, titanium film, titanium nitride film, etc., and also maintains the flatness of the surface. In this way, the source electrode or drain electrode 130a, By planarizing the surface including the source or drain electrode 130b, it is possible to This makes it possible to form good electrodes, wiring, insulating layers, semiconductor layers, and the like.

[0119] Here, the source electrode or drain electrode 130 in contact with the metal compound region 124 Although only the gate electrode 130a and the source electrode or the drain electrode 130b are shown, An electrode in contact with the source electrode 110a may also be formed. can be used as the drain electrode 130a, the source electrode or the drain electrode 130b. There is no particular limitation on the material that can be used, and various conductive materials can be used. For example, molybdenum Titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium In addition, in consideration of the heat treatment to be performed later, The source or drain electrode 130a and the source or drain electrode 130b are It is desirable to form the insulating layer using a material that has sufficient heat resistance to withstand the processing.

[0120] As a result of the above, a transistor 160 using the substrate 100 containing a semiconductor material is formed (see FIG. 8(H)). The transistor 160 using a semiconductor material other than an oxide semiconductor can operate at high speed. It is possible to create

[0121] After the above steps, electrodes, wiring, an insulating layer, etc. may be further formed. By adopting a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers, A highly integrated semiconductor device can be provided.

[0122] <Method of manufacturing the upper transistor> Next, referring to FIG. 9, a process for manufacturing the transistor 162 on the interlayer insulating layer 128 will be described. 9 shows various electrodes on the interlayer insulating layer 128, the transistor 162, etc. Since this shows the manufacturing process, the transistor 162 located below the transistor 16 0 etc. are omitted.

[0123] First, a conductive layer is formed on the interlayer insulating layer 128, and the conductive layer is selectively etched to form a soaked a source or drain electrode 142a, and a source or drain electrode 142b. (See Figure 9(A)).

[0124] The conductive layer is formed using PVD methods such as sputtering, or CVD methods such as plasma CVD. The conductive layer can be formed using a material such as aluminum, chromium, copper, An element selected from tantalum, titanium, molybdenum, and tungsten, or the above-mentioned elements Alloys containing manganese, magnesium, zirconium, and beryllium can be used. Alternatively, a material containing aluminum or a combination of these may be used. Titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium Alternatively, an element selected from the group consisting of aluminum and ammonium, or a material combining a plurality of these elements may be used.

[0125] The conductive layer may have a single layer structure or a laminated structure of two or more layers. single-layer structure of silicon film or titanium nitride film, single-layer structure of aluminum film containing silicon, Two-layer structure with titanium film laminated on titanium nitride film, two-layer structure with titanium film laminated on titanium nitride film Examples include a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated. In addition, when the conductive layer has a single layer structure of a titanium film or a titanium nitride film, a tapered shape is The source or drain electrode 142a and the source or drain electrode 142 It has the advantage of being easy to process into b.

[0126] The conductive layer may be formed using a conductive metal oxide. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), Indium tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO), oxide Indium-zinc oxide alloy (In2O3-ZnO), or these metal oxide materials It is possible to use a material containing silicon or silicon oxide.

[0127] The etching of the conductive layer is performed to form the source or drain electrode 142a and the source It is preferable to perform this process so that the end of the source or drain electrode 142b has a tapered shape. Here, the taper angle is preferably, for example, 30° or more and 60° or less. The ends of the source or drain electrodes 142a and 142b are By etching to form a tapered shape, the gate insulating layer 14 to be formed later can be This improves the covering property of 6 and prevents breakage.

[0128] The channel length (L) of the transistor is determined by the distance between the source or drain electrode 142a and the The distance between the source electrode or the drain electrode 142b and the lower end of the channel is determined by the distance between the source electrode and the lower end of the drain electrode 142b. The exposure for forming a mask used to form a transistor with a channel length (L) of less than 25 nm When doing this, extreme ultraviolet rays with a wavelength of a few nm to a few tens of nm are used. It is desirable to use ultraviolet light. Extreme ultraviolet light exposure provides high resolution and a large depth of focus. Therefore, the channel length (L) of the transistor to be formed later is set to 10 nm or more and 100 nm or less. It is possible to make it 0 nm (1 μm) or less, which makes it possible to increase the operating speed of the circuit. Furthermore, miniaturization also makes it possible to reduce the power consumption of semiconductor devices.

[0129] Note that an insulating layer that functions as a base may be provided on the interlayer insulating layer 128. can be formed by using a PVD method, a CVD method, or the like.

[0130] Also, the source electrode or drain electrode 142a and the source electrode or drain electrode 1 An insulating layer may be formed on 42b. By providing the insulating layer, the insulating layer can be formed later. a gate electrode connected to the source or drain electrode 142a, and a source or drain electrode It is possible to reduce the parasitic capacitance between the drain electrode 142b and the drain electrode 142a.

[0131] Next, the source or drain electrode 142a and the source or drain electrode 142b are An oxide semiconductor layer 144 is formed to cover 42b (see FIG. 9B).

[0132] The oxide semiconductor layer 144 may be a quaternary metal oxide such as In—Sn—Ga—Zn—O, or a ternary metal oxide such as In—Sn—Ga—Zn—O. The metal oxides In-Ga-Zn-O, In-Sn-Zn-O, and In-Al- Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O and binary metal oxides such as In-Zn-O, Sn-Zn-O, and Al-Zn-O. Zn-Mg-O, Sn-Mg-O, In-Mg-O, and single-component metal oxides It can be formed using oxide semiconductors such as In-O, Sn-O, and Zn-O. .

[0133] Among these, In-Ga-Zn-O oxide semiconductor materials have a sufficiently high resistance in the absence of an electric field. It is possible to make the current sufficiently small, and the current is lower than that of ordinary silicon semiconductors. It also has a high field effect mobility, making it suitable as a semiconductor material for use in semiconductor devices.

[0134] A typical example of an In-Ga-Zn-O oxide semiconductor material is InGaO3(ZnO). m (m>0). Also, M is used instead of Ga, and InMO3(Zn O) m There are oxide semiconductor materials that are written as (m>0), where M is gallium. (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), It refers to one or more metal elements selected from the group consisting of cobalt (Co), etc. For example, M includes Ga, Ga and Al, Ga and Fe, Ga and Ni, and Ga and Mn. The above composition is derived from the crystal structure. Please note that this is merely an example.

[0135] The oxide semiconductor layer 144 is formed by sputtering using a target such as In:Ga: The composition is expressed by the formula Zn=1:x:y (x is 0 or more, y is 0.5 or more and 5 or less). For example, In:Ga:Zn=1:1:1 [atomic ratio] (x=1, y =1), (i.e., In2O3:Ga2O3:ZnO=1:1:2 [molar ratio]) A target having a composition ratio of In:Ga:Zn=1:1 can be used. :0.5 [atom ratio] (x=1, y=0.5), (i.e., In2O3:Ga2O3 ZnO=1:1:1 [molar ratio]), and n=1:1:2 [atom ratio] (x=1, y=2), (i.e., In2O3:Ga2O ZnO=1:1:4 (molar ratio), and Zn=1:0:1 [atom ratio] (x=0, y=1), (i.e., In2O3:ZnO A target having a composition ratio of 0.01 to 0.2 (molar ratio) can also be used.

[0136] In this embodiment, the amorphous oxide semiconductor layer 144 is made of an In—Ga—Zn—O-based metal. The film is formed by sputtering using a metal oxide target.

[0137] The relative density of the metal oxide in the metal oxide target is 80% or more, preferably 95% or more; More preferably, it is 99.9% or more. A metal oxide target with a high relative density is used. This makes it possible to form the oxide semiconductor layer 144 with a dense structure.

[0138] The oxide semiconductor layer 144 is formed in a rare gas (typically, argon) atmosphere or an oxygen atmosphere. It is preferable to use a mixed atmosphere of oxygen or a rare gas (typically argon) and oxygen. Specifically, impurities such as hydrogen, water, hydroxyl groups, and hydrides are contained at a concentration of 1 ppm or less. It is preferable to use a high-purity gas atmosphere in which the concentration has been reduced to 10 ppb or less. is.

[0139] When the oxide semiconductor layer 144 is formed, for example, a processing chamber is maintained in a reduced pressure state. The object is held in a state where the temperature of the object to be treated is 100°C or higher but lower than 550°C, preferably 200°C or higher but lower than 40°C. The object to be processed is heated to 0° C. or lower. The temperature of the object to be treated may be room temperature. Then, while removing moisture from the treatment chamber, hydrogen, water, etc. A sputtering gas from which the oxide semiconductor layer 144 is removed is introduced, and the oxide semiconductor layer 144 is formed using the target. The oxide semiconductor layer 144 is formed while heating the object to be processed. It is possible to reduce impurities contained in the conductor layer 144. In addition, damage caused by sputtering can be reduced. To remove moisture from the processing chamber, an adsorption type vacuum pump is used. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. A turbo pump with a cold trap can also be used. Hydrogen and water can be removed from the processing chamber by evacuating it using a cryopump or the like. Since the impurities can be removed, the impurity concentration in the oxide semiconductor layer 144 can be reduced.

[0140] The conditions for forming the oxide semiconductor layer 144 include, for example, the distance between the object to be processed and the target. The diameter was 170 mm, the pressure was 0.4 Pa, the direct current (DC) power was 0.5 kW, and the atmosphere was oxygen (oxygen 100%) atmosphere, or argon (100% argon) atmosphere, or oxygen and argon It is possible to apply conditions such as a mixed atmosphere of pulsed direct current (DC) power supply. By using this, it is possible to reduce dust (such as powdery substances formed during film formation) and to make the film thickness distribution uniform. The thickness of the oxide semiconductor layer 144 is preferably greater than or equal to 1 nm and less than or equal to 50 nm. The thickness is set to 1 nm or more and 30 nm or less, and more preferably 1 nm or more and 10 nm or less. By using the oxide semiconductor layer 144 having a small thickness, the short channel effect that accompanies miniaturization can be suppressed. However, it is possible to select an appropriate method depending on the oxide semiconductor material to be used and the application of the semiconductor device. The thickness varies depending on the material and application. .

[0141] Before the oxide semiconductor layer 144 is formed by sputtering, argon gas is introduced. Then, a reverse sputtering process is performed to generate plasma, and the surface to be formed (for example, the surface of the interlayer insulating layer 128) is Here, the reverse sputtering is a method of removing the deposits in the normal sputtering. Instead of bombarding ions onto the sputtering target, the ions are bombarded onto the surface to be treated. This refers to a method of modifying the surface by bombarding the surface with ions. The method is to apply a high frequency voltage to the surface to be treated in an argon atmosphere, and In addition, nitrogen, helium, An atmosphere such as oxygen may be used.

[0142] After that, the oxide semiconductor layer 144 is preferably subjected to heat treatment (first heat treatment). The first heat treatment removes excess hydrogen (including water and a hydroxyl group) from the oxide semiconductor layer 144. ) to improve the structure of the oxide semiconductor layer and reduce the defect level in the energy gap. The temperature of the first heat treatment can be, for example, 300°C or higher and lower than 550°C, or 40 The temperature must be between 0℃ and 500℃.

[0143] The heat treatment is carried out by, for example, placing the object to be treated in an electric furnace using a resistance heating element, and heating the object in a nitrogen atmosphere. The heat treatment can be performed under conditions of 450° C. and 1 hour. During this time, the oxide semiconductor layer 144 is not exposed to the air. Do not allow leakage and prevent contamination with water or hydrogen.

[0144] Heat treatment equipment is not limited to electric furnaces, and may be heat conduction or heat radiation from a medium such as heated gas. For example, a GRTA (Gas Rap id Thermal Anneal) equipment, LRTA (Lamp Rapid The RTA (Rapid Thermal Anneal) equipment ) equipment can be used. The LRTA equipment uses halogen lamps, metal halide lamps, etc. , xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. The gas used is argon. or an inert gas such as nitrogen that does not react with the material to be treated by heat treatment. It is used.

[0145] For example, in the first heat treatment, the workpiece is placed in a heated inert gas atmosphere and heated for several minutes. After the heating, the object to be treated may be taken out of the inert gas atmosphere and subjected to GRTA treatment. GRTA treatment allows high-temperature heat treatment in a short time. It is possible to apply this method even under temperature conditions exceeding the specified temperature. The first heat treatment may be performed in an atmosphere containing oxygen. This is because the defect level in the energy gap caused by oxygen vacancies can be reduced. do.

[0146] The inert gas atmosphere is nitrogen or a rare gas (helium, neon, argon, etc.). It is desirable to use an atmosphere containing ) as the main component and not containing water, hydrogen, etc. For example, nitrogen and rare gases such as helium, neon, and argon introduced into a heat treatment device Purity should be 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher ( That is, the impurity concentration is set to 1 ppm or less, preferably 0.1 ppm or less.

[0147] In either case, the first heat treatment reduces impurities and produces an i-type (intrinsic semiconductor) or i-type By forming the oxide semiconductor layer 144 that is as close to the This can be realized.

[0148] By the way, the above-mentioned heat treatment (first heat treatment) has the effect of removing hydrogen, water, etc. This heat treatment can also be called a dehydration treatment or a dehydrogenation treatment. The dehydrogenation treatment is performed after the formation of an oxide semiconductor layer or a gate insulating layer. It is also possible to carry out the dehydration treatment at a timing such as after the formation. The dehydrogenation treatment may be carried out not only once but also multiple times.

[0149] Next, the gate insulating layer 146 is formed in contact with the oxide semiconductor layer 144 (see FIG. 9C). The gate insulating layer 146 can be formed by a CVD method, a sputtering method, or the like. The gate insulating layer 146 may be made of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like. tantalum oxide, hafnium oxide, yttrium oxide, hafnium silicate (Hf Si x O y (x>0, y>0)), nitrogen-doped hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen-doped hafnium aluminate (HfAl x O y (x>0, y>0)). The thickness of the film may be a single layer or a multilayer structure. However, when miniaturizing semiconductor devices, the thickness must be reduced to ensure the operation of the transistor. For example, when silicon oxide is used, the thickness is preferably 1 nm or more and 100 nm or less. Preferably, it can be set to 10 nm or more and 50 nm or less.

[0150] As mentioned above, when the gate insulating layer is made thin, the gate leakage caused by the tunnel effect etc. To solve the gate leakage problem, the gate insulating layer 146 is doped with hafnium oxide. tantalum oxide, yttrium oxide, hafnium silicate (HfSi x O y (x>0 , y>0), nitrogen-doped hafnium silicate (HfSi x O y (x>0, y> 0)), nitrogen-doped hafnium aluminate (HfAl x O y (x>0, y>0) It is recommended to use high-dielectric constant (high-k) materials such as By using this material for the gate insulating layer 146, the electrical characteristics are maintained while the gate leakage is suppressed. In addition, it is possible to increase the film thickness by using high dielectric constant (high-k) materials. and a film containing silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, silicon oxide It may also have a laminated structure with a film containing either aluminum or the like.

[0151] After the gate insulating layer 146 is formed, a second thermal treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200°C or higher and 450°C or lower, preferably 25 The temperature is between 0°C and 350°C. For example, heat treatment can be performed at 250°C for 1 hour in a nitrogen atmosphere. By performing the second heat treatment, the variation in the electrical characteristics of the transistors can be reduced. When the gate insulating layer 146 contains oxygen, the oxide semiconductor layer 144 Oxygen is supplied to the oxide semiconductor layer 144 to compensate for oxygen vacancies in the oxide semiconductor layer 144, thereby forming an i-type (intrinsic) or Alternatively, an oxide semiconductor layer that is as close to i-type as possible can be formed.

[0152] In this embodiment, the second heat treatment is performed after the gate insulating layer 146 is formed. The timing of the second heat treatment is not particularly limited to this. For example, the second heat treatment may be performed after the formation of the gate electrode. Alternatively, the second heat treatment may be performed after the first heat treatment. The first heat treatment may also serve as the second heat treatment, or the second heat treatment may also serve as the first heat treatment. It's okay to let them sleep.

[0153] Next, a gate electrode is formed on the gate insulating layer 146 in a region overlapping with the oxide semiconductor layer 144. 148a, and the electrode 148 is formed in the region overlapping with the source electrode or drain electrode 142a. The gate electrode 148a and the electrode 148b are gate insulators. After forming a conductive layer on the edge layer 146, the conductive layer is selectively etched. The conductive layer that becomes the gate electrode 148a and the electrode 148b can be formed by sputtering. It can be formed using PVD methods such as the evaporative deposition method, or CVD methods such as plasma CVD. The details are the same as those for the source electrode or drain electrode 142a, etc. These descriptions can be taken into consideration.

[0154] Next, an interlayer insulating layer is formed on the gate insulating layer 146, the gate electrode 148a, and the electrode 148b. 9(E) , the interlayer insulating layer 150 and the interlayer insulating layer 152 are formed. The interlayer insulating layer 152 can be formed by using a PVD method, a CVD method, or the like. silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, oxide It can be formed using a material containing an inorganic insulating material such as tantalum. In this embodiment, the interlayer insulating layer 150 and the interlayer insulating layer 152 are laminated together. One embodiment is not limited to this, and may be a single layer or a laminated structure of three or more layers. It is also possible to have a structure in which no interlayer insulating layer is provided.

[0155] It is desirable that the interlayer insulating layer 152 be formed so that its surface is flat. By forming the interlayer insulating layer 152 so that the surface is flat, it is possible to Even in such a case, electrodes, wiring, and the like can be suitably formed on the interlayer insulating layer 152. The interlayer insulating layer 152 can be planarized by a method such as CMP (chemical mechanical polishing). This can be done using the method.

[0156] Through the above steps, the transistor 162 including the highly purified oxide semiconductor layer 144 is completed. (See FIG. 9(E)). Also, the capacitor element 164 is completed.

[0157] The transistor 162 illustrated in FIG. 9E includes an oxide semiconductor layer 144 and an oxide semiconductor layer 14 4, a source electrode or drain electrode 142a electrically connected to the source electrode or drain electrode 142b. The oxide semiconductor layer 144, the source electrode or drain electrode 142a, and the a gate insulating layer 146 covering the source or drain electrode 142b; The capacitor element 164 has a source electrode or a drain electrode 148a. The source electrode 142a, the oxide semiconductor layer 144, and the source or drain electrode 142a A gate insulating layer 146 covering the oxide semiconductor layer 144 and an electrode 1 on the gate insulating layer 146 48b and

[0158] In the transistor 162 described in this embodiment, the oxide semiconductor layer 144 is highly purified. Therefore, the hydrogen concentration is 5×10 19 atoms / cm 3 Below, preferably 5x 10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 below The carrier density of the oxide semiconductor layer 144 is 1 / 2 times that of a general silicon wafer. The carrier density (1×10 14 / cm 3 A sufficiently small value (e.g., 1 x10 12 / cm 3 less than 1.45 x 10 10 / cm 3 (less than) This results in a sufficiently small off-state current. The off-state current (here, the value per unit channel width (1 μm)) is 100 zA / μm (1zA (zeptoampere) is 1 x 10 -21 A) or less, preferably 10zA / μm or less It becomes below.

[0159] By using the oxide semiconductor layer 144 that has been highly purified and made intrinsic, The off-state current of the transistor can be sufficiently reduced. This makes it possible to obtain a semiconductor device that can retain stored data for an extremely long period of time.

[0160] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0161] (Fourth embodiment) In this embodiment, a semiconductor device according to one embodiment of the disclosed invention, which is different from that in Embodiment 3, will be described. The structure and manufacturing method thereof will be described with reference to FIGS.

[0162] <Cross-sectional and planar configurations of semiconductor device> 10A and 10B show an example of the configuration of a semiconductor device. 10(B) shows a plan view of the semiconductor device. 10(A) and 10(B). The semiconductor device shown in FIG. 0(B) has a transistor using a semiconductor material other than an oxide semiconductor at the bottom. The semiconductor device has a transistor 160 and a transistor 162 using an oxide semiconductor thereon. The transistor 160 using a semiconductor material other than an oxide semiconductor has a higher conductivity than an oxide semiconductor material. By using a material with a higher field-effect mobility than that of a silicon nitride semiconductor, high-speed operation becomes possible. The transistor 162 using an oxide semiconductor material can hold charge for a long time due to its characteristics. It is possible.

[0163] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can also be used. The technical essence of the present invention is to use an oxide semiconductor as the transistor 162 to store data. The specific configuration of the semiconductor device does not need to be limited to that shown here. .

[0164] The transistor 160 in FIG. 10 is a substrate comprising a semiconductor material (e.g., silicon). The channel forming region 116 provided in the first electrode 100 and the second electrode 112 provided in the second electrode 100 are sandwiched between the channel forming region 116 and the second electrode 112. The impurity region 114 and the high concentration impurity region 120 (collectively referred to simply as the impurity region) a gate insulating layer 108a provided on the channel forming region 116; A gate electrode 110a provided on the gate insulating layer 108a and a gate electrode 110b electrically connected to the impurity region The source or drain electrode 130a and the source or drain electrode 130 Also, the source or drain electrode 130a and the source or drain electrode 130b are On the rain electrode 130b, there are a wiring 142c and a wiring 142d.

[0165] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110a. Also, when viewed from the direction perpendicular to the surface of the substrate 100, the sidewall insulating layer 118 is not overlapped. The lower region has a high-concentration impurity region 120, and a metal compound in contact with the high-concentration impurity region 120. The substrate 100 also has an element region 124 surrounding the transistor 160. An isolation insulating layer 106 is provided. An opening is provided on the gate electrode 110a and the transistor An interlayer insulating layer 126 and an interlayer insulating layer 128 are provided to cover the stator 160 . Source or drain electrode 130a and source or drain electrode 130b The metal compound region is exposed through the openings formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. The source or drain electrode 130a is electrically connected to the region 124. The source electrode or drain electrode 130b is formed by a high concentration of the metal compound region 124. The impurity region 120 is electrically connected to the impurity region 114. In some cases, the sidewall insulating layer 118 may not be formed due to the integration of the capacitor 160 or the like.

[0166] The transistor 162 in FIG. 10 has a source electrode or The drain electrode 142a and the source or drain electrode 142b are connected to the source electrode or drain electrode 142a, and the source or drain electrode 142b. The island-shaped oxide semiconductor layer 144 and the source or drain electrode 142 are connected to each other. a, a source electrode or a drain electrode 142b, and a gate electrode covering the island-shaped oxide semiconductor layer 144 The insulating layer 146 is formed on the gate insulating layer 146 so as to overlap with the island-shaped oxide semiconductor layer 144. and a gate electrode 148a.

[0167] Here, the lower transistor 160 and the upper transistor 162 are connected to the gate electrode 110a. The source electrode or drain electrode 142a is formed directly on the surface of the That is, the semiconductor device described in this embodiment has the same structure as the semiconductor device described in Embodiment 3. The upper part of the gate electrode 110a is removed, and the upper part of the transistor 160 is removed. An upper transistor 162 is formed.

[0168] Note that the oxide semiconductor layer 144 can be formed by sufficiently removing impurities such as hydrogen or by using a silicon dioxide gas. It is desirable that the oxygen gas be highly purified by supplying a sufficient amount of oxygen. Specifically, for example, the hydrogen concentration in the oxide semiconductor layer 144 is 5×10 19 atoms / cm 3 Below 5×10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 Note that the hydrogen concentration in the oxide semiconductor layer 144 is as follows: Secondary Ion Mass Spectroscopy (SIMS) As shown, the hydrogen concentration was sufficiently reduced and high purity was obtained. The defect level in the energy gap caused by oxygen deficiency is In the oxide semiconductor layer 144, the carrier concentration is reduced to 1×10 12 / cm 3 Less than desired Or 1×10 11 / cm 3 Less than 1.45 × 10 10 / cm 3 Less than and For example, the off-state current at room temperature (here, the value per unit channel width (1 μm)) is , 100zA / μm (1zA (zeptoampere) is 1×10 -21 A) The following is desirable: In this way, the i-type (intrinsic) or substantially i-type By using an oxide semiconductor, the transistor 162 can have excellent off-state current characteristics. It is possible.

[0169] The capacitor 164 includes a source electrode or a drain electrode 142a, an oxide semiconductor layer 144, a gate electrode 142b, and a gate insulating film 142c. The gate insulating layer 146 and the electrode 148b are the source or drain electrodes. The drain electrode 142a functions as one electrode of the capacitance element 164, and the electrode 148b functions as the capacitance element 164. This will function as the other electrode of the capacitor 164.

[0170] In the capacitor element 164 of FIG. 10, the oxide semiconductor layer 144 and the gate insulating layer 146 are stacked. By this, the insulation between the source electrode or drain electrode 142a and the electrode 148b is This allows for sufficient compatibility.

[0171] Note that in the transistor 162 and the capacitor 164, the source electrode or the drain electrode The ends of the electrode 142a and the source or drain electrode 142b are tapered. Here, the taper angle is preferably set to, for example, 30° or more and 60° or less. The taper angle is the angle at which a layer having a tapered shape (for example, a source electrode or a drain electrode) 42a) from a direction perpendicular to its cross section (a plane perpendicular to the surface of the substrate). The inclination angle between the side and bottom surfaces of the source electrode or drain electrode 142a, The end of the electrode 142b is tapered, so that the oxide semiconductor layer This is because the covering property of 144 can be improved and step disconnection can be prevented.

[0172] In addition, an interlayer insulating layer 150 is provided on the transistor 162 and the capacitor element 164. An interlayer insulating layer 152 is provided on the interlayer insulating layer 150 .

[0173] <Method for manufacturing semiconductor device> Next, an example of a method for manufacturing the semiconductor device will be described. The process after forming the transistor 160 and the method for manufacturing the upper transistor 162 are shown in FIG. The lower transistor 160 is formed in the same manner as in the third embodiment. The description in Embodiment 3 can be referred to.

[0174] First, the lower transistor 160 is formed by the method shown in the third embodiment, and then the transistor The upper part of the gate electrode 110a of the transistor 160 is removed (see FIG. 11(A)). The removal of the part of the transistor 160 is performed by removing the lower transistor 160 until the upper surface of the gate electrode 110a is exposed. This is done by performing a polishing process (CMP process) on the transistor 160. The interlayer insulating layers 126, 128, the source electrode or the drain electrode, which are located above the source electrode 110a, At this time, the interlayer insulating layers 126 and 128, the source electrode, and the like are removed. By planarizing the surface including the drain electrodes 130a and 130b, the following process can be performed. This makes it possible to form good electrodes, wiring, insulating layers, semiconductor layers, etc. The electrode 130c shown in the third embodiment is completely removed by this CMP process. There is no need to do so.

[0175] In this way, by performing the CMP process and exposing the upper surface of the gate electrode 110a, The gate electrode 110a and the source electrode or the drain electrode 142a can be directly connected. Therefore, the transistor 160 and the transistor 162 can be easily electrically connected. do.

[0176] Next, a conductive layer is formed on the interlayer insulating layers 126 and 128, and the conductive layer is selectively etched. The source or drain electrode 142a and the source or drain electrode 142b are Then, wirings 142c and 142d are formed (see FIG. 11(B)). The source or drain electrode 142a is connected to the gate electrode 110a, and the wiring 142c is connected to the source or drain electrode 142b. The line 142d is connected to the source or drain electrode 130b. and are formed so as to be directly connected to each other.

[0177] Here, the source or drain electrode 142a, the source or drain electrode 142 b, the conductive layer forming the wiring 142c and the wiring 142d is made of the same material as that shown in Embodiment 3. The following materials can be used, and the description in Embodiment 3 can be referred to. The etching can be performed in the same manner as in the third embodiment. The description in Form 3 can be taken into consideration.

[0178] As shown in the third embodiment, the source electrode or drain electrode 142a and the An insulating layer may be formed on the source electrode or the drain electrode 142b. By providing the gate electrode and the source or drain electrode 142 which will be formed later, a and the source or drain electrode 142b. It is Noh.

[0179] Next, the source or drain electrode 142a, the source or drain electrode 142b An oxide semiconductor layer is formed to cover the wiring 142c and the wiring 142d. The layer is selectively etched to form the source or drain electrode 142a and the source electrode The oxide semiconductor layer 144 is formed so as to be in contact with the electrode 142b (FIG. 11). (See (C)).

[0180] The oxide semiconductor layer is formed using the same material and method as those described in Embodiment 3. Therefore, for the material and the formation method of the oxide semiconductor layer, refer to Embodiment 3. You can pour drinks.

[0181] The oxide semiconductor layer thus formed can be etched using a mask or the like. The oxide semiconductor layer 144 is processed into an island shape.

[0182] The oxide semiconductor layer can be etched by either dry etching or wet etching. Of course, both of them can be used in combination. The etching conditions (etching gas, etc.) can be adjusted to suit the material so that the desired shape can be etched. The etching solution, etching time, temperature, etc. are set appropriately.

[0183] In addition, the oxide semiconductor layer 144 is formed by heat treatment (first heat treatment) as described in Embodiment 3. The first heat treatment can be performed by the method shown in the third embodiment. Embodiment 3 can be referred to. The first heat treatment reduces impurities and forms an i-type (true) By forming the oxide semiconductor layer 144 which is almost i-type, Note that the first heat treatment is performed on the oxide semiconductor The etching may be performed before etching the oxide semiconductor layer, or after etching the oxide semiconductor layer to form islands. You can go there.

[0184] Next, the gate insulating layer 146 is formed in contact with the oxide semiconductor layer 144 (see FIG. 11C). ).

[0185] The gate insulating layer 146 is formed using the same material and method as in the third embodiment. Therefore, the material and film formation method of the gate insulating layer 146 are as follows: Condition 3 can be taken into consideration.

[0186] After the gate insulating layer 146 is formed, as shown in the third embodiment, It is preferable to perform the second heat treatment in an oxygen atmosphere. The second heat treatment can be performed by the method shown in Embodiment 3, and the third embodiment can be referred to. By performing this process, it is possible to reduce variations in the electrical characteristics of the transistors. When the gate insulating layer 146 contains oxygen, oxygen is supplied to the oxide semiconductor layer 144, and the oxide semiconductor The oxygen deficiency in the conductor layer 144 is compensated for to form an i-type (intrinsic semiconductor) or an oxide as close to i-type as possible. A compound semiconductor layer can also be formed.

[0187] In this embodiment, the second heat treatment is performed after the gate insulating layer 146 is formed. The timing of the second heat treatment is not particularly limited to this. For example, the second heat treatment may be performed after the formation of the gate electrode. Alternatively, the second heat treatment may be performed after the first heat treatment. The first heat treatment may also serve as the second heat treatment, or the second heat treatment may also serve as the first heat treatment. It's okay to let them sleep.

[0188] Next, a gate electrode is formed on the gate insulating layer 146 in a region overlapping with the oxide semiconductor layer 144. 148a, and the electrode 148 is formed in the region overlapping with the source electrode or drain electrode 142a. The gate electrode 148a and the electrode 148b are formed as shown in FIG. After forming a conductive layer on the insulating layer 146, the conductive layer is selectively etched. The conductive layer that becomes the gate electrode 148a and the electrode 148b can be formed by Formed using PVD methods such as sputtering and CVD methods such as plasma CVD. The details are the same as those of the source electrode or drain electrode 142a. These descriptions can be taken into consideration.

[0189] Next, as shown in the third embodiment, the gate insulating layer 146, the gate electrode 148a, and Interlayer insulating layer 150 and interlayer insulating layer 152 are formed on electrode 148b. The insulating layer 50 and the interlayer insulating layer 152 are made of the same materials as those shown in the third embodiment. Therefore, the materials of the interlayer insulating layer 150 and the interlayer insulating layer 152 can be formed by the method. Embodiment 3 can be referred to for a deposition method.

[0190] It is desirable that the interlayer insulating layer 152 be formed so that its surface is flat. By forming the interlayer insulating layer 152 so that the surface is flat, it is possible to Even in such a case, electrodes, wiring, and the like can be suitably formed on the interlayer insulating layer 152. The interlayer insulating layer 152 can be planarized by a method such as CMP (chemical mechanical polishing). This can be done using the method.

[0191] Through the above steps, the transistor 162 including the highly purified oxide semiconductor layer 144 is completed. (See FIG. 10.) Furthermore, the capacitive element 164 is completed.

[0192] The transistor 162 illustrated in FIG. 10 includes an oxide semiconductor layer 144 and a The source electrode or drain electrode 142a, which is electrically connected to the source electrode or drain electrode The oxide semiconductor layer 144, the source or drain electrode 142a, the source electrode 142b, a gate insulating layer 146 covering the electrode or drain electrode 142b; The capacitor 164 has a source electrode or a drain electrode. The electrode 142a, the oxide semiconductor layer 144, and the source or drain electrode 142a are covered with the oxide semiconductor layer 144. The gate insulating layer 146 has a gate insulating layer 146a and an electrode 148b on the gate insulating layer 146.

[0193] In the transistor 162 described in this embodiment, the oxide semiconductor layer 144 is highly purified. Therefore, the hydrogen concentration is 5×10 19 atoms / cm 3 Below, preferably 5x 10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 below The carrier density of the oxide semiconductor layer 144 is 1 / 2 times that of a general silicon wafer. The carrier density (1×10 14 / cm 3 A sufficiently small value (e.g., 1 x10 12 / cm 3 less than 1.45 x 10 10 / cm 3 (less than) This results in a sufficiently small off-state current. The off-state current (here, the value per unit channel width (1 μm)) is 100 zA / μm (1zA (zeptoampere) is 1 x 10 -21 A) or less, preferably 10zA / μm or less It becomes below.

[0194] By using the oxide semiconductor layer 144 that has been highly purified and made intrinsic, The off-state current of the transistor can be sufficiently reduced. This makes it possible to obtain a semiconductor device that can retain stored data for an extremely long period of time.

[0195] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0196] (Embodiment 5) This embodiment relates to one mode of the disclosed invention, which is different from the third and fourth embodiments. The structure of the semiconductor device and a manufacturing method thereof will be described with reference to FIGS.

[0197] <Cross-sectional and planar configurations of semiconductor device> FIG. 4 shows an example of the configuration of a semiconductor device. FIG. 4(A) shows a cross section of the semiconductor device, and FIG. 4B) shows a plan view of the semiconductor device. Here, FIG. 4A shows the C of FIG. 4B. This corresponds to the cross section taken along lines C1-C2 and D1-D2. To avoid clutter, the source electrode or drain electrode 154, wiring 156, etc. Some of the components are omitted. The semiconductor device shown in FIGS. 4(A) and 4(B) includes: The transistor 160 includes a transistor using a semiconductor material other than an oxide semiconductor in the lower part, and the transistor 160 includes an oxide semiconductor in the upper part. The semiconductor device includes a transistor 162 using a semiconductor material other than an oxide semiconductor. The transistor 160 using this material has a higher field-effect mobility than that of an oxide semiconductor material. On the other hand, transistors using oxide semiconductor materials are The resistor 162 has a characteristic that allows it to retain charge for a long period of time.

[0198] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can also be used. The technical essence of the present invention is to use an oxide semiconductor as the transistor 162 to store data. The specific configuration of the semiconductor device does not need to be limited to that shown here. .

[0199] One of the differences between the semiconductor device shown in FIG. 4 and the semiconductor device shown in the previous embodiment is that 1 is a planar layout of the semiconductor device. In this embodiment, the transistor 162 and the capacitor element 164 is provided so as to overlap with the transistor 160. By adopting the out, high integration is possible. For example, if the minimum processing dimension is F, , the area occupied by the memory cell is 15F 2 ~25F 2 It is possible to do so.

[0200] Another difference between the semiconductor device shown in FIG. 4 and the semiconductor device shown in the previous embodiment is that The presence or absence of the sidewall insulating layer 118 in the transistor 160. The semiconductor device shown does not have a sidewall insulating layer. As a result, the impurity region 114 is not formed. When the wall insulating layer is not provided, the concentration is lower than when the sidewall insulating layer 118 is provided. Furthermore, compared to the case where the sidewall insulating layer 118 is provided, the manufacturing process is simpler. It is possible to simplify the process.

[0201] Another difference between the semiconductor device shown in FIG. 4 and the semiconductor device shown in the previous embodiment is that The presence or absence of the interlayer insulating layer 125 in the transistor 160. The semiconductor device has an interlayer insulating layer 125. The interlayer insulating layer 125 is an insulating layer containing hydrogen. By applying this, hydrogen is supplied to the transistor 160, and the characteristics of the transistor 160 are Such an interlayer insulating layer 125 can be, for example, a plasma The interlayer insulating layer 1 may be a silicon nitride layer containing hydrogen formed by a CVD method. 26, the characteristics of the transistor 162 can be improved by using an insulating layer in which hydrogen is sufficiently reduced. This makes it possible to prevent hydrogen, which may deteriorate the performance, from entering the transistor 162. Such an interlayer insulating layer 126 may be, for example, a nitride silicon layer formed by sputtering. By adopting such a configuration, the transistor 160 and the transistor The characteristics of the transistor 162 can be sufficiently improved.

[0202] Another difference between the semiconductor device shown in FIG. 4 and the semiconductor device shown in the previous embodiment is that The presence or absence of the insulating layer 143a and the insulating layer 143b in the transistor 162. The semiconductor device shown in FIG. 4 has an insulating layer 143a and an insulating layer 143b. As shown, by providing the insulating layer 143a and the insulating layer 143b, the gate electrode 148a and the , the source electrode or drain electrode 142a (or the gate electrode 148a and the source electrode or drain electrode 142b) to reduce the so-called gate capacitance, 62 operating speed can be improved.

[0203] As in the fourth embodiment, the lower transistor 160 and the upper transistor 162 are The source electrode or drain electrode 142a is formed directly on the gate electrode 110a. By using such a configuration, it is possible to achieve a high level of reliability compared to the case where electrodes and wiring are provided separately. In comparison, the degree of integration is improved and the manufacturing process is simplified.

[0204] In this embodiment, the configuration in which the above-mentioned differences are integrated is shown. A configuration having only one of the above may be adopted.

[0205] <Method for manufacturing semiconductor device> Next, an example of a method for manufacturing the semiconductor device will be described. The process after forming the capacitor 160 and the method for fabricating the upper transistor 162 are shown in FIGS. The description will be made with reference to FIG. 6. The lower transistor 160 is the same as that shown in Embodiment 3. For details, see the description of Embodiment 3. In this embodiment, an interlayer insulating layer 125 is formed to cover the transistor 160. Three types of interlayer insulating layers are formed: an interlayer insulating layer 126, an interlayer insulating layer 128 ( 8G). In this embodiment, in the manufacturing process of the transistor 160, Forming a source or drain electrode 130a and a source or drain electrode 130b However, the source electrode or drain electrode 130a and the source electrode Alternatively, even if the drain electrode 130b is not formed, the transistor may be formed for convenience. Let's call it 160.

[0206] First, the lower transistor 160 is formed by the method shown in the third embodiment, and then the transistor The upper part of the gate electrode 110a of the film 160 is removed. By this, the surface of the gate electrode 110a is polished. The interlayer insulating layers 125, 126, and 128 above the surface are removed. By sufficiently flattening the surface by polishing, it is possible to obtain a good electrode in the subsequent process. It is possible to form wiring, insulating layers, semiconductor layers, etc.

[0207] Next, the gate electrode 110a, the interlayer insulating layer 125, the interlayer insulating layer 126, and the interlayer insulating layer 128 are a conductive layer is formed on the surface of the semiconductor substrate, and the conductive layer is selectively etched to form a source electrode or a drain electrode. 142a and a source or drain electrode 142b are formed (see FIG. 5(A)). The source electrode or drain electrode 142a is directly connected to the gate electrode 110a. It forms a sea urchin.

[0208] Forming a source or drain electrode 142a and a source or drain electrode 142b The conductive layer for this purpose can be formed using the same material as that shown in Embodiment Mode 3. The conductive layer can be etched in the same manner as in the third embodiment. For details, the description of embodiment 3 can be referred to. .

[0209] Next, the source or drain electrode 142a, the source or drain electrode 142b An insulating layer is formed to cover the source electrode or the drain electrode, and the insulating layer is selectively etched. An insulating layer 143a is formed on the source or drain electrode 142a, and an insulating layer 143b is formed on the source or drain electrode 142b. An insulating layer 143b is formed on each of the insulating layers 143a and 143b (see FIG. 5B).

[0210] By providing the insulating layers 143a and 143b, the gate electrode to be formed later can be formed. , between the source electrode or drain electrode 142a and the gate electrode to be formed later. and the source electrode or drain electrode 142b, it is possible to reduce the parasitic capacitance between the do.

[0211] Next, the source or drain electrode 142a, the source or drain electrode 142b An oxide semiconductor layer 144 is formed to cover the gate insulating layer 1 46 is formed (see FIG. 5(C)).

[0212] The oxide semiconductor layer 144 can be formed using the material and the method described in Embodiment 3. The oxide semiconductor layer 144 is preferably subjected to heat treatment (first heat treatment). For details, please refer to the description in embodiment 3.

[0213] The gate insulating layer 146 can be formed using the material and the method described in Embodiment 3. After the gate insulating layer 146 is formed, the gate insulating layer 146 is heated in an inert gas atmosphere or an oxygen atmosphere. For details, please refer to the description of the third embodiment. It is possible.

[0214] Next, a region to be a channel formation region of the transistor 162 is formed on the gate insulating layer 146. A gate electrode 148a is formed in a region overlapping the source electrode or drain electrode 142. An electrode 148b is formed in the region overlapping with a (see FIG. 5(D)).

[0215] The gate electrode 148a and the electrode 148b are formed by forming a conductive layer on the gate insulating layer 146. The gate electrode can be formed by selectively etching the conductive layer. The conductive layers that become the electrodes 148a and 148b can be formed by PVD methods such as sputtering, It can be formed by using a CVD method such as a plasma CVD method. The same applies to the case of the drain electrode 142a, etc., and the descriptions therefor can be taken into consideration.

[0216] Next, an interlayer insulating layer is formed on the gate insulating layer 146, the gate electrode 148a, and the electrode 148b. 150 and an interlayer insulating layer 152 are formed (see FIG. 6(A)). The interlayer insulating layer 152 can be formed using the materials and the method described in Embodiment 3. For details, please refer to the description in embodiment 3.

[0217] It is desirable that the interlayer insulating layer 152 be formed so that its surface is flat. By forming the interlayer insulating layer 152 so that the surface is flat, it is possible to Even in such a case, electrodes, wiring, and the like can be suitably formed on the interlayer insulating layer 152. The interlayer insulating layer 152 can be planarized by a method such as CMP (chemical mechanical polishing). This can be done using the method.

[0218] Next, the interlayer insulating layer 125, the interlayer insulating layer 126, the interlayer insulating layer 128, and the oxide semiconductor layer 144 , the gate insulating layer 146, the interlayer insulating layer 150, and the interlayer insulating layer 152 are selectively etched. , an opening is formed that reaches the metal compound region 124 of the transistor 160 (FIG. 6(B) For etching, either dry etching or wet etching can be used. However, from the viewpoint of miniaturization, it is preferable to use dry etching.

[0219] Then, the source electrode or drain electrode 154 is formed so as to fill the opening. Then, a wiring 156 is formed to connect to the source electrode or drain electrode 154 (FIG. 6( See C).

[0220] The source electrode or drain electrode 154 is formed by, for example, PVD or CVD in the area including the opening. After forming a conductive layer using a method such as etching or CMP, It can be formed by removing a part of the conductive layer. A thin titanium film is formed on the area including the mouth by the PVD method, and a thin titanium nitride film is formed on the area by the CVD method. After forming the opening, a tungsten film is formed so as to fill the opening. Here, the titanium film formed by the PVD method does not form an oxide film (natural oxide film) on the surface on which it is formed. and the like) to reduce the contact resistance with the lower electrode and the like (here, the metal compound region 124). In addition, the titanium nitride film formed afterwards suppresses the diffusion of the conductive material. It also has a barrier function that prevents the formation of a barrier film made of titanium or titanium nitride. Alternatively, the copper film may be formed by plating.

[0221] The wiring 156 is formed by forming a conductive layer in contact with the source electrode or drain electrode 154. The conductive layer can be formed by selectively etching the conductive layer. It is formed using PVD methods such as sputtering and CVD methods such as plasma CVD. The details are the same as those for the source electrode or drain electrode 142a. do.

[0222] As a result, a semiconductor device including the transistor 160, the transistor 162, and the capacitor 164 is formed. The conductor device is completed.

[0223] In the semiconductor device described in this embodiment, the transistor 162 and the capacitor 164 are The transistor 160 has a structure overlapping the sidewall insulating layer. The absence of an edge layer and the presence of a source electrode or drain electrode 142a on the gate electrode 110a High integration is possible because the device is directly formed on the substrate. It has been turned into

[0224] In addition, in the semiconductor device described in this embodiment, an insulating layer containing hydrogen is used as the interlayer insulating layer 125. By applying an insulating layer in which hydrogen is sufficiently reduced as the interlayer insulating layer 126, The characteristics of the transistor 160 and the transistor 162 are improved. By providing the insulating layer 143b, the so-called gate capacitance is reduced, and the transistor The operating speed of the controller 162 has been improved.

[0225] The above-described features of the present embodiment provide a semiconductor device with extremely excellent characteristics. is possible.

[0226] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0227] (Sixth embodiment) In this embodiment, when the semiconductor device described in the above embodiment is applied to an electronic device, This will be described with reference to FIG. 12. In this embodiment, telephones, mobile phone devices), portable information terminals (including portable game consoles and audio playback devices) digital cameras, digital video cameras, electronic paper, television equipment (television The semiconductor device described above is applied to electronic devices such as a television receiver. This section explains the case where

[0228] FIG. 12A shows a notebook personal computer, which includes a housing 701, a housing 702, The display unit 703, the keyboard 704, etc. The semiconductor device described in the above embodiment is provided inside the memory cell. It has high speed readout, long-term memory retention, and sufficiently low power consumption. A notebook-type personal computer is realized.

[0229] FIG. 12B shows a personal digital assistant (PDA), and a main body 711 includes a display unit 713 and an external An external interface 715, operation buttons 714, etc. are provided. The main body 711 is provided with a stylus 712 for operating the terminal. Therefore, writing and reading of information can be performed at high speed. A portable information terminal capable of long-term memory retention and sufficiently reduced power consumption is realized. .

[0230] FIG. 12C shows an electronic book 720 equipped with electronic paper. The electronic book 720 has a housing 721 and a housing 722. The display unit 721 and the display unit 723 are configured as two housings. 25 and a display unit 727 are provided. The housing 721 and the housing 723 are connected by a shaft portion 737. The housing 7 is connected to the shaft 737, and can be opened and closed around the shaft 737. 21 includes a power supply 731, operation keys 733, a speaker 735, etc. At least one of the housings 723 is provided with the semiconductor device described in the above embodiment. Therefore, information can be written and read at high speed, can be stored for a long period of time, and can be erased. This allows for the realization of an electronic book with significantly reduced power consumption.

[0231] FIG. 12D shows a mobile phone that is composed of two housings, a housing 740 and a housing 741. Furthermore, the housing 740 and the housing 741 slide and unfold as shown in FIG. 12(D). The two can be folded into an overlapping state, making them compact and suitable for portability. The housing 741 also includes a display panel 742, a speaker 743, a microphone 744, a pointing device, and a The camera includes a viewing device 746, a camera lens 747, and an external connection terminal 748. The housing 740 also includes a solar cell 749 for charging the mobile phone, an external memory slot, and The antenna is built into the housing 741. At least one of the housing 741 and the housing 40 is provided with the semiconductor device described in the previous embodiment. Therefore, information can be written and read at high speed, and long-term storage is possible. A mobile phone with sufficiently reduced power consumption is realized.

[0232] FIG. 12(E) shows a digital camera, which includes a main body 761, a display unit 767, an eyepiece unit 763, and an operation unit. It is composed of an operation switch 764, a display unit 765, a battery 766, etc. The semiconductor device described in the above embodiment is provided in the memory 761. High speed writing and reading, long-term memory retention, and low power consumption A digital camera having such a configuration is realized.

[0233] FIG. 12F shows a television device 770, which includes a housing 771, a display portion 773, a stand, and the like. The television device 770 is operated by a switch provided in the housing 771. This can be done using a switch or a remote control 780. The semiconductor device described in the above embodiment is mounted on the device 780. High speed writing and reading, long-term memory retention, and low power consumption A reduced television set is realized.

[0234] As described above, the electronic device described in this embodiment mode is equipped with the semiconductor device according to the above embodiment. This allows for the realization of electronic devices with reduced power consumption. [Example]

[0235] The number of times that a semiconductor device according to one embodiment of the disclosed invention can be rewritten was investigated. The survey results will now be explained with reference to FIG.

[0236] The semiconductor device used in the investigation has a circuit configuration shown in FIG. The transistor corresponding to the transistor 162 is formed using an oxide semiconductor. The capacitance element used had a capacitance value of 0.33 pF.

[0237] The investigation involves setting the initial memory window width and repeating the retention and writing of information a predetermined number of times. This is done by comparing the memory window width after the data is returned. The write operation is performed by applying 0V or 5V to the wiring corresponding to the third wiring in FIG. 1(A-1). Apply either 0V or 5V to the wire corresponding to the fourth wire. When the potential of the wiring corresponding to the fourth wiring is 0V, the transistor 162 Since the transistor (write transistor) corresponding to If the potential of the wiring corresponding to the fourth wiring is 5V, Since the transistor corresponding to the transistor 162 is in the ON state, the third wiring The potential of the wiring is applied to node FG.

[0238] The memory window width is one of the indicators that show the characteristics of a memory device. Between the states, the potential Vcg of the wiring corresponding to the fifth wiring and the potential Vcg of the wiring corresponding to the transistor 160 The curve (V The difference between the memory states is the shift amount ΔVcg of the memory state (cg-Id curve). The state where 0V is applied to FG (hereinafter referred to as the Low state) and the state where 5V is applied to node FG are In other words, the memory window width is This can be confirmed by sweeping the potential Vcg in the low and high states.

[0239] Figure 13 shows the memory window width in the initial state and the 9 After writing The horizontal axis in Figure 13 represents Vcg (V). The vertical axis shows Id(A). 9 Before and after writing, It can be seen that the memory window width has not changed. 9 Before and after writing The fact that the memory window width remains unchanged means that the semiconductor device will This indicates that there is no deterioration.

[0240] As described above, the semiconductor device according to one embodiment of the disclosed invention can store and write data in 10 9 Even if the rewriting is repeated many times, the characteristics do not change and the rewriting durability is extremely high. According to one embodiment of the present invention, a highly reliable semiconductor device can be realized. [Example]

[0241] In this example, the off-state current of a transistor including a highly purified oxide semiconductor was measured. Explain the results.

[0242] In this example, a transistor is fabricated using a highly purified oxide semiconductor according to Embodiment 3. First, we fabricated a transistor using a highly purified oxide semiconductor. Considering that the channel width W is small, we prepare a transistor with a sufficiently large channel width W of 1 m. The off-state current was measured. The result of measuring the off-state current of a transistor with a channel width W of 1 m This is shown in Figure 14. In Figure 14, the horizontal axis represents the gate voltage VG and the vertical axis represents the drain current ID. When the drain voltage VD is +1V or +10V, the gate voltage VG is -5V to -2V. In the 0V range, the off-state current of the transistor is 1×10, which is the detection limit. -13 A or below In addition, the off-state current of the transistor (here, the unit channel width (1 μm ) is 1aA / μm (1×10 -18 A / μm or less.

[0243] Next, we aimed to more accurately determine the off-state current of a transistor using a highly purified oxide semiconductor. As described above, the transistor using the highly purified oxide semiconductor The off-state current of the transistor is 1×10, which is the detection limit of the measuring instrument. -13 It turns out that it is below A. Therefore, we fabricated a device for characteristic evaluation to obtain a more accurate value of the off-state current (measured in the above measurement). The results of the calculation (values ​​below the detection limit of the detector) are explained below.

[0244] First, the characteristic evaluation element used in the current measurement method will be described with reference to FIG.

[0245] The characteristic evaluation element shown in FIG. 15 has three measurement systems 800 connected in parallel. 0 represents the capacitor element 802, the transistor 804, the transistor 805, and the transistor 806. , and transistor 808. The transistor manufactured according to the third embodiment was used for the transistor 806 .

[0246] In the measurement system 800, one of the source terminal and the drain terminal of the transistor 804, One of the terminals of the capacitor 802 and the source terminal and drain terminal of the transistor 805 One end is connected to a power supply (the power supply that provides V2). the other of the source and drain terminals of the transistor 808 One of the terminals of the capacitor 802, the other terminal of the capacitor 802, and the gate terminal of the transistor 805 are connected to each other. The other of the source terminal and the drain terminal of the transistor 808 is connected to the One of the source terminal and the drain terminal of the transistor 806 and the gate of the transistor 806 The output terminal of the transistor 805 is connected to a power supply (the power supply that provides V1). the other of the source and drain terminals of the transistor 806 The other terminal is connected to form an output terminal Vout.

[0247] The gate terminal of the transistor 804 is connected to a resistor R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R A potential Vext_b2 that controls the state of the transistor 808 is supplied to the gate terminal of the transistor 808. A potential Vext_b1 that controls the on and off states of the transistor 808 is supplied. Furthermore, the potential Vout is output from the output terminal.

[0248] Next, a current measurement method using the above measurement system will be described.

[0249] First, an outline of the initialization period during which a potential difference is applied to measure the off-state current will be described. During the initialization period, the gate terminal of the transistor 808 is connected to the transistor 808. A potential Vext_b1 is input to the source terminal or drain of the transistor 804. a node connected to the other of the input terminals (i.e., the source terminal and the drain terminal of the transistor 808) One of the drain terminals, the other terminal of the capacitor 802, and the gate terminal of the transistor 805 A potential V1 is applied to node A, which is a node connected to a child. For example, the potential is set to high. The transistor 804 is kept in an off state.

[0250] Then, a potential that turns off the transistor 808 is applied to the gate terminal of the transistor 808. Vext_b1 is input to turn off the transistor 808. After turning off the transistor 804, the potential V1 is set to a low potential. The potential V2 is set to the same potential as the potential V1. When the initialization period is over, the node A and the source voltage of the transistor 804 A potential difference is generated between one of the electrode and drain electrodes of the transistor 808. A potential difference occurs between the source electrode and the drain electrode of the transistor. A small amount of charge flows through the transistor 804 and the transistor 808. In other words, an off-current occurs. do.

[0251] Next, an outline of the measurement period of the off-state current will be described. The potential of one of the source terminal or drain terminal of 804 (i.e., V2) and The potential of the other terminal of the source terminal or the drain terminal of the transistor 808 (i.e., V1) is On the other hand, during the measurement period, the potential of the node A is not fixed (floor As a result, charge flows through the transistor 804, and over time, The amount of charge held at node A changes. In other words, the output potential Vout of the output terminal also fluctuates. do.

[0252] The details of the relationship between the potentials during the initialization period in which the above potential difference is applied and the subsequent measurement period are as follows: The timing chart is shown in FIG.

[0253] In the initialization period, first, the potential Vext_b2 is set to the ON state by the transistor 804. This sets the potential of node A to V2, that is, a low potential ( VSS). After that, the potential Vext_b2 is set to Vext_b1 when the transistor 804 is turned off. The transistor 804 is turned off by applying a voltage (low potential) to the transistor 804. The potential Vext_b1 is set to a potential (high potential) that turns on the transistor 808. This causes the potential of node A to become V1, i.e., the high potential (VDD). The potential Vext_b1 is set to a potential that turns off the transistor 808. As a result, node A goes into a floating state, and the initialization period ends.

[0254] In the subsequent measurement period, charges flow into node A, causing potentials V1 and V2 to Or, the potential is set so that charge flows out from node A. Here, the potential V1 and the potential V 2 is the low potential (VSS). However, at the timing when the output potential Vout is measured, In this case, it is necessary to operate the output circuit, so V1 is temporarily set to a high potential (VDD). The period when V1 is at a high potential (VDD) should be short enough so as not to affect the measurement. The period.

[0255] As described above, when a potential difference is applied and the measurement period begins, the voltage at node A increases over time. The amount of charge held changes, and the potential at node A changes accordingly. This means that the potential of the gate terminal of the transistor 805 fluctuates, so over time, the output The potential of the output potential Vout of the terminal also changes.

[0256] A method for calculating the off-state current from the obtained output potential Vout will be described below.

[0257] Before calculating the off-state current, the relationship between the potential VA of node A and the output potential Vout is calculated. This allows the potential VA of node A to be calculated from the output potential Vout. From the above relationship, the potential VA of node A can be expressed as a function of the output potential Vout as follows: It is possible.

[0258]

number

[0259] The charge QA at node A is calculated by the potential VA of node A, the capacitance CA connected to node A, and the constant Using a constant, it is expressed as follows: CA is the sum of the capacitance of the capacitive element 802 and other capacitances.

[0260]

number

[0261] The current IA at node A is the sum of the charge flowing into (or out of) node A. Since it is a time derivative, the current IA at node A can be expressed as follows:

[0262]

number

[0263] In this way, the capacitance CA connected to node A and the output potential Vout of the output terminal The current IA of the diode A can be calculated.

[0264] By using the method described above, the leakage current flowing between the source and drain of the transistor in the off state can be reduced. The off-state current (off current) can be measured.

[0265] In this example, a highly purified oxide film having a channel length L=10 μm and a channel width W=50 μm was used. A transistor 804, a transistor 805, a transistor 806, and a transistor 807 are formed using a compound semiconductor. In each of the paralleled measurement systems 800, a capacitance element 802 The capacitance values ​​of the capacitive element 802a, 802b, and 802c are set to 100 fF and The capacitance of the capacitance element 802b is set to 1 pF, and the capacitance of the capacitance element 802c is set to 3 pF.

[0266] In the measurement according to this embodiment, VDD=5V and VSS=0V. In this case, the potential V1 is set to VSS as a rule, and the voltage is increased by 100 msec every 10 to 300 sec. Vout was measured as VDD for the period c. The time Δt was set to approximately 30,000 seconds.

[0267] FIG. 17 shows the relationship between the elapsed time Time in the current measurement and the output potential Vout. From FIG. 17, it can be seen that the potential changes over time.

[0268] Figure 18 shows the off-state current calculated by the above current measurement. 18 shows the relationship between the source-drain voltage V and the off-state current I. At an on-voltage of 4 V, the off-current was found to be approximately 40 zA / μm at room temperature. In addition, under the condition of a source-drain voltage of 3.1 V, the off-state current was 10 zA at room temperature. / μm or less. -21 Represents A.

[0269] As described above, in this example, in a transistor using a highly purified oxide semiconductor, It was confirmed that the flow was sufficiently small. [Explanation of symbols]

[0270] 100 boards 102 Protective layer 104 Semiconductor Area 106 Element isolation insulating layer 108a Gate insulating layer 110a gate electrode 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulating layer 120 High concentration impurity region 122 Metal layer 124 Metal compound area 125 Interlayer insulation layer 126 Interlayer insulation layer 128 Interlayer Insulation Layer 130a Source electrode or drain electrode 130b Source electrode or drain electrode 130c electrode 142a Source electrode or drain electrode 142b Source electrode or drain electrode 143a Insulating layer 143b Insulating layer 144 Oxide semiconductor layer 146 Gate insulating layer 148a Gate electrode 148b Electrode 150 Interlayer insulation layer 152 Interlayer insulation layer 154 Source or drain electrode 160 transistors 162 transistors 164 Capacitor 701 Case 702 Case 703 Display section 704 keyboard 711 Main Unit 712 Stylus 713 Display section 714 Operation Button 715 external interface 720 e-books 721 Case 723 Case 725 Display section 727 Display section 731 Power supply 733 Operation Key 735 Speaker 737 Shaft 740 chassis 741 Case 742 Display Panel 743 Speaker 744 microphone 746 Pointing Device 747 Camera Lens 748 External connection terminal 749 Solar Cells 750 external memory slot 761 Main Unit 763 Eyepiece 764 Operation Switch 765 Display section 766 Battery 767 Display section 770 Television Equipment 771 Case 773 Display section 775 Stand 780 Remote Controlled Machine 802 Capacitor element 802a Capacitive element 802b Capacitive element 802c Capacitive Element 804 transistor 805 transistor 806 Transistor 808 Transistor

Claims

[Claim 1] a memory cell including a first transistor, a second transistor, and a capacitor; the first transistor and the second transistor comprise different semiconductor materials; the second transistor includes an oxide semiconductor; writing information to the memory cell is performed by supplying a first potential to a node to which one of a source electrode or a drain electrode of the second transistor, one of the electrodes of the capacitor element, and a gate electrode of the first transistor are electrically connected, and then turning off the second transistor; Without supplying power, the information is ４ A semiconductor device capable of maintaining a temperature for more than 1000 s.

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