Chip electronic components

Abstract

To provide a chip electronic component that is difficult to be charged even when housed in a carrier tape. [Solution] A chip electronic component CE1 includes an element body 3 including a main surface 3a constituting a mounting surface, a main surface 3b opposite to the main surface 3a, and side surfaces 3c adjacent to the main surface 3a and the main surface 3b, and an external electrode 5 including an electrode portion 5a arranged on the main surface 3a. The main surface 3b is exposed from the external electrode 5 and has a surface roughness that is greater than the surface roughness of the main surface 3a and greater than the surface roughness of the side surfaces 3c.

Description

[Technical Field]

[0001] The present invention relates to chip electronic components. [Background technology]

[0002] A known chip electronic component includes an element body and external electrodes disposed on the element body. The element body includes, for example, a first main surface constituting a mounting surface, a second main surface opposite the first main surface, and side surfaces adjacent to the first and second main surfaces. The external electrodes include electrode portions disposed on the first main surface. The second main surface is exposed from the external electrodes. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2024-003627 Summary of the Invention [Problem to be solved by the invention]

[0004] The chip electronic components are transported, for example, in the form of an electronic component package. The electronic component package includes a plurality of chip electronic components, a carrier tape, and a cover tape. The carrier tape has a plurality of cavities in which the plurality of chip electronic components are housed. The cover tape covers the opening of each cavity. The chip electronic components are housed in the cavities so that the first main surface faces the bottom surface of the cavity. After the chip electronic components are housed in the cavities, the cover tape is bonded to the carrier tape so that the cover tape covers the opening of the cavity. When a chip electronic component is mounted on an electronic device, the cover tape is peeled off from the carrier tape, and the chip electronic component is picked up from the carrier tape. The second main surface is attracted to a nozzle of a mounter. The chip electronic component picked up by the mounter is placed at a predetermined position on the electronic device so that the first main surface faces the electronic device. The electronic device includes, for example, a circuit board or an electronic component.

[0005] An object of one aspect of the present invention is to provide a chip electronic component that is resistant to static electricity even when housed in a carrier tape. [Means for solving the problem]

[0006] As a result of research and study, the present inventors have newly discovered the following information regarding charging of chip electronic components. In the chip electronic component contained in the electronic component package, the second main surface faces the cover tape. The second main surface is exposed from the external electrode. The second main surface is likely to come into contact with the cover tape. For example, when the chip electronic component is transported, the chip electronic component may move within the cavity with the second main surface in contact with the cover tape. In this case, static electricity is likely to be generated, and there is a risk that the chip electronic component (element) may become charged. For example, static electricity may be generated when the cover tape is peeled off from the carrier tape, which may also cause the chip electronic component (element) to become charged.

[0007] The static electricity of the chip electronic component can cause defective mounting of the chip electronic component as follows. For example, when the cover tape is peeled off from the carrier tape, the charged chip electronic components adhere to the cover tape and are carried away from the cavities, in which case the chip electronic components cannot be mounted in an electronic device. For example, when the cover tape is peeled off from the carrier tape, the charged chip electronic component may rotate within the cavity as the cover tape is peeled off. In this case, the orientation of the chip electronic component within the cavity changes. If the orientation of the chip electronic component within the cavity changes, the second main surface cannot be attracted to the nozzle. If a surface other than the second main surface is attracted to the nozzle, the chip electronic component cannot be mounted on the electronic device so that the first main surface and the electronic device face each other. If the mounter cannot pick up the chip electronic component, the chip electronic component cannot be mounted on the electronic device.

[0008] The present inventors have further investigated and researched chip electronic components that are difficult to charge, and as a result, have newly obtained the following findings. Even when the second main surface comes into contact with the cover tape, static electricity is unlikely to be generated if the second main surface has a surface roughness greater than that of the first main surface and greater than that of the side surface. In other words, with this configuration, charging of the chip electronic component is unlikely to occur.

[0009] The present inventors have come up with the following idea based on newly obtained knowledge about charging of chip electronic components. A chip electronic component according to one embodiment comprises an element body including a first main surface constituting a mounting surface, a second main surface opposite the first main surface, and side surfaces adjacent to the first and second main surfaces, and an external electrode including an electrode portion disposed on the first main surface. The second main surface is exposed from the external electrode and has a surface roughness greater than that of the first main surface and greater than that of the side surfaces. [Effects of the Invention]

[0010] One aspect of the present invention provides a chip electronic component that is resistant to static buildup even when housed in a carrier tape. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a perspective view of a chip electronic component according to one embodiment. [Figure 2] FIG. 2 is a diagram showing a cross-sectional configuration of the chip electronic component according to this embodiment. [Figure 3] FIG. 3 is a diagram showing a cross-sectional configuration of the chip electronic component according to this embodiment. [Figure 4] FIG. 4 is a diagram showing a cross-sectional structure of an electronic component packaging body. [Figure 5] FIG. 5 is a diagram showing a cross-sectional structure of an electronic component packaging body. [Figure 6] FIG. 6 is a diagram showing a cross-sectional configuration of the electronic component device. [Figure 7]FIG. 7 is a diagram showing a cross-sectional configuration of the electronic component device. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same elements or elements having the same functions will be denoted by the same reference numerals, and redundant description will be omitted.

[0013] (chip electronic components) The configuration of a chip electronic component CE1 according to this embodiment will be described with reference to Figures 1 to 3. Figure 1 is a perspective view of the chip electronic component according to this embodiment. Figures 2 and 3 are views showing the cross-sectional configuration of the chip electronic component according to this embodiment. The chip electronic component CE1 includes, for example, a coil component.

[0014] The chip electronic component CE1 includes an element body 3 and a plurality of external electrodes 5. The chip electronic component CE1 includes, for example, a pair of external electrodes 5. The pair of external electrodes 5 are arranged on the outer surface of the element body 3. The pair of external electrodes 5 are spaced apart from each other. The element body 3 has a rectangular parallelepiped shape. The rectangular parallelepiped shape may include a rectangular parallelepiped shape with chamfered corners and edges, or a rectangular parallelepiped shape with rounded corners and edges.

[0015] The outer surface of the element body 3 includes a pair of opposing main surfaces 3a, 3b and a plurality of side surfaces 3c. Each of the main surfaces 3a, 3b and each of the side surfaces 3c has, for example, a rectangular shape. The plurality of side surfaces 3c include a pair of opposing side surfaces 3c1 and a pair of opposing side surfaces 3c2. The chip electronic component CE1 is solder-mounted to an electronic device. The electronic device includes, for example, a circuit board or another electronic component. In the chip electronic component CE1, the main surface 3a faces the electronic device. The main surface 3a is arranged to form a mounting surface. The main surface 3a is the mounting surface. For example, when the main surface 3a includes a first main surface, the main surface 3b includes a second main surface.

[0016] The pair of main surfaces 3a, 3b face each other in direction D1. The pair of side surfaces 3c1 face each other in direction D2. The pair of side surfaces 3c2 face each other in direction D3. Directions D1, D2, and D3 are substantially perpendicular to each other. The pair of side surfaces 3c1 extend in direction D1 to connect the pair of main surfaces 3a, 3b. The pair of side surfaces 3c1 extend in direction D3 to connect the pair of side surfaces 3c2. The pair of side surfaces 3c2 extend in direction D1 to connect the pair of main surfaces 3a, 3b. The pair of side surfaces 3c2 extend in direction D2 to connect the pair of side surfaces 3c1.

[0017] The length of element body 3 in direction D2 is, for example, greater than the length of element body 3 in direction D1 and greater than the length of element body 3 in direction D3. Direction D2 is the longitudinal direction of element body 3. The length of element body 3 in direction D1 and the length of element body 3 in direction D3 may be equal to each other. The length of element body 3 in direction D1 and the length of element body 3 in direction D3 may be different from each other. The length of element body 3 in direction D1 is the height of element body 3. The length of element body 3 in direction D2 is the length of element body 3. The length of element body 3 in direction D3 is the width of element body 3. The length of element body 3 is 0.4 mm or less, the width of element body 3 is 0.2 mm or less, and the height of element body 3 is 0.2 mm or less. For example, the length of element body 3 is 0.4 mm, the width of element body 3 is 0.2 mm, and the height of element body 3 is 0.2 mm.

[0018] The chip electronic component CE1 is 0402 size in JIS notation. The chip electronic component CE1 is 01005 size in EIA notation. The length of the element body 3 may be 0.2 mm, the width of the element body 3 may be 0.1 mm, and the height of the element body 3 may be 0.1 mm. In other words, the chip electronic component CE1 may be 0201 size in JIS notation. The chip electronic component CE1 may be 008004 size in EIA notation.

[0019] The element body 3 may include ridges located between each of the main surfaces 3a, 3b and the side surface 3c, and ridges located between the side surface 3c1 and the side surface 3c2. For example, each ridge may be rounded to be curved. The element body 3 may be subjected to so-called R-chamfering. Each of the main surfaces 3a, 3b and the side surface 3c may be indirectly adjacent to each other via a ridge located between each of the main surfaces 3a, 3b and the side surface 3c. The side surface 3c1 and the side surface 3c2 may be indirectly adjacent to each other via a ridge located between the side surface 3c1 and the side surface 3c2.

[0020] The element body 3 includes, for example, an element body made of resin. The element body 3 may also include an element body made of only resin. The element body 3 includes, for example, a plurality of element body layers. The plurality of element body layers are stacked, for example, in direction D1. In an actual element body 3, the plurality of element body layers may be integrated to the extent that the boundaries between the layers are not visible, or may be integrated so that the boundaries between the layers are visible. Each element layer includes a resin material. The resin material includes, for example, at least one selected from liquid crystal polymer, polyimide resin, crystalline polystyrene, epoxy resin, acrylic resin, bismaleimide resin, and fluororesin. Each element layer may include a filler in addition to the resin material. The filler includes, for example, an inorganic filler. The inorganic filler includes, for example, silica (SiO2). Each element layer may not include a filler. The element body 3 may be optically transparent. The element body 3 may be transparent or translucent to visible light.

[0021] The pair of external electrodes 5 are arranged on the main surface 3a. The pair of external electrodes 5 include electrode portions 5a arranged on the main surface 3a. The pair of external electrodes 5 may include only the electrode portions 5a. The pair of external electrodes 5 are spaced apart from each other in direction D2. The pair of external electrodes 5 may also be spaced apart from each other in direction D3. Each external electrode 5 has, for example, a rectangular shape when viewed in direction D1. The outline of each external electrode 5, i.e., the outline of each electrode portion 5a, may include a pair of sides that face each other and extend along direction D2, and another pair of sides that face each other and extend along direction D3.

[0022] Each external electrode 5 (each electrode portion 5a) includes a surface 5s exposed from the main surface 3a. The surface 5s is, for example, flush with the main surface 3a. Each external electrode 5 does not protrude from the main surface 3a. The surface 5s is included in an imaginary plane including the main surface 3a. Each external electrode 5 is disposed in a recess formed in the main surface 3a. Except for the surface 5s, each external electrode 5 is located within the element body 3. The surface of each external electrode 5 is covered by the element body 3 except for the surface 5s. The surface 5s may be spaced apart in the direction D1 from the imaginary plane including the main surface 3a. For example, a portion of each external electrode 5, including the surface 5s, may protrude from the element body 3.

[0023] Each external electrode 5 includes a conductive material, such as Ag, Pd, Cu, or Al, or may include an Ag-Pd alloy, an Ag-Cu alloy, an Ag-Au alloy, or an Ag-Pt alloy. A plating film (not shown) may be disposed on the surface 5s of each external electrode 5. The plating film is formed, for example, by electrolytic plating or electroless plating. The plating film includes, for example, a Ni plating film, a Sn plating film, a Cu plating film, or an Au plating film. The plating film may have a multi-layer structure. For example, the plating film may include a Ni plating layer and an Au plating layer. The Ni plating layer is formed on the surface 5s. The Au plating layer is formed on the Ni plating layer. The Au plating layer covers the Ni plating layer.

[0024] The principal surface 3b is exposed from the pair of external electrodes 5. The pair of external electrodes 5 are not arranged on the principal surface 3b. Each external electrode 5 does not include an electrode portion arranged on the principal surface 3b. The principal surface 3b is not covered by the pair of external electrodes 5. The entire principal surface 3b is exposed from the pair of external electrodes 5. Each external electrode 5 may include an electrode portion disposed on a corresponding one of the pair of side surfaces 3c2. Each external electrode 5 may include an electrode portion disposed on each of the pair of side surfaces 3c1. The electrode portion 5a may be continuous with the electrode portion disposed on the side surface 3c2 and the electrode portion disposed on each of the pair of side surfaces 3c1.

[0025] The chip electronic component CE1 includes an internal conductor (not shown). In a configuration in which the chip electronic component CE1 includes a coil component, the internal conductor includes, for example, multiple coil conductors electrically connected to each other. In a configuration in which the chip electronic component CE1 includes a capacitor component, the internal conductor includes, for example, multiple internal electrodes facing each other. Even in a configuration in which the chip electronic component CE1 includes a piezoelectric component, a varistor component, or a thermistor component, the internal conductor includes, for example, multiple internal electrodes facing each other. As described above, the internal conductor includes, for example, multiple coil conductors or multiple internal electrodes. Internal conductors are known in this technical field, and detailed description will be omitted. In addition to the above-mentioned electronic components, the chip electronic component CE1 may also include composite components such as filter components or solid-state battery components.

[0026] The surface roughness of the outer surface of the element body 3 will be described with reference to Figures 2 and 3. Figures 2 and 3 include enlarged views of a portion of the element body 3. The main surface 3b has a surface roughness that is greater than that of the main surface 3a and greater than that of the side surface 3c. The surface roughness of the main surface 3a is smaller than that of the side surface 3c. The surface roughness of the main surface 3a is determined by the surface roughness of the area of ​​the main surface 3a that is exposed from the external electrode 5. The main surface 3b having a large surface roughness can be realized, for example, by polishing the main surface 3b. In this case, the main surface 3b includes a polished surface. Polishing the main surface 3b includes, for example, grind-polishing the main surface 3b. The magnitude of the surface roughness of the main surface 3b can be adjusted, for example, by controlling the grind roughness. The main surface 3a may include, for example, a polished surface, and the side surface 3c may include, for example, a cut surface.

[0027] (Electronic component packaging) The configuration of the electronic component packaging EP will be described with reference to Figures 4 and 5. Figures 4 and 5 are diagrams showing the cross-sectional configuration of the electronic component packaging. In Figures 4 and 5, hatching indicating a cross section is omitted. The electronic component packaging body EP includes a plurality of chip electronic components CE1, a carrier tape 20, and a cover tape 30. The carrier tape 20 and the cover tape 30 include long or strip-shaped members. The carrier tape 20 has a plurality of cavities 21. The plurality of cavities 21 are provided at predetermined intervals along the longitudinal direction of the carrier tape 20. Each cavity 21 has an opening. The cover tape 30 is disposed on the carrier tape 20 so as to cover the multiple cavities 21. The opening of each cavity 21 is covered by the cover tape 30. The cover tape 30 is joined to the carrier tape 20 so as to be releasable from the carrier tape 20.

[0028] Each chip electronic component CE1 is accommodated in a corresponding cavity 21 among the plurality of cavities 21. Each chip electronic component CE1 is inserted into the corresponding cavity 21 through the opening of the corresponding cavity 21. Each chip electronic component CE1 is removed from the cavity 21 through the opening of the corresponding cavity 21. Each chip electronic component CE1 is accommodated in a corresponding cavity 21 such that its main surface 3a faces the bottom surface of the corresponding cavity 21. The main surface 3b faces the opening of the corresponding cavity 21. The main surface 3b is configured within the carrier tape 20 so as to include a surface facing the opening of the cavity 21. Each chip electronic component CE1 is accommodated in a corresponding cavity 21 such that its main surface 3b includes a surface facing the opening of the corresponding cavity 21.

[0029] Each of the multiple chip electronic components CE1 included in the electronic component packaging EP is picked up by, for example, a nozzle of a mounter and removed from the corresponding cavity 21. The main surface 3b is sucked onto the nozzle. The chip electronic component CE1 removed from the corresponding cavity 21 is placed at a predetermined position on the electronic device by the mounter with the main surface 3b still sucked onto the nozzle. The chip electronic component CE1 is placed on the electronic device so that the main surface 3a faces the electronic device. The chip electronic component CE1 placed on the electronic device is mounted to the electronic device by, for example, soldering. The electronic device includes, for example, a circuit board or an electronic component.

[0030] The main surface 3b of the chip electronic component CE1 included in the electronic component packaging EP faces the cover tape 30. The main surface 3b is exposed from the external electrodes 5. The main surface 3b is likely to come into contact with the cover tape 30. For example, when the electronic component packaging EP (chip electronic component CE1) is transported, the chip electronic component CE1 may move within the cavity 21 with the main surface 3b in contact with the cover tape 30. In this case, static electricity is likely to be generated, and there is a risk that the chip electronic component CE1 (element body 3) may become charged. For example, static electricity may be generated when the cover tape 30 is peeled off from the carrier tape 20. In this case as well, the chip electronic component CE1 (element body 3) may become charged.

[0031] The charging of the chip electronic component CE1 can cause defective mounting of the chip electronic component CE1 as follows. For example, when the cover tape 30 is peeled off from the carrier tape 20, the charged chip electronic component CE1 adheres to the cover tape 30 and is carried away from the cavity 21. In this case, the chip electronic component CE1 cannot be mounted in an electronic device. For example, when the cover tape 30 is peeled off from the carrier tape 20, the electrically charged chip electronic component CE1 may rotate within the cavity 21 as the cover tape 30 is peeled off. When the chip electronic component CE1 rotates within the cavity 21, the orientation of the chip electronic component CE1 within the cavity 21 changes. When the orientation of the chip electronic component CE1 within the cavity 21 changes, the main surface 3b cannot be attracted to the nozzle. If a surface other than the main surface 3b is attracted to the nozzle, the chip electronic component CE1 cannot be mounted on the electronic device so that the main surface 3a faces the electronic device. If the mounter cannot pick up the chip electronic component CE1, the chip electronic component CE1 cannot be mounted on the electronic device.

[0032] As described above, in the chip electronic component CE1, the main surface 3b exposed from the external electrodes 5 has a surface roughness greater than that of the main surface 3a and greater than that of the side surfaces 3c. A configuration in which the surface roughness of the main surface 3b is greater than that of each of the main surface 3a and the side surfaces 3c reduces the contact area between the main surface 3b and the cover tape 30 compared to a configuration in which the surface roughness of the main surface 3b is smaller than that of each of the main surface 3a and the side surfaces 3c. Therefore, even when the chip electronic component CE1 moves within the cavity 21 with the main surface 3b in contact with the cover tape 30, static electricity is unlikely to be generated. As a result, the chip electronic component CE1 (element body 3) is unlikely to be charged.

[0033] The element body 3 includes an element body made of resin. Elements made of resin have a significant tendency to become charged. However, in the chip electronic component CE1, the surface roughness of the main surface 3b is greater than the surface roughness of the main surface 3a and the side surface 3c. Therefore, even when the chip electronic component CE1 is housed in the carrier tape 20, the chip electronic component CE1 (element body 3) is unlikely to become charged.

[0034] Chip electronic components CE1 that are 0402 size or smaller are lighter than chip electronic components CE1 that are larger than 0402 size. Therefore, chip electronic components CE1 that are 0402 size or smaller are more likely to cause mounting defects. However, in the chip electronic component CE1, the surface roughness of the main surface 3b is greater than the surface roughness of the main surface 3a and the side surface 3c, so the chip electronic component CE1 is less likely to become charged and less likely to cause mounting defects.

[0035] The electronic component packaging EP includes a plurality of chip electronic components CE1. Each chip electronic component CE1 is accommodated in the cavity 21 with the main surface 3b facing the opening of the cavity 21. In the electronic component packaging body EP, there is a risk that the main surface 3b may come into contact with the cover tape 30. However, each chip electronic component CE1 has a configuration in which the surface roughness of the main surface 3b is greater than the surface roughness of each of the main surface 3a and the side surface 3c, so that even if the main surface 3b comes into contact with the cover tape 30, the chip electronic component CE1 (element body 3) is unlikely to be charged.

[0036] (Electronic component equipment) The configuration of the electronic component device will be described with reference to Figures 6 and 7. Figures 6 and 7 are diagrams showing the cross-sectional configuration of the electronic component device. The electronic component device includes, for example, a plurality of chip electronic components CE1, an electronic device ED, and an encapsulant SL. The electronic device ED is, for example, a circuit board or an electronic component. Each chip electronic component CE1 is solder-mounted to the electronic device ED. Although two chip electronic components CE1 are shown in FIG. 6, the electronic component device may include a plurality of chip electronic components CE1 arranged in a matrix. The electronic device ED includes a main surface EDa and a plurality of pad electrodes PE. Each pad electrode PE is arranged on the main surface EDa. The plurality of pad electrodes PE are spaced apart from each other. Each chip electronic component CE1 is arranged on the electronic device ED so that the main surface 3a and the main surface EDa face each other. Corresponding external electrodes 5 and pad electrodes PE are connected via solder fillets SF. The distance between the main surface 3a and the main surface EDa is, for example, 20 to 30 μm. The distance between adjacent chip electronic components CE1 is, for example, 50 to 80 μm. The distance between the main surface 3a and the main surface EDa is smaller than the distance between adjacent chip electronic components CE1.

[0037] The sealing material SL seals a plurality of chip electronic components CE1 mounted on the electronic device ED. The sealing material SL covers each chip electronic component CE1. The sealing material SL protects each chip electronic component CE1. The sealing material SL has electrical insulating properties. The sealing material SL includes, for example, a resin material. The resin material includes, for example, a silicone resin or an epoxy resin. The sealing material SL is formed, for example, using a molding method or a potting method. The encapsulating material SL includes portions located between adjacent chip electronic components CE1 and portions located between each chip electronic component CE1 and the electronic device ED. The portions located between adjacent chip electronic components CE1 contact each side surface 3c of the adjacent chip electronic components CE1. The portions located between adjacent chip electronic components CE1 are formed by hardening a resin material placed between the side surfaces 3c of the adjacent chip electronic components CE1. The portions located between each chip electronic component CE1 and the electronic device ED contact each main surface 3a and the main surface EDa. The portions located between each chip electronic component CE1 and the electronic device ED are formed by hardening a resin material placed between each main surface 3a and the main surface EDa.

[0038] As described above, in the chip electronic component CE1, the surface roughness of the main surface 3b is greater than the surface roughness of the main surface 3a and the side surface 3c. That is, the surface roughness of the main surface 3a and the side surface 3c is smaller than the surface roughness of the main surface 3b. In a configuration in which the surface roughness of each of the main surface 3a and the side surface 3c is smaller than that of the main surface 3b, the resin material before hardening is more likely to enter between adjacent chip electronic components CE1 and between the chip electronic component CE1 and the electronic device ED than in a configuration in which the surface roughness of each of the main surface 3a and the side surface 3c is larger than that of the main surface 3b. Therefore, in a configuration in which the surface roughness of each of the main surface 3a and the side surface 3c is smaller than that of the main surface 3b, the sealing material SL reliably seals each chip electronic component CE1.

[0039] In the chip electronic component CE1, the main surface 3a has a surface roughness that is smaller than the surface roughness of the side surface 3c. In the electronic component device, the distance between the main surface 3a and the main surface EDa is smaller than the distance between adjacent chip electronic components CE1. Therefore, the resin material before hardening is less likely to enter between the chip electronic component CE1 and the electronic device ED than between adjacent chip electronic components CE1. In a configuration in which the surface roughness of the main surface 3a is smaller than that of the side surface 3c, the resin material before hardening is more likely to enter between the chip electronic component CE1 and the electronic device ED than in a configuration in which the surface roughness of the main surface 3a is larger than that of the side surface 3c. Therefore, in a configuration in which the surface roughness of the main surface 3a is smaller than that of the side surface 3c, the sealing material SL is reliably disposed between the chip electronic component CE1 and the electronic device ED.

[0040] (Pickup test) The surface roughness of the main surface 3b will be described. The present inventors conducted a pickup test to clarify the surface roughness of the main surface 3b. In this pickup test, the present inventors prepared samples S1 and S2 with different surface roughnesses of the main surface 3b and determined the pickup rate for each sample S1 and S2. Each sample S1 and S2 is a lot containing multiple specimens. Each sample S1 and S2 has the same configuration as the chip electronic component CE1, except for the different surface roughnesses of the main surface 3b. In this pickup test, the surface roughness is defined as the arithmetic mean height Sa. The arithmetic mean height Sa is defined in "ISO 25178 Surface Texture (Surface Roughness Measurement)." In sample S1, the arithmetic mean height Sa of the main surface 3b is 0.4 μm. In sample S2, the arithmetic mean height Sa of the main surface 3b is 0.2 μm.

[0041] For each of samples S1 and S2, electronic device packages containing a plurality of specimens were prepared. The plurality of specimens were housed in a plurality of cavities with the main surfaces 3b facing the openings of the cavities. Using a mounter, each specimen was picked up from the electronic component packaging and placed consecutively on a test board. The test board included a number of electrode pads corresponding to the number of specimens to be placed on the test board. Solder paste was applied to each electrode pad. In this pickup test, 10,000 specimens were picked up from the electronic component packaging and placed on the test board. The number of specimens placed with their main surfaces 3a facing the test substrate was counted, and the pickup rate was calculated as a percentage by dividing the counted number by 10,000.

[0042] The pick-up rate for sample S1 was 98.35%, and the pick-up rate for sample S2 was 44.44%. When the electronic component package of sample S2 was inspected, a specimen was found attached to the cover tape peeled from the carrier tape. When the specimens of sample S2 picked up by the mounter were inspected, a specimen was found in which a portion other than the main surface 3b was adsorbed by the nozzle. Specimens in which a portion other than the main surface 3b was adsorbed by the nozzle include, for example, specimens in which the side surface 3c was adsorbed by the nozzle, or specimens in which the edge portion of the element body 3 was adsorbed by the nozzle. In contrast, in sample S1, no specimen was found to be attached to the cover tape, and no specimen was found to have any part other than the main surface 3b adsorbed to the nozzle. Based on the results of the pickup test, it is estimated that sample S1 is less likely to be charged than sample S2, even when housed in a carrier tape.

[0043] A configuration in which the arithmetic mean height Sa of the main surface 3b is 0.4 μm or more reliably prevents charging of the chip electronic component CE1 (element body 3).

[0044] Although the embodiments of the present invention have been described above, the present invention is not necessarily limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present invention.

[0045] As can be understood from the above description of the embodiments, the present specification includes disclosure of the following aspects. (Appendix 1) an element body including a first main surface constituting a mounting surface, a second main surface opposite to the first main surface, and side surfaces adjacent to the first main surface and the second main surface; an external electrode including an electrode portion disposed on the first main surface, The second main surface is exposed from the external electrode and has a surface roughness that is greater than the surface roughness of the first main surface and greater than the surface roughness of the side surface. (Appendix 2) 2. The chip electronic component according to claim 1, wherein the second main surface has an arithmetic mean height Sa of 0.4 μm or more. (Appendix 3) 3. The chip electronic component according to claim 1, wherein the surface roughness of the first main surface is smaller than the surface roughness of the side surface. (Appendix 4) 4. The chip electronic component according to any one of claims 1 to 3, wherein the element body includes an element body made of resin. (Appendix 5) 5. The chip electronic component according to claim 1, which is 0402 size or smaller. (Appendix 6) 6. The chip electronic component according to any one of appendices 1 to 5, wherein the second main surface is configured to include a surface facing an opening of a cavity in the carrier tape. (Appendix 7) A chip electronic component according to any one of appendices 1 to 6; a carrier tape having a cavity in which the chip electronic component is accommodated; a cover tape that covers the opening of the cavity, An electronic component packaging body, wherein the chip electronic component is accommodated in the cavity such that the second main surface includes a surface facing the opening of the cavity. [Explanation of symbols]

[0046] 3...element body, 3a, 3b...main surfaces, 3c...side surface, 5...external electrode, 5a...electrode portion, 20...carrier tape, 21...cavity, 30...cover tape, CE1...chip electronic component, EP...electronic component packaging body.

Claims

1. an element body including a first main surface constituting a mounting surface, a second main surface opposite to the first main surface, and side surfaces adjacent to the first main surface and the second main surface; an external electrode including an electrode portion disposed on the first main surface, The second main surface is exposed from the external electrode and has a surface roughness that is greater than the surface roughness of the first main surface and greater than the surface roughness of the side surface.

2. 2. The chip electronic component according to claim 1, wherein the second main surface has an arithmetic mean height Sa of 0.4 μm or more.

3. The chip electronic component according to claim 1 , wherein the surface roughness of the first main surface is smaller than the surface roughness of the side surface.

4. 2. The chip electronic component according to claim 1, wherein the element body includes an element body made of resin.

5. The chip electronic component according to claim 1 , which is 0402 size or smaller.

6. The chip electronic component according to claim 1 , wherein the second main surface is configured to include a surface facing an opening of a cavity in the carrier tape.

7. The chip electronic component according to any one of claims 1 to 6, a carrier tape having a cavity in which the chip electronic component is accommodated; a cover tape that covers the opening of the cavity, An electronic component packaging body, wherein the chip electronic component is accommodated in the cavity such that the second main surface includes a surface facing the opening of the cavity.

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