Printed circuit board

Abstract

The present invention provides a printed circuit board that can be applied to large bodies, is easy to control for warping, and yet can improve signal and / or power paths to enhance signal and / or power characteristics. [Solution] This disclosure relates to a printed circuit board comprising a glass layer, a cavity penetrating a portion of the glass layer from the upper surface of the glass layer, an interconnect unit comprising at least a portion disposed within the cavity and including a plurality of first through-vias penetrating a polymer layer and the polymer layer, respectively, and a plurality of second through-vias penetrating the glass layer from the lower surface of the glass layer to the bottom surface of the cavity, wherein the plurality of first through-vias are each connected to the plurality of second through-vias.

Description

Technical Field

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[0001] The present disclosure relates to a printed circuit board.

Background Art

[0002] To achieve high performance in products for high performance computing (HPC) such as servers, artificial intelligence (AI), and networks, the body size of packages has been increasing, and the number of layers has also been increasing. In this case, it may be difficult to control the warpage of the substrate. In response, it is possible to consider applying a thicker core, but when the core becomes thicker, the signal path and power path may also become longer. Therefore, the signal and power characteristics may deteriorate.

Summary of the Invention

Problems to be Solved by the Invention

[0003] One of the various objectives of the present disclosure is to provide a printed circuit board that can be applied to large bodies, is easy to control warpage, and yet can improve signal and / or power paths to enhance signal and / or power characteristics.

Means for Solving the Problems

[0004] One of the various solutions proposed through the present disclosure is to form a blind-shaped cavity in a glass core, arrange an interconnect unit including a first through-via with a fine pitch in such a cavity, and also form a second through-via with a fine pitch that penetrates the glass core and is connected to the first through-via below such a cavity, thereby forming an electrical path having a fine pitch and a fine size in a specific region of the glass core.

[0005] For example, a printed circuit board according to one example includes a glass layer, a cavity penetrating a portion of the glass layer from its upper surface, an interconnect unit comprising at least a portion of a polymer layer and a plurality of first through-vias penetrating the polymer layer, and a plurality of second through-vias penetrating the glass layer from its lower surface to the bottom surface of the cavity, wherein the plurality of first through-vias may be connected to the plurality of second through-vias.

[0006] For example, a printed circuit board according to one example may include: a glass core having a blind cavity; an interconnect unit, at least a portion of which is disposed within the blind cavity; a plurality of second through-vias that penetrate the glass core in a region overlapping with the blind cavity when viewed through the glass core from above; a plurality of third through-vias that penetrate the glass core in a region separated from the blind cavity when viewed through the glass core from above; a first build-up structure disposed above the glass core and including a plurality of first wiring layers; and a second build-up structure disposed below the glass core and including a plurality of second wiring layers. [Effects of the Invention]

[0007] One of the various effects of this disclosure is the ability to provide a printed circuit board that can be applied to large bodies, allows for easy warp control, and yet improves signal and / or power paths to enhance signal and / or power characteristics. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram illustrating an example of an electronic equipment system. [Figure 2] This is a schematic cross-sectional view showing an example of a printed circuit board. [Figure 3] Figure 2 is a schematic process diagram showing an example of the manufacturing process of a printed circuit board. [Figure 4] This is a schematic cross-sectional view showing a modified example of the printed circuit board shown in Figure 2. [Figure 5] This is a schematic cross-sectional view showing another example of a printed circuit board. [Figure 6] This is a schematic cross-sectional view showing a modified example of the printed circuit board shown in Figure 5. [Figure 7] This is a schematic cross-sectional view showing yet another example of a printed circuit board. [Figure 8] This is a schematic cross-sectional view showing a modified example of the printed circuit board in Figure 7. [Modes for carrying out the invention]

[0009] The disclosure will be described below with reference to the attached drawings. The shapes and sizes of elements in the drawings may be enlarged or reduced (or highlighted or simplified) for clearer explanation.

[0010] Figure 1 is a block diagram illustrating an example of an electronic equipment system.

[0011] Referring to the drawing, the electronic device 1000 houses a main board 1010. The main board 1010 is physically and / or electrically connected to chip-related components 1020, network-related components 1030, and other components 1040, etc. These are also coupled with other electronic components, which will be described later, to form various signal lines 1090.

[0012] Chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPUs), graphics processors (e.g., GPUs), digital signal processors, cryptographic processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Furthermore, these chip-related components 1020 can be combined with each other. Chip-related components 1020 can also be in the form of a package containing the aforementioned chips and electronic components.

[0013] Network-related component 1030 includes, but is not limited to, any other wireless and wired protocols designated as Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth®, 3G, 4G, 5G, and later. It may also include any other numerous wireless or wired standards and protocols. Furthermore, network-related component 1030 can be combined with chip-related component 1020.

[0014] Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCCs (low-temperature co-firing ceramics), EMI (electromagnetic interference) filters, and MLCCs (multi-layer ceramic condensers). However, they are not limited to these, and may also include passive elements in the form of chip components used for various other applications. Furthermore, other components 1040 can be combined with chip-related components 1020 and / or network-related components 1030.

[0015] Depending on the type of electronic device 1000, it may include other electronic components that are physically and / or electrically connected to the main board 1010, or not connected. Examples of other electronic components include a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. However, it is not limited to these, and may also include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), CDs (compact disks), DVDs (digital versatile disks), etc. In addition, depending on the type of electronic device 1000, it may also include other electronic components used for various purposes.

[0016] Electronic device 1000 can be a smartphone, personal digital assistant, digital video camera, digital still camera, network system, computer, monitor, tablet, laptop, netbook, television, video game, smartwatch, automobile, etc. However, it is not limited to these, and can also be any other electronic device that processes data.

[0017] Figure 2 is a schematic cross-sectional view showing an example of a printed circuit board.

[0018] Referring to the drawings, an example printed circuit board 500A may include a glass layer 110, a cavity C penetrating a portion of the glass layer 110 from its upper surface, an interconnect unit 200 located at least a portion within the cavity C and including a plurality of first through-vias 231, and a plurality of second through-vias 132 each penetrating the glass layer 110 from its lower surface to the bottom of the cavity C. The plurality of first through-vias 231 can each be connected to the plurality of second through-vias 132.

[0019] Thus, since the printed circuit board 500A includes the glass layer 110, it can be easily applied to a large body and can be effective in warpage control. Also, an interconnect unit 200 including a plurality of first through vias 231 is disposed in the cavity C, and a plurality of second through vias 132 respectively connected to the plurality of first through vias 231 are disposed below such a cavity C. At this time, since the plurality of first and second through vias 231, 132 can be formed with a fine pitch and a fine size, even when the thickness of the glass layer 110 is considerable, an electrical path having a fine pitch and a fine size can be provided in a specific region. Therefore, signals and / or power paths transmitted from semiconductor chips or the like that can be mounted on the printed circuit board 500A can be improved. Therefore, signal and / or power characteristics can be improved. Also, since the separately manufactured interconnect unit 200 is used, the yield can also be improved.

[0020] On the other hand, the cavity C can have a blind form that penetrates a part of the glass layer 110 from the upper surface to the lower surface of the glass layer 110. For example, the cavity C can be a blind cavity C. The interconnect unit 200 can be attached to the bottom surface of such a blind cavity C via an adhesive layer 250. At this time, the plurality of second through vias 132 can further penetrate the adhesive layer 250 respectively, and thus can be easily connected to the plurality of first through vias 231 respectively. For example, the plurality of second through vias 132 can be formed as via holes that penetrate the glass layer 110 and the adhesive layer 250 in one go from the lower surface of the glass layer 110 to the interconnect unit 200, and can have a substantially tapered form in which the width on the cross section of the lower end portion is wider than the width on the cross section of the upper end portion.

[0021] On the one hand, the number of cavities C and interconnect units 200 can each be plural. For example, a plurality of cavities C can be formed in the glass layer 110 spaced apart from each other, and a plurality of interconnect units 200 can be respectively arranged in the plurality of cavities C. Also, a plurality of second through vias 132 can be arranged below each of the plurality of cavities C. However, it is not limited to this, and if necessary, a plurality of interconnect units 200 can also be arranged in any at least one blind cavity C.

[0022] On the other hand, the interconnect unit 200 can include a polymer layer 211 and a plurality of first through vias 231 penetrating the polymer layer 211 respectively. For example, the interconnect unit 200 can be an organic substrate. Therefore, it can be manufactured by a relatively simple process and the cost can be effectively reduced. Also, since the polymer layer 211 can have a relatively thin thickness, it can be easier to make the fine pitch and fine size of the plurality of first through vias 231.

[0023] On the other hand, the interconnect unit 200 can further include a plurality of first pads 221 respectively arranged below the polymer layer 211 and respectively connected to the lower sides of the plurality of first through vias 231, a plurality of second pads 222 respectively arranged above the polymer layer 211 and respectively connected to the upper sides of the plurality of first through vias 231, a first passivation layer 212 arranged below the polymer layer 211 and covering at least a part of the plurality of first pads 221, and / or a second passivation layer 213 arranged above the polymer layer 211 and covering at least a part of the plurality of second pads 222. For example, the interconnect unit 200 can be a two-layer organic substrate, but is not limited to this. The plurality of second through vias 132 can be respectively connected to the plurality of first through vias 231 through the plurality of first pads 221.

[0024] On the other hand, the printed circuit board 500A may further include a plurality of third through vias 133 that penetrate between the upper and lower surfaces of the glass layer 110 in a region separated from the region where the cavity C is located. The plurality of third through vias 133 may be TGVs (Through Glass Vias) corresponding to the total thickness of the glass layer 110. In this case, the minimum pitch between the plurality of first through vias 231 and the minimum pitch between the plurality of second through vias 132 may each be smaller than the minimum pitch between the plurality of third through vias 133. Furthermore, the minimum diameter of each of the plurality of first through vias 231 and the minimum diameter of each of the plurality of second through vias 132 may each be smaller than the minimum diameter of each of the plurality of third through vias 133. Therefore, it is possible to more easily provide electrical paths with fine pitch and fine size in a specific region of the glass layer 110.

[0025] On the other hand, the pitch between multiple through vias can be the distance between the centerlines of any two adjacent through vias, and the minimum pitch between multiple through vias can be the smallest of these pitches. Also, the diameter of each of the multiple through vias can be measured on a cross-section cut along the central axis of the through via in the thickness direction, and the minimum diameter can be the smallest of these diameters.

[0026] On the one hand, when the glass layer 110 is viewed from above, the multiple second through-vias 132 can each penetrate the glass layer 110 in the region overlapping with the cavity C. On the other hand, when the glass layer 110 is viewed from above, the multiple third through-vias 133 can each penetrate the glass layer 110 in the region separated from the cavity C. Therefore, it is possible to more easily provide electrical paths with fine pitch and fine size in specific regions of the glass layer 110.

[0027] On the other hand, the printed circuit board 500A may further include a plurality of third pads 123, each positioned on the lower surface of the glass layer 110 and connected to the underside of each of the plurality of second through vias 132; a plurality of fourth pads 124, each positioned on the upper surface of the glass layer 110 and connected to the upperside of each of the plurality of third through vias 133; and / or a plurality of fifth pads 125, each positioned on the lower surface of the glass layer 110 and connected to the underside of each of the plurality of third through vias 133. Through these, electrical connection reliability can be further improved. If necessary, conductive patterns for various applications can be formed on the upper and / or lower surfaces of the glass layer 110 in addition to the plurality of third to fifth pads 123, 124, and 125.

[0028] The components of a printed circuit board 500A will be described in more detail below, with reference to the drawings.

[0029] The glass layer 110 may include glass, which is an amorphous solid. Examples of glass include pure silicon dioxide (approximately 100% SiO2), soda-lime glass, borosilicate glass, and aluminosilicate glass. However, it is not limited to these; alternative glass materials, such as fluoroglass, phosphate glass, and chalcogenide glass, can also be used. Furthermore, other additives may be included to form glass with specific physical properties. Such additives may include not only calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), but also magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, as well as carbonates and / or oxides of these elements and other elements. The glass layer 110 may be distinct from organic insulating materials containing glass fibers (Glass Fiber, Glass Cloth, Glass Fabric), such as CCL (Copper Clad Laminate) and PPG (Prepreg). For example, the glass layer 110 can include a glass panel that can be made to cover a large area, such as a glass plate.

[0030] The multiple second and third through vias 132, 133 can each contain a metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, it can contain copper (Cu), but is not limited thereto. The multiple second and third through vias 132, 133 can each contain a filled via that fills the through hole, for example, a TGV (Through Glass Via). The multiple second and third through vias 132, 133 can perform various functions depending on the design. For example, they can include ground through vias, power through vias, signal through vias, etc. The multiple second through vias 132 can each have a substantially tapered shape in cross-section. The multiple third through vias 133 can each have a substantially hourglass shape in cross-section. Multiple second and third through vias 132, 133 may each include a sputtering layer as a seed layer, and the via holes may be substantially filled with an electroplated layer. The sputtering layer may be a multilayer structure including a titanium (Ti) layer and a copper (Cu) layer. The electroplated layer may be a copper (Cu) layer formed of electrolytic copper. However, it is not limited to this, and an electroless plating layer may also be formed as a seed layer, and both a sputtering layer and an electroless plating layer may be formed as a seed layer if necessary.

[0031] Each of the third to fifth pads 123, 124, and 125 can contain a metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, it can contain copper (Cu), but is not limited to this. Each of the third to fifth pads 123, 124, and 125 can perform various functions depending on the design. For example, it can include signal pads, power pads, ground pads, etc. Each of the third to fifth pads 123, 124, and 125 can contain a sputtering layer as a seed layer, and can also contain an electroplated layer placed on the seed layer. The sputtering layer can be a multilayer structure containing a titanium (Ti) layer and a copper (Cu) layer. The electroplated layer can be a copper (Cu) layer formed of electrolytic copper. However, this is not the only option; an electroless plating layer can also be formed in the seed layer, and both a sputtering layer and an electroless plating layer can be formed as the seed layer if necessary.

[0032] The polymer layer 211 may contain an organic insulating material. The organic insulating material may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or inorganic and / or organic fillers together with these resins. For example, the polymer layer 211 may contain ABF (Ajinomoto Build-up Film). However, it is not limited to this, and the organic insulating material may further contain glass fiber (glass cloth, glass fabric). For example, the polymer layer 211 may also be CCL (copper clad laminate), PPG (prepreg), etc. The polymer layer 211 may be a single layer, but may also consist of multiple layers as needed.

[0033] The first and second passivation layers 212 and 213 may each contain a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or inorganic and / or organic fillers together with these resins. For example, the first and second passivation layers 212 and 213 may each contain, but are not limited to, ABF (Ajinomoto Build-up Film) and SR (Solder Resist). The first and second passivation layers 212 and 213 may each expose a plurality of first and second pads 221 and 222, and may, if necessary, each have a plurality of openings in the form of SMD (Solder Mask Defined) and / or NSMD (Non Solder Mask Defined).

[0034] Each of the multiple first through vias 231 may contain a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, it may contain, but is not limited to, copper (Cu). Each of the multiple first through vias 231 may contain a filled via that fills the through hole. The multiple first through vias 231 can perform various functions depending on the design. For example, they may include power through vias, signal through vias, etc. Each of the multiple first through vias 231 may have a substantially hourglass shape in cross-section. Each of the multiple first through vias 231 may contain an electroless plating layer as a seed layer, and the via hole may be substantially filled with an electroplating layer. The electroless plating layer may contain a copper (Cu) layer formed of chemical copper, and the electroplating layer may contain a copper (Cu) layer formed of electrolytic copper. However, this is not the only option; a sputtering layer can also be formed in the seed layer, and, if necessary, both a sputtering layer and an electroless plating layer can be formed in the seed layer.

[0035] Each of the multiple first and second pads 221, 222 may contain a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, it may contain copper (Cu), but is not limited thereto. Each of the multiple first and second pads 221, 222 can perform various functions depending on the design. For example, it may include signal pads, power pads, etc. Each of the multiple first and second pads 221, 222 may contain an electroless plating layer as a seed layer, and may also contain an electroplated layer formed on such a seed layer. The electroless plating layer may contain a copper (Cu) layer formed of chemical copper, and the electroplated layer may contain a copper (Cu) layer formed of electrolytic copper. However, it is not limited thereto, and a sputtering layer may also be formed as a seed layer, and if necessary, both a sputtering layer and an electroless plating layer may be formed as seed layers.

[0036] The adhesive layer 250 may contain an adhesive. The adhesive may include epoxy resin, silicone resin, polyimide, acrylic resin, and / or polyurethane. For example, the adhesive layer 250 may contain DAF (Die Attach Film).

[0037] Figure 3 is a schematic process diagram showing an example of the manufacturing process for the printed circuit board shown in Figure 2.

[0038] Referring to the drawings, first, a glass layer 110 can be prepared. The glass layer 110 can be in the form of a large-area panel, for example, a glass plate, but is not limited to this. Next, a blind cavity C with a bottom surface can be formed in the glass layer 110. The cavity C can be formed by processes such as wet etching, dry etching, laser processing and / or injection molding. The bottom surface of the cavity C can be formed at approximately half the thickness of the glass layer 110, with respect to the thickness direction. Next, an interconnect unit 200 manufactured in a separate substrate process can be embedded. For example, the interconnect unit 200 can be attached to the bottom surface of the cavity C using an adhesive layer 250. Next, a plurality of via holes V can be formed on the underside of the cavity C, penetrating both the glass layer 110 and the adhesive layer 250 simultaneously. The plurality of via holes V can be formed by laser processing and etching processes. The plurality of first pads 221 can be used as stopper layers when forming the plurality of via holes V. Next, multiple via holes V can be filled with metal to form multiple second through vias 132. Furthermore, multiple third pads 123, each connected to the multiple second through vias 132, can be formed on the lower surface of the glass layer 110. The multiple second through vias 132 and the multiple third pads 123 can be formed by sputtering and electroplating, and electroless plating can also be used if necessary. Next, multiple third through vias 133 and multiple fourth and fifth pads 124 and 125 can be formed in the glass layer 110. Via holes for forming the multiple third through vias 133 can also be formed by laser processing and etching. The multiple third through vias 133 and the multiple fourth and fifth pads 124 and 125 can also be formed by sputtering and electroplating, and electroless plating can also be used if necessary. On the other hand, the multiple third pads 123 can also be formed when forming the multiple fifth pads 125.

[0039] Through a series of processes, the printed circuit board 500A according to the example described above can be manufactured, and the other descriptions can be substantially the same as those described above.

[0040] Figure 4 is a schematic cross-sectional view showing a modified example of the printed circuit board shown in Figure 2.

[0041] Referring to the drawings, the modified printed circuit board 500B can be a double-sided build-up multilayer printed circuit board structure that includes the printed circuit board 500A described above as a core structure. For example, the printed circuit board 500B can include a glass layer 110 as a glass core 110, and can include a first build-up structure 310 disposed above such glass core 110 and a second build-up structure 320 disposed below such glass core 110. If necessary, the printed circuit board 500B can further include a first resist layer 331 disposed on the first build-up structure 310, a second resist layer 332 disposed on the second build-up structure 320, a plurality of first electrically connecting metals 341 disposed in a plurality of first openings of the first resist layer 331, and / or a plurality of second electrically connecting metals 342 disposed in a plurality of second openings of the second resist layer 332.

[0042] Thus, since the printed circuit board 500B includes the printed circuit board 500A as a core structure, it can substantially include the same technical effects as the printed circuit board 500A. For example, it can be applied to large bodies, warping control is easy, and yet it can improve signal and / or power paths to enhance signal and / or power characteristics. Therefore, it can be easily applied to large-area boards for servers. In addition, because signal loss can be reduced, the design freedom and design flexibility of the second build-up structure 320 located below the core structure can be increased.

[0043] Below, the components of the printed circuit board 500B, including modified examples, will be described in more detail with reference to the drawings.

[0044] The first build-up structure 310 may include a plurality of first insulating layers 311 laminated on the upper surface of the glass layer 110, a plurality of first wiring layers 312 each disposed on or within the plurality of first insulating layers 311, and a plurality of first via layers 313 each disposed within the plurality of first insulating layers 311. The first build-up structure 310, for example, the lowest first insulating layer 311 among the plurality of first insulating layers 311, can cover at least a portion of the interconnect unit 200 and can fill at least a portion of the cavity C. The second build-up structure 320 may include a plurality of second insulating layers 321 laminated on the lower surface of the glass layer 110, a plurality of second wiring layers 322 each disposed on or within the plurality of second insulating layers 321, and a plurality of second via layers 323 each disposed within the plurality of second insulating layers 321.

[0045] The multiple first and second insulating layers 311, 321 can each be a build-up insulating layer, and each can contain a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or an inorganic filler, an organic filler, and / or glass fiber (glass cloth, glass fabric) together with the resin. For example, the multiple first and second insulating layers 311, 321 can each be PPG (Prepreg), ABF (Ajinomoto Build-up Film), etc., but are not limited thereto. The multiple first and second insulating layers 311, 321 can be substantially identical in material to each other, but are not limited thereto. The multiple first and second insulating layers 311, 321 can be identical in number of layers to each other, but are not limited thereto.

[0046] The multiple first and second wiring layers 312, 322 can each be a build-up wiring layer and may each contain a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, it may contain copper (Cu), but is not limited thereto. The multiple first and second wiring layers 312, 322 can each perform various functions depending on the design. For example, they may include signal patterns, power patterns, ground patterns, etc. These patterns may each have various forms such as lines, planes, and pads. The multiple first and second wiring layers 312, 322 may each include a seed layer and a plating layer. The seed layer may be formed by electroless plating (e.g., chemical copper) and, if necessary, by a sputtering process. Or, both may be used. The plating layer may be formed by electroplating (e.g., electrolytic copper). Copper foil may be added as needed.

[0047] The multiple first and second via layers 313, 323 can each be a build-up via layer and may each contain a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, it may contain, but is not limited to, copper (Cu). The multiple first and second via layers 313, 323 may each contain multiple connection vias that penetrate at least a portion of each of the multiple first and second insulating layers 311, 321, thereby providing electrical connection paths within the multiple first and second insulating layers 311, 321, respectively. Each of the multiple connection vias can perform various functions depending on the design. For example, they may include signal vias, power vias, ground vias, etc. Each of the multiple connection vias may include filled vias, in which the via hole is filled with metal, or conformal vias, in which the metal is positioned along the wall of the via hole. Multiple connection vias can each have a substantially tapered shape in cross-section. For example, multiple connection vias of multiple first via layers 313 can have a tapered shape in cross-section where the width of the upper end is wider than the width of the lower end. Similarly, multiple connection vias of multiple second via layers 323 can have a tapered shape in cross-section where the width of the lower end is wider than the width of the upper end. Multiple first and second via layers 313, 323 can include seed layers and plating layers contained in multiple first and second wiring layers 312, 322.

[0048] The first and second resist layers 331 and 332 may each contain a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or an inorganic filler and / or organic filler together with the resin. For example, the first and second resist layers 331 and 332 may be ABF (Ajinomoto Build-up Film), SR (Solder Resist), etc., but are not limited thereto. Multiple first and second openings may be formed in the first and second resist layers 331 and 332, respectively. In this case, the pad patterns of the uppermost first wiring layer 312 and the lowermost second wiring layer 322 exposed through the multiple first and second openings may be in the form of SMD (Solder Mask Defined) and / or NSMD (Non-Solder Mask Defined), but are not limited thereto.

[0049] Multiple first and second electrical connecting metals 341, 342 can be connected to the respective pad patterns of the uppermost first wiring layer 312 and the lowermost second wiring layer 322, which are exposed through multiple first and second openings. Multiple first and second electrical connecting metals 341, 342 can each be formed from a low-melting-point metal, such as tin (Sn)-aluminum (Al)-copper (Cu) solder, but this is just an example and the material is not particularly limited thereto. Multiple first and second electrical connecting metals 341, 342 can each be balls, pins, etc. Multiple first and second electrical connecting metals 341, 342 can each be formed from multiple layers or a single layer. When formed from multiple layers, copper columns and solder may be included, and when formed from a single layer, tin-silver solder may be included, but is not limited thereto.

[0050] Multiple semiconductor chips can be mounted on the first resist layer 331 via multiple first electrically coupled metals 341. Each of the multiple semiconductor chips may include an integrated circuit (IC) die in which hundreds to millions or more elements are integrated within a single chip. The integrated circuit can be, but is not limited to, logic chips such as a central processor (e.g., CPU), graphics processor (e.g., GPU), field-programmable gate array (FPGA), digital signal processor, cryptographic processor, microprocessor, microcontroller, application processor (e.g., AP), analog-to-digital converter, or ASIC (application-specific IC), and can also be of different types such as memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, HBM (High Bandwidth Memory), or PIC (Photonic Integrated Circuit).

[0051] Other explanations can be substantially the same as those described in the above example of printed circuit board 500A and its manufacturing example.

[0052] Figure 5 is a schematic cross-sectional view showing another example of a printed circuit board.

[0053] Referring to the drawings, another example of a printed circuit board 500C may further include electronic components 410 embedded within the glass layer 110 in the printed circuit board 500A of the above example. The electronic components 410 can be various types of active and / or passive components. Thus, various technologies necessary for next-generation semiconductors can be provided. The electronic components 410 may have a plurality of electrode pads 412. The plurality of electrode pads 412 can each be connected to a plurality of metal patterns 126 via a plurality of metal vias 135. The electronic components 410 may be embedded directly within the glass layer 110, but are not limited thereto, and may also be embedded in a cavity that has been additionally formed in the glass layer 110. The plurality of metal vias 135 and the plurality of metal patterns 126 may be formed in the glass layer 110, but are not limited thereto, and may also be formed in an insulating material that fills the further formed cavity. The number of electronic components 410 is not particularly limited and can be embedded in the glass layer 110 as needed.

[0054] Other explanations can be substantially the same as those provided in the examples of the manufacture of printed circuit boards 500A, 500B, and printed circuit board 500A.

[0055] Figure 6 is a schematic cross-sectional view showing a modified example of the printed circuit board shown in Figure 5.

[0056] Referring to the drawings, the modified printed circuit board 500D may further include electronic components 410 embedded within the glass layer 110 in the modified printed circuit board 500B described above. The electronic components 410 may be connected to the first build-up structure 310 and / or the second build-up structure 320 depending on their embedded location. For example, the electronic components 410 may be electrically connected to at least one part of at least one of the multiple first wiring layers 312 and multiple second wiring layers 322 via at least one part of at least one of the multiple first via layers 313 and multiple second via layers 323.

[0057] Other explanations can be substantially the same as those provided in the examples of the manufacture of printed circuit boards 500A, 500B, 500C and printed circuit board 500A.

[0058] Figure 7 is a schematic cross-sectional view showing yet another example of a printed circuit board.

[0059] Referring to the drawings, in another example, printed circuit board 500E, the interconnect unit 200' may not include multiple second pads in printed circuit board 500A as described above. Also, multiple third pads may not be placed on the underside of the glass layer 110. For example, multiple second and third pads may be omitted. For example, landlessness can be achieved in specific regions of the glass layer 110 that provide electrical paths with fine pitch and fine size, thereby further improving signal and / or power characteristics.

[0060] Other explanations can be substantially the same as those provided in the examples of the manufacture of printed circuit boards 500A, 500B, 500C, and 500D, and printed circuit board 500A.

[0061] Figure 8 is a schematic cross-sectional view showing a modified example of the printed circuit board shown in Figure 7.

[0062] Referring to the drawings, the modified printed circuit board 500F can be such that the interconnect unit 200' does not include a plurality of second pads in the modified printed circuit board 500B described above. Also, a plurality of third pads may not be placed on the lower surface of the glass layer 110. For example, a plurality of second and third pads may be omitted. Thus, the lowest of the plurality of first via layers 313 can include a plurality of first connecting vias that are directly connected to the upper side of each of the plurality of first through vias 231. Also, the uppermost of the plurality of second via layers 323 can include a plurality of second connecting vias that are directly connected to the lower side of each of the plurality of second through vias 132. On the other hand, the plurality of first connecting vias can each further penetrate a portion of the second passivation layer 213 and thus be in direct contact with each of the plurality of first through vias 231.

[0063] Other explanations can be substantially the same as those provided for printed circuit boards 500A, 500B, 500C, 500D, 500E and for the example of manufacturing printed circuit board 500A.

[0064] In this disclosure, thickness, width, length, pitch, depth, etc., can be measured using a scanning microscope or optical microscope based on a cross-section obtained by polishing or cutting the printed circuit board. The cut cross-section can be a vertical or horizontal cross-section, and each value can be measured based on the required cut cross-section. If the values ​​are not constant, the values ​​can be determined by the average value of the values ​​measured at any five points. The width of the upper and / or lower ends of the via can be measured on a cross-section cut along the central axis of the via in the thickness direction. The depth of the via can be measured as the distance from the upper end to the lower end of the via on a cross-section cut along the central axis of the via in the thickness direction of the substrate.

[0065] In this disclosure, the expression "cover" may include not only covering the entire surface but also covering at least a portion of it, and may include not only direct covering but also indirect covering. Similarly, the expression "satisfy" may include not only completely satisfying the surface but also satisfying it roughly, for example, if there are some gaps or voids.

[0066] In this disclosure, "substantially" can be determined to include process errors, positional deviations, and measurement errors that occur during the manufacturing process. For example, substantially the same line width, spacing, thickness, and height can include not only cases where the numerical values ​​are exactly the same, but also cases where they are roughly similar. Furthermore, substantially any shape can include cases where the shape is exactly that, but also cases where it is roughly that shape.

[0067] In this disclosure, the term "same insulating material" can mean not only that it is exactly the same insulating material, but also that it includes insulating materials of the same type. Therefore, the composition of the insulating materials may be substantially the same, but their specific compositional ratios may differ slightly.

[0068] In this disclosure, "on a cross-section" can mean the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed from the side. Furthermore, "on a plane" can mean the planar shape when the object is cut horizontally, or the planar shape when the object is viewed from the top or bottom.

[0069] In this disclosure, terms such as "lower side," "bottom," and "bottom surface" are used for convenience to mean the downward direction relative to the cross-section of the drawing, while terms such as "upper side," "upper part," and "top surface" are used to mean the opposite direction. Furthermore, terms such as "side" and "side" are used to mean the direction perpendicular to the top and bottom surfaces. However, these are merely definitions of directions for explanatory purposes, and the scope of the claims is not specifically limited by such descriptions of directions; the concepts of "up" and "down" can change at any time.

[0070] In this disclosure, the term "connected" includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, the term "electrically connected" includes both physically connected and non-connected cases. In addition, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of those components. In some cases, without departing from the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component.

[0071] The expression "example" as used in this disclosure does not mean that each embodiment is identical to the others, but is provided to highlight and illustrate the unique and distinct features of each embodiment. However, the examples presented above do not preclude their implementation in combination with features of other examples. For example, even if a matter described in one example is not described in another example, it can be understood as a description related to the other example, unless there is a description in the other example that contradicts or inconsistes with that matter.

[0072] The terms used in this disclosure are for illustrative purposes only and are not intended to limit the disclosure. Where otherwise, singular expressions include plural expressions unless the context clearly indicates otherwise. [Explanation of symbols]

[0073] 1000 electronic equipment 1010 Mainboard 1020 Chip-related components 1030 Network-related components 1040 Other parts 1050 Camera 1060 Antenna 1070 Display 1080 Battery 1090 signal line 500A, 500B, 500C, 500D, 500E, 500F Printed Circuit Boards 110 Glass layer (glass core) C Cavity (Blind Cavity) 123, 124, 125 pads 126 Metal Patterns 132, 133 Through vias 135 Metal Vias 200, 200' Interconnect Unit 211 Polymer layer 212, 213 Passivation Layer 221, 222 pads 231 Through via 250 Adhesive layer 310, 320 Build-up Structures 311, 321 Insulating layer 312, 322 wiring layer 313, 323 via layers 331, 332 Resist layer 341, 342 Electrically connected metals 410 Electronic Components 412 Electrode Pads

Claims

1. A glass layer, A cavity extending from the upper surface of the glass layer through a portion of the glass layer, An interconnect unit comprising at least a portion disposed within the cavity and including a polymer layer and a plurality of first through vias that penetrate the polymer layer, It includes a plurality of second through vias that penetrate the glass layer from the lower surface of the glass layer to the bottom surface of the cavity, A printed circuit board in which the plurality of first through vias are each connected to the plurality of second through vias.

2. The interconnect unit is attached to the bottom surface of the cavity via an adhesive layer. The printed circuit board according to claim 1, wherein the plurality of second through vias each further penetrate the adhesive layer.

3. The printed circuit board according to claim 2, wherein each of the plurality of second through vias has a substantially tapered shape in which the width on the cross-section of the lower end is wider than the width on the cross-section of the upper end.

4. The interconnect unit further includes a plurality of first pads, each positioned beneath the polymer layer and each connected beneath each of the plurality of first through vias, The printed circuit board according to claim 1, wherein the plurality of second through vias are each connected to the plurality of first through vias via the plurality of first pads.

5. The printed circuit board according to claim 4, wherein the interconnect unit further comprises a plurality of second pads, each disposed above the polymer layer and each connected to the upper side of each of the plurality of first through vias.

6. The printed circuit board according to claim 4, further comprising a plurality of third pads, each disposed on the lower surface of the glass layer and each connected to the lower side of each of the plurality of second through vias.

7. The printed circuit board according to claim 1, further comprising a plurality of third through-vias that penetrate between the upper and lower surfaces of the glass layer in a region separated from the region in which the cavity is located.

8. The minimum pitch between the plurality of first through vias and the minimum pitch between the plurality of second through vias are each smaller than the minimum pitch between the plurality of third through vias. The printed circuit board according to claim 7, wherein the minimum diameter of each of the plurality of first through vias and the minimum diameter of each of the plurality of second through vias are smaller than the minimum diameter of each of the plurality of third through vias.

9. A plurality of fourth pads are arranged on the upper surface of the glass layer and connected to the upper side of each of the plurality of third through vias, The printed circuit board according to claim 7, further comprising a plurality of fifth pads, each disposed on the lower surface of the glass layer and each connected to the lower side of each of the plurality of third through vias.

10. A first build-up structure is disposed on the upper surface of the glass layer, The present invention further includes a second build-up structure disposed on the lower surface of the glass layer, The first build-up structure includes a plurality of first insulating layers laminated on the upper surface of the glass layer, a plurality of first wiring layers disposed on or within the plurality of first insulating layers, and a plurality of first via layers disposed within the plurality of first insulating layers. The printed circuit board according to claim 1, wherein the second build-up structure includes a plurality of second insulating layers laminated on the lower surface of the glass layer, a plurality of second wiring layers disposed on or within the plurality of second insulating layers, and a plurality of second via layers disposed within the plurality of second insulating layers.

11. The lowest of the plurality of first via layers includes a plurality of first connecting vias that are directly connected to the upper side of each of the plurality of first through vias. The uppermost of the plurality of second via layers includes a plurality of second connecting vias that are directly connected to the lower side of each of the plurality of second through vias. The interconnect unit further includes a first passivation layer and a second passivation layer disposed on the lower and upper surfaces of the polymer layer, respectively. The printed circuit board according to claim 10, wherein each of the plurality of first connection vias further penetrates a portion of the second passivation layer.

12. The glass layer further includes electronic components embedded within it. The printed circuit board according to claim 10, wherein the electronic component is electrically connected to at least one part of the plurality of first via layers and the plurality of second via layers via at least one part of the plurality of first wiring layers and the plurality of second wiring layers.

13. The aforementioned cavities and interconnect units are each multiple in number. The printed circuit board according to claim 1, wherein the plurality of interconnect units are arranged in the plurality of cavities.

14. A glass core with a blind cavity, An interconnect unit, at least a portion of which is located within the blind cavity, When the glass core is viewed from above, there are a plurality of second through vias that penetrate the glass core in the region overlapping with the blind cavity, When the glass core is viewed from above, a plurality of third through vias are seen penetrating the glass core in a region separated from the blind cavity, A first build-up structure is disposed above the glass core and includes a plurality of first wiring layers, A printed circuit board comprising: a second build-up structure disposed below the glass core and including a plurality of second wiring layers.

15. The minimum pitch between the plurality of second through vias is smaller than the minimum pitch between the plurality of third through vias. The printed circuit board according to claim 14, wherein the minimum diameter of each of the plurality of second through vias is smaller than the minimum diameter of each of the plurality of third through vias.

16. The blind cavity penetrates a portion of the glass core from the upper surface to the lower surface, The printed circuit board according to claim 14, wherein the first build-up structure covers at least a portion of the interconnect unit and fills at least a portion of the blind cavity.

17. The interconnect unit includes a plurality of first through vias, The plurality of first through vias are each connected to the plurality of second through vias, The printed circuit board according to claim 14, wherein at least a portion of the plurality of first wiring layers and at least a portion of the plurality of second wiring layers are electrically connected to each other via at least a portion of the plurality of first through vias and at least a portion of the plurality of second through vias.

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