Memory system

Abstract

To provide a memory system that improves performance and lifespan. [Solution] The memory system 1 comprises a non-volatile memory 30 and a memory controller 10 connected to the non-volatile memory. The non-volatile memory includes a plurality of physical full blocks FB, each of which includes a plurality of physical subblocks SB, and in each of the plurality of physical full blocks, the memory cells included in each of the plurality of physical subblocks are connected in series or parallel to the same bit line. The memory controller causes each of the plurality of physical subblocks to independently perform a data erasure operation in each of the plurality of physical full blocks, and sets all of the plurality of physical subblocks in each of the plurality of physical full blocks to the same storage mode. The storage mode is a setting state that indicates the number of bits of data stored in the memory cells included in each of the plurality of physical subblocks.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory system.

Background Art

[0002] As a memory system, a solid state drive (SSD) including a memory controller and a memory device is known. The memory device is, for example, a non-volatile memory. The non-volatile memory is, for example, a NAND type flash memory.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to improve the performance and extend the lifespan of a memory system.

Means for Solving the Problems

[0005] The memory system of the embodiment comprises a non-volatile memory and a memory controller electrically connected to the non-volatile memory. The non-volatile memory includes a plurality of physical full blocks, each of which includes a plurality of physical subblocks, and in each of the plurality of physical full blocks, the memory cells included in each of the plurality of physical subblocks are connected in series or in parallel to the same bit line. The memory controller is configured to independently perform a data erasure operation for each of the plurality of physical subblocks in each of the plurality of physical full blocks, and to set all of the plurality of physical subblocks in each of the plurality of physical full blocks to the same storage mode. The storage mode is a setting state that indicates the number of bits of data stored in the memory cells included in each of the plurality of physical subblocks. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example configuration of an information processing system including a memory system according to the first embodiment. [Figure 2] A block diagram showing an example configuration of a non-volatile memory according to the first embodiment. [Figure 3] Circuit diagram of a memory cell array of a non-volatile memory according to the first embodiment. [Figure 4] A schematic diagram showing an example of block configuration in the memory system of the first embodiment. [Figure 5] A schematic diagram showing an example of operation of the memory system of the first embodiment. [Figure 6] A schematic diagram showing an example of the operation of a comparative memory system. [Figure 7] Block diagram showing an example configuration of the memory system of the second embodiment. [Figure 8] A schematic diagram showing an example of the data efficiency in the memory system of the second embodiment. [Figure 9] A flowchart illustrating a first example of garbage collection operation in a memory system of the second embodiment. [Figure 10]Flowchart showing a second operation example of garbage collection in the memory system of the second embodiment. [Figure 11] Flowchart showing a third operation example of garbage collection in the memory system of the second embodiment. [Figure 12] Block diagram showing a configuration example of the memory system of the third embodiment. [Figure 13] Flowchart showing a first operation example of wear leveling in the memory system of the third embodiment. [Figure 14] Flowchart showing a second operation example of wear leveling in the memory system of the third embodiment. [Figure 15] Flowchart showing a third operation example of wear leveling in the memory system of the third embodiment.

Mode for Carrying Out the Invention

[0007] Referring to FIGS. 1 to 15, the memory system and memory device of the embodiment will be described. In the following description, elements having the same functions and configurations are denoted by the same reference numerals. Also, in each of the following embodiments, when components (for example, circuits, wirings, various voltages and signals, etc.) with reference numerals accompanied by numbers / letters for distinction at the end do not need to be distinguished from each other, descriptions (reference numerals) with the numbers / letters at the end omitted are used.

[0008] <Embodiment> (1) First Embodiment Referring to FIGS. 1 to 6, the memory system of the first embodiment and its control method will be described.

[0009] (a) Configuration Example FIG. 1 is a block diagram showing a configuration example of the information processing system 9.

[0010] As shown in FIG. 1, the information processing system 9 includes a memory system 1 and a host 2.

[0011] The memory system 1 is a device that stores data. The memory system 1 is, for example, an SSD (solid state drive), a UFS (Universal Flash Storage) device, a USB (Universal Serial Bus) memory, an MMC (Multi-Media Card), or an SD TM card. The memory system 1 can be connected to the host 2 via the host bus HBS. The memory system 1 performs processing based on a request (command or host command) received from the host 2 or a spontaneous processing request generated inside the memory system 1.

[0012] The host 2 is a computing device that controls the memory system 1. The host 2 is, for example, a personal computer, a server, a mobile device, an in-vehicle device, or a digital camera.

[0013] (a-1-1) Internal configuration of the memory system The memory system 1 includes a memory controller 10 and a memory device 30. The memory device 30 is, for example, a non-volatile memory. More specifically, the memory device 30 is a non-volatile semiconductor memory such as a NAND-type flash memory. Hereinafter, the memory device 30 is referred to as a non-volatile memory 30 or a NAND memory 30.

[0014] The memory controller 10 is a device that controls the NAND memory 30. The memory controller 10 is connected to the host 2 via the host bus HBS. The memory controller 10 receives a request from the host 2 via the host bus HBS. The type of the host bus HBS depends on the application applied to the memory system 1. When the memory system 1 is an SSD, the host bus HBS is, for example, SAS (Serial Attached SCSI), SATA (Serial ATA), or PCIe TMIt conforms to the Peripheral Component Interconnect Express (CSI) standard. If memory system 1 is a UFS device, the host bus HBS conforms to the M-PHY standard. If memory system 1 is a USB memory, the host bus HBS conforms to the USB standard. If memory system 1 is an SD TM If it is a card, the host bus HBS is SD TM To comply with standards.

[0015] The memory controller 10 controls the NAND memory 30 via the NAND bus NBS based on requests received from the host 2 or spontaneous processing requests generated within the memory system 1. The NAND bus NBS conforms to, for example, the Toggle NAND Flash Interface standard or the Open NAND Flash Interface standard.

[0016] The NAND memory 30 is a device for storing data. The NAND memory 30 includes multiple memory cells. Each of the multiple memory cells stores data nonvolatilously according to the threshold voltage of the memory cell. The NAND memory 30 stores the data received from the memory controller 10 nonvolatilously in the multiple memory cells. The NAND memory 30 outputs the data read from the multiple memory cells to the memory controller 10.

[0017] (a-1-2) Memory controller An example of the internal configuration of the memory controller 10 will be described below.

[0018] As shown in Figure 1, the memory controller 10 includes a host interface (host I / F) circuit 11, a processor 12, a buffer memory 13, an ECC (error checking and correcting) circuit 14, a ROM (read-only memory) 15, a RAM (random access memory) 16, and a NAND interface (NAND I / F) circuit 17. The memory controller 10 may be configured as, for example, a SoC (system-on-a-chip). The memory controller 10 may be composed of multiple chips. The functions of each part of the memory controller 10 can be realized by dedicated hardware circuits, a processor that executes a program (firmware), or a combination thereof.

[0019] The host interface circuit 11 is responsible for communication between the memory controller 10 and the host 2. The host interface circuit 11 is connected to the host 2 via the host bus HBS.

[0020] The processor 12 is the control circuit of the memory controller 10. The processor 12 is, for example, a CPU (central processing unit). The processor 12 controls the operation of the entire memory controller 10 by executing the program (firmware) stored in the ROM 15. For example, when the processor 12 receives a write request from the host 2, it controls the write operation based on the received write request. The same applies to read operations.

[0021] Buffer memory 13 is memory that temporarily stores data. Buffer memory 13 is, for example, SRAM (static random access memory). Buffer memory 13 temporarily stores written data and read data, etc. Written data is data written to NAND memory 30. Read data is data read from NAND memory 30.

[0022] The ECC circuit 14 is a circuit that performs ECC processing for error correction of data. During a data writing operation, the ECC circuit 14 generates error correction codes based on the data to be written in predetermined units. During a data reading operation, the ECC circuit 14 generates a syndrome based on the error correction codes in predetermined units and detects errors. The ECC circuit 14 corrects the detected errors.

[0023] ROM15 is a non-volatile memory. ROM15 is, for example, an EEPROM. TM It is an electrically erasable, programmable, read-only memory. ROM15 stores programs such as firmware.

[0024] RAM16 is volatile memory. RAM16 is, for example, SRAM or DRAM (dynamic random access memory). RAM16 is used as a work area for processor 12. RAM16 stores firmware for managing NAND memory 30 and various management information. RAM16 stores, for example, various tables TBL.

[0025] The NAND interface circuit 17 is responsible for communication between the memory controller 10 and the NAND memory 30. The NAND interface circuit 17 is connected to the NAND memory 30 via the NAND bus NBS. For example, the NAND interface circuit 17 controls the transfer of data, commands, and addresses between the memory controller 10 and the NAND memory 30.

[0026] For example, NAND memory 30 contains M memory chips (memory dies) 300. One memory chip 300 contains N planes PLN. A plane PLN is an independently operating control unit. M and N are integers greater than or equal to 1.

[0027] (a-1-3) NAND flash memory Referring to Figure 2, the configuration of the NAND memory 30 will be explained.

[0028] Figure 2 is a block diagram showing an example of the configuration of a NAND memory 30. Figure 2 shows the configuration of one of the M memory chips 300 contained in the NAND memory 30 as an example of the configuration of the NAND memory 30. The NAND memory 30 includes a memory cell array 31, input / output circuits 32, logic control circuits 33, ready / busy control circuits 34, registers 35, a sequencer 36, a driver module 37, a raw decoder module 38, a sense amplifier module 39, and a data latch 40.

[0029] The memory cell array 31 is a circuit for storing data. The memory cell array 31 includes one or more physical full blocks FB0, FB1, ..., FB(k-1), where k is an integer of 1 or more. For example, the memory cell array 31 may be divided into one or more planes PLN, each containing multiple physical full blocks. Each physical block FB(FB0, FB1, ..., FB(k-1)) includes multiple physical subblocks SB. The physical subblocks SB are control units for various operations of the NAND memory 30. A physical subblock SB is, for example, a collection of multiple memory cells whose data is erased collectively. The physical subblocks SB are used as units for data erasure operations. In the following, when physical full blocks and physical subblocks are not distinguished from each other, they are referred to as physical blocks.

[0030] Multiple bit lines and multiple word lines are provided within the memory cell array 31. Each memory cell is associated, for example, with one bit line and one word line. Details of the memory cell array 31 will be described later.

[0031] The input / output circuit 32 is a circuit that sends and receives signals and information to and from the memory controller 10. The input / output circuit 32 sends and receives input / output signals DQ (for example, 8-bit signals DQ0 to DQ7) and data strobe signals DQS to and from the memory controller 10. Signal DQ is the actual data that is sent and received between the NAND memory 30 and the memory controller 10. Signal DQ is, for example, a command CMD, an address ADD, status information STS, and data DAT. Signal DQS is a signal (clock signal) for controlling the timing of sending and receiving signals DQ. For example, when writing data, signal DQS is sent from the memory controller 10 to the NAND memory 30 along with signal DQ containing the data to be written. The input / output circuit 32 receives signal DQ containing the data to be written in synchronization with signal DQS. When reading data, signal DQS is sent from the input / output circuit 32 to the memory controller 10 along with signal DQ containing the data to be read. The memory controller 10 receives signal DQ, which contains the read data, in synchronization with signal DQS. Alternatively, the input / output circuit 32 may receive signal DQS from the memory controller 10 via the logic control circuit 33.

[0032] The input / output circuit 32 transmits the command CMD in signal DQ to the command register 35A. The input / output circuit 32 transmits the address ADD in signal DQ to the address register 35B. The input / output circuit 32 receives the status information STS from the status register 35C. The input / output circuit 32 transmits and receives the data DAT in signal DQ to and from the data latch 40.

[0033] The logic control circuit 33 is a circuit that controls the input / output circuit 32 and the sequencer 36 based on control signals. The logic control circuit 33 receives the chip enable signal CEn, command latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, and read enable signal REn from the memory controller 10. Signal CEn is a signal for enabling the NAND memory 30. Signal CLE is a signal that indicates that the signal DQ received by the NAND memory 30 is the command CMD. Signal ALE is a signal that indicates that the signal DQ received by the NAND memory 30 is the address ADD. Signal WEn is a signal that commands the NAND memory 30 to input signal DQ. Signal REn is a signal that commands the NAND memory 30 to output signal DQ. The NAND memory 30 generates signal DQS based on signal REn. The NAND memory 30 outputs signal DQ to the memory controller 10 based on the generated signal DQS.

[0034] The ready / busy control circuit 34 is a circuit that informs the memory controller 10 of the operating status of the sequencer 36. Based on the operating status of the sequencer 36, the ready / busy control circuit 34 sends a ready / busy signal RBn to the memory controller 10. Signal RBn is a signal that indicates whether the NAND memory 30 is in a ready state or a busy state. The signal level of signal RBn is, for example, high level ("H" level) when the NAND memory 30 is in a ready state. The ready state is a state in which the NAND memory 30 can accept commands from the memory controller 10. The signal level of signal RBn is, for example, low level ("L" level) when the NAND memory 30 is in a busy state. The busy state is a state in which the NAND memory 30 cannot accept commands from the memory controller 10.

[0035] Register 35 is a circuit for temporarily storing information. Register 35 includes the command register 35A, the address register 35B, and the status register 35C.

[0036] Command register 35A is a circuit that stores command CMDs. Command CMDs include, for example, instructions that cause the sequencer 36 to perform a read operation, a write operation, or an erase operation.

[0037] Address register 35B is a circuit that stores address ADD. Address ADD includes, for example, row addresses and column addresses. Row addresses include block addresses and page addresses (word line addresses). Block addresses, page addresses, and column addresses are used, for example, to select physical full blocks FB (or physical subblocks SB), word lines, and bit lines, respectively.

[0038] The status register 35C is a circuit that temporarily stores status information STS during, for example, a read operation, write operation, or erase operation. The status information STS is used to notify the memory controller 10 whether or not the operation has been completed successfully.

[0039] The sequencer 36 is a circuit that controls the operation of other circuits according to a predetermined program. The sequencer 36 controls the operation of the entire NAND memory 30. For example, the sequencer 36 controls the ready / busy control circuit 34, the driver module 37, the raw decoder module 38, and the sense amplifier module 39 based on the command CMD stored in the command register 35A. For example, the sequencer 36 performs read operations, write operations, and erase operations.

[0040] The driver module 37 is a circuit that generates various voltages used in read, write, and erase operations. Based on the page address stored in the address register 35B, the driver module 37 applies the generated voltage to the signal line corresponding to the selected word line.

[0041] The row decoder module 38 is a circuit that selects one physical full block FB (or physical subblock SB) in the memory cell array 31 based on the block address stored in the address register 35B. The row decoder module 38 transfers the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected physical full block FB (or physical subblock SB).

[0042] During a write operation, the sense amplifier module 39 receives the write data DAT from the input / output circuit 32 via the data latch 40. The sense amplifier module 39 applies a voltage to the bit line based on the received write data DAT. During a read operation, the sense amplifier module 39 determines the data stored in the memory cell based on whether or not current flows through the bit line or the voltage of the bit line. The sense amplifier module 39 transfers the determination result as read data DAT to the input / output circuit 32 via the data latch 40.

[0043] The data latch (data cache) 40 includes multiple latch circuits (not shown). Each latch circuit temporarily stores write data or read data. For example, during a write operation, the data latch 40 temporarily stores the write data received from the input / output circuit 32 and transmits it to the sense amplifier module 39. Similarly, during a read operation, the data latch 40 temporarily stores the read data received from the sense amplifier module 39 and transmits it to the input / output circuit 32.

[0044] (Example of a memory cell array circuit) The circuit configuration of the memory cell array 31 will be described with reference to Figure 3. Figure 3 is a circuit diagram of the memory cell array 31. Figure 3 shows the circuit configuration of the physical full block FB0 included in the memory cell array 31 as an example of the circuit configuration of the memory cell array 31. Other physical full block FBs have a similar configuration to that shown in Figure 3.

[0045] The physical full block FB0 includes, for example, five string units SU0, SU1, SU2, SU3, and SU4. Each string unit SU is a set of multiple NAND strings NS that are selected collectively in, for example, a write or read operation. Each string unit SU includes multiple NAND strings NS associated with bit lines BL0, BL1, ..., BL(m-1), where m is an integer greater than or equal to 1. The NAND strings NS are a set of multiple memory cells MC(MC0, ..., MC(n-1)) connected in series. Each NAND string NS includes, for example, memory cells MC0, MC1, MC2, MC3, ..., MC(n-2), MC(n-1), select transistor ST1, and select transistor ST2, where n is an integer greater than or equal to 1. The memory cell (also called a memory cell transistor) MC is a field-effect transistor including a control gate and a charge storage layer. The select transistors ST1 and ST2 are switching elements. The select transistors ST1 and ST2 are used to select the string unit SU during various operations.

[0046] In each NAND string NS, memory cells MC0,...,MC(n-1) are connected in series. The drain of select transistor ST1 is connected to the associated bit line BL. The source of select transistor ST1 is connected to one end of the series-connected memory cells MC0,...,MC(n-1). The drain of select transistor ST2 is connected to the other end of the series-connected memory cells MC0,...,MC(n-1). The source of select transistor ST2 is connected to the source line SL.

[0047] In the same physical full block FB, the control gates of memory cells MC0, MC1, MC2, MC3, ..., MC(n-2), MC(n-1) are commonly connected to word lines WL0, WL1, WL2, WL3, ..., WL(n-2), WL(n-1), respectively, across multiple NAND strings. The gates of select transistors ST1 in string units SU0, SU1, SU2, SU3, SU4 are commonly connected to select gate lines SGD0, SGD1, SGD2, SGD3, SGD4, respectively, across multiple NAND strings. The gate of select transistor ST2 included in the same block BLK is commonly connected to select gate line SGS across multiple NAND strings.

[0048] In the circuit configuration of the memory cell array 31 described above, the bit line BL is shared, for example, by NAND strings NS to which the same column address is assigned in each string unit SU. The source line SL is shared, for example, between multiple physical full blocks FB.

[0049] A physical subblock SB is a control unit composed of a predetermined number of word lines WL or a predetermined number of string units SU.

[0050] For example, in a physical full block FB containing 96 word lines WL0 to WL95, the set of word lines WL0 to WL47 is assigned to the first physical subblock SB, and the set of word lines WL48 to WL95 is assigned to the second physical subblock SB. In this case, one physical full block FB contains two physical subblocks SB. One physical full block FB may also contain three physical subblocks SB. For example, the set of word lines WL0 to WL31 is assigned to the first physical subblock SB, the set of word lines WL32 to WL63 is assigned to the second physical subblock SB, and the set of word lines WL64 to WL95 is assigned to the third physical subblock SB.

[0051] As another example, in a physical full block FB containing six string units SU0-SU5, the set of string units SU0-SU2 is assigned to the first physical subblock SB, and the set of string units SU3-SU5 is assigned to the second physical subblock SB. In this case, one physical full block FB contains two physical subblocks SB. One physical full block FB may also contain three physical subblocks SB. For example, the set of string units SU0-SU1 is assigned to the first physical subblock SB, the set of string units SU2-SU3 is assigned to the second physical subblock SB, and the set of string units SU4-SU5 is assigned to the third physical subblock SB.

[0052] As yet another example, a physical subblock SB may be defined within the range of word lines WL and string units SU. For example, in a physical full block FB containing 96 word lines WL0 to WL95 and 6 string units SU0 to SU5, if four physical subblocks SB are defined, the set of word lines WL0 to WL47 of three string units SU0 to SU2 is assigned to the first physical subblock SB, the set of word lines WL0 to WL47 of three string units SU3 to SU5 is assigned to the second physical subblock SB, the set of word lines WL48 to WL95 of three string units SU0 to SU2 is assigned to the third physical subblock SB, and the set of word lines WL48 to WL95 of three string units SU3 to SU5 is assigned to the fourth physical subblock SB.

[0053] In this way, multiple physical subblocks SB are defined within each physical full block FB, depending on the number of word lines WL and the configuration of string units SU.

[0054] A collection of multiple memory cells MC connected to a common word line WL within a single string unit SU is called, for example, a cell unit CU. A physical full block FB contains multiple cell unit CUs. The data stored in a cell unit CU, which contains multiple memory cells MCs each storing 1-bit data according to a threshold voltage, corresponds to one page of data. A cell unit CU can store more than one page of data, based on the number of bits of data stored by the memory cells MCs. When one memory cell MC stores 1-bit data, the memory cell MC is an SLC (single-level cell). In this case, the data stored in the cell unit CU corresponds to one page of data. When one memory cell MC stores 3-bit data, the memory cell MC is a TLC (triple-level cell). In this case, the data stored in the cell unit CU corresponds to three pages of data. The number of bits of data that a memory cell MC can store can be any real number. For example, a memory cell MC may be an MLC (multi-level cell) that stores 2 bits of data, a QLC (quad-level cell) that stores 4 bits of data, or a PLC (penta-level cell) that stores 5 bits of data.

[0055] In the following, the setting state (mode) indicating the number of bits of data stored by a single memory cell MC is referred to as the storage mode. If the memory cell MC is SLC, the storage mode is SLC mode. If the memory cell MC is MLC, the storage mode is MLC mode. If the memory cell MC is TLC, the storage mode is TLC mode. If the memory cell MC is QLC, the storage mode is QLC mode. If the memory cell MC is PLC, the storage mode is PLC mode. Depending on the storage mode of the memory cell MC, the cell unit CU can store more than one page of data.

[0056] Furthermore, changing the memory mode is called a mode change. A mode change alters the number of bits that a single memory cell MC can store (the number of pages allocated to a single cell unit CU).

[0057] The following examples illustrate cases where either SLC mode or TLC mode is used as the memory mode.

[0058] The circuit configuration of the memory cell array 31 is not limited to the configuration described above. For example, the number of string units SU included in the physical full block FB, and the number of memory cells MC and select transistors ST1 and ST2 included in each NAND string NS, can be any number.

[0059] (Example of block structure) Referring to Figure 4, the various blocks of the NAND memory 30 in the memory system 1 of this embodiment will be described. Figure 4 is a schematic diagram showing an example of the block configuration in the memory system 1 of this embodiment.

[0060] As described above, the NAND memory 30 includes multiple physical full block FBs. Each physical full block FB includes multiple physical subblocks SBs.

[0061] As shown in Figure 4, a logical full block (LFB) is defined. A logical full block (LFB) is a set of physical full blocks (FBs) that can be accessed in parallel. Note that a logical full block (LFB) may include multiple physical full blocks (FBs) that cannot be accessed in parallel with each other. In memory systems that do not employ the logical subblock (LSB) described later, the logical full block (LFB) becomes the unit of erase operation. A logical full block (LFB) is also called a super full block (SFB). A logical subblock (LSB) is also called a super subblock (SSB). In the following, when logical full blocks (or super full blocks) and logical subblocks (or super subblocks) are not distinguished from each other, they are referred to as a logical block (or superblock).

[0062] For example, a logical full block LFB contains multiple physical full blocks FB, one selected from each of the N planes PLN of each of the M memory chips 300. In this case, one logical full block LFB contains M × N physical full blocks FB. If each plane PLN contains p physical full blocks FB0 to FB(p-1), then p logical full blocks LFB0 to LFB(p-1) are formed in the memory system 1, where p is an integer greater than or equal to 1.

[0063] Multiple logical subblocks (LSBs) are defined within each logical full block (LFB). For example, q logical subblocks LSB0 to LSB(q-1) are formed within one logical full block (LFB), where q is an integer greater than or equal to 2. In this case, p × q logical subblocks (LSBs) are formed within memory system 1. A logical subblock (LSB) is, for example, a set of multiple physical subblocks (SBs) that can be accessed in parallel. In a memory system employing physical subblocks (SBs), a logical subblock (LSB) becomes the unit of erasure operation.

[0064] A single logical subblock LSB contains multiple physical subblocks SB. The number of physical subblocks SB contained within each physical subblock SB in a single logical full block LFB is equal to the number of physical subblocks SB in each physical subblock SB.

[0065] Figure 4 shows an example where each logical subblock LSB is formed to span multiple memory chips 300. However, the logical subblock LSB may also be formed to be contained within a single memory chip 300.

[0066] In the memory system 1 of this embodiment, the management table TBL of the memory controller 10 includes a table showing the correspondence between logical full block LFB, logical subblock LSB, physical full block FB, and physical subblock SB.

[0067] In the memory system 1 of this embodiment, one or more logical subblocks (LSBs) are configured to fit into a single set (e.g., a logical full block LFB) that includes multiple physical full blocks (FBs). Multiple logical subblocks (LSBs) are commonly allocated to a single set that includes multiple physical full blocks (FBs).

[0068] For example, in the first and second logical subblocks LSB (LSB0, LSB1) allocated to two physical full blocks FB (physical full block FB0, physical full block FB1) of the NAND memory 30, the first logical subblock LSB0 includes one physical subblock SB of physical full block FB0 and one physical subblock SB of physical full block FB1. The second logical subblock LSB1 includes another physical subblock SB of physical full block FB0 and another physical subblock SB of physical full block FB1.

[0069] In the memory system 1 of this embodiment, the memory controller 10 commands the NAND memory 30 to perform various operations specifying the storage mode. For example, the memory controller 10 commands the NAND memory 30 to perform various operations specifying the storage mode by adding a prefix command indicating the number of pages (number of bits to be stored in the memory cell) allocated to one cell unit CU to the command sequence. As an example, the memory controller 10 specifies the storage mode when issuing an erase operation command. More specifically, the memory controller 10 sends an erase command sequence including a prefix command to the NAND memory 30. When a mode change is performed, the memory controller 10 commands the NAND memory 30 to perform various operations specifying the changed storage mode.

[0070] If a logical subblock LSB is defined in the memory system 1, the memory controller 10 commands various operations that specify the storage mode on a per-logical subblock LSB basis. That is, the storage modes of all memory cells MC within all physical subblocks SB contained within the logical subblock LSB are the same.

[0071] Depending on the memory mode specified during the erase or write operation, the memory mode of the memory cell MC in the physical subblock SB is changed from SLC mode to TLC mode, or from TLC mode to SLC mode.

[0072] As described above, the memory controller 10 specifies the storage mode on a logical subblock LSB basis. Therefore, when the memory controller 10 performs a mode change on a certain physical subblock SB, other physical subblocks SB belonging to the same logical subblock LSB as that physical subblock SB are also subject to the mode change.

[0073] Furthermore, multiple physical subblocks SB within a physical full block FB are constrained to store data in the memory cell MC in the same storage mode. That is, within a physical full block FB, for example, a physical subblock SB in SLC mode and a physical subblock SB in TLC mode cannot coexist simultaneously. Within a physical full block FB, all physical subblocks SB have the same storage mode in terms of data storage state. Therefore, when the memory controller 10 performs a mode change on a certain physical subblock SB within a physical full block FB, other physical subblocks SB within that physical full block FB are also affected by the mode change.

[0074] As a result, all logical subblock LSBs, including other physical subblock SBs within the same physical full block FB as the logical subblock LSB that was targeted for mode change, become subject to mode change in a chain reaction. In this way, multiple logical subblock LSBs other than the one selected by the memory controller 10 for mode change become subject to mode change as well.

[0075] In the memory system 1 of this embodiment, multiple logical subblocks (LSBs) are commonly allocated to a single set that includes multiple physical full blocks (FBs).

[0076] As a result, the memory system 1 of this embodiment can reduce the occurrence of a chain reaction of mode changes.

[0077] (b) Example of operation An example of the operation of the memory system 1 of this embodiment will be described with reference to Figure 5.

[0078] Figure 5 is a schematic diagram illustrating the state of the memory system 1 in this embodiment when a mode change occurs. Figure 5 shows an example in which six physical full blocks FB (FBa, FBb, FBc, FBd, FBe, FBf) are provided, and two physical subblocks SB (SBa, SBb) are provided in each physical full block FB. Each of the multiple logical subblocks LSB (LSB1, LSB2, LSB3, LSB4, LSB5, LSB6) is assigned to a set containing multiple physical full blocks FB. Each logical subblock LSB contains two physical subblocks SB. The two logical subblocks LSB are assigned to a set containing two physical full blocks FB.

[0079] Specifically, logical subblock LSB1 includes physical subblock SBa of physical full block FBa and physical subblock SBa of physical full block FBb. Logical subblock LSB2 includes physical subblock SBb of physical full block FBa and physical subblock SBb of physical full block FBb. In other words, the set of physical full blocks FB to which logical subblock LSB1 is assigned (physical full blocks FBa, FBb) is the same as the set of physical full blocks FB to which logical subblock LSB2 is assigned (physical full blocks FBa, FBb).

[0080] Logical subblock LSB3 includes physical subblock SBa of physical full block FBc and physical subblock SBa of physical full block FBe. Logical subblock LSB4 includes physical subblock SBb of physical full block FBc and physical subblock SBb of physical full block FBe. In other words, the set of physical full blocks FB to which logical subblock LSB3 is assigned (physical full blocks FBc, FBe) is the same as the set of physical full blocks FB to which logical subblock LSB4 is assigned (physical full blocks FBc, FBe).

[0081] Logical subblock LSB5 includes physical subblock SBa of physical full block FBd and physical subblock SBa of physical full block FBf. Logical subblock LSB6 includes physical subblock SBb of physical full block FBd and physical subblock SBb of physical full block FBf. In other words, the set of physical full blocks FB to which logical subblock LSB5 is assigned (physical full blocks FBd, FBf) is the same as the set of physical full blocks FB to which logical subblock LSB6 is assigned (physical full blocks FBd, FBf).

[0082] In the memory system 1 of this embodiment, the memory controller 10, for example, selects the logical subblock LSB that is the target of the mode change when an erase operation command is issued.

[0083] In the example shown in Figure 5, we assume that the memory controller 10 selects the logical subblock LSB1 as the target for mode change.

[0084] Based on the storage mode specified in the instruction from the memory controller 10, the NAND memory 30 executes various processes and operations in the specified storage mode for the physical subblock SBa belonging to each of the physical full blocks FBa and FBb contained in the logical subblock LSB1 that is the target of the mode change.

[0085] As a result, in the selected logical subblock LSB1, the two physical subblocks SBa change modes, for example, from TLC mode to SLC mode, or from SLC mode to TLC mode. In this case, the physical subblock SBa of the physical full block FBa belonging to logical subblock LSB1 and the physical subblock SBa of the physical full block FBb belonging to logical subblock LSB1 change modes.

[0086] As mentioned above, there is a constraint that all physical subblocks SB of a physical full block FB must be set to the same memory mode. Therefore, physical subblocks SBb belonging to the same physical full block FBa as the physical subblock SBa that is undergoing a mode change, and physical subblocks SBb belonging to the physical full block FBb that is undergoing a mode change, will undergo a chain reaction of mode changes. The physical subblocks SBb within the physical full block FBa that undergo a chain reaction of mode changes, and the physical subblocks SBb within the physical full block FBb, belong to the logical subblock LSB2.

[0087] In the example shown in Figure 5, the set of physical full blocks FB to which logical subblock LSB1 is set (physical full blocks FBa, FBb) and the set of physical full blocks FB to which logical subblock LSB2 is set (physical full blocks FBa, FBb) are the same. As a result, in the memory system 1 of this embodiment, the impact of a mode change is contained within one set of physical full blocks FB (i.e., the set of physical full blocks FBa, FBb). Physical subblocks SB of logical subblocks LSB3, LSB4, LSB5, LSB6 assigned to the other sets of physical full blocks FBc, FBd, FBe, FBf are not subject to the mode change.

[0088] The memory controller 10 reads data from the physical subblock SB that is the target of the mode change, copies it to another physical subblock SB, and then commands the target physical subblock SB to perform an erase operation in the changed storage mode.

[0089] As described above, the mode change operation in the memory system 1 of this embodiment is completed.

[0090] (c) Comparative example Figure 6 is a schematic diagram illustrating the state of the comparative memory system when a mode change occurs. Figure 6 shows an example where six physical full blocks (FB) are provided, and two physical subblocks (SB) are provided within each physical full block (FB). The logical subblock (LSB) contains two physical subblocks (SB). Furthermore, in the comparative example, it is assumed that all physical subblocks (SB) of a physical full block (FB) are set to the same storage mode.

[0091] For example, physical full block FBa includes physical subblock SBa and physical subblock SBc. Physical full block FBb includes physical subblock SBa and physical subblock SBb. Physical full block FBc includes physical subblock SBc and physical subblock SBe. Physical full block FBd includes physical subblock SBb and physical subblock SBd. Physical full block FBe includes physical subblock SBe and physical subblock SBx. Physical full block FBf includes physical subblock SBd and physical subblock SBf.

[0092] In the comparative example, each logical subblock LSBa, LSBb, LSBc, LSBd, LSBBe, and LSBf is assigned to a physical full block FB. Each of the logical subblocks LSB in the comparative example is assigned to two distinct sets of physical full blocks FB.

[0093] Specifically, the logical subblock LSBa includes the physical subblock SBa of the physical full block FBa and the physical subblock SBa of the physical full block FBb. The logical subblock LSBc includes the physical subblock SBc of the physical full block FBa and the physical subblock SBc of the physical full block FBc. In other words, the set of physical full blocks FB to which the logical subblock LSBa is assigned (physical full blocks FBa, FBb) and the set of physical full blocks FB to which the logical subblock LSBc is assigned (physical full blocks FBa, FBc) are different from each other.

[0094] Logical subblock LSBb includes physical subblock SBb of physical full block FBb and physical subblock SBb of physical full block FBd. Logical subblock LSBd includes physical subblock SBd of physical full block FBd and physical subblock SBd of physical full block FBf. That is, the set of physical full blocks FB to which logical subblock LSBb is assigned (physical full blocks FBb, FBd) is different from the set of physical full blocks FB to which logical subblock LSBb is assigned (physical full blocks FBa, FBb). Also, the set of physical full blocks FB to which logical subblock LSBb is assigned (physical full blocks FBb, FBd) is different from the set of physical full blocks FB to which logical subblock LSBd is assigned (physical full blocks FBd, FBf).

[0095] The logical subblock LSBe includes the physical subblock SBe of the physical full block FBc and the physical subblock SBe of the physical full block FBe. That is, the set of physical full blocks FB to which the logical subblock LSBe is assigned (physical full blocks FBc, FBe) and the set of physical full blocks FB to which the logical subblock LSBc is assigned (physical full blocks FBa, FBc) are different from each other.

[0096] In the example shown in Figure 6, we assume that the memory controller of the comparative memory system selects the logical subblock LSBa as the target for mode change.

[0097] The NAND memory of the comparative example memory system performs various processes and operations in the specified storage mode for the physical subblock SBa of the physical full block FBa containing the logical subblock LSBa, and for the physical subblock SBa of the physical full block FBb containing the logical subblock LSBa, based on the storage mode specification included in the instructions from the memory controller.

[0098] As mentioned above, there is a constraint that all physical subblocks SB of a physical full block FB are set to the same memory mode. Therefore, when the mode change of logical subblock LSBa occurs, logical subblocks LSBb and LSBc are also subject to mode change. In other words, in logical subblock LSBb, in addition to the mode change of physical subblock SBb of physical full block FBb, physical subblock SBb of physical full block FBd is also subject to mode change. Similarly, in logical subblock LSBc, in addition to the mode change of physical subblock SBc of physical full block FBa, physical subblock SBc of physical full block FBc is also subject to mode change.

[0099] In response to the mode change for the logical subblocks LSBb and LSBc, the physical subblock SBd of the physical full block FBd and the physical subblock SBe of the physical full block FBc are also subject to the mode change, respectively.

[0100] Therefore, the logical subblocks LSBd and LSBe are also subject to mode change. Specifically, in the logical subblock LSBd, the physical subblock SBd of the physical full block FBd and the physical subblock SBd of the physical full block FBf are subject to mode change. Furthermore, the physical subblock SBf of the physical full block FBf is also subject to mode change. In addition, in the logical subblock LSBe, the physical subblock SBe of the physical full block FBc and the physical subblock SBe of the physical full block FBe are subject to mode change. Furthermore, the other physical subblock SBx of the physical full block FBe is also subject to mode change.

[0101] The memory controller in the comparative example reads data from the physical subblock SB to be changed, copies it to another physical subblock SB, and then commands the target physical subblock SB to perform an erase operation in the changed storage mode.

[0102] In the comparative example, a large number of physical subblocks SB are subject to a chain reaction of mode changes depending on the assignment of logical subblocks LSB to the physical full block FB. As a result, the amount of data copied between physical subblocks SB increases, and the write amplification factor (WAF) deteriorates.

[0103] (c) Summary As NAND memory generations advance, the size of physical full blocks (storage capacity) increases. The number of physical full blocks contained in a memory system with the same implemented storage capacity decreases as NAND memory generations advance. Therefore, the over-provisioning (OP) rate of the memory system may decrease.

[0104] To ensure an OP (Operational Purpose) ratio, the application of subblocks as elimination units is being considered.

[0105] In NAND memory to which subblocks are applied, if one subblock becomes subject to a mode change, due to various constraints of the NAND memory, there was a possibility that many subblocks other than the selected subblock would also become subject to a mode change in a chain reaction.

[0106] In the memory system 1 of this embodiment, multiple logical subblocks (LSBs) are commonly assigned to a single set containing multiple physical full blocks (FBs). As a result, according to the memory system 1 of this embodiment, the mode change chain is completed within that set of physical full blocks (FBs). Therefore, the memory system of this embodiment can suppress the number of subblocks that are subject to mode change.

[0107] Therefore, the memory system 1 of this embodiment can suppress the deterioration of the WAF.

[0108] As described above, the memory system 1 of this embodiment can improve the performance of the memory system.

[0109] (2) Second embodiment A memory system and its control method according to a second embodiment will be described with reference to Figures 7 to 10.

[0110] (a) Configuration example In this embodiment, the memory controller 10 selects logical full blocks to be garbage collected with a mode change based on the data efficiency of the logical full blocks. The memory controller 10 also selects logical subblocks to be garbage collected without a mode change based on the data efficiency of the logical subblocks.

[0111] In this embodiment, the memory controller 10 manages logical blocks (logical full blocks, logical subblocks) as user blocks (user logical full blocks, user logical subblocks) or system blocks (system logical full blocks, system logical subblocks).

[0112] A user block is a logical block (logical full block, logical subblock) that stores data (user data) received from host 2. The memory controller 10 uses a logical block that stores data in SLC mode or TLC mode as a user block.

[0113] A system block is a logical block (logical full block, logical subblock) that stores data related to the management of the memory system 1. The memory controller 10 uses a logical block that stores data in SLC mode as the system block.

[0114] An example of data stored in the system block is a Look Up Table (LUT) for managing the relationship between logical addresses specified by the host 2 and physical addresses in the NAND memory 30. The LUT has multiple entries. Each entry in the LUT stores information for managing the mapping between each logical address and each physical address indicating the location in the NAND memory 30 where user data with that logical address is stored. The memory controller 10 caches at least some of the multiple entries of the LUT in the RAM 16, for example, when the memory system 1 starts up. If user data with the same logical address is written to the NAND memory 30 multiple times, the memory controller 10 stores the mapping information for that logical address in different entries of the LUT cached in the RAM 16. The memory controller 10 periodically or irregularly devolves the entries of the LUT cached in the RAM 16 into the NAND memory 30. The mapping information for the same logical address may be devolved into the NAND memory 30 multiple times.

[0115] The following example illustrates a case where the data stored in a system block is a LUT. A system block is also referred to as a LUT block.

[0116] Figure 7 is a block diagram showing an example configuration of the memory system 1 of this embodiment.

[0117] As shown in Figure 7, the memory controller 10 stores a management table TBL1 in RAM 16 that contains data efficiency rates for multiple logical full blocks (LFBs) and multiple logical subblocks (LSBs) during the operation of the memory system 1. This allows the memory controller 10 to understand the data efficiency rates for each logical full block (LFB) and each logical subblock (LSB).

[0118] The memory controller 10 may manage the data efficiency for each logical block's purpose. For example, the memory controller 10 may manage the data efficiency for each logical block used as a LUT block. The memory controller 10 may manage the data efficiency for each logical block used as a user block in SLC mode. Furthermore, the memory controller 10 may manage the data efficiency for each logical block used as a user block in TLC mode.

[0119] The data efficiency of a logical block (logical full block, logical subblock) used as a user block is the ratio of the total amount of valid user data within the logical block to the storage capacity of the logical block. Valid user data is user data associated with a logical address that Host 2 can specify. Invalid user data is user data that is not associated with any logical address that Host 2 can specify. Valid user data is user data that Host 2 may request to read. Invalid user data is user data that Host 2 will not request to read.

[0120] The data efficiency of a logical block (logical full block, logical subblock) used as a LUT block is the ratio of the total amount of valid entries within the logical block to the storage capacity of the logical block. A valid entry is an entry that stores the mapping information for a given logical address that has been made non-volatile in the NAND memory 30. An invalid entry is an entry that stores the mapping information for a given logical address other than the mapping information that has been made non-volatile in the NAND memory 30.

[0121] Logical blocks used as user blocks but not storing valid user data, and logical blocks used as LUT blocks but not storing valid entries, are called free logical blocks (free logical full blocks, free logical subblocks).

[0122] In the following, the data effectiveness rate will also be simply referred to as the effectiveness rate. Furthermore, when effective user data and effective entries are not distinguished from each other, they will be referred to as effective data.

[0123] Figure 8 is a schematic diagram illustrating an example of the efficiency ratio in the memory system of this embodiment.

[0124] Figure 8 illustrates three logical full blocks LFB0, LFB1, and LFB2. Logical full block LFB0 has an efficiency of 60%, logical full block LFB1 has an efficiency of 80%, and logical full block LFB2 has an efficiency of 50%.

[0125] In Figure 8, each logic full block LFB contains two logic subblocks LSBa and LSBb. In logic full block LFB0, logic subblock LSB0a has a 30% efficiency rate, and logic subblock LSB0b has a 90% efficiency rate. In logic full block LFB1, logic subblock LSB1a has a 70% efficiency rate, and logic subblock LSB1b has a 90% efficiency rate. In logic full block LFB2, logic subblock LSB2a has a 50% efficiency rate, and logic subblock LSB2b has a 50% efficiency rate.

[0126] The memory controller 10 performs garbage collection as background processing based on spontaneous processing requests generated within the memory system 1. Garbage collection is also referred to as data copy operation, data move operation, or data transfer operation. For example, garbage collection may include two types of operation patterns: garbage collection with a mode change and garbage collection without a mode change. In garbage collection, valid data is copied (moved) between multiple logical blocks. That is, valid data read from the source logical block is written to the destination logical block. Garbage collection is performed, for example, when the number of free logical subblocks falls below a threshold.

[0127] In garbage collection involving mode changes, for example, valid data read from a logical subblock LSB in a certain storage mode (e.g., SLC mode or TLC mode) is written to another logical subblock LSB in the same storage mode (e.g., SLC mode or TLC mode), after which the storage mode of the source logical subblock LSB is changed, for example, from SLC mode to TLC mode, or from TLC mode to SLC mode.

[0128] In this embodiment, when garbage collection with a mode change is performed, the memory controller 10 selects a logical full block LFB from among multiple logical full block LFBs to be garbage collected based on the efficiency rate of the logical full block LFBs. For example, the memory controller 10 selects the logical full block LFB with the lowest efficiency rate from among the multiple logical full block LFBs as the target of garbage collection without a mode change (i.e., the source for copying). For example, the memory controller 10 performs garbage collection on the selected logical full block LFB.

[0129] In garbage collection without a mode change, valid data read from a logical subblock LSB in a certain storage mode (e.g., SLC mode or TLC mode) is written to another logical subblock LSB in the same storage mode (e.g., SLC mode or TLC mode), and the storage mode of the source logical subblock LSB is not changed.

[0130] In this embodiment, when garbage collection is performed without a mode change, the memory controller 10 selects a logical subblock LSB to be garbage collected from among multiple logical subblock LSBs based on the efficiency rate of the logical subblock LSBs. For example, the memory controller 10 selects the logical subblock LSB with the lowest efficiency rate from among the multiple logical subblock LSBs as the target of garbage collection without a mode change (i.e., the source of the copy). For example, the memory controller 10 performs garbage collection on the selected logical subblock LSB.

[0131] In the example shown in Figure 8, of the three logical full blocks LFB0, LFB1, and LFB2, logical full block LFB2 has the minimum efficiency. The memory controller 10 selects logical full block LFB2 as the target for garbage collection with a mode change.

[0132] On the other hand, if the target of garbage collection involving a mode change is selected based on the efficiency of the logical subblock LSB, then among the six logical subblocks LSB0a, LSB0b, LSB1a, LSB1b, LSB2a, and LSB2b, the logical subblock LSB0a with the lowest efficiency will be selected. As mentioned above, there is a constraint that physical subblocks SB with different storage modes cannot coexist simultaneously within the physical full block FB. Therefore, even if logical subblock LSB0a is selected, the entire logical full block LFB0, including the selected logical subblock LSB0a, will be subject to garbage collection. However, logical full block LFB0 has a higher efficiency than logical full block LFB2. Consequently, the WAF performance will be worse compared to when logical full block LFB2 is selected for garbage collection.

[0133] In the example shown in Figure 8, among the six logical subblocks LSB0a, LSB0b, LSB1a, LSB1b, LSB2a, and LSB2b, logical subblock LSB0a has the minimum efficiency. The memory controller 10 selects logical subblock LSB0a as the target for garbage collection without a mode change.

[0134] On the other hand, if garbage collection without a mode change is selected based on the efficiency of the logical full block LFB, then logical full block LFB2, which has the lowest efficiency among the three logical full blocks LFB0, LFB1, and LFB2, will be selected as the target. In other words, the logical subblock LSB2a (or logical subblock LSB2b) contained within logical full block LFB2 will be targeted for garbage collection. However, logical subblock LSB2a (or logical subblock LSB2b) has a higher efficiency than logical subblock LSB0a. Therefore, the WAF performance will worsen compared to when logical subblock LSB0a is selected as the target for garbage collection.

[0135] As described above, the memory system 1 of this embodiment selects targets for garbage collection that do not involve a mode change based on the efficiency of the logical subblock LSB, and selects targets for garbage collection that do involve a mode change based on the efficiency of the logical full block LFB.

[0136] (b) Example of operation An example of the operation of the memory system 1 of this embodiment will be described with reference to Figures 9 to 11.

[0137] (b-1) Garbage collection for user blocks in SLC mode Figure 9 is a flowchart showing the garbage collection process for SLC mode user blocks in the memory system 1 of this embodiment. The process shown in Figure 9 is executed, for example, when the writing of user data to a certain logical subblock LSB used as an SLC mode user block is completed.

[0138] <s10> As shown in Figure 9, the memory controller 10 checks the number of free logical subblocks reserved as user blocks in SLC mode.

[0139] <s11> If the number of free logical subblocks reserved as user blocks in SLC mode is less than or equal to a threshold (threshold ThA) (S11-Yes), the memory controller 10 proceeds to step S12. If the number of free logical subblocks reserved as user blocks in SLC mode is greater than a threshold (threshold ThA) (S11-No), the memory controller 10 terminates its processing.

[0140] <s12> The memory controller 10 refers to the management table TBL1 regarding the efficiency of logical blocks and searches for logical blocks to be garbage collected based on the efficiency of the logical blocks. Specifically, the memory controller 10 compares the minimum efficiency of the logical subblock LSB used as a user block in SLC mode (A) with the minimum efficiency of the logical full block LFB used as a user block in TLC mode (B).

[0141] <s13> <s14> If the efficiency rate (A) is less than or equal to the efficiency rate (B) (S13-Yes), the memory controller 10 selects the logical subblock LSB (user block in SLC mode) having the efficiency rate (A) as the target for garbage collection (S14). In this case, garbage collection without a mode change is performed.

[0142] <s15> The memory controller 10 performs garbage collection on the selected logical subblock LSB (user block in SLC mode). Specifically, the memory controller 10 reads valid data from each physical subblock SB within the selected logical subblock LSB. The read valid data is written to other physical subblocks SB in SLC mode. The memory controller 10 sets the logical subblock LSB from which all valid data has been read as a free logical subblock.

[0143] <s16> The memory controller 10 performs an erase operation on each physical subblock SB within the logical subblock LSB set as a free logical subblock, specifying SLC mode. The logical subblock LSB on which the erase operation has been performed is used as a user block in SLC mode. In this case, the erase operation is not performed on other logical subblock LSBs included in the logical full block LFB that contains the logical subblock LSB targeted for garbage collection. Therefore, the storage mode of these other logical subblock LSBs does not change before and after garbage collection is performed on the target logical subblock LSB.

[0144] <s13> <s17> On the other hand, if the efficiency ratio (A) is greater than the efficiency ratio (B) (S13-No), the memory controller 10 selects the logical full block LFB (user block in TLC mode) with efficiency ratio (B) as the target for garbage collection (S17). In this case, garbage collection accompanied by a mode change is performed.

[0145] <s18> The memory controller 10 performs garbage collection on the selected logical full block LFB (user block in TLC mode). Specifically, the memory controller 10 reads valid data from each physical subblock SB within the multiple logical subblock LSBs contained in the selected logical full block LFB. The read valid data is written to other physical subblock SBs in TLC mode. The memory controller 10 sets the logical subblock LSB from which all valid data has been read as a free logical subblock.

[0146] <s19> The memory controller 10 performs an erase operation on each physical subblock SB within the logical subblock LSB set as a free logical subblock (i.e., all logical subblock LSBs included in the logical full block LFB selected as the target of garbage collection), specifying SLC mode. In this case, the storage mode of the logical full block LFB selected as the target of garbage collection changes from TLC mode to SLC mode. Each logical subblock LSB on which the erase operation has been performed is used as a user block in SLC mode.

[0147] As described above, in the memory system of this embodiment, garbage collection for user blocks in SLC mode is completed.

[0148] (b-2) Garbage collection for user blocks in TLC mode Figure 10 is a flowchart showing the garbage collection process for user blocks in TLC mode in the memory system 1 of this embodiment. The process shown in Figure 10 is executed, for example, when the writing of user data to the logical subblock LSB used as a user block in TLC mode is completed.

[0149] <s20> As shown in Figure 10, the memory controller 10 checks the number of free logical subblocks reserved as user blocks in TLC mode.

[0150] <s21> If the number of free logical subblocks reserved as user blocks in TLC mode is less than or equal to the threshold (threshold ThB) (S21-Yes), the memory controller 10 proceeds to step S22. If the number of free logical subblocks reserved as user blocks in TLC mode is greater than the threshold (threshold ThB) (S21-No), the memory controller 10 terminates its processing.

[0151] <s22> The memory controller 10 searches for logical blocks to be garbage collected, similar to the process in step S12 as described with reference to Figure 9. Specifically, the memory controller 10 compares the minimum effective rate (A) of the logical subblock LSB used as a user block in TLC mode with the minimum effective rate (B) of the logical full block LFB used as a user block in SLC mode.

[0152] <s23> <s24> If the efficiency rate (A) is less than or equal to the efficiency rate (B) (S23-Yes), the memory controller 10 selects the logical subblock LSB (user block in TLC mode) having the efficiency rate (A) as the target for garbage collection (S24). In this case, garbage collection without a mode change is performed.

[0153] <s25> The memory controller 10 performs garbage collection on the selected logical subblock LSB (user block in TLC mode) in the same manner as the process in step S15 described with reference to Figure 9.

[0154] <s26> The memory controller 10 performs an erase operation on each physical subblock SB within the logical subblock LSB, which is set as a free logical subblock, specifying TLC mode. The logical subblock LSB on which the erase operation has been performed is used as a user block in TLC mode.

[0155] <s23> <s27> On the other hand, if the efficiency ratio (A) is greater than the efficiency ratio (B) (S13-No), the memory controller 10 selects the logical full block LFB (user block in SLC mode) with efficiency ratio (B) as the target for garbage collection (S17). In this case, garbage collection accompanied by a mode change is performed.

[0156] <s28> The memory controller 10 performs garbage collection on the selected logical full block LFB (user block in SLC mode) in the same manner as the process in step S18 described with reference to Figure 9.

[0157] <s29> The memory controller 10 performs an erase operation on each physical subblock SB within the logical subblock LSB set as a free logical subblock (i.e., all logical subblock LSBs included in the logical full block LFB selected as the target of garbage collection), specifying the TLC mode.

[0158] As described above, in the memory system of this embodiment, garbage collection for user blocks in TLC mode is completed.

[0159] (b-3) Garbage collection for LUT blocks in SLC mode Figure 11 is a flowchart showing the garbage collection process for an SLC mode LUT block in the memory system 1 of this embodiment. The process shown in Figure 11 is executed, for example, when the writing of entries to the logical subblock LSB used as an SLC mode LUT block is completed.

[0160] <s30> As shown in Figure 11, the memory controller 10 checks the number of free logic subblocks reserved as LUT blocks in SLC mode.

[0161] <s31> If the number of free logical subblocks reserved as LUT blocks in SLC mode is less than or equal to the threshold (threshold ThC) (S31-Yes), the memory controller 10 proceeds to step S32. If the number of free logical subblocks reserved as LUT blocks in SLC mode is greater than the threshold (threshold ThC) (S31-No), the memory controller 10 terminates its processing.

[0162] <s32> The memory controller 10 refers to the management table TBL1, which contains information on the efficiency of logical blocks, and searches for logical blocks to be garbage collected based on their efficiency. Specifically, the memory controller 10 selects the logical subblock LSB with the lowest efficiency among the logical subblocks LSB used as LUT blocks in SLC mode to be garbage collected. In this case, garbage collection is performed without a mode change.

[0163] The memory controller 10 may also select a logic block to be used as a LUT block in SLC mode from among multiple free logic blocks using a FIFO (First-In First-Out) method. In this case, the memory controller 10 may select the logic subblock LSB with the oldest valid entries written to it from among the multiple logic subblock LSBs used as LUT blocks as the target for garbage collection, instead of the logic subblock LSB with the lowest effective rate.

[0164] <s33> The memory controller 10 performs garbage collection on the selected logical subblock LSB (LUT block in SLC mode). Specifically, the memory controller 10 reads valid entries from each physical subblock SB within the selected logical subblock LSB. The read valid entries are written to other physical subblocks SB in SLC mode. The memory controller 10 sets the logical subblock LSB from which all valid entries have been read as a free logical subblock.

[0165] <s34> The memory controller 10 performs an erase operation on each physical subblock SB within the logical subblock LSB, which is set as a free logical subblock, specifying SLC mode. The logical subblock LSB on which the erase operation has been performed is used as a LUT block in SLC mode.

[0166] As described above, in the memory system of this embodiment, garbage collection for the LUT block in SLC mode is completed.

[0167] (c) Summary In memory systems that do not employ logical subblocks, the logical full block with the lowest efficiency among multiple logical full blocks may be selected for garbage collection.

[0168] However, even if a logical full block has the lowest efficiency, the logical subblocks contained within that full block may not necessarily have the lowest efficiency among multiple logical subblocks. If garbage collection targeting is selected at the logical full block level without a mode change, data will be copied even from logical subblocks with relatively high efficiency. This can potentially degrade the WAF's performance.

[0169] In contrast, the memory system 1 of this embodiment selects the targets for garbage collection without a mode change based on the validity rate of each logical subblock. This makes it possible to suppress an increase in the amount of valid data copied (moved) by garbage collection without a mode change.

[0170] Furthermore, because a mode change is not performed on the logical subblock targeted for garbage collection, the storage mode of other logical subblocks included in the same logical full block as the targeted logical subblock remains unchanged. As a result, these other logical subblocks can continue to store valid data without being affected by garbage collection. Therefore, if these other logical subblocks have a relatively high efficiency rate, that high efficiency rate can be maintained.

[0171] On the other hand, even if a logical subblock has the lowest efficiency, the logical full block containing that subblock may not necessarily have the lowest efficiency among multiple logical full blocks. Furthermore, a mode change affects all logical subblocks included in the logical full block to which the mode change is performed. Therefore, if garbage collection involving a mode change is selected at the logical subblock level, data may be copied from logical full blocks with relatively high efficiency. This could potentially degrade the WAF's performance.

[0172] In contrast, the memory system 1 of this embodiment selects the targets for garbage collection involving mode changes based on the validity rate of each logical full block. This makes it possible to suppress the increase in the amount of valid data copied (moved) by garbage collection involving mode changes.

[0173] Therefore, the memory system 1 of this embodiment can improve the performance and lifespan of the memory system.

[0174] (3) Third Embodiment A memory system and its control method according to a third embodiment will be described with reference to Figures 12 to 15.

[0175] (a) Configuration example In this embodiment, the memory controller 10 selects logical full blocks to be subjected to wear leveling with a mode change based on the fatigue level of the logical full blocks. The memory controller 10 also selects logical subblocks to be subjected to wear leveling without a mode change based on the fatigue level of the logical subblocks.

[0176] Figure 12 is a block diagram showing an example configuration of the memory system 1 of this embodiment.

[0177] As shown in Figure 12, when the memory system 1 is operating, the memory controller 10 stores in RAM 16 a management table TBL2 containing information on the fatigue levels of multiple logical full blocks (LFBs) and multiple logical subblocks (LSBs), in addition to the management table TBL1 described with reference to Figure 7. This allows the memory controller 10 to understand the fatigue levels of each logical full block (LFB) and each logical subblock (LSB).

[0178] The fatigue level of a logical full block (LFB) is determined, for example, based on the number of erase operations performed on each of the multiple physical full block (FB) contained within that logical full block (LFB). For example, the fatigue level of a logical full block (LFB) is determined based on the average number of erase operations performed on each of the multiple physical full block (FB) contained within that logical full block (LFB). Alternatively, the fatigue level of a logical full block (LFB) is determined based on the maximum number of erase operations performed on each of the multiple physical full block (FB) contained within that logical full block (LFB). If a logical full block (LFB) has a high number of erase operations, its fatigue level is high.

[0179] The exhaustion level of a logical subblock LSB is determined, for example, based on the number of erase operations performed on each of the multiple physical subblocks SB contained within that logical subblock LSB. For example, the exhaustion level of a logical subblock LSB is determined based on the average number of erase operations performed on each of the multiple physical subblocks SB contained within that logical subblock LSB. Alternatively, the exhaustion level of a logical subblock LSB is determined based on the maximum number of erase operations performed on each of the multiple physical subblocks SB contained within that logical subblock LSB. If a logical subblock LSB has a high number of erase operations, its exhaustion level is high.

[0180] The wear level of a physical full block (FB) is determined, for example, based on the number of erase operations performed on each of the multiple physical subblocks (SB) contained within that FB. For example, the wear level of a physical full block (FB) is determined based on the average number of erase operations performed on each of the multiple physical subblocks (SB) contained within that FB. Alternatively, the wear level of a physical full block (FB) is determined based on the maximum number of erase operations performed on each of the multiple physical subblocks (SB) contained within that FB. If a physical full block (FB) has had many erase operations, its wear level is high.

[0181] The memory controller 10 may manage the fatigue level of each logical block according to its intended use. For example, the memory controller 10 may manage the fatigue level of each logical block used as a LUT block. The memory controller 10 may manage the fatigue level of each logical block used as a user block in SLC mode. Furthermore, the memory controller 10 may manage the fatigue level of each logical block used as a user block in TLC mode.

[0182] The number of logical blocks (user blocks, LUT blocks) used in SLC mode is less than the number of logical blocks (user blocks) used in TLC mode. The total storage capacity of logical blocks used in SLC mode is less than the total storage capacity of logical blocks used in TLC mode. The rate at which logical blocks used in SLC mode and TLC mode become exhausted varies depending on their number, storage capacity, and the rate at which they are written, but generally, logical blocks used in SLC mode become exhausted more quickly than those used in TLC mode.

[0183] The memory controller 10 performs wear leveling as background processing based on spontaneous processing requests generated within the memory system 1. Wear leveling is also referred to as data copy operation, data move operation, or data transfer operation. For example, wear leveling may include two types of operation patterns: wear leveling with a mode change and wear leveling without a mode change. In wear leveling, valid data is copied (moved) between multiple logical blocks. That is, valid data read from the source logical block is written to the destination logical block. Wear leveling is performed, for example, when the difference in fatigue levels between multiple logical blocks exceeds a threshold.

[0184] In wear leveling involving a mode change, for example, valid data read from a logical subblock LSB in a certain storage mode (e.g., SLC mode or TLC mode) is written to another logical subblock LSB in the same storage mode (e.g., SLC mode or TLC mode), after which the storage mode of the source logical subblock LSB is changed, for example, from SLC mode to TLC mode, or from TLC mode to SLC mode.

[0185] Wear leveling with mode changes is performed, for example, when there is a difference in the degree of fatigue between multiple logical full block LFBs in different memory modes. Specifically, the memory controller 10 selects the logical full block LFB with the least fatigue as the target for wear leveling (i.e., the source for copying). If there are multiple logical full block LFBs with the least fatigue, the memory controller 10 selects the logical full block LFB to be used for wear leveling based on the efficiency rate of the logical full block LFBs. Furthermore, the memory controller 10 also selects the logical full block LFB with the most fatigue as a target for wear leveling. If there are multiple logical full block LFBs with the most fatigue, the memory controller 10 selects the logical full block LFB to be used for wear leveling based on the efficiency rate of the logical full block LFBs.

[0186] In wear leveling without a mode change, valid data read from a logical subblock LSB in a certain storage mode (e.g., SLC mode or TLC mode) is written to another logical subblock LSB in the same storage mode (e.g., SLC mode or TLC mode), and the storage mode of the source logical subblock LSB is not changed.

[0187] Wear leveling without a mode change is performed, for example, when there is a difference in the degree of fatigue among multiple logical subblock LSBs in the same memory mode. Specifically, the memory controller 10 selects the logical subblock LSB with the least fatigue as the target for wear leveling (i.e., the source of the copy). If there are multiple logical subblock LSBs with the least fatigue, the memory controller 10 selects the logical subblock LSB to be used for wear leveling based on the efficiency rate of the logical subblock LSBs.

[0188] As described above, the memory system 1 of this embodiment selects targets for wear leveling with mode change based on the fatigue level of the logical full block LFB, and selects targets for wear leveling without mode change based on the fatigue level of the logical subblock LSB.

[0189] (b) Example of operation An example of the operation of the memory system 1 of this embodiment will be described with reference to Figures 13 to 15.

[0190] (b-1) Wear leveling between user blocks Figure 13 is a flowchart showing the wear leveling process between user blocks in the memory system of this embodiment. The process shown in Figure 13 is executed, for example, upon completion of an erase operation on a certain logical subblock LSB that was used as a user block.

[0191] <s40> The memory controller 10 manages the total number of erase operations performed on each of the multiple logical subblocks LSB since the last wear leveling was performed. As shown in Figure 13, if the total number of erase operations performed on a certain logical subblock LSB reaches N (S40-Yes), the memory controller 10 resets the total to 0, and the memory controller 10 proceeds to step S41. If the total number of erase operations does not reach N (S40-No), the memory controller 10 terminates its processing. Here, N is an integer greater than or equal to 1. For example, N is 1000.

[0192] <s41> The memory controller 10 refers to a management table TBL2 regarding the wear level of logical blocks and searches for logical subblock LSBs that are subject to wear leveling based on the wear level of the logical subblock LSBs. Specifically, the memory controller 10 calculates the difference in wear levels between multiple logical subblock LSBs used as user blocks in the same storage mode. For example, the memory controller 10 calculates the difference between the average wear level of each of the multiple logical subblock LSBs used as user blocks in the same storage mode and the minimum wear level among the multiple logical subblock LSBs used as user blocks in the same storage mode.

[0193] <s42> If the difference in wear levels is greater than or equal to the threshold (threshold ThD) (S42-Yes), the memory controller 10 proceeds to step S43. In this case, wear leveling without a mode change is performed. If the difference in wear levels is less than the threshold (threshold ThD) (S42-No), the memory controller 10 terminates its processing.

[0194] <s43> The memory controller 10 refers to the management table TBL2 regarding the fatigue level of logical blocks and checks whether there are multiple logical subblock LSBs with the lowest fatigue level among the multiple logical subblock LSBs used as user blocks in the same storage mode. If there are multiple logical subblock LSBs with the lowest fatigue level (S43-Yes), the memory controller 10 proceeds to step S44. If there are not multiple logical subblock LSBs with the lowest fatigue level (S43-No), the memory controller 10 proceeds to step S45.

[0195] <s44> If there are multiple logical subblock LSBs with the lowest fatigue level (S43-Yes), the memory controller 10 refers to the management table TBL1 regarding the efficiency of logical blocks and searches for a logical block to be targeted for wear leveling based on the efficiency of the logical blocks. Specifically, the memory controller 10 selects the logical subblock LSB with the lowest efficiency level from among the multiple logical subblock LSBs with the lowest fatigue level as the target for wear leveling.

[0196] <s45> If there are no multiple logical subblock LSBs with the lowest degree of wear (S43-No), the memory controller 10 selects the logical subblock LSB with the lowest degree of wear as the target for wear leveling.

[0197] <s46> The memory controller 10 performs wear leveling on the selected logical subblock LSB. Specifically, the memory controller 10 reads valid data from each physical subblock SB within the selected logical subblock LSB. The read valid data is written to other physical subblocks SB. The memory controller 10 writes valid data to other physical subblocks SB in the same storage mode as the physical subblock SB from which the valid data was read. The memory controller 10 sets the logical subblock LSB from which all valid data has been read as a free logical subblock.

[0198] <s47> The memory controller 10 performs an erase operation on each physical subblock SB within the logical subblock LSB set as a free logical subblock, specifying the same storage mode as before. The logical subblock LSB on which the erase operation has been performed is used as a user block in the same storage mode as before. By using the logical subblock LSB with the least fatigue level as a user block for writing new user data, it is expected that the fatigue level of that logical subblock LSB will be leveled with that of the other logical subblock LSBs.

[0199] Furthermore, the erase operation is not performed on other logical subblock LSBs included in the logical full block LFB that contains the logical subblock LSB targeted for wear leveling. Therefore, the storage mode of these other logical subblock LSBs does not change before and after the wear leveling is performed on the target logical subblock LSB.

[0200] As described above, in the memory system of this embodiment, wear leveling between user blocks is completed.

[0201] (b-2) Wear leveling between LUT blocks Figure 14 is a flowchart showing the wear leveling process between LUT blocks in the memory system of this embodiment. The process shown in Figure 14 is executed, for example, upon completion of an erase operation on a certain logical subblock LSB that was used as a LUT block.

[0202] <s50> Similar to the process in step S40 as explained with reference to Figure 13, if the total number of erase operations performed on a certain logical subblock LSB reaches N (S50-Yes), the memory controller 10 resets the total count to 0, and the memory controller 10 proceeds to step S51. If the total count is not N (S50-No), the memory controller 10 terminates its operation.

[0203] <s51> Similar to the process in step S41 described with reference to Figure 13, the memory controller 10 searches for the logical subblock LSB to be wear-leveled. Specifically, the memory controller 10 calculates the difference in fatigue levels between multiple logical subblock LSBs that are used as LUT blocks in the same storage mode.

[0204] <s52> If the difference in wear levels is greater than or equal to the threshold (threshold ThE) (S52-Yes), the memory controller 10 proceeds to step S53. In this case, wear leveling without a mode change is performed. If the difference in wear levels is less than the threshold (threshold ThE) (S52-No), the memory controller 10 terminates its processing.

[0205] <s53> Similar to the process in step S43 described with reference to Figure 13, the memory controller 10 checks whether there are multiple logical subblock LSBs with the lowest exhaustion level among the multiple logical subblock LSBs used as LUT blocks in the same storage mode.

[0206] <s54> If there are multiple logical subblock LSBs with the lowest degree of wear (S53-Yes), the memory controller 10 searches for a logical block to be wear-leveled, similar to the process in step S44 as described with reference to Figure 13. Specifically, the memory controller 10 selects the logical subblock LSB with the lowest effective rate from among the multiple logical subblock LSBs with the lowest degree of wear as the target for wear-leveling.

[0207] <s55> If there are no multiple logical subblock LSBs with the lowest degree of wear (S53-No), the memory controller 10 selects the logical subblock LSB with the lowest degree of wear as the target for wear leveling, similar to the process in step S45 as described with reference to Figure 13.

[0208] <s56> Similar to the process in step S46 described with reference to Figure 13, the memory controller 10 performs wear leveling on the selected logical subblock LSB.

[0209] <s57> Similar to the process in step S47 described with reference to Figure 13, the memory controller 10 performs an erase operation on each physical subblock SB within the logical subblock LSB set as a free logical subblock, specifying the same storage mode as before. The logical subblock LSB on which the erase operation has been performed is used as a LUT block with the same storage mode as before. By using the logical subblock LSB with the least fatigue as the LUT block for writing new entries, it is expected that the fatigue level of that logical subblock LSB will be leveled with that of the other logical subblock LSBs.

[0210] Furthermore, the erase operation is not performed on other logical subblock LSBs included in the logical full block LFB that contains the logical subblock LSB targeted for wear leveling. Therefore, the storage mode of these other logical subblock LSBs does not change before and after the wear leveling is performed on the target logical subblock LSB.

[0211] As described above, in the memory system of this embodiment, wear leveling between LUT blocks is completed.

[0212] (b-3) Wear leveling between user blocks and LUT blocks Figure 15 is a flowchart showing the wear leveling process between user blocks and LUT blocks in the memory system of this embodiment. The process shown in Figure 15 is executed, for example, upon completion of an erase operation on a certain logical subblock LSB that was used as a user block in TLC mode, or upon completion of an erase operation on a certain logical subblock LSB that was used as a LUT block in SLC mode.

[0213] <s60> Similar to the process in step S40 as explained with reference to Figure 13, if the total number of erase operations performed on a certain logical subblock LSB reaches N (S60-Yes), the memory controller 10 resets the total count to 0, and the memory controller 10 proceeds to step S61. If the total count is not N (S60-No), the memory controller 10 terminates its operation.

[0214] <s61> The memory controller 10 refers to a management table TBL2 regarding the wear level of logical blocks and searches for logical full block LFBs to be targeted for wear leveling based on the wear level of the logical full block LFBs. Specifically, the memory controller 10 calculates the difference in wear levels between logical full block LFBs used as user blocks in TLC mode and logical full block LFBs used as LUT blocks in SLC mode. For example, the memory controller 10 calculates the difference between the minimum wear level (A) of multiple logical full block LFBs used as user blocks in TLC mode and the maximum wear level (B) of multiple logical full block LFBs used as LUT blocks in SLC mode.

[0215] <s62> If the difference in wear levels is greater than or equal to the threshold (threshold ThF) (S62-Yes), the memory controller 10 proceeds to step S63. In this case, wear leveling accompanied by a mode change is performed. If the difference in wear levels is less than the threshold (threshold ThF) (S62-No), the memory controller 10 terminates its processing.

[0216] <s63> The memory controller 10 refers to the management table TBL2 regarding the fatigue level of logical blocks and checks whether there are multiple logical full block LFBs with the minimum fatigue level among the multiple logical full block LFBs used as user blocks in TLC mode. If there are multiple logical full block LFBs with the minimum fatigue level (S63-Yes), the memory controller 10 proceeds to step S64. If there are not multiple logical full block LFBs with the minimum fatigue level (S63-No), the memory controller 10 proceeds to step S65.

[0217] <s64> If there are multiple logical full block LFBs with the lowest fatigue level (S63-Yes), the memory controller 10 refers to the management table TBL1 regarding the efficiency of logical blocks and searches for a logical block to be targeted for wear leveling based on the efficiency of the logical blocks. Specifically, the memory controller 10 selects the logical full block LFB with the lowest efficiency level among the multiple logical full block LFBs with the lowest fatigue level as the target for wear leveling.

[0218] <s65> If there are no multiple logical full block LFBs with the lowest wear level (S63-No), the memory controller 10 selects the logical full block LFB with the lowest wear level as the target for wear leveling.

[0219] <s66> The memory controller 10 performs wear leveling on the selected logical full block LFB. Specifically, the memory controller 10 reads valid data from each physical subblock SB within the multiple logical subblock LSBs contained in the selected logical full block LFB. The read valid data is written to other physical subblock SBs in TLC mode. The memory controller 10 sets the logical subblock LSB from which all valid data has been read as a free logical subblock.

[0220] <s67> The memory controller 10 performs an erase operation on each physical subblock SB within the logical subblock LSB set as a free logical subblock (i.e., all logical subblock LSBs included in the logical full block LFB selected as the target of wear leveling), specifying SLC mode. In this case, the storage mode of the logical full block LFB selected as the target of wear leveling changes from TLC mode to SLC mode. Each logical subblock LSB on which the erase operation has been performed is used as a LUT block in SLC mode. It is expected that the wear level of the logical full block LFB with the least wear level (the user block in TLC mode) will be leveled by using it as the LUT block for writing new entries.

[0221] <s68> The memory controller 10 refers to the management table TBL2 regarding the fatigue level of logical blocks and checks whether there are multiple logical full block LFBs with the highest fatigue level among the multiple logical full block LFBs used as LUT blocks in SLC mode. If there are multiple logical full block LFBs with the highest fatigue level (S68-Yes), the memory controller 10 proceeds to step S69. If there are no multiple logical full block LFBs with the highest fatigue level (S68-No), the memory controller 10 proceeds to step S70.

[0222] <s69> If there are multiple logical full block LFBs with the highest level of wear (S68-Yes), the memory controller 10 refers to the management table TBL1 regarding the efficiency of logical blocks and searches for a logical block to be targeted for wear leveling based on the efficiency of the logical blocks. Specifically, the memory controller 10 selects the logical full block LFB with the lowest efficiency among the multiple logical full block LFBs with the highest level of wear as the target for wear leveling.

[0223] <s70> If there are no multiple logical full block LFBs with the highest level of wear (S68-No), the memory controller 10 selects the logical full block LFB with the highest level of wear as the target for wear leveling.

[0224] <s71> The memory controller 10 performs wear leveling on the selected logical full block LFB. Specifically, the memory controller 10 reads valid data from each physical subblock SB within the multiple logical subblock LSBs included in the selected logical full block LFB. The read valid data is written to other physical subblock SBs in SLC mode. The memory controller 10 sets the logical subblock LSB from which all valid data has been read as a free logical subblock.

[0225] <s72> The memory controller 10 performs an erase operation on each physical subblock SB within the logical subblock LSB set as a free logical subblock (i.e., all logical subblock LSBs included in the logical full block LFB selected as the target of wear leveling), specifying TLC mode. In this case, the storage mode of the logical full block LFB selected as the target of wear leveling changes from SLC mode to TLC mode. Each logical subblock LSB on which the erase operation has been performed is used as a user block in TLC mode. It is expected that the wear level of the logical full block LFB with the greatest wear level (the LUT block in SLC mode) will be leveled out by using it as a user block for writing new user data.

[0226] As described above, in the memory system of this embodiment, wear leveling between user blocks and LUT blocks is completed.

[0227] (modified version) In the process of step S43, as explained with reference to Figure 13, the memory controller 10 checked whether there were multiple logical subblock LSBs with the minimum wear level among the multiple logical subblock LSBs used as user blocks in the same storage mode. However, the method of selecting the logical subblock LSBs to be targeted for wear leveling is not limited to this. For example, the memory controller 10 may check whether there are multiple logical subblock LSBs with wear levels in a range from the minimum wear level to a wear level one number greater than that minimum. If there are multiple logical subblock LSBs with wear levels in this range, the memory controller 10 selects the logical subblock LSB with the minimum effective rate among those multiple logical subblock LSBs to be targeted for wear leveling. The same applies to the process of step S53, as explained with reference to Figure 14.

[0228] In the process of step S63, as explained with reference to Figure 15, the memory controller 10 checked whether there were multiple logical full block LFBs with the minimum wear level among the multiple logical full block LFBs used as user blocks in TLC mode. However, the method of selecting the logical full block LFBs to be targeted for wear leveling is not limited to this. For example, the memory controller 10 may check whether there are multiple logical full block LFBs with wear levels in the range from the minimum wear level to a wear level two numbers greater than that minimum. If there are multiple logical full block LFBs with wear levels in this range, the memory controller 10 selects the logical full block LFB with the minimum effective rate among those multiple logical full block LFBs to be targeted for wear leveling.

[0229] In step S68, as explained with reference to Figure 15, the memory controller 10 checked whether there were multiple logical full block LFBs with the highest degree of wear among the multiple logical full block LFBs used as LUT blocks in SLC mode. However, the method for selecting the logical full block LFBs to be worn leveled is not limited to this. For example, the memory controller 10 may check whether there are multiple logical full block LFBs with wear levels in the range from the highest degree of wear to a third smaller degree of wear. If there are multiple logical full block LFBs with wear levels in this range, the memory controller 10 selects the logical full block LFB with the lowest effective rate among those multiple logical full block LFBs to be worn leveled.

[0230] In the process of step S61, as explained with reference to Figure 15, the memory controller 10 calculated the difference between the minimum value (A) of the wear levels of multiple logical full block LFBs used as user blocks in TLC mode and the maximum value (B) of the wear levels of multiple logical full block LFBs used as LUT blocks in SLC mode. However, the method for determining whether or not to perform wear leveling is not limited to this. Instead of the minimum value (A), the average value of the wear levels of each of the multiple logical full block LFBs used as user blocks in TLC mode may be used. Instead of the minimum value (B), the average value of the wear levels of each of the multiple logical full block LFBs used as LUT blocks in SLC mode may be used.

[0231] (c) Summary The memory system 1 of this embodiment selects the logical blocks to be subjected to wear leveling based on the degree of wear of the logical blocks. This allows the memory system 1 of this embodiment to equalize the degree of wear between logical blocks.

[0232] Therefore, the memory system 1 of this embodiment can improve the performance and lifespan of the memory system.

[0233] (5) Others While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0234] 1: Memory system, 2: Host, 9: Information processing system, 10: Memory controller, 11: Host interface circuit, 12: Processor, 13: Buffer memory, 14: ECC circuit, 15: ROM, 16: RAM, 17: NAND interface circuit, 30: Memory device, 31: Memory cell array, 32: Input / output circuit, 33: Logic control circuit, 34: Ready / busy control circuit 34, 35: Register, 36: Sequencer, 37: Driver module, 38: Raw decoder module, 39: Sense amplifier module, 40: Data latch, 300: Memory chip, FB: Physical full block, SB: Physical subblock, LFB: Logic full block, LSB: Logic subblock. < / s23> < / s23> < / s13> < / s13>

Claims

1. Non-volatile memory comprising multiple physical full blocks, Each of the aforementioned physical full blocks includes a plurality of physical subblocks, In each of the plurality of physical full blocks, the memory cells included in each of the plurality of physical subblocks are non-volatile memories connected in series or in parallel to the same bit line. A memory controller electrically connected to the aforementioned non-volatile memory, It is equipped with, The aforementioned memory controller In each of the aforementioned multiple physical full blocks, a data erasure operation is performed independently on each of the aforementioned multiple physical subblocks. Each of the aforementioned multiple physical full blocks is configured to set all of the aforementioned multiple physical subblocks to the same storage mode. The aforementioned storage mode is a setting state that indicates the number of bits of data stored in each of the plurality of physical subblocks, Memory system.

2. Each of the plurality of physical subblocks in the plurality of physical full blocks includes at least a first physical subblock and a second physical subblock. The aforementioned memory controller The set of the first physical subblock of the first physical full block among the plurality of physical full blocks and the first physical subblock of the second physical full block among the plurality of physical full blocks is managed as the first logical subblock. The set of the second physical subblock of the first physical full block and the second physical subblock of the second physical full block is managed as a second logical subblock. The same storage mode is set for the first physical subblock of the first physical full block and the first physical subblock of the second physical full block, which are included in the first logical subblock. The system is configured to set the same storage mode in the second physical subblock of the first physical full block and the second physical subblock of the second physical full block, which are included in the second logical subblock. The memory system according to claim 1.

3. The aforementioned memory controller further, The first physical subblock of the first physical full block and the first physical subblock of the second physical full block, which are included in the first logical subblock, are to be subjected to a data erasure operation simultaneously. The system is configured to perform a data erasure operation on the second physical subblock of the first physical full block and the second physical subblock of the second physical full block, which are included in the second logical subblock, independently and collectively with respect to the first logical subblock. The memory system according to claim 2.

4. The aforementioned memory controller further, The set of the first logical subblock and the second logical subblock is managed as the first logical full block. The system is configured to perform a data erasure operation on the first logical subblock and the second logical subblock, which are included in the first logical full block, all at once. The memory system according to claim 2.

5. The aforementioned memory controller further, It manages multiple logical full blocks, each containing at least two of the aforementioned multiple physical full blocks, Each of the aforementioned multiple physical full blocks manages multiple logical subblocks, each containing at least two physical subblocks from the aforementioned multiple physical subblocks. The system is configured to set all of the at least two physical subblocks contained in each of the plurality of logical subblocks to the same storage mode. The number of physical subblocks contained in each of the plurality of physical full blocks and the number of logical subblocks contained in each of the plurality of logical full blocks are equal to each other. The memory system according to claim 1.

6. The aforementioned memory controller further, It manages multiple logical full blocks, each containing at least two of the aforementioned multiple physical full blocks, Each of the aforementioned multiple physical full blocks manages multiple logical subblocks, each containing at least two physical subblocks from the aforementioned multiple physical subblocks. The system is configured to set all of the at least two physical subblocks contained in each of the plurality of logical subblocks to the same storage mode. Each of the plurality of logical subblocks contains at least two physical subblocks that are not included in two different logical full blocks among the plurality of logical full blocks. The memory system according to claim 1.

7. The aforementioned memory controller further, It manages multiple logical full blocks, each containing at least two of the aforementioned multiple physical full blocks, Each of the aforementioned multiple physical full blocks manages multiple logical subblocks, each containing at least two physical subblocks from the aforementioned multiple physical subblocks. The system is configured to select a logical full block or logical subblock to be garbage collected based on at least one of the efficiency rates of the plurality of logical full blocks and the efficiency rates of the plurality of logical subblocks. The memory system according to claim 1.

8. The aforementioned memory controller The first effectiveness rate, which is the effectiveness rate of the first logical subblock set to a first storage mode among the plurality of logical subblocks, and the second effectiveness rate, which is the effectiveness rate of the first logical full block set to a second storage mode different from the first storage mode among the plurality of logical full blocks, are compared. If the first efficiency rate is less than or equal to the second efficiency rate, the first logical subblock is selected as the target of garbage collection. The system is configured to select the first logical full block as the target of garbage collection when the first efficiency rate is greater than the second efficiency rate. The memory system according to claim 7.

9. The memory controller further, when the first efficiency rate is less than or equal to the second efficiency rate, The valid data is copied from the first logical subblock to the physical subblocks among the plurality of physical subblocks that are not included in the first logical subblock, in the first storage mode. After copying the valid data, the system is configured to perform a data erasure operation in the first storage mode on the first logical subblock. The memory system according to claim 8.

10. The memory controller further, when the first efficiency ratio is greater than the second efficiency ratio, The valid data is copied from the first logical full block to the physical subblocks within the physical full blocks that are not included in the first logical full block, in the second storage mode. After copying the valid data, the system is configured to perform a data erasure operation in the first storage mode on the first logical full block. The memory system according to claim 8.

11. The aforementioned memory controller The system is configured to compare the first effectiveness rate with the second effectiveness rate when the number of logical subblocks among the plurality of logical subblocks set to the first storage mode that do not store valid data falls below a first threshold. The memory system according to claim 8.

12. The aforementioned memory controller In response to the number of logical subblocks among the plurality of logical subblocks set to a first storage mode that do not store valid data falling below a second threshold, the logical subblock with the minimum validity rate among the plurality of first logical subblocks is selected as the target of garbage collection. The memory system according to claim 7.

13. The aforementioned memory controller further, It manages multiple logical full blocks, each containing at least two of the aforementioned multiple physical full blocks, Each of the aforementioned multiple physical full blocks manages multiple logical subblocks, each containing at least two physical subblocks from the aforementioned multiple physical subblocks. The system is configured to select a logical full block or logical subblock to be subjected to wear leveling based on at least one of the wear levels of the plurality of logical full blocks or the wear levels of the plurality of logical subblocks. The memory system according to claim 1.

14. The aforementioned memory controller further, A first difference is calculated, which is the difference between the first fatigue level, which is the fatigue level of a first logical subblock set to a first storage mode among the plurality of logical subblocks, and the second fatigue level, which is the fatigue level of a second logical subblock, which is set to the first storage mode among the plurality of logical subblocks but is different from the first logical subblock. If the first difference is greater than or equal to the third threshold, the system is configured to select the third logical subblock with the minimum wear level among a plurality of logical subblocks set in the first storage mode as the target for wear leveling. The memory system according to claim 13.

15. The memory controller further, if the first difference is greater than or equal to the third threshold, The valid data is copied from the third logical subblock to the physical subblocks among the plurality of physical subblocks that are not included in the third logical subblock, in the first storage mode. After copying the valid data, the system is configured to perform a data erasure operation in the first storage mode on the third logical subblock. The memory system according to claim 14.

16. The aforementioned memory controller further, The effectiveness rate of the aforementioned multiple logical subblocks is managed, When there are multiple third logical subblocks, the system is configured to select the fourth logical subblock with the minimum effectiveness rate among the multiple third logical subblocks as the target for wear leveling. The memory system according to claim 14.

17. The aforementioned memory controller further, A second difference is calculated, which is the difference between the first fatigue level, which is the fatigue level of the first logical full block set to a first memory mode among the plurality of logical full blocks, and the second fatigue level, which is the fatigue level of the second logical full block set to a second memory mode different from the first memory mode among the plurality of logical full blocks. If the second difference is greater than or equal to the fourth threshold, the system is configured to select the third logical full block with the minimum wear level among a plurality of logical full blocks set in the first storage mode as the target for wear leveling. The memory system according to claim 13.

18. The memory controller further, if the second difference is greater than or equal to the fourth threshold, The valid data is copied from the third logical full block to a physical subblock within a physical full block that is not included in the third logical full block, among the plurality of physical full blocks, in the first storage mode. After copying the valid data, the system is configured to perform a data erasure operation in the second storage mode on the third logical full block. The memory system according to claim 17.

19. The memory controller further, if the second difference is greater than or equal to the fourth threshold, The system is configured to select the fourth logical full block, which has the highest degree of wear among a plurality of logical full blocks set in the second memory mode, as the target for wear leveling. The memory system according to claim 18.

20. The aforementioned memory controller further, The valid data is copied from the fourth logical full block to the physical subblocks within the physical full blocks that are not included in the fourth logical full block, using the second storage mode. After copying the valid data, the system is configured to perform a data erasure operation in the first storage mode on the fourth logical full block. The memory system according to claim 19.

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